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Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October 17, 2007

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Page 1: Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October

Sine Wave Generation on the XUP Virtex-II Pro Development System

Steven WassonECE 443 – Hardware Design in VHDLAssignment 3 – Sine Wave GenerationOctober 17, 2007

Page 2: Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October

Sine Computation via CORDIC 16-Bit Architecture with Radix Point

after the MSB The Input Angle (Z0) is represented as

Fractions of pi not radians Can be signed [-1, +1) or unsigned [0, 2)

Output is signed and is computed from the following iterative equations for i = [0..15]: Zi+1 = Zi – σiαi, where αi = atan(2-i) / π. Xi+1 = Xi – σiYi

Yi+1 = Yi + σiXi

║(X0, Y0)║ ≈ 0.607253 σi = +1 if Zi ≥ 0 else -1

Signed Fractions of Pi Representation of Input Angle

Unsigned Fractions of Pi Representation of Input Angle

Page 3: Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October

Sine Wave Generation Discrete Sine Wave in radians: sin(2πfnTS) Discrete Sine Wave in fractions of pi: sin(2fnTS) Let TS = 2-16 (FS = 65,536 Hz) sin(2-15fn)

Place the radix point of f after the MSB The parameter, f, can either be interpreted as an integer

frequency value or a fraction of the Nyquist rate (32,768 Hz) Use the MULT18X18 Virtex-II primitive to compute f * n Compute the sine wave for f periods and repeat

indefinitely One period: N = 1 / (f * TS) = 65,536 / f BAD!! f periods: Nf = 1 / TS = 65,536 GOOD!! n can now be derived from a free-running 16-bit counter

Page 4: Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October

Block Diagram

SINE_WAVE_OUT (16-bit)

DONE

Y

GO

Frequency

16-bit

System_Clock

100 MHz

16-BitCounter

Clock Divider

fout = fin / 2

Clock Divider

fout = fin / 1526

Sample_Clock

≈ 65,536 Hz

CORDIC_Clock

50 MHz

16-bit Multiplier

MULT18X18

Sine Wave Controller

CORDIC16-Bit Sequential Implementation

DA

TA

_IN

SAMPLE_PULSE

n

f

* SINE_WAVE_OUT is valid on Rising Edge of SAMPLE_PULSE

Page 5: Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October

Simulation with ModelSim & MATLABSimulate with frequency = 100 Hz for 100 ms

Save simulation data to a text fileRead data into MATLAB and plot

Page 6: Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October

Verification with Chipscope & MATLABCapture 8192 samples

Save captured data to a text fileRead data into MATLAB and plot

Page 7: Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October

Resource Utilization without Chipscope

Page 8: Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October

Resource Utilization with Chipscope

Page 9: Sine Wave Generation on the XUP Virtex-II Pro Development System Steven Wasson ECE 443 – Hardware Design in VHDL Assignment 3 – Sine Wave Generation October

Preview of Next Week’s Presentation

PC_BEEP_TONE_INDivider

Buttons[4:0] Switch Debouncer

Tone Select

Sine Wave Generator

Square Wave Generator

Frequency

AC97 CODEC

Switch[0]

DATA_IN

The goal is to hear the difference in sound between a “pure” tone (sine wave) and a heavily distorted tone (square wave).