simultaneous escape routing (ser) with application to...

Simultaneous Escape Routing (SER) withapplication to PCB

By

Kashif Sattar

(Master of Science in Information Technology, NUST 2011)

2011-NUST-TfrPhD-IT-63

A thesis submitted in partial fulfillment of the requirements for the degree of

Doctor of Philosophy

School of Electrical Engineering and Computer Science,

National University of Sciences and Technology (NUST),

Islamabad, Pakistan.

March 2017

Copyright c©2017, Kashif Sattar

Approval

It is certified that the contents and form of the thesis entitled

“Simultaneous Escape Routing (SER) with application to PCB”

submitted by Kashif Sattar have been found satisfactory for the

requirement of the doctor of philosophy degree.

Advisor: Dr. Anjum Naveed

Signature:

Date:

i

ii

Committee Member 1(Co-Advisor): Dr. Hassan Aqeel

Signature:

Date:

Committee Member 2: Dr. Arsalan Ahmad

Signature:

Date:

Committee Member 3: Dr. Taha Ali

Signature:

Date:

Committee Member 4 (External): Dr. Muhammad Junaid

Signature:

Date:

Abstract

With the advancement in technology, the use of compact ball grid ar-

ray (BGA) components is being increased in printed circuit boards

(PCB). The problem of routing pins from under the body of BGA,

towards component boundary is known as escape routing. It is of-

ten desirable to perform simultaneous escape routing (SER) to pro-

duce elegant PCB design. The task of SER is non-trivial, given the

small size of components and hundreds of pins arranged in random

order in each component that need ordered connectivity. This the-

sis proposes the use of optimization models with multiple routing

constraints that simultaneously solves the net ordering and net es-

cape problem. It is hypothesized that optimization model along with

all necessary constraints can route more number of nets, instead of

solving constraints one by one. In the first part of thesis, flow models

are proposed for different types of pin arrays for multiple capacities

and the routing problem is mapped to planar bipartite graph prob-

lem. In the second part, integer linear programming (ILP) based op-

iii

iv

timization model is proposed for single component ordered escape

routing to see the effect of planar routing, net ordering and system

constraints. In the third part, ILP optimization model for SER prob-

lem is proposed and finally an algorithm is proposed to find the valid

net order to reduce the complexity of SER problem. Both optimiza-

tion models prove that they can route maximum possible nets in their

respective scenarios, by considering the design rules. Comparative

analysis shows that the proposed optimization models perform bet-

ter than the existing routing algorithms in terms of number of nets

routed. Also the use of net ordering algorithm reduces the complex-

ity and converts the SER problem to simple ordered escape routing

problem.

Certificate of Originality

I hereby declare that this submission is my own work and to the

best of my knowledge it contains no materials previously published

or written by another person, nor material which to a substantial

extent has been accepted for the award of any degree or diploma

at National University of Sciences & Technology (NUST) School

of Electrical Engineering & Computer Science (SEECS) or at any

other educational institute, except where due acknowledgement has

been made in the thesis. Any contribution made to the research by

others, with whom I have worked at NUST SEECS or elsewhere, is

explicitly acknowledged in the thesis.

I also declare that the intellectual content of this thesis is the prod-

uct of my own work, except for the assistance from others in the

project’s design and conception or in style, presentation and linguis-

tics which has been acknowledged.

Author Name: Kashif Sattar

Signature:

v

Author’s Declaration

I Kashif Sattar hereby state that my PhD thesis titled ”Simulta-

neous Escape Routing (SER) with application to PCB” is my

own work and has not been submitted previously by me for taking

any degree from ”National University of Sciences and Technology

(NUST)” Or anywhere else in the country/world.

At any time if my statement is found to be incorrect even after my

Graduate the university has the right to withdraw my PhD degree.

Name of Student: Kashif Sattar

Date:

vi

Plagiarism Undertaking

I solemnly declare that research work presented in the thesis titled

”Simultaneous Escape Routing (SER) with application to PCB”

is solely my research work with no significant contribution from any

other person. Small contribution/help wherever taken has been duly

acknowledged and that complete thesis has been written by me.

I understand the zero tolerance policy of the HEC and ”National

University of Sciences and Technology (NUST)” towards plagia-

rism. Therefore I as an Author of the above titled thesis declare that

no portion of my thesis has been plagiarized and any material used

as reference is properly referred/cited.

I undertake that if I found guilty of any formal plagiarism in the

above titled thesis even after award of PhD degree, the University re-

serves the rights to withdraw/revoke my PhD degree and that HEC

and the University has the right to publish my name on the HEC

vii

viii

/University Website on which names of students are placed who sub-

mitted plagiarized thesis.

Student /Author Signature:

Name: Kashif Sattar

Certificate of Approval

This is to certify that the research work presented in this thesis, en-

titled “Simultaneous Escape Routing (SER) with application to

PCB” was conducted by Mr. Kashif Sattar under the supervision

of Dr. Anjum Naveed. No part of this thesis has been submitted

anywhere else for any other degree. This thesis is submitted to the

School of Electrical Engineering and Computer Science (SEECS),

in partial fulfillment of the requirements for the degree of Doctor of

Philosophy in Field of Information Technology from National Uni-

versity of Sciences and Technology (NUST).

Student Name: Kashif Sattar Signature:

Examination Committee:

a) External Examiner 1: Dr. Chun Tung Chou Signature:

Associate Professor

Department of CSE,

University of New South Wales (UNSW), Australia

ix

x

b) External Examiner 2: Dr. Mohsin Iftikhar Signature:

Senior Lecturer

Department of Computing,

Charles Sturt University (CSU), Australia

c) Internal Examiner: Dr. Hasan Mujtaba Signature:

Associate Professor

Department of CS,

FAST, Islamabad, Pakistan

Supervisor Name: Dr. Anjum Naveed Signature:

Dean/HOD: Signature:

Acknowledgment

Foremost I am very thankful to Almighty Allah who gave me the

courage and strength to pursue this research.

Pursuing a research is not an easy task and I am indeed grateful

to my supervisor Dr. Anjum Naveed and would like to express my

sincere gratitude for his continuous support during my PhD study

and for his patience, motivation, enthusiasm, and immense knowl-

edge. His guidance helped me in all phases of research and writing

of this thesis.

Besides my supervisor, I would like to thank my co-supervisor

Dr. Hassan Aqeel and rest of my thesis committee members: Dr. Ar-

salan Ahmad, Dr. Taha Ali and Dr. Muhammad Junaid for their con-

tinuous support, encouragement, insightful comments, hard ques-

tions, precious time and valuable feedback on my thesis. Also, i am

very thankful to Dr. Hassaan Khaliq, Dr. Adnan Khalid and Dr. Us-

man Ilyas for their continuous support, feed back and evaluation on

the preliminary version of this thesis. I would also like to extend my

xi

xii

heartfelt thanks to all of my external thesis evaluators: Dr. Hasan

Mujtaba Kayani, Dr. Chun Tung Chou and Dr. Mohsin Iftikhar. It

is not an easy task to review a thesis, and I am indebted for their

thoughtful and detailed comments.

I would particularly like to acknowledge Principal SEECS and

Dean Dr. Syed Muhammad Hassan Zaidi; Senior HoD Dr. Nadeem

Ahmed and Mr. Habeel Ahmad; PG Coordinator Dr. Asad Waqar

Malik. I would have not succeeded without their invaluable sup-

port. My sincere wishes are for the entire lab members, friends, col-

leagues and all others who always encouraged me for the successful

accomplishment of this thesis.

Most importantly, I would like to thank my family; my parents,

for unconditional support and instilling in me confidence and a drive

for pursuing my Ph.D. I dedicate this thesis to the memory of my

beloved father Mian Abdul Sattar, whose role in my life was, and

remains, immense.

Kashif Sattar

Contents

1 INTRODUCTION 1

1.1 Pin Array Types . . . . . . . . . . . . . . . . . . . . 2

1.2 PCB Routing . . . . . . . . . . . . . . . . . . . . . 2

1.3 Escape Routing . . . . . . . . . . . . . . . . . . . . 5

1.4 Simultaneous Escape Routing . . . . . . . . . . . . 6

1.4.1 SER Support for Area Routing . . . . . . . . 6

1.5 PCB Design Issues . . . . . . . . . . . . . . . . . . 8

1.6 Proposed Research Summary . . . . . . . . . . . . . 9

1.6.1 Research Contributions . . . . . . . . . . . . 10

1.7 Structure of the Thesis . . . . . . . . . . . . . . . . 12

2 Literature Review 13

2.1 Unordered Escape Routing . . . . . . . . . . . . . . 14

2.2 Ordered Escape Routing . . . . . . . . . . . . . . . 16


2.4 Net Ordering Algorithms . . . . . . . . . . . . . . . 24

xiii

CONTENTS xiv

2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . 25

3 Problem Formulation 27

3.1 Related Terminology . . . . . . . . . . . . . . . . . 27

3.2 Proposed Flow Models . . . . . . . . . . . . . . . . 30

3.2.1 Flow model for IPC=1 . . . . . . . . . . . . 34



3.3 SER as Planar Bipartite Graph Construction . . . . . 37

3.4 Flow model for Staggered Pin Arrays . . . . . . . . 40

3.4.1 Staggered Flow model for IPC=1 . . . . . . 42

3.4.2 Staggered Flow model for IPC=2 . . . . . . 43

3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . 47

4 Model based Ordered Escape Routing 48

4.1 Ordered Net Escape . . . . . . . . . . . . . . . . . . 48

4.2 Optimization Model . . . . . . . . . . . . . . . . . . 49

4.2.1 Connectivity Constraints . . . . . . . . . . . 52

4.2.2 Planar Graph Constraint . . . . . . . . . . . 54

4.2.3 Net Order Constraint . . . . . . . . . . . . . 54

4.2.4 System Constraint . . . . . . . . . . . . . . 55

4.2.5 Objective Function . . . . . . . . . . . . . . 56

4.3 Top Level Diagram for Escape Routing . . . . . . . 58

CONTENTS xv

4.4 Results and Discussion . . . . . . . . . . . . . . . . 59

4.4.1 Model Validation . . . . . . . . . . . . . . . 60

4.4.2 Experimental Results . . . . . . . . . . . . . 62

4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . 64

5 Constraint based model for SER 67

5.1 Escape Routing for Multiple Components . . . . . . 67

5.2 SER Model . . . . . . . . . . . . . . . . . . . . . . 70

5.2.1 Connectivity Constraints . . . . . . . . . . . 72

5.2.2 Planar Graph Constraint . . . . . . . . . . . 75

5.2.3 Net Order Constraint . . . . . . . . . . . . . 76

5.2.4 System Constraints . . . . . . . . . . . . . . 77

5.2.5 Objective Function . . . . . . . . . . . . . . 78

5.3 Evaluation . . . . . . . . . . . . . . . . . . . . . . . 80


5.3.2 Model Validation for Multiple Component . 84

5.3.3 Performance Analysis . . . . . . . . . . . . 85

5.3.4 Net Routing Analysis . . . . . . . . . . . . . 91

5.3.5 Routing Time Analysis . . . . . . . . . . . . 93

5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . 94

6 Mobility based Net Ordering 96

6.1 Proposed Algorithm for Net Ordering . . . . . . . . 96

CONTENTS xvi

6.1.1 Net Ordering Algorithm . . . . . . . . . . . 97

6.2 Optimization model for Ordered Escape . . . . . . . 109

6.3 Evaluation . . . . . . . . . . . . . . . . . . . . . . . 111

6.3.1 Algorithm Validation . . . . . . . . . . . . . 112


6.3.3 Performance Analysis . . . . . . . . . . . . 116

6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . 123

7 Conclusions and Future Work 125

7.1 Contributions . . . . . . . . . . . . . . . . . . . . . 126

7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . 128

List of Abbreviations

AMPL A Mathematical Programming Language

BGA Ball Grid Array

DPS Dynamic Pin Sequence

EON Elastic Optical Network

HUM Hybrid Unilateral Monotonic

IC Integrated Circuits

ILP Integer Linear Program

LP Linear Program

MBNO Mobility Based Net Ordering

NEOS Network Enabled Optimization Server

PCB Printed Circuit Board

RDNO Routability Driven Net Ordering

SER Simultaneous Escape Routing

SS Set Sequence

TLD Top Level Diagram

URDF Up Rear Down Front

xvii

List of Figures

1.1 Types of Pin Array . . . . . . . . . . . . . . . . . . 3

1.2 PCB Routing . . . . . . . . . . . . . . . . . . . . . 5


3.1 4-Pins BGA Tile . . . . . . . . . . . . . . . . . . . 30

3.2 Proposed Flow Model . . . . . . . . . . . . . . . . 32

3.3 Flow model for IPC=2 . . . . . . . . . . . . . . . . 36

3.4 Flow model for IPC=3 . . . . . . . . . . . . . . . . 36

3.5 Graph construction using flow model with IPC=1 . . 38

3.6 Planar Bipartite Graph Construction . . . . . . . . . 39

3.7 Staggered Pin Array Tile Model . . . . . . . . . . . 41

3.8 Staggered Pins Flow Model for IPC=1 . . . . . . . . 42

3.9 Staggered Pins Boundary Tiles for IPC=1 . . . . . . 44

3.10 Staggered Pins Flow Model for IPC=2 . . . . . . . . 45

3.11 Staggered Pins Boundary Tiles for IPC=2 . . . . . . 46

4.1 BGA Ordered Net Escape . . . . . . . . . . . . . . 49

xviii

LIST OF FIGURES xix

4.2 Flow Model Boundary Points . . . . . . . . . . . . . 50

4.3 TLD for finding Model Based Escape Routing . . . . 59

4.4 BGA Size 5x4 Routing for Ordered Escape . . . . . 61

4.5 System Constraint Validation . . . . . . . . . . . . . 63

4.6 BGA Size 17x6 Routing Solution . . . . . . . . . . 65

5.1 Net Ordering Significance . . . . . . . . . . . . . . 69

5.2 Pins position on BGA11 49 1.27 . . . . . . . . . . . 81

5.3 SER Routing with Proposed Model . . . . . . . . . . 83

5.4 System Constraints effect on Routing . . . . . . . . 83

5.5 SER Routing for Multiple Component . . . . . . . . 84

5.6 SER Routing with Proteus . . . . . . . . . . . . . . 86

5.7 Proteus SER Routing for different size BGA’s . . . . 87

5.8 Model SER Routing for different size BGA’s . . . . 88

5.9 Proteus SER Routing for 100 nets BGA’s . . . . . . 90

5.10 Model Comparison with Proteus . . . . . . . . . . . 92

6.1 BGA Component of Size 6x4 . . . . . . . . . . . . 100

6.2 Three step process to find initial net order . . . . . . 102

6.3 Finding the URDF mobility values . . . . . . . . . . 103

6.4 Finding the final net order . . . . . . . . . . . . . . 106

6.5 SER in BGA 24 1.5 . . . . . . . . . . . . . . . . . 113

6.6 Proteus incomplete routing . . . . . . . . . . . . . . 115

LIST OF FIGURES xx

6.7 Ordered escape routing with proposed model . . . . 116

6.8 Routability driven Net ordering [1] . . . . . . . . . 117

6.9 Proposed Mobility based Net ordering . . . . . . . . 118

6.10 RDNO routing for swap pin scenario . . . . . . . . 119

6.11 MBNO routing for swap pin scenario . . . . . . . . 119

6.12 RDNO routing for back boundary pin scenario . . . 120

6.13 MBNO partial routing for back boundary pin sce-

nario . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.14 MBNO complete routing for back boundary pin sce-

nario . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.15 MBNO results for varying size BGA′s scenario . . . 122

List of Tables

4.1 Experimental Results . . . . . . . . . . . . . . . . . 64

5.1 Experiment results and Net comparison with Proteus 92

5.2 Experiment results and Time comparison with Proteus 94

6.1 Validation Results and Comparison With Proteus . . 114

6.2 Experiment Results and Comparison with RDNO

Algorithm . . . . . . . . . . . . . . . . . . . . . . . 123

xxi

Chapter 1

INTRODUCTION

There is a constant demand for reducing the weight and size of elec-

tronic devices. Small light weight devices require sophisticated de-

sign and significantly advanced technologies for producing small

sized electronic circuit boards. Smaller size of electronic circuits

with more pin count [2, 3] is achieved using Integrated Circuits (ICs)

that are based on ultra small-scale integration and often contain en-

tire system on chip [4]. Majority of these circuits are BGA type

which usually are equiped with hundreds of connectivity pins [5–7].

Unlike conventional ICs where the pins exist at the boundary of the

IC, BGA components have the connectivity pins arranged as a grid

of small soldering balls under the entire body of IC. A single printed

circuit board (PCB) contains multiple ICs of BGA type. Presence

of BGA components on PCBs and the smaller size of PCBs signifi-

cantly increase the complexity of routing.

1

CHAPTER 1. INTRODUCTION 2

1.1 Pin Array Types

Mostly BGA components have grid array of balls/pins under the sur-

face in a square form, however in modern PCB designs we can see

BGA’s of different shapes called staggered pin arrays. These kind

of BGA’s have hexagonal arrays, rotated square arrays or diamond

shape arrays. As compare to grid pin arrays, staggered pin arrays in-

crease the number of pins in the same component area with the same

inter pin distance [8, 9]. The distance between two neighboring pins

is ∆d as shown in Figure 1.1. On one side, these modifications pro-

vides compactness in devices by increasing pin numbers but on the

other side it also increase complexity in the flow modeling and rout-

ing. Therefore, we need to find correct flow models for PCB routing

to get optimized solutions.

1.2 PCB Routing

Routing in PCBs is the problem of connecting the pins of the PCB

components that are required to be on the same signal/voltage level

for the circuit to be operational. A net is a conductive path/connection

between each pin pair that needs connectivity. A single PCB can

have multiple of tens to a few thousand nets, depending upon the

complexity of the electronic circuit. The pins of different compo-


Figure 1.1: Types of Pin Array


nents mounted over PCB are connected via nets, which actually are

conductive pathways. Ideally, the routing algorithm shall connect

all nets in such a way that the nets do not overlap (graph emerging

from nets shall be planar) and the nets shall be entirely contained

within the area of the PCB. In addition, the constraints like syn-

chronous signaling and signal-power separation are also considered.

Given the smaller sizes of PCBs, high density of components and

thousands of nets to be routed, a single layer is not sufficient for the

planar routing of all nets. Therefore, multiple routing layers are used

as shown in Figure 1.2. In this case, all nets being routed in a single

layer must result in a planar graph.

The problem of PCB routing is a specific instance of the generic

problem of constructing planar graph for a given set of nodes, which

is known as NP-Hard [10]. The complexity of the problem increases

because of BGA components. For BGA components, routing the

desired pins below the body to the component boundary is a chal-

lenge within itself. Therefore, PCB routing has been divided into

two parts: (i) Escape routing where pin to component boundary

route is established and (ii) Area routing where the net between the

component boundaries is established. The two parts are shown in

Figure 1.2.


Figure 1.2: PCB Routing

1.3 Escape Routing

Escape routing is a problem of escaping the connecting pins from

inside the component towards the boundary of the PCB components

(e.g. IC’s or BGA’s). Escape routing is of three types: 1)Un-ordered

esape routing which is relatively easy and we can escape as many

pins as possible in any order within the limits of capacity constraint,

2) Ordered escape routing which is relatively difficult and we have

to do escaping of connecting pins in a particular order to reduce the

complexity in the area routing and 3)Simultaneous escape routing

which is more complex due to connectivity of pins among multiple

components in a particular order and is a focus of our research.


1.4 Simultaneous Escape Routing

Given the high number of pins of BGA components, it is generally

desirable that pin escaping for multiple components is done simul-

taneously in a specific order. Ordered escaping of pins for multiple

components is known as simultaneous escape routing (SER) [11–

17]. Figure 1.3 shows an example instance of SER. If a pin uses top

most boundary point in one component for escape then the same pin

number of other component also uses the top most boundary point

for escape to maintain the ordered escaping. In this way the area

routing becomes very simple and it is just a matter of connectivity

of straight wires without any crossing to maintain planarity. Com-

plexity of escape routing further increases when different types of

nets are considered, types include signal, ground/power nets. It also

is worth mentioning that consideration of these net types is generally

desires and is effective in reducing cross cable interference.

1.4.1 SER Support for Area Routing

SER is an escaping of nets from muliple components in a particular

order. It means that the sequence of escaped nets from one compo-

nent is the same to the sequence of escape nets of second component

facing escape side to each other. This reduces the complexity of


Figure 1.3: Simultaneous Escape Routing

area routing because it is just to connect the escaped nets of multiple

component over the PCB. The area routing connections are already

planar so no need to use extra wire for planarity. We can implement

the length matching constraint very easily. Also this helps in PCB

designing by reducing the layers and crossovers in area routing.

There exist many automated tools for PCB designing but none re-

ally is efficient for providing complete route-ability, specifically in

a situation when there are many complex components in PCB. This

gap is currently filled by experts as they manually optimize PCB

routing and this surely is more time consuming and costly as well.

This work focused on developing optimization model for simulta-

neous escape routing with an objective to produce optimized routes

with minimum human intervention.


1.5 PCB Design Issues

PCB is the most commonly used method for assembling electronic

components. It may contains multiple copper layers and each layer

may contain the power, ground and signal wires/nets. PCB design-

ing is the most important step for the performance of the system.

PCB effects, that create problem to the precision of circuit perfor-

mance can be divided in two types: 1) those who affect DC or static

operations and 2) those who affect AC or dynamic operations, par-

ticularly at higher frequencies [18]. Grounding is another problem-

atic area in PCB designs of analog as well as mixed signal. Ground

wires and signal wires can degrade the performance of each other.

This may be due to common currents, externally created signal cou-

pling or ground wire higher IR drops. Therefore, one of the impor-

tant constraint is to keep these wires apart from each other on the

PCBs. To avoid crosstalk, digital and analog signals that creates in-

terference with each other, must be physically separated. Practically

this is a difficult task in modern PCB designs. High and low level

analog signals must be separately placed on PCB. It is also important

that we place ground wires between signal wires to reduce coupling

effect (Faraday shield) between the two signal wires. We need to ad-

dress all these issues of PCB designing while connecting pins, in the


escape routing as well as area routing. Here one thing is important

that if we do escape routing by keeping these issues in mind, then

area routing becomes simplified because all issues already addressed

in escape routing.

1.6 Proposed Research Summary

The need of this thesis is to provide the PCB designers, a better

routing techniques for pin array type of BGA components. These

techniques provide escape routing to the connecting pins, within

the space available between pins under the PCB components. Since

most of the existing techniques reduce the search space for time sav-

ing or do not met all design constraints automatically, hence do not

provide optimal solution and still people are doing manual routing

for the left over nets. This task is very tedious and time taking. Due

to complexity and importance the focus of this research is simulta-

neous escape routing (SER), which is the need of today’s state of

art PCB designs. We believe that if there exist a valid routing solu-

tion then it should be solved automatically with the PCB routers in

a single iteration by considering all the design rules.

We propose an optimization model for SER, which can be used

to identify the net escape order for a given pair of components as


well as establish the escape routes for the nets within multiple com-

ponents. With the nets of two components escaped in order, the area

routing becomes a trivial task if single side escaping is used. The

model has the objective of maximizing the number of nets that can

be connected for a given PCB and component placement. The ob-

jective is constrained by planar graph of connected nets, path length,

power signal integrity and ordered escaping constraints. Compara-

tive evaluation shows that the proposed optimization model can con-

nect more number of nets in all tested examples when compared

with the well-known commercial tools. The proposed optimization

model is a contribution towards enhancing the capabilities of PCB

designers and can be integrated into commercial software for use.

1.6.1 Research Contributions

This thesis investigates the effectiveness of the proposed hypothesis

through a four step study. Following are the salient contributions of

this thesis.

• In the first step we proposed flow models for grid pin array

as well as for staggered pin array type of BGA components.

We show that separate edges are required in order to achieve

planarity in PCB designs.


• In the second step we proposed ILP optimization model for or-

dered escape routing, which helps us in finding the ordered net

escape from a single component. The results are very encour-

aging for the use of optimization theoretic approach for such

problems.

• In the third step we proposed optimization model for the rel-

atively complex problem of simultaneous escape routing. The

results show that the proposed model for multiple component

is very helpful in finding the more number of planar routes as

compare to other tools. By using this model area routing be-

comes very easy (just connect straight wires) and we get op-

timized routing solution in single iteration, which satisfies all

the design rules.

• Finally we proposed an algorithm to find the optimal net order.

This algorithm helps us by converting the complex problem of

simultaneous escape routing into simple and single component

ordered escape problem. Ultimately with this reduction, now

we can easily solve the routing problem with the help of opti-

mization theoretic approach proposed in second step with little

modification.


1.7 Structure of the Thesis

This thesis focuses on solutions for simultaneous escape routing.

Chapter 2 reviews the prior state of the art work in the domain of

escape routing, simultaneous escape routing and net ordering algo-

rithms. Chapter 3 presents the terminologies used in the models

and discuss the proposed flow models. Chapter 4 presents the op-

timization model to solve ordered escape routing problem. Chap-

ter 5 presents the proposed optimization model for simultaneous es-

cape routing problem for multiple components. Chapter 6 presents

the proposed net ordering algorithm for reducing the problem com-

plexity. Also we presents the modified escape routing optimization

model to solve the routing problem. Chapter 7 concludes the thesis

with possible future directions to the proposed thesis.

Chapter 2

Literature Review

Routing of nets on PCB, is divided into two main categories, one is

area and the other is escape routing [12]. The objective of escape

routing is to establish the planar routes by escaping the nets from

pins to the component boundary in an ordered or unordered way,

based on constraints on available capacity between adjacent pins.

With the escape routes established, the problem of PCB routing is

reduced to conventional PCB routing problem of area routing [19,

20]. Whereas to meet the objective of area routing, we establish

routes between the boundaries of components by using constraints

like matching net length [21], timing and signal integrity.

Escape routing is of three types [22, 23]. (i) Unordered escape

routing where pins of a single component are routed to the compo-

nent boundary without considering any specific escape order of the

pins [24–32]. (ii) Ordered escape routing where pins of one com-

13

CHAPTER 2. LITERATURE REVIEW 14

ponent are escaped in a pre-defined order [33]. Bus escape [34] is

an example of this type of routing, and (iii) Simultaneous escape

routing where pins of two components are escaped simultaneously,

ensuring that the nets of both components are escaped in same or-

der. There are many applications for each type in PCB routing and

package industry. Focus of this thesis is SER and we present related

literature in more detail in the next subsection.

2.1 Unordered Escape Routing

Lei et al. [29] considers escape routing and pin assignment as two

very closely related problems. The focus of their research is to do

routing during pin assignment as a co-design for a single component.

They also consider two important factors, which mainly affect the

design of modern PCB, one is differential pair and the other is blind

via. The simultaneous consideration of these two factors improved

the results by using their proposed co-design method. However the

results can be improved further by considering the other important

system constraint i.e. power and signal integrity with a little over-

head of cost in terms of time. Also proposed work does not consider

the ordered escape routing which may creates problem to the area

routing.


In some PCB designs, it is desirable to meet the length matching

constraint. Previously researchers used to minimize the clock period

by using the technique of clock insertion (unit delay elements) [35–

37]. However, practically it is not possible that these elements exist

in all PCB’s. Therefore, this technique cannot applied to the today’s

state of the art PCB designs. In order to satisfy the high performance

designs, length matching constraint has to be considered.

Yao et al. [30] present a practical control-layer routing flow (PA-

COR) considering the critical length-matching constraint. One of

the features of PACOR is to improve routability by formulating the

problem of simultaneous escape routing. Authors claim 100% rout-

ing completion rate, however this research work is specifically for

microfluidic biochips and only considers length matching constraint

by constructing steiner trees. In PCB design, a heuristic algorithm

is proposed by Zhang et al. [31] for disordered pins to obtain length

matching routing. This algorithm assigns layers to the pins based

on longest common subsequence. The algorithm works well for less

number of pins. However, for more number of pins the results are

not good due to the limitation of C-flip and R-flip and the interaction

between wires.


2.2 Ordered Escape Routing

The nets which need to be escaped together forms a bus and the es-

caping has to be done in the form of bus (all nets together) from one

component to the other in a particular order [34, 38–42]. Lot of re-

search work has been done on bus escaping so far, however none of

them is able to provide complete routing solution using all necessary

constraints. Routing as a Bus Escape, also referred as maximum dis-

joint subset problem has been proposed by Kong et al. [34]. It solves

escape routing in a particular order for a singe component. This so-

lution is capable of considering multiple nets simultaneously instead

of single net. Bus refers to a group of nets; hence this approach tries

to route bus towards nearest boundary with an objective to maximize

the number of buses. This approach surely reduces the routing com-

plexity but is unfeasible for optimizing routes for ordered escape.

Fixed escape boundary points techniques are proposed in [43, 44]

for individual nets, they tried to reduce routing complexity by se-

lecting subset of graph but are unable to consider all possible paths.

With the increase in design complexity, some times it is possible to

move backward to look alternate paths for allowing more number of

routable nets. In addition to that, we need to apply some important

constraint manually after getting the routing solution, which is very


difficult to manage. Authors in [45] proposed ordered escape rout-

ing technique for mapping routing problem to optimization problem

based on Boolean satisfy-ability. But this approach is unstable in

situation of large problems due to the fact that its time complexity is

quite high.

Various researchers worked on optimization of unordered escape

routing but most of these solutions are based on very limited set of

constraints. They only considered a subset of constraints including

planarity and capacity and also rely mostly on heuristics. These

limited set of constraints do not emulate realistic routing problems.

Most of solutions in existing literature ignored potential constraints

like power, signal separation and signal integrity.

2.3 Simultaneous Escape Routing

The initial work on SER considered unordered escaping of one com-

ponent followed by ordered escape routing of second component to

match the order of first component pins. However, this approach

leaves a number of unconnected nets. The first well known research

on SER was carried out by Ozdal et al. [12]. The authors used graph

based approach to find maximal escape nets. This approach per-

forms well if the pins of both components are closely aligned to each


other. However, fixed escape patterns used in this approach cannot

solve complex SER problems. This work extended by the same au-

thors Ozdal et al. [13] and proposed randomized algorithm for large

scale problems. However, the assumption that each net must be es-

caped monotonically in one direction, limits the optimized results

and its applications. As we discussed earlier that with the increase

in design complexity, some times it is possible to move backward to

look alternate paths for allowing more number of routable nets. Oz-

dal et al. [14] used congestion driven router for routing pattern gen-

eration; however, the graph of escape patterns becomes complicated

for large scale SER problems and also they did not consider system

constraints while making escape patterns. Liu et al. [46] proposed

hybrid unilateral monotonic routing algorithm (HUM). It basically

considers each point on the routing graph, as an intermediate point.

The path finally established between source node and destination

node consists of two sub paths created by unilateral monotonic rout-

ing. Monotonic routing can be horizontal or vertical, therefore being

a hybrid approach, this algorithm has four possible combinations for

path routing. Although the time complexity is less in this proposed

algorithm however it does not consider capacity, net ordering and

system constraints which we have discussed earlier and thus cannot

be used for SER problem.


B-Escape algorithm for SER proposed by Luo et al. [15]. The

algorithm focus on greedy approach of boundary routing. In this al-

gorithm one net is routed at a time and the routing area is reduced by

excluding the area having already used by the recently routed net.

This algorithm performs well when compared with Allegro PCB

router [15]; however, it uses heuristic approach based on dynamic

net ordering and is more costly in terms of time to find a suitable net

order. In addition to that it also takes longer paths, which reduces

the remaining space for escaping of nets and consumes more wire

length. Also after placing each net we are reducing the escaping

space for rest of the nets which limits the optimal solution.

Simultaneous Pin Escape [17] is a flow model based approach.

Authors show that their approach guarantees planar routing if planar

graph construction for the specific instance is possible. The exis-

tence of solution can be judged by the relation between maximum

flow and number of escape pins of the BGA component [17, 24]. If

maximum flow is greater or equal to the escape pins then this ap-

proach must provide planar solution; however, exact value of max-

imum flow is not known and we cannot ensure no net crossing, for

higher inter pin capacities.

SER for components having fixed pins is relatively difficult as

compare to pin assignment and routing problems. Zhang et al. [47]


proposed a method of parallel routing using virtual boundary for

fixed pins by partitioning the entire area into many sub areas. The

algorithm does routing of wires for each sub area separately. Al-

though this proposed algorithm reduces the wire length, however it

increases the cost by adding additional layers to avoid net crossings.

We can reduce the complexity of the design by avoiding unnecessary

layers and can use relatively longer paths.

Another heuristic algorithm proposed for SER for multiple com-

ponents is to find possible solutions by using partial order candi-

dates [48]. For the escaping of nets the authors use dynamic graph

for routing and also consider multiple buses simultaneously. This

proposed algorithm provides planar escape to the pins of different

buses. However, the division of entire grid in four parts reduces the

solution set and the algorithm cannot gives us optimal result partic-

ularly in a dense PCBs.

Another way to solve such problem is by making decision trees,

which is a support tool for decision making by creating tree like

graphs as a predictive model. It is a good tool in choosing best

action among several possible actions. In our problem we can use it

for creating all possible paths between each source destination pair

of pins and then for choosing the best path. However sometimes it

is very difficult to comprehend decision trees particularly when the


trees are bigger in size [49].

Recently researchers are using constraint based optimization mod-

els [50–56] in many applications, from high crowd density facilities

[57] to mobile cloud computing [58], to solve such kind of problems.

These modelers find optimal result by exploring all possible areas

where solution can exist by considering all the given constraints. In

research work proposed by [51], the author divided his work in two

parts. In first part, he discussed the heuristic algorithm for traveling

sales man problem and showed that how optimization models help

us in finding optimal path length for the real time problems. Subse-

quently he used his proposed optimization model for PCB process-

ing time calculation, which showed the efficient use of his proposed

algorithm to find the optimal path length. This reduction in path

length ultimately reduces the PCB’s processing time. The challenge

of tradeoffs among multiple solutions is often faced by managers,

analysts and engineers to get the required results [54]. Optimization

models help us in choosing the best solution to achieve a particular

objective. In the book, authors explain that we can map many engi-

neering problems as an optimization problems. Some of these prob-

lems include, process synthesis analysis and design, transportation,

mobile cloud computing, complex networks, logistics, scheduling,

robotics, fuzzy models, optimal set of parameters for controllers,


emergency logistics, optical network routing, ground water manage-

ment, PCB process time and routing, etc. Due to large search space,

it is not an easy task to find a solution in an acceptable time but

optimization models help us to do so.

In future, elastic optical network (EON) is a very effective solu-

tion for optical transport networks. In [53], authors proposed ILP

optimization model for EON’s and concluded that proposed work

saves the spectrum significantly. In mobile cloud computing, we

shift the application processing which needs high computation re-

sources to the mobile cloud data centers. Due to wireless data trans-

mission medium, we have certain link capacities and therefore we

need some techniques to achieve optimal cloud performance. Ahmed

et al. [58] proposed mobile application framework using optimiza-

tion strategies to achieve optimal performance in mobile cloud com-

puting. This work facilitates in achieving effective design, deploy-

ment and application migration. Katagiri et al. [56] proposed a

model for PCB route optimization and also mapped the problem as

pickup and delivery traveling salesman problem (PDTSP). This al-

gorithm improves the cost and time, however works only for optimal

routing path inspection and cannot be used straight away for escape

routing problems. Hence optimization modeling is being used in

almost every field of life for better performance and also some re-


searchers used it for different types of PCB routing. As we know

that for efficient PCB routing, we need to consider planarity, ca-

pacity, net ordering and system constraints. However none of the

research work discussed so far, considered all these constraints in a

single optimization model to get optimized results in a single itera-

tion of PCB routing.

PCB contains multiple copper layers and each layer may contain

the power, ground and signal wires. PCB designing is the most im-

portant step for the performance of the system. Lot of research has

been done so far on the PCB design issues [59–63]. All research

work shows that PCB effects create problem to the precision of cir-

cuit performance. Ground wires and signal wires can degrade the

performance of each other. High and low level analog signals must

be separately placed on PCB. To avoid crosstalk, digital and analog

signals that creates interference with each other, must be physically

separated. Practically this is a difficult task in modern PCB designs.

However we can solve this problem by adding as a power and sig-

nal integrity constraint in the optimization model to get PCB design

having better performance.


2.4 Net Ordering Algorithms

To find the solution of SER is a time consuming process, particu-

larly for larger problems. We can reduce this time if we know the

escape net order in advance. Escape net order is a sequence of nets

to escape from the boundary of a component. This prior net order-

ing information converts the problem of SER into ordered escape

routing of a single component.

B-Escape is a routing algorithm proposed by Luo et al. [15].

This algorithm uses dynamic net ordering approach and consumes

significant time to find a suitable net order and in reordering of nets

again and again.

Rout-ability Driven Net Order proposed by Yan et al. [1] is a

multi-step approach. A subsequent step uses global and detailed

routing technique under the constraints of planar routing and escape

capacity. This approach improves the computation time by 54.1% as

compare to Kong et al. [17]. The drawback is that the second step is

totally dependent on the output of first step i.e. net ordering. It does

not explore all possible paths and may lead to sub-optimal results

in complex problem instances. Furthermore, it is not possible to

integrate important constraints like signal and power integrity and

length matching.


For High Speed Boards, Chin et al. [64] proposed routing for es-

caped boundary pins. This algorithm uses dynamic pin sequence

(DPS) in finding static net ordering. Another work proposed by

Kumtong et al. [65] is based on set sequence (SS) technique. While

these algorithms are good in utilizing routing space and adapting

requirements for shape and wire length, their focus is on boundary

pin routing and are not suitable for BGA type of PCB components

which need escaping from inside the components; their use can also

be more challenging, particularly in case of SER.

2.5 Summary

Existing Literature has been reviewed in this chapter. It is noted that

most of the research on SER is based on heuristic approaches with

basic constraints on capacity and planar graph construction. In this

research, we consider optimization theoretic approach. Instead of

solving the problem in parts to get sub-optimal solution, this opti-

mization approach is expected to produce optimal results. This ap-

proach not only considers capacity and planarity but also considers

constraint of power-signal integrity, net route length and net escape

order altogether, to solve the SER problem at the cost of higher com-

putational time. However, with high speed computing units, cluster-


ing of computational resources to perform complex computational

tasks and using net ordering techniques, the drawback can easily be

overcome.

Chapter 3

Problem Formulation

First of all, in this chapter we discuss the related terminology used

in our models. After that we discuss the proposed flow models for

escape routing. These models help the connecting pins to escape

through BGA component towards the boundary. Subsequently, we

discuss that how the SER problem can be considered as planar bipar-

tite graph construction problem. In the last section, we discuss our

proposed flow models for staggered pin arrays to meet the modern

PCB designs.

3.1 Related Terminology

Escape Boundary: A virtual line is assumed to exist outside the ac-

tual boundary of component on the side (sides) that are to be used for

escape routing of nets, for the pair of components. This virtual line

27

CHAPTER 3. PROBLEM FORMULATION 28

is known as escape boundary. Where, escape routing is the problem

of finding the routes from connectivity pins of the component to the

points on escape boundary.

Inter-pin Escape Capacity: Inter-pin escape capacity is the num-

ber of wires (nets) passing through, between two consecutive pins

of the BGA component. There are three types of capacities i.e. hori-

zontal, vertical and diagonal between adjacent pins as shown in Fig-

ure 3.1. We can notate these capacities as IPC(hcap, vcap, dcap). This

capacity is constrained by inter-pin gap, wire thickness necessary for

error free signal propagation and gap between adjacent wires that is

necessary to avoid cross talk or coupling effect. In this research

work, for the sake of simplicity, we considers all inter-pin capaci-

ties equal to ’1’, but it can be extendable for any generic scenario.

Therefore, IPC = 1 implies that IPC = (1, 1, x). Where x is the dcap

and it varies according to the geometrical shape of the flow model

and can be calculated by the equation, x = 2.(hcap − 1) + 1.

Intermediate Points: Intermediate points are created between the

adjacent pins for flow modeling of BGA type of components. For

a set of four adjacent pins, 1, 5, 13 intermediate points can exist,

depending upon inter-pin capacity of IPC = 1, 2, 3 and is shown in

Figure 3.2(a), 3.3(a) and 3.4(a) respectively. Adjacent intermediate

points can be connected at later stage to form links and wires that


can be used for routing the nets.

Escape Boundary Points: These points exist on the escape bound-

ary. There are two types of escape boundary points. (i) Adjacent to

every connectivity pin of the component that is on the component

boundary (towards escape boundary) and needs to be connected. (ii)

Escape boundary points equal to the inter-pin capacity may be cre-

ated at equal distance on the escape boundary between every pair of

component boundary pins. For IPC = 1, it is shown in Figure 3.5(b).

Potential Routing Edges: There are five types of potential edges:

(i) Edges between Intermediate points and adjacent connectivity pins

that need routing, (ii) Edges between adjacent intermediate points,

(iii) Edges between intermediate points and adjacent escape bound-

ary points, (iv) Edges between component boundary pins and escape

boundary points and (v) Edges between the boundary points of both

components. The first four edges are highlighted with (i), (ii), (iii)

and (iv) in the left component as shown in Figure 3.5(b), where as

the last type of edges are shown in Figure 3.5(c). All edges can

be diagonal, horizontal or vertical except the intermediate to escape

boundary point edges and boundary pin to escape boundary point

edges that can either be horizontal or vertical, depending upon the

escape side. These edges become part of the wires that are used in

routing. The edges of type (ii) and (v) are bidirectional whereas all


Figure 3.1: 4-Pins BGA Tile

other are unidirectional.

3.2 Proposed Flow Models

Many researchers used network flow model for escape routing [24,

26, 66–69]. Fang et al. [66] and Yan et al. [24] used square tile

model for network flow. Fang et al. [68] used triangular tile model

for staggered pin arrays. Shi et al. [70] proposed hexagonal tile

model for staggered pin arrays. Ho et al. [26] proposed an algorithm

for escape routing based on hexagonal and triangle staggered pin ar-

ray. All the proposed work is only for unordered escape routing

problem and cannot ensure planar routing. Since they are modeling

only one edge for higher inter pin capacities, therefore we cannot

judge the crossings of nets and also cannot applied directly to rela-


tively difficult problems of ordered escape routing and simultaneous

escape routing.

In our proposed flow model we consider separate edge for all

higher inter pin capacities. If there is a capacity of two nets that can

pass through between two adjacent pins, then we use two separate

edges for each of them. This helps the mathematical models for get-

ting planar routing without crossing each other. We discussed flow

models for both type of pin arrays i.e. grid pin array and staggered

pin array for multiple inter pin capacities.

Initially for grid pin array, we take a BGA tile as shown in Figure

3.1, which actually comprising of four adjacent pins as a subset of

BGA grid. For this sample tile we propose working flow model,

which can easily be draw out for the entire BGA grid for complete

escape routing solution. As described in Figure 3.1, there are three

types of inter-pin capacities within a tile and these include Vertical

(V -cap), Horizontal (H-cap) and Diagonal (D-cap).

We assume an intermediate point preferably in the centre of tile.

Actually it is effective in establishing escape path by utilizing avail-

able edge set. Multiple points can be taken for higher capacity inside

a tile. As shown in Figure 3.2 (a), the edges between two interme-

diate points of adjacent tiles are bidirectional however we have also

unidirectional edges, which are from connectivity pin to one of the


Figure 3.2: Proposed Flow Model


adjacent intermediate point of BGA grid. In a situation where we

have only one intermediate point in a tile, we have all the Vertical

(V -cap), Horizontal (H-cap) and Diagonal (D-cap), equals to one.

It can be observed in Figure 3.2 (b) and Figure 3.2 (c), that interme-

diate point is either a pass through point for another net of the grid

or it can be directly connected with the connecting pin.

With reference to earlier discussion, number of intermediate points

can be increased for more D-cap but we need to make sure that ca-

ble length and cable separation constraints are satisfied. As shown

in 3.2 (d), it is important to maintain planarity as it is critical for

avoiding net crossing, value of D-cap can be raised to 2, keeping

the same value for other capabilities like H-cap ← V -cap ← 1.

This change is quite productive as shown in Figure 3.2 (e) and Fig-

ure 3.2 (f). We can see that now it is possible for two wires to cross

single tile.

Apart from intermediate points, we also considers boundary points

for net escape. These points are usually outside component’s bound-

ary for connecting two adjacent points. But in a situation when al-

ready there is a boundary connectivity pin towards the escape side

of the BGA component then boundary point serve as an extra direct

point for net escape.

In order to formulate flow model for planar routing we need inter-


mediate points ′I ′ (according to the capacity IPC) and edges between

them in a tile, such that the net (flow) using these edges must be dis-

joint and must not cross each other. Single flow model for higher

capacities sometimes cannot ensure ‘no net crossings’ (planarity)

or sometimes overburden with many intermediate points and edges.

We propose separate flow models for different IPC values, with ex-

act required number of intermediate points. We show that how 1,

5 and 13 intermediate points are exactly required for planar routing

for IPC = 1, 2 and 3 respectively.

3.2.1 Flow model for IPC=1

In this scenario, as we discussed already, we are assuming that only

one wire (net) is allowed to pass between the two orthogonal pins

and diagonal pins of a tile. In Figure 3.2(a), we can see the flow

model for IPC = 1. In the tile centre, there is an intermediate

point, highlighted with dotted circle. For IPC = 1, this can be used

only once either by any other neighboring intermediate point or by

connecting pin of the tile as we can see in Figure 3.2(b) and Fig-

ure 3.2(c) respectively. Dotted lines (edges) show the possible path,

which can be used by any net to complete the escape routing towards

the boundary of the BGA component. All the edges which connects

connecting pin and intermediate points are uni-directional and rest


of the edges are bi-directional.

Similarly if we want to increase the diagonal capacity to make

IPC = (1, 1, 2), then the central intermediate point of a tile is re-

placed by four intermediate points as shown in Figure 3.2(d). The

connectivity pin can be connected to any one out of two possible

intermediate points. Figure 3.2(e) shows that how two nets can pass

through now, with the increase in diagonal capacity whereas in Fig-

ure 3.2(f), we shows that how one ‘connecting pin net’ and other

‘passing through net’ use the flow model.


In this scenario, we show that two edges (nets) can pass through be-

tween the two horizontal and vertical pins of a tile. The flow model

for IPC = 2, is shown in Figure 3.3(a). There are five intermediate

points in the center of the tile, highlighted with dotted circle that en-

sures ‘no net crossings’. By geometrical layout, possibly three nets

can pass through diagonal space (i.e. dcap or x = 3) and this turns

the inter-pin capacity to IPC = (2, 2, 3), as shown in Figure 3.3(b).


The last scenario, shows that three nets can pass through now be-

tween the two horizontal and vertical pins of a tile. The flow model


Figure 3.3: Flow model for IPC=2

Figure 3.4: Flow model for IPC=3

for IPC = 3, is shown in Figure 3.4(a). There are now thirteen

intermediate points in the tile to ensure ‘no net crossings’. By ge-

ometrical layout, now it is possible by five nets to pass through at

maximum, through diagonal space (i.e. dcap or x = 5) in this case

and the inter-pin capacity notation now turns to IPC = (3, 3, 5) as

shown in Figure 3.4(b).


3.3 SER as Planar Bipartite Graph Construction

Problem of SER can be considered as planar bipartite graph con-

struction problem. We demonstrate it with a simple example having

two BGA components of grid size 5x4 as shown in Figure 3.5(a).

We also assume here that its single side escape highlighted with a

dashed line boundary. Out of 20 pins, only 5 pins are connectiv-

ity pins in each component. We draw, intermediate points, escape

boundary points for boundary connectivity pin and escape bound-

ary points according to the flow model with IPC = 1, as shown in

Figure 3.5(b). Also, we draw all unidirectional and bidirectional

potential edges and removes unnecessary actual pins, as shown in

Figure 3.5(c). This clearly shows that pins requiring planar con-

nectivity and the possible connections represent the graph. Hence

the problem is planer graph connectivity problem for which we are

going to present optimization model.

We define escape routing problem as: Given set V of connectiv-

ity pins that need routing, set U of escape boundary points such that

|U| ≥ |V |, set I of intermediate points and set E ′ of potential routing

edges, construct the bipartite graph G(V , U, E) where:

(i) E is set of paths comprising of i ∈ I and e ∈ E ′.

(ii) ∀i ∈ I and e ∈ E ′, i and e belong to only one path p ∈ E at the


1 2

4 5 4

1

3

2

1 2

4 5

5

1

3

2

Actual PinsIntermediate Points Escape Boundary

C 1 C 2

1 2

4 5

5

1

3

2

3 5

3

4

BoundaryConnectivity Pin

3

4

(a)

(i)Boundary Pointsfor boundary pin

(ii)EscapeBoundary Points

(b)

ComponentEscape Side

(c)

(iv)

(i) (ii) (iii)

Connectivity Pin

Boundary Edges

Figure 3.5: Graph construction using flow model with IPC=1


Figure 3.6: Planar Bipartite Graph Construction

most.

(iii) ∀v ∈ V , Deg(v ) = 1 and ∀u ∈ U, Deg(u) ≤ 1.

We map all the pins, points and potential edges of Figure 3.5(c)

into vertices and edges of planar bipartite graph as shown in Fig-

ure. 3.6(a). Set V1&V2 consists of connectivity pins of compo-

nent 1 and 2 respectively. Similarly, set U1&U2 consists of escape

boundary points of each component. The edges between the vertices


of set U1&U2 are single bidirectional edges, whereas the edges be-

tween the vertices of V1&U1 and V2&U2 consist of paths from a

connectivity pin vertices of set V1 (V2) to boundary pin vertices of

set U1 (U2). These paths must be disjoint with each other (i.e no

intermediate vertex or potential edge is common when compare to

any other path), to ensure planarity. Planar and maximal net rout-

ing requires proper net ordering (sequence of escaping) as shown in

Figure 3.6(b).

3.4 Flow model for Staggered Pin Arrays

We have discussed so far only about square grid pin arrays and pro-

posed flow model for that kind of BGA’s. However as we know that

modern designs adopt pin arrays of different shapes called staggered

pin arrays. These BGA’s provides high pin density as compare to

grid pin array for the same component area. On the other side if we

keep the number of pins same in staggered pin arrays, then we can

get more inter pin capacity due to its structure. Routing is relatively

difficult for this kind of components due to its irregular shape.

We extend our flow models for staggered pin arrays with minor

modifications to fulfill the requirement of modern PCB designs. We

take a staggered pin array tile as shown in Figure 3.7, which actu-


Figure 3.7: Staggered Pin Array Tile Model

ally comprising of four adjacent pins as a subset of BGA grid. For

this sample tile we propose working flow model, which can easily

be draw out for the entire BGA grid for complete escape routing so-

lution. As described in Figure 3.7, there are three types of inter-pin

capacities within a tile and these include Vertical (V -cap), Horizon-

tal (H-cap) and Boundary (B-cap). In our proposed flow model,

we are using four intermediate points in a tile, for B-cap=1 and five

intermediate points for B-cap=2 respectively. If we consider rotated

square type staggered pin array, then with B-cap=1, we can achieve

H-cap=V -cap=2. Also with B-cap=2, we can achieve H-cap=V -

cap=3. It is not necessary that H-cap and V -cap are same, it can

vary with the geometrical shape of the staggered pin array.


Figure 3.8: Staggered Pins Flow Model for IPC=1

3.4.1 Staggered Flow model for IPC=1

In this scenario, as we discussed already, we are assuming that only

one edge (net) can pass through between the two adjacent pins. The

flow model for IPC = 1 is shown in Figure 3.8(a). Here in the

tile center, we have four intermediate point in a square form, high-

lighted with dotted circle. These points can be used either by any

other neighboring intermediate point or by connecting pin of the tile

as shown in Figure 3.8(b) and Figure 3.8(c) respectively. Dotted

lines (edges) show the possible path, which can be used by any net

to complete the escape routing towards the boundary of the BGA

component. All the incident edges on intermediate points coming

from connectivity pins are uni-directional and all other edges are bi-

directional. We can see that with IPC = 1, two nets can easily pass

through the vertical capacity or horizontal capacity.


We also discuss here about the left over tiles in a staggered pin

array component. One possibility is the corner tile which consist of

only two pins and is modeled as shown in Figure 3.9(a). This tile

appears if a row having less pins is at the top and/or at bottom of the

component. There is only one intermediate point in this tile, which

connects the incoming net from other neighboring tile to the bound-

ary point. The edge from intermediate point to the boundary point

is uni-directional. The other possibility is the half tiles on all the

four sides of a component. These tiles are modeled as shown in Fig-

ure 3.9(b). There are two intermediate points in this tile. These two

intermediate points and the boundary pins, all are connected with a

unidirectional link with boundary points. This tile can also act as a

transient for other nets or the connecting pins of this tile can escape

directly as shown in Figure 3.9(c), Figure 3.9(d) and Figure 3.9(e)

respectively.

3.4.2 Staggered Flow model for IPC=2

In this scenario, we are assuming that two edge can pass through be-

tween the two adjacent pins. The flow model for IPC = 2 is shown in

Figure 3.10(a). In the tile center, there are five intermediate point in

a rotated square form, highlighted with dotted circle. These points

can be used either by any other neighboring intermediate point or


Figure 3.9: Staggered Pins Boundary Tiles for IPC=1


Figure 3.10: Staggered Pins Flow Model for IPC=2

by connecting pin of the tile as described in Figure 3.10(b) and Fig-

ure 3.10(c) respectively. Dotted lines (edges) show the possible path,

which can be used by any net to complete the escape routing towards

the boundary of the BGA component. We can see that with IPC = 2,

three nets can easily pass through the vertical capacity or horizontal

capacity.

We also discuss here about the left over tiles in a staggered pin

array component. One possibility is the corner tile which consists

of only two pins and is modeled as shown in Figure 3.11(a). This

tile appears if a row having less pins is at the top and/or at bottom

of the component. There are only two intermediate point in this tile,

which connects the incoming net from other neighboring tile to the

boundary point. The edges from intermediate points to the boundary


Figure 3.11: Staggered Pins Boundary Tiles for IPC=2

points are uni-directional. The other possibility is the half tiles on

all the four sides of a component. These tiles are modeled as shown

in Figure 3.11(b). There are four intermediate points in this tile. The

three intermediate points on the boundary side and boundary pins,

all are connected with a unidirectional link with boundary points.

This tile can also act as a transient for other nets or the connect-

ing pins of this tile can escape directly as shown in Figure 3.11(c),

Figure 3.11(d) and Figure 3.11(e) respectively.


3.5 Summary

This research has proposed the flow models based on inter-pin ca-

pacity by introducing edges equivalent to capacity. These flow mod-

els provide help in creating input data files for optimization model.

Finally the optimization model solves PCB routing problem based

on given constraints. These BGA components include traditional

grid pin arrays as well as modern staggered pin arrays. In addition

to that we explained that the for a planar routing solution the prob-

lem of SER can be mapped as planar bipartite construction problem.

In the following chapter, we use the proposed flow models, initially

for single component ordered escape routing.

Chapter 4

Model based Ordered Escape

Routing

In this chapter, we discuss the proposed optimization model for pla-

nar ordered escape routing for single component. We also discuss,

how system constraints affects the routing. Subsequently, we vali-

date the model and compare the results with commercially available

software.

4.1 Ordered Net Escape

The BGA component pins generally consists of two dimensional ar-

ray/grid and for PCB to be operational few of them are required to

have connectivity with pins in other components. These pins are

referred to as connecting pins. In ordered escape routing, these con-

48

CHAPTER 4. MODEL BASED ORDERED ESCAPE ROUTING 49

Figure 4.1: BGA Ordered Net Escape

nectivity pins needs to be escaped from below the BGA towards the

boundary of the component as shown in Figure 4.1.

Apart from intermediate points as discussed in Figure 3.2, this

work also considers boundary points for net escape as explained in

Figure 4.2 (b). These points are usually outside component’s bound-

ary for connecting two adjacent points. But in a situation as shown

in Figure 4.2 (a), when already there is a boundary connectivity pin

towards the escape side of the BGA component then that boundary

pin can escape directly by using the extra boundary point as pre-

scribed in Figure 4.2 (b).

4.2 Optimization Model

In this section, we discuss our proposed Integer linear program based

optimization model. As an input we provide graph G(V , E) to this


Figure 4.2: Flow Model Boundary Points

model, where V is a set of vertices. This set consists of boundary

points, intermediate points and connecting pins. All the possible

edges are in set E and the nets use these edges for escape towards

the boundary of the component. Based on the given constraints,

the proposed model returns another graph G′(V ′, E ′) , which shows

the maximum number of possible escaped nets, with G′(V ′, E ′) ≤

G(V , E), which also implies that V ′ ≤ V and E ′ ≤ E . We formu-

late a linear programming model that can perform ordered escape

routing of nets from a component. These are the sets used as input

in the proposed model:

N= Set of required nets.

I = All intermediate and boundary points.

V = All intermediate points, boundary points, connecting pins and

external boundary points.

BE= All edges at the component’s boundary (Between component


boundary points and external boundary points).

E = All possible edges of a BGA.

NE [eij ]= All neighboring edges of the edge eij ∈ BE .

It is possible that we have net pairs that are not allowed to escape

together from the component boundary neighboring points. These

pairs are expressed with a set P in the model. This set helps the

’power and signal integrity’ constraint of the model for best routing

results without any performance error.

The proposed model has a decision variable X(na,eij ), which is a

Boolean variable for all nets na ∈ N and for all edges eij ∈ E . If

the solver assign true or 1 to the decision variable then we are using

that edge eij for a particular net na for escape routing, otherwise the

solver assigns false or zero value to the decision variable.

X(na,eij ) =

1 if eij edge is being used for net na

0 if eij is not being used for na

By using this optimization model, routing is constrained by the

constraints of planar graph, connectivity, net order and system con-

straint. Each constraint is important in terms of achieving error free

routing designs. Each constraint is explained in detail as below.


4.2.1 Connectivity Constraints

The constraints included in this set ensure that the connecting pin

escapes from the component boundary by following only one path

(consists subset of edges from E) from connecting pin to boundary

point and also there is no disconnection of the net along that routing

path.

Activation of Single Path: Connecting pins have mutiple neigh-

bors that includes other pins and intermediate points. Since connect-

ing pin cannot be connected to any neighboring non connecting pin,

therefore we have to consider only the neighbors which are interme-

diate points. As we know that by looking at the graph each connect-

ing pin can be connecting to multiple intermediate points, however

we have to choose only one edge among them to maintain a single

path. We also know that these edges are unidirectional from pin to

intermediate point, therefore the constraint does not allow routing

for those nets which have no complete planar path from connecting

pin to escape boundary point.

∑eij∈E&i=a

X(na,eij ) ≤ 1 ∀na ∈ N

End-to-end Route Completion: The proposed model also ensures

by using end-to-end route completion constraint that all the interme-


diate nodes of a graph for a particular net path, if one incoming edge

is active then one outgoing edge must be active to ensure continuity

of the flow or net routing. We can also ensure with this constraint

that the flow only initiates from the connectivity pin and ends on

boundary points.

∑eij∈E

X(na,eij ) =∑ejk∈E

X(na,ejk )

∀na ∈ N,∀j ∈ I

This constraint work well to achieve basic routing, however it

does not make sure that any edge is being used only once. Therefore

we need to add an additional constraint which avoids reverse flow

for a single net and edge reusability for different nets. The following

constraint make sure that the construction of routing path does not

stop at intermediate node and no edge is selected twice for any net.

X(na,eij ) + X(na,eji ) ≤ 1

∀na ∈ N,∀eij , eji ∈ E


4.2.2 Planar Graph Constraint

The constraints discussed so far provide routing of nets from con-

necting pins to the escape boundary points if exists, however these

routing paths may intersect with each other at intermediate nodes of

graph. This intersection of nets, violates the planarity. Introducing

a simple constraint can eliminate this condition. The following con-

straint ensures the one time usage of any point/node of a graph for

any net. ∑eij∈E

∑na∈N

X(na,eij ) ≤ 1, ∀j ∈ I

4.2.3 Net Order Constraint

In ordered escape routing, a particular net order has to be followed

for escaping pins. To get ordered routing, temporarily we assign

ascending number to each net. With the help of following constraint

we get routing solution in that order and then we assign back the

original number to each net. Since we have assumption here that

escaping of all the nets is in ascending order, therefore it is obvious

that the (a + 1)th net must be greater than ath net number. If we have

two external boundary points named as ‘j’and ‘l’with a relation such

that j < l , then ath net escapes at external boundary point ‘j’and

(a + 1)th net escapes at external boundary point ‘l’, to ensure given


net order. Here the equality sign in the model equation is necessary

because the BE edge can be assigned to only one net and for rest of

the nets the decision variable for this edge must be zero. Therefore

by doing this we are avoiding, the decision variables having zero

values. ∑eij∈BE

X(na,eij ).j ≤∑

ekl∈BE

X(na+1,ekl ).l , ∀na ∈ N

4.2.4 System Constraint

There is possibility of adding many other system constraints to a

model. It is highly recommended that control and data signal wires

should not be close or adjacent to power wires or nets specifically in

a situation when wires have less width. Such a setting of adjacency

of these wires results in considerable signal errors. We added this

constraint in our proposed model keeping this as a potential exam-

ple.

Power Signal Integrity Constraint

This constraint makes sure that adjacent boundary points do not al-

low escaping to specific pair of nets and a safe distance is maintained

so that error free signals can be transferred. Following constraint

ensures that one of the net from a pair is not active on any adjacent


boundary edges of neighbors in a situation when other net of the

same pair is already active on boundary edge.

X(na,eij ) +∑

ekl∈NE [eij ]

X(nb,ekl ) ≤ 1, ∀(na, nb) ∈ P,∀eij ∈ BE

4.2.5 Objective Function

To maximize the ordered escape routing in terms of number of pla-

nar routable nets in a specific order of given nets. We can achieve

this objective with the following mathematical expression:

max .∑na∈N

∑eaj∈E

X(na,eaj )


The following set of equations 4.1 - 4.7, completely represents the

optimization model.

max .∑na∈N

∑eaj∈E

X(na,eaj )

(4.1)

subject to: ∑eij∈E & i=a

X(na,eij ) ≤ 1 ∀na ∈ N

(4.2)∑eij∈E


X(na,ejk ) ∀na ∈ N,∀j ∈ I

(4.3)

X(na,eij ) + X(na,eji ) ≤ 1 ∀na ∈ N,∀eij , eji ∈ E

(4.4)∑eij∈E

∑na∈N

X(na,eij ) ≤ 1 ∀j ∈ I

(4.5)∑eij∈BE

X(na,eij ).j ≤∑

ekl∈BE

X(na+1,ekl ).l ∀na ∈ N

(4.6)

X(na,eij ) +∑

ekl∈NE [eij ]

X(nb,ekl ) ≤ 1, ∀(na, nb) ∈ P,∀eij ∈ BE

(4.7)

In general, optimization models are NP-hard problems. In a the-


ory of computational complexity, these problems are equivalent to

the NP hardest problem. In other words, we have a NP-hard prob-

lem ’A’, when all the problems ’B’ in NP are reducible to ’A’ in a

polynomial time. However, for an instance of a specific problem and

by using the available optimization solvers, the optimization models

gives us optimal results. The next section explains the use of solvers

which are commercially available and provides help in solving the

example instances using our proposed optimization model.

4.3 Top Level Diagram for Escape Routing

This section explains the working of optimization model based es-

cape routing process using our proposed model. There are four main

sub processes to get the correct escape routing solution. These are

”Generate Data File”, ”AMPL Model File”, ”Gurobi ILP Solver”

and ”Escaped Routing” as shown in Figure 4.3. In the first sub

process, initially we get the requirement of routing which includes,

component, pins, nets, ordering, capacity and system constraints.

With the help of this information we generate data file by us-

ing our C++ code, specifically written to calculate all vertices and

edges. In the second sub process, we implement our proposed ILP

optimization model in AMPL language and generate the model file.


Figure 4.3: TLD for finding Model Based Escape Routing

In next sub process we feed these two files to Gurobi solver which

solves and gives us the optimal net routing solution in a given order.

Finally in the last sub process, we draw the escape routing solution

based on the active/inactive edges provided by the solver, from con-

nectivity pins to the boundary pins.

4.4 Results and Discussion

This section validates our Integer Linear Program (ILP) based opti-

mization model proposed in Section-4.2 on some example instances,

for performance evaluation and correctness of the model.


4.4.1 Model Validation

This section verifies that desired routing is achieved for given set

of constraints including planar graph construction, route-ability and

net ordering constraints. We perform model testing for this purpose

and use BGA component as an example. This component has grid

pin array size of 5x4 and has total of 20 pins as shown in Figure

4.4(a). For this testing, we randomly select 5 connecting pins for the

purpose of escape routing. We also assume IPcap = 1 and permit

escape routing from a single side of the component for the purpose

of better understanding.

As shown in Figure 4.4(b), we draw boundary points, interme-

diate points and possible edges that connect these points. A graph

G(V , E) is obtained as shown in Figure 4.4(c) by removing all un-

necessary pins. We provide this graph to the proposed optimization

model and after resolving all constraints we receive another graph

G′(V ′, E ′) as a result output and solution to escape routing prob-

lem as shown in Figure 4.4(d). This resulting graph clearly confirms

that proposed model performs ordered escape routing efficiently for

PCB components based on BGA. There are maximum 5 boundary

points in the BGA and model chooses to route all five nets by es-

caping in a given order and the chosen sequence is 1, 2, 3, 4 and 5.

It is evident that this solution ensures planarity by not selecting any


Figure 4.4: BGA Size 5x4 Routing for Ordered Escape


vertex or edge twice. This example performs comprehensive valida-

tion of proposed optimization model and ensures all constraints of

connectivity, net order and planar graph.

We also consider the same example for system constraints vali-

dation. The proposed model takes set P (net 4 and 5) as a pair of

nets that cannot be escaped together. We maintain all the constraints

as described previously but now we additionally enable constraint

related to power and signal integrity and execute the model again.

Proposed model is again able to route all nets ensuring planarity but

this time the order of nets is different as shown in Figure 4.5 and the

order in solution graph is now 5, 2, 3, 4 and 1. This solution also

ensures that model is able to satisfy system constraints be keeping

net 4 away from net 5 and hence convincingly performs validation

of system constraints.

4.4.2 Experimental Results

Proposed flow model is implemented in C++ . This program gener-

ates data files which are then fed to optimization model as an input.

We implement the optimization model in AMPL language and used

AMPL modeler [71] to get the optimization modeling results. The

used modeler is available on NEOS server [72]. We test proposed

optimization model on six different data sets with variation in both,


Figure 4.5: System Constraint Validation

BGA components and net routing requirements. We make compari-

son between our results and those obtained from Proteus auto router

by Lab center Electronics Ltds, as shown in Table 4.1. It is quite ev-

ident from the results that routing of all nets is not possible by using

Proteus and the degree of un-routed nets is directly proportional to

complexity of routing problem. However the proposed model con-

vincingly provides 100% routing for all the experiments. We now

discuss one sample test in details, as shown in Figure 4.6. The BGA

size is 17x6 and there are 18 number of nets that requires routing.

The output of Proteus is shown in Figure 4.6(a) , whereas our pro-

posed model output is shown in Figure 4.6(b). It is impressive that

proposed model is able to route all 18 nets where as in comparison


Table 4.1: Experimental Results

Array Escape Proteus (Routing) Proposed Model

RxC Pins Nets %age Nets %age

Exp-1 5x4 05 05 100% 05 100%

Exp-2 7x7 07 06 85% 07 100%

Exp-3 10x7 12 10 83% 12 100%

Exp-4 17x6 18 15 83% 18 100%

Exp-5 50x32 56 45 80% 56 100%

Exp-6 86x50 100 78 78% 100 100%

we can see that the Proteus only able to route 15 nets in required

order.

4.5 Summary

The research work discussed in this chapter, proposes the use of

mathematical modeling for BGA components, to solve routing prob-

lem for ordered escape. We proposed a mathematical model for pla-

nar graph and validated the model with the results obtained by com-

mercially available software.The results shows better performance

of our proposed model, in terms of number of routed nets. The or-

dered escape of nets provides support to the designers for better and

easy area routing with less routing wire. In the following chapter, we


Figure 4.6: BGA Size 17x6 Routing Solution


will use this optimization theoretic approach for relatively complex

problem i.e. simultaneous escape routing.

Chapter 5

Constraint based model for SER

In this chapter, we first propose a constraint based optimization model

for SER, that can construct maximum routes for the nets under given

set of constraints. Finally we validate the model and compare the

results with the commercially available software for performance

evaluation.

5.1 Escape Routing for Multiple Components

SER is escape routing of two components simultaneously such that

the respective pins of both components are escaped in the same or-

der. Effectively, the SER comprises of two sub-problems that need

to be solved simultaneously. First problem is to decide upon the

order in which the nets are to be escaped. The second problem

is escape routing of the two components in the desired order. It

67

CHAPTER 5. CONSTRAINT BASED MODEL FOR SER 68

is possible to define the escape order before escape routing is per-

formed. This significantly reduces the complexity; however, the so-

lution space is also significantly reduced, resulting in fewer con-

nected nets. We present a simple example that shows the signifi-

cance of net ordering.

Consider Figure 5.1(a) which shows a simple 5x4 grid BGA com-

ponents that requires 4 pin connectivity using single side escaping.

Suppose that the component-1 necessitates the order of escaping

1,2,3,4, as shown in the Figure 5.1(a). It is obvious to see that even

for this trivial example, the escaping in desired order is not possible

for component-2 for all its pins. However, if the order of escaping

is changed to 1,2,4,3, the nets can be escaped easily as shown in

Figure 5.1(b). Hence the problem of identifying a feasible order is

non-trivial and requires to be simultaneously solved with the escape

routing problem.

We now propose the optimization model that takes as input the

set V of connectivity pins, set U of boundary points, set I of inter-

mediate points and set E ′ of edges for the components and returns a

planar connected graph with maximum possible nets of the compo-

nents connected under given set of constraints. For any of the two

given components Ci and Cj , the optimization model simultaneously

decides on the net order for escaping and constructs the two bipartite


Figure 5.1: Net Ordering Significance


graphs Gi(Vi , Ui , E ′i ) and Gj(Vj , Uj , E ′j ).

5.2 SER Model

We formulate a linear programming model that can perform simulta-

neous routing for multiple components. Let set C = {c1, c2, ..., cn}

be the set of n BGA components for which the routing is to be per-

formed. As explained in the previous section, let Vci be the set of

connectivity pins of component ci that need routing. Let Ici and Bci

be the sets of intermediate points and boundary points respectively

of component ci . The following are the input sets which are being

used in the model:

Set Vall = ∪ci (Vci ∪ Ici ∪ Bci ), it includes all the connectivity pins,

intermediate and boundary points of all components.

Set Iall = ∪ci (Ici ∪ Bci ), it includes all the intermediate and boundary

points of all components.

Set E ′all = ∪ci E′ci

, the set of all possible edges of all components.

The edges are identified by their end points as eij where i , j ∈ Vall .

Note that the edges between pins to intermediate points and interme-

diate points to escape boundary points are unidirectional while all

other edges are bidirectional. Unidirectional edges make modeling

easy but do not affect the routing outcome. The inter pin capacity is


maintained with the number of intermediate points/edges according

to the flow model, which satisfies the capacity constraint. If there

are only 2 edges between adjacent pins then maximum 2 nets can

pass through.

Set BEall = ∪ci BEci , It includes all the edges at escape boundary of

all components.

Set N = {(vi , vj)|vi ∈ Vci , vj ∈ Vcj}, The net list (pin pairs that need

to be connected)

Set NE [eij ] be the set of neighboring edges, where eij ∈ BECi . Each

set consists of all the neighboring boundary edges of eij ∈ BECi .

In addition, we provide the set T to the model which have nets that

have limit on the route length. The set consists of the ordered pair

where first element is the net while second element is the length

threshold given in terms of number of edges.

It is possible that we have net pairs that are not allowed to escape

together from the component boundary neighboring points. These

pairs are expressed with a set P in the model. This set helps the

’power and signal integrity’ constraint of the model for best routing

results without any performance error. Here, we are considering this

constraint only at the boundary edges but it can be extended within

the component by making sets of neighbors for all the edges. The

output of the model is number of nets connected and the edges used


to create the routes for the nets.

The proposed model has a decision variable X(rab,eij ), which is a

Boolean variable for all nets rab ∈ N and for all edges eij ∈ E ′all . If


that edge eij for a particular net rab for escape routing, otherwise the


X(rab,eij ) =

1 if eij edge is being used for net rab

0 otherwise


constraints of planar graph, connectivity, net order and system con-


routing designs. and is explained in detail as below.

5.2.1 Connectivity Constraints

The constraints included in this set ensure that the connecting pin

escapes from the component boundary by following only one path

(consists subset of edges from E ′all) from connecting pin to boundary

point and also there is no disconnection of the net along that routing

path.

Activation of Single Path: Connecting pins have mutiple neigh-

bors that includes other pins and intermediate points. Since connect-

ing pin cannot be connected to any neighboring non connecting pin,


therefore we have to consider only the neighbors which are interme-

diate points. As we know that by looking at the graph each connect-

ing pin can be connected to multiple intermediate points, however

we have to choose only one edge among them to maintain a single

path. We also know that these edges are unidirectional from pin to

intermediate point, therefore the constraint does not allow routing

for those nets which have no complete planar path from connecting

pin to escape boundary point.

∑eij∈E ′

all& i=(a OR b)

X(rab,eij ) ≤ 1 ∀rab ∈ N

Net Ends Match Constraint: The two ends of every net should

have the same connectivity state. This means that either both con-

nectivity pins of a net should use one incident edge for the particular

net or both pins should not use any net. This constraint combined

with the subsequent constraints ensures that there are no incomplete

routes. Either the complete route exists between pins of the net or

no edge is used for that net. The constraint equation shows that for

each net rab (where ′a′ is the connectivity pin in component 1 and

′b′ is the connectivity pin in component 2), the sum of decision vari-

able for the incident edges on pin ′a′ must be equal to the sum of

decision variable for the incident edges on pin ′b′. This constraint

makes sure that either the net connects both pins by completing the


path or never started from both pins.∑eij∈E ′

all&(i=a)

X(rab,eij ) =∑

epq∈E ′all&(p=b)

X(rab,epq)

∀rab ∈ N

Route Completion Constraints: Above two constraints deal with

the connectivity pins. If the routing of net is initiated for one pin, the

other pin also needs to be connected. Furthermore, the constraints

ensure that only one route is initiated for every net. This constraint

deals with the intermediate and boundary points. The following two

constraints ensures that a route is completed if it is initiated at the

connectivity pins. These constraints also ensure that there is no un-

wanted and unconnected route that does not belong to any net.

The proposed model also ensures by using end-to-end route route

completion constraint that all the intermediate nodes of a graph for a

particular net path, if one incoming edge is active then one outgoing

edge must be active to ensure continuity of the flow or net routing.

We can also ensure with this constraint that the flow only initiates

from the connectivity pin and ends on the connectivity pin of other


component. ∑eij∈E ′

all

X(rab,eij ) =∑

ejk∈E ′all

X(rab,ejk )

∀rab ∈ N,∀j ∈ Iall

The above constraint work well to achieve basic routing, however

it does not make sure that any edge is being used only once. There-

fore we need to add an additional constraint which avoids reverse

flow for a single net and edge reusability for different nets. The

following constraint make sure that the construction of routing path

does not stop at intermediate node and no edge is selected twice for

any net.

X(rab,eij ) + X(rab,eji ) ≤ 1

∀rab ∈ N,∀eij , eji ∈ E ′all

5.2.2 Planar Graph Constraint

The constraints discussed so far provide routing of nets from con-

necting pins to the escape boundary points if exists, however these

routing paths may intersect with each other at intermediate nodes of

graph. This intersection of nets, violates the planarity. Introducing


a simple constraint can eliminate this condition. The following con-

straint ensures the one time usage of any point/node of a graph for

any net. ∑rab∈N

∑eij∈E ′

all

X(rab,eij ) ≤ 1, ∀j ∈ Iall

5.2.3 Net Order Constraint

In simultaneous escape routing, all escaped nets between any two

components must be in the same order to ensure SER. Actually, for

a net rab, if pin ‘a’ belongs to component Ci and pin ‘b’ belongs

to component Cj , then all the escaped nets between Ci and Cj must

be in the same order. This constraint also act as a global routing

(to find the escape boundary points for nets) which forces the other

constraints to find detailed routing (how to reach at the boundary

points from connectivity pins) in that order to find maximal rout-

ing solution. Based on global routing, the model tries to find the

path from connectivity pin to the escape boundary point by using

the route completion constraints. Other constraints help in finding


single path and planarity during detailed routing.

X(rab,eij ) = X(rab,eji )

∀rab ∈ N,∀eij , eji ∈ BEall

5.2.4 System Constraints

There is possibility of adding many other system constraints to a

model. For example, the model can be constrained to use equal

length paths for a set of nets to ensure the synchronous signaling.

Similarly, It is highly recommended that control and data signal

wires should not be close or adjacent to power wires or nets specif-

ically in a situation when wires have less width. Such a setting of

adjacency of these wires results in considerable signal errors. We

add these two constraints in our proposed model keeping this as a

potential example.

Path Length Constraint: Path lengths of certain nets can be re-

stricted to a threshold value, allowing timing budget requirements to

be incorporated. Following constraint limits the path length of the

nets given in a set to the respective threshold.∑eij∈E ′

all

X(rab,eij ) ≤ trab, ∀rab ∈ T

Power Signal Integrity Constraint: This constraint makes sure that

adjacent boundary points do not allow escaping to specific pair of


nets and a safe distance is maintained so that error free signals can

be transferred. Following constraint ensures that one of the net from

a pair is not active on any adjacent boundary edges of neighbors

in a situation when other net of the same pair is already active on

boundary edge.

X(rab,eij ) +∑

ekl∈NE [eij ]

X(rcd ,ekl ) ≤ 1

∀(rab, rcd ) ∈ P,∀eij ∈ BEall

5.2.5 Objective Function

To maximize the simultaneous escape routing in terms of number

of planar routable nets in a specific order of given nets. Here it

is noted that objective is not maximizing the links, so it does not

choose longest paths. However in order to increase the number of

routable nets the model tries to select shorter paths. If the model

selects longer path by utilizing more edges then the remaining edges

reduce the chance to maximize the routable nets. We can achieve

this objective with the following mathematical expression:

max .∑

rab∈N

∑eij∈E ′

all

X(rab,eij )

The following set of equations 5.1 - 5.9, completely represents


the optimization model..

max .∑

rab∈N

∑eij∈E ′

all

X(rab,eij ) (5.1)

subject to:∑eij∈E ′

all&i=(a OR b)

X(rab,eij ) ≤ 1 ∀rab ∈ N (5.2)

∑eij∈E ′

all&(i=a)

X(rab,eij ) =∑

epq∈E ′all&(p=b)

X(rab,epq)

∀rab ∈ N (5.3)∑eij∈E ′

all

X(rab,eij ) =∑

ejk∈E ′all

X(rab,ejk )

∀rab ∈ N,∀j ∈ Iall (5.4)

X(rab,eij ) + X(rab,eji ) ≤ 1

∀rab ∈ N,∀eij , eji ∈ E ′all (5.5)∑rab∈N

∑eij∈E ′

all

X(rab,eij ) ≤ 1 ∀j ∈ Iall (5.6)

X(rab,eij ) = X(rab,eji )

∀rab ∈ N,∀eij , eji ∈ BEall (5.7)∑eij∈E ′

all

X(rab,eij ) ≤ trab ∀rab ∈ T (5.8)

X(rab,eij ) +∑

ekl∈NE [eij ]

X(rcd ,ekl ) <= 1

∀(rab, rcd ) ∈ P,∀eij ∈ BEall (5.9)


As we already discussed that generally optimization models are NP-

hard problems. However, for an instance of a specific problem and

by using the available optimization solvers, the optimization mod-

els gives us optimal results. The next section explains that how we

use the solver which is commercially available and provides help

in solving and comparing the results for the example instances by

using our proposed optimization model.

5.3 Evaluation

In this section, the proposed optimization model discussed in sec-

tion 5.2 has been validated. Subsequently, we present the perfor-

mance comparison of the proposed model and Proteus auto router by

Labcenter Electronics Ltd. We implement the optimization model

in AMPL language and used AMPL modeler [71] to get the opti-

mization modeling results. The used modeler is available on NEOS

server [72]. The comparison with the state of the art research work

was not possible because of the unavailability of the examples be-

ing tested. The authors have contacted multiple researchers in the

domain; however, none of the examples presented in the literature

were made available, primarily because of proprietary designs.


Figure 5.2: Pins position on BGA11 49 1.27


This section verifies that desired routing is achieved for given set of

constraints including planar graph construction, route-ability and net

ordering constraints. We perform model testing for this purpose and

use BGA component available in Proteus as BGA11 49 1.27. This

BGA has 49 pins based on 7x7 grid pin array, as shown in Figure 5.2.

We took two components and randomly selected 6 pins from each

component to be connected to form 6 nets. We also assumed here

that IPC = 1 in all examples and single side escaping is permitted

for both components.

This resulting graph clearly confirms that proposed model per-

forms efficient SER for PCB components based on BGA, as shown

in Figure 5.3. There are maximum 6 boundary points in the BGA

and model chooses to route all six nets by escaping in the same order

and the chosen sequence is 1, 2, 3, 4 5 and 6. Escape order of all the


pins of component 1 is same as the escape order of all the pins of

component 2, which ensures net ordering. It is also evident that this

solution ensures planarity by not selecting any vertex or edge twice.

This example performs comprehensive validation of proposed opti-

mization model and ensures all constraints of connectivity, net order

and planar graph.

System Constraints Validation: We also consider the same exam-

ple for system constraints validation. The proposed model takes set

P (net 1 and 2) as a pair of nets that cannot be escaped together. We

maintain all the constraints as described previously but now we ad-

ditionally enable constraint related to power and signal integrity and

execute the model again. Proposed model is again able to route all

nets ensuring planarity but this time the order of nets is different as

shown in Figure 5.4 and the order in solution graph is now 1,3,2,4,5

and 6. This solution also ensures that model is able to satisfy system

constraints be keeping net 1 away from net 2 and hence convincingly

performs validation of system constraints.

Similarly, we validate the ‘Path length’ constraint. The path length

of net 3 is 11 edges, as shown in Figure 5.3. In component 1 we

have 7 edges from pin to boundary point, whereas in component

2 we have 3 edges and one edge is between both boundary points.

We restrict the length of net 3 to a threshold value of 9 (shortest


Figure 5.3: SER Routing with Proposed Model

Figure 5.4: System Constraints effect on Routing

path) edges. Therefore by using the proposed model we are not only

getting the optimized shorter routes but also can control the wire

length, which is not possible as compare to other algorithms such as

boundary escape routing [15]. Now we disable the ‘power and sig-

nal integrity’ constraint and enable the ‘Path length’ constraint, to

see the effect of this constraint on the original routing output. Once

again, the model not only route net 3 on its shortest path with path

length of 9 edges, but also routes all other nets as usual in a planar

way, as shown in Figure 5.4.


Figure 5.5: SER Routing for Multiple Component

5.3.2 Model Validation for Multiple Component

This section validates the model for 3 components. Component 1

and 2 have 20 pins grid array of size 5x4, whereas component 3

has 16 pins grid array of size 4x4. We randomly selected 6 pins

from component 1. Out of 6 connectivity pins, first 3 pins needs

to be connected with the 3 randomly selected pins of component

3, whereas rest of the 3 pins needs to be connected with randomly

selected pins of component 2 as shown in Figure 5.5. All the 3

components need to be connected to form 6 nets. We also assumed

here that IPC = 1 in this example. The figure clearly shows that our

proposed model provides routing for all the nets in their respective

components without violating any constraint.


Hence, our proposed model proves that it achieves the required

SER solution with the help of planarity constraint, routability con-

straint, net order constraint and system constraint. In the following

section, we compare the performance of the model against Proteus.

5.3.3 Performance Analysis

The performance comparison in this section is based on a single

metric of number of route-able nets keeping in view the fact that the

design constraints are met. Although the execution time is also im-

portant, as long as all nets can be routed within an acceptable time,

the significance of execution time decreases. We have considered

three different examples for the purpose of evaluation. Each exam-

ple highlights different aspect of the proposed model as explained in

respective section.

BGA11 49 1.27 Example

To validate we compare the results obtained by our proposed ana-

lytical model with the results obtained by Proteus Software. Proteus

placed 5/6 nets even if we run interactively for 10 times for stable

results. The routing of nets is shown in Figure5.6. It could not pro-

vide routing for 5th net. With Proteus, the only solution here to route

this net, is manual routing which is very difficult specially when we


Figure 5.6: SER Routing with Proteus

do routing for large number of pins and nets. Whereas our model,

with the input of the same example, results having routing of all 6/6

nets as shown in Figure 5.3.

BGA 18x9 17x6 Example

We test our SER optimization model on a two different grid size

components. One BGA has 18x9 grid size while other has 17x6 grid

size, as shown in Figure 5.7. In this example we test two things

i) model testing for different size BGA’s and ii) model testing for

boundary connectivity pins. We randomly selected 2 boundary con-

nectivity pins and 16 others from each component. Left compo-

nent has 17 inter pin capacity boundary points and 2 boundary con-

nectivity pins, results in 19 escape boundary points in total. Right

component has 16 inter pin capacity boundary points and 2 bound-

ary connectivity pins, results in 18 escape boundary points in total.

Therefore for SER, there are 18 maximum possible nets that can be


Figure 5.7: Proteus SER Routing for different size BGA’s

escaped, simultaneously from both components.

We compare the results obtained by our proposed model with the

results obtained by Proteus. In first run Proteus placed 12/18 nets

and after 10 runs it placed 15/18 nets as shown in Figure 5.7. It

could not provide routing for 11th,12th and 16th net. We can see

once again that manual routing is very difficult in this case. How-

ever when we run our model for this example, we get results having

routing of all 18/18 nets as shown in Figure 5.8.


Figure 5.8: Model SER Routing for different size BGA’s


BGA 98x49 86x50 Example

We also validate our SER optimization model on a relatively bigger

example which requires connectivity of 100 nets. Among two differ-

ent grid size components, one BGA has 98x49 grid size while other

has 86x50 grid size, as shown in Figure 5.9. In this example we

test two things i) what is the behavior of model when we have large

number of nets ii) difference of routed nets with increased complex-

ity. We randomly selected 100 pins from each component. Left

component has 97 inter pin capacity boundary points and 19 bound-

ary connectivity pins, results in 116 escape boundary points in total.

Right component has 85 inter pin capacity boundary points and 15

boundary connectivity pins, results in 100 escape boundary points

in total. Therefore for SER, there are 100 maximum possible nets

that can be escaped, simultaneously from both components.

We compare the results obtained by our proposed model with the

results obtained by Proteus. In first run Proteus placed 65/100 nets

as shown in Figure 5.9. Even after 10 runs (stable results) it placed

82/100 nets. It could not provide routing for 18 nets and the manual

routing is almost impossible in this case. However, when we run this

example with our model, again we get results having routing of all

100/100 nets with the same escaping net order and without violating

any design rule.


Figure 5.9: Proteus SER Routing for 100 nets BGA’s


5.3.4 Net Routing Analysis

In this section, we compare the results achieved by different experi-

ments discussed so far. Our proposed optimization model performed

100% routing in all the five examples as shown in Table 5.1, how-

ever Proteus could not route all nets in experiments 2, 3, 4 and 5.

Here one thing is important that manual routing of even for a single

left behind net is very difficult and needs lots of time in rearranging

of all the nets once again. It is also clear from the results that as the

grid size increases or number of required nets increases, the routing

performance by Proteus decreases and left behind nets increases as

shown in Figure 5.10. However proposed model outperforms in all

cases even for larger examples. The main important thing is rout-

ing of all the nets or maximal possible nets to avoid very tedious

task of manual routing of left behind nets. Also, Proteus multiple

passes produce different results in all examples. This indicates that

a heuristic is being used which produces different results with differ-

ent starting point and we cannot be sure that the results are optimal,

whereas proposed model produces the same results all the time, in

all experiments.

It is obvious that the proposed optimization model is able to route

upto 20% more nets compared to best case routing from Proteus.


Table 5.1: Experiment results and Net comparison with Proteus

Exp No. of Proteus (Routing) Model

No. C1 Size C2 Size Nets 1stRun 10thRun %age Routing %age

1 5x4 5x4 5 4/5 5/5 100% 5/5 100%

2 7x7 7x7 6 4/6 5/6 83% 6/6 100%

3 18x9 17x6 18 12/18 15/18 83% 18/18 100%

4 48x40 44x44 50 36/50 41/50 82% 50/50 100%

5 98x49 86x50 100 65/100 82/100 82% 100/100 100%

Figure 5.10: Model Comparison with Proteus


5.3.5 Routing Time Analysis

Although the focus of this research is on improving the net order in-

stead of improving time, however in this section we discuss the rout-

ing time. We believe that manual routing of left over nets is very dif-

ficult or impossible for larger examples. The running times of larger

examples are significantly high for model but we can overcome this

deficiency by using high performance computing systems. Also the

PCB design is only one time activity for the entire manufacturing of

the PCB. In our results, time is not comparable because experiments

run on two different machines. Proteus results are taken on Core 2

Duo, 2.0 GHz processor with 2 GB Ram and model results are taken

on NEOS server. The solver runs on this server, use optimization

model and decides the running time. The time depends on the num-

ber of decision variable. In our case the decision variables are NE

(where N is the number of nets and E is the number of edges). Since

the decision variable is binary (0 or 1), hence the asymptotic running

time of the model is O(2NE ). However the solver uses branch and

bound algorithm and some heuristics to reduce the exponential time.

Our proposed optimization model performed 100% routing in all the

five examples but times are higher as shown in Table 5.2. However

Proteus could not route all nets in experiments 2, 3, 4 and 5, but

times are very small. Here one thing is important that manual rout-


Table 5.2: Experiment results and Time comparison with Proteus

Exp No. C1 Size C2 Size No. of Nets Proteus Time Model Time

1 5x4 5x4 5 3 sec 3 sec

2 7x7 7x7 6 6 sec 8 sec

3 18x9 17x6 18 11 sec 18 sec

4 48x40 44x44 50 18 sec 249 sec

5 98x49 86x50 100 30 sec 3687 sec

ing of even for a single left behind net is very difficult and needs lots

of time in rearranging of all the nets once again.

We observe that the execution time for the proposed model is

relatively higher compared to the execution time for Proteus on the

same instance. Optimization model with improved execution time

remains as a future development of the proposed work.

5.4 Summary

The research work discussed in this chapter, proposes the use of

mathematical modeling for BGA components, to solve routing prob-

lem for Simultaneous escape routing of multiple components. we

mapped the SER problem as a problem of planar bipartite graph

construction, using disjoint node and edge paths. Also we proposed

a mathematical model for planar graph and validated the model with


the results obtained by commercially available software. To best of

our knowledge this is the first work which uses optimization model

to solve the problem of SER by considering all necessary constraints.

Comparison with commercially available software shows that the

optimization model can route upto 20% extra nets. However, still

we need to utilize these properties to propose time efficient opti-

mization model.

Chapter 6

Mobility based Net Ordering

In this chapter, we first define the proposed algorithm for net order-

ing and its functions in detail along with an example instance. Sub-

sequently, we discuss our modified optimization model for ordered

escape routing and finally we evaluate the results by validating the

algorithm and model.

6.1 Proposed Algorithm for Net Ordering

In this section, we first define the terms used in the algorithm and

then we discuss the tile model and net ordering algorithm in detail.

We also assume here that there are only two components and only

one side escape is possible from the side of the component, which is

facing toward the other component.

RowsCi : Number of rows of pins for the component Ci

96

CHAPTER 6. MOBILITY BASED NET ORDERING 97

OrthogonalCap: This capacity refers to the number of nets that

can pass through between two neighboring pins vertically or hori-

zontally

DiagonalCap: It refers to the number of nets that can pass through

between two neighboring diagonal pins.

CapCi : Escape routing capacity for component Ci .

SERCap: Simultaneous Escape Routing capacity

BoundaryPinsCi : Number of pins on Escape boundary line

which needs connectivity for component Ci .

URDF MobilityPi : Number of nets that can pass from Up, Rear,

Down and Front side of pin Pi .

6.1.1 Net Ordering Algorithm

This algorithm calls four basic functions in sequence as discussed in

Algorithm 1, which are SER Capacity (), Initial NetOrdering(),

URDF Mobility Values() and Final NetOrdering() respectively.

This algorithm returns the optimal net order for SER, if it exists.

Then we do escape routing for each component separately according

to that net order with the help of an optimization model.


Algorithm 1 Net Ordering Algorithm1: procedure NET ORDERING()

2: Routable⇐ SER Capacity ()

3: if !Routable then

4: print ’Complete Routing not possible’ and exit

5: end if

6: PinsC1[n]⇐ ’n’ Connectivity pins of component 1

7: PinsC2[n]⇐ ’n’ Connectivity pins of component 2

8: I[n]⇐ Initial NetOrdering(PinsC1[n], PinsC2[n])

9: M1[n][4]⇐ URDF Mobility Values(PinsC1[n])

10: M2[n][4]⇐ URDF Mobility Values(PinsC2[n])

11: F [n]⇐ Final NetOrdering(I[n], M1[n][4], M2[n][4])

12: if F [n] = Null then

13: print ’Complete Routing not possible’ and exit

14: else

15: return F [n]

16: end if

17: end procedure


SER Capacity Function

We discussed SER Capacity () function in Algorithm 2. First we

calculate the escape capacity of each component. Here we also add

BoundaryPinsCi in CapCi , because they can escape directly from

the component boundary without effecting the other nets or orthog-

onal capacity. Obviously the SER capacity must be the minimum

escape capacity of both components. Then we verify whether the

routing with the required number of nets ′n′ is possible or not.

Algorithm 2 SER Capacity Algorithm1: procedure SER CAPACITY()

2: CapC1 = (RowsC1 − 1)xOrthogonalCap + BoundaryPinsC1

3: CapC2 = (RowsC2 − 1)xOrthogonalCap + BoundaryPinsC2

4: SERCap = min(CapC1, CapC2)

5: if SERCap >= n then

6: return true

7: else

8: return false

9: end if

10: end procedure

Consider an example instance of two BGA components of size

6x4, having 5 connectivity pins as shown in Figure 6.1. We are con-

sidering left component as C1 and right component as C2. RowsC1

and RowsC2 are 6, whereas OrthogonalCap is 1. Since there is no


Figure 6.1: BGA Component of Size 6x4

boundary connectivity pin, therefore CapC1 is 5 and CapC2 is also

5. According to Algorithm 2, SERCap is also 5. There are 5 pins

which need connectivity (escape routing) and these are less than or

equal to the SERCap, therefore the Algorithm 2 returns true and we

move on the next step of the main Algorithm 1.

Initial Net Ordering

We discussed Initial NetOrdering() function in Algorithm 3. We

find the initial net order, according to the position of pins in the grid

of the component. Also we define some rules for rearrangement of

the initial net order.

In the first step, we convert each row in a vertex for both com-

ponents as shown in Figure 6.2. Then for the rows having multiple


Algorithm 3 Initial NetOrdering Algorithm1: procedure INITIAL NETORDERING(PinsC1[n], PinsC2[n])

2: Read row wise all pins from top to bottom and put them in column form,

separately for each component.

3: if there are multiple pins in a single row then

4: if there are multiple pins in the first row then

5: order must be from the escape side to non-escape side.

6: else if there are multiple pins in a last row then

7: order must be from the non-escape side to the escape side.

8: else if there is a pin on the non-escape boundary column and the

number of escape boundary points are greater than the number of pins above

that row then

9: select this pin first and we name it prioritized rear boundary pin.

10: else if In cases, where the same multiple pins are in a single row in

both components then

11: select from the escape side to the non-escape side.

12: else

13: For all other rows order should be according to the row number of

the corresponding pin in the other component.

14: end if

15: end if

16: We have now two separate columns having number of rows equals to the

number of pins. This is called initial net ordering that facilitates in finding the

final net ordering. Connect pin in the left column with its corresponding pin

in the right column with edges as shown in the last step of Figure 6.2.

17: end procedure


Figure 6.2: Three step process to find initial net order

connectivity pins we apply the rules defined in Step 2 to Step 13 of

Algorithm 3. In this example we have Pin-3 on non-escape boundary

of left component and also there is one pin above that row whereas

we have two escape boundary points above that row. Therefore we

select Pin-3, first in order. Similarly we select Pin-1, first in order

in the right component. In the third step we connect all pins to their

corresponding pins with edges, as shown in Figure 6.2.

URDF Mobility Values

In the third basic function of Algorithm 1, we find the URDF mo-

bility values of a pin according to the position of the pin in the com-

ponent as shown in Figure 6.3.

According to the example of Figure 6.1, Pin-1 is in second row

and third column of the left component, which implies that there are

one row on the upside of the pin, four rows on the down side, two


Figure 6.3: Finding the URDF mobility values


Algorithm 4 URDF Mobility Values Algorithm1: procedure URDF MOBILITY VALUES(PinsCi [n])

2: Find the Up, Rear, Down and Front (URDF ) mobility values of a pin by

identifying its position in the grid.

3: U = i , R = j , D = k and F = l implies that there are (i/OrthogonalCap)

number of rows on the up side of the connectivity pin, (i/OrthogonalCap)

number of columns on the rear side, (k/OrthogonalCap) number of rows on

the down side and (l/OrthogonalCap) number of columns on the front side

(escape side) of the pin respectively, in a component. These values help in

finding the number of nets that can possibly be passed through, from that side

of the pin.

4: end procedure

columns on the rear side and one column on the front side. Since

we are considering here OrthogonalCap = 1, therefore the URDF

values are U = (No. of rows on Up side *OrthogonalCap) = 1,

R = 2, D = 4 and F = 1 respectively as shown in Figure 6.3.

Furthermore, U = 1 implies that only one net can pass through the

upside of Pin-1 and similarly for the other values.

Final Net Ordering

In the last function of Algorithm 1, we find the final net order as

shown in Figure 6.4, by eliminating a crossing of edges among two

columns. To eliminate the cross, there are four possibilities. For ex-

ample, consider the first crossing between Pin-1 and Pin-5, as shown


in Figure 6.3. The first possibility is to move the Pin-5 in left col-

umn to the top of the Pin-1 in the left column. Second possibility

is to move Pin-1 in the left column to the bottom of the Pin-5 in the

same column. Similarly, the third possibility is to move the Pin-1 in

the right column to the top of Pin-5 of the right column and finally

the fourth possibility is to move Pin-5 of the right column to the bot-

tom of Pin-1 in the same column. We try all the four possibilities

in some order, till we select the one, which is allowed by URDF

values as discussed in Algorithm 5. Failure of all the possibilities

shows that routing of both nets is not possible in this scenario.

In final net ordering process, first we consider first pin of each

column, which is Pin-1 and Pin-5 as shown in Figure 6.4. Since the

row of Pin-5 in its component is higher (smaller row number), there-

fore we select Pin-5 and try to move its corresponding pin from left

component towards upside. But on the way we have Pin-3, which

has rear value, R = 0. This implies that Pin-5 cannot route from

rear side of Pin-3. Therefore, first we move Pin-3 towards downside

of Pin-5. Since the rear and down values of Pin-5 are greater than

zero, hence we can route Pin-3 from the rear side of Pin-5. After the

routing of Pin-3, we route Pin-5 towards upside at the level of se-

lected Pin-5 of right component as shown in Figure 6.4. In this way

we eliminate all the crossings and get the final nets order if exists.


Figure 6.4: Finding the final net order

The proposed algorithm not only converts the SER problem into

much simplified ordered escape routing problem by providing the

net order, but also provides the global routing of each net. In the

next section we use optimization model for detailed routing.


Algorithm 5 Final NetOrdering Algorithmprocedure FINAL NETORDERING(I[n], M1[n][4], M2[n][4])

Consider a current variable, which initially points to the first pin of each

column as shown in Figure 6.4. In each iteration, the current variable moves

to the next row. Let Pin-A be from left column and Pin-B be from the right

column.

Select the pin, which needs reordering according to the following rules:

if Escape boundary connectivity pins are already fixed with their escape

boundary points then

we select it first and arrange its counter pin.

else if A and B both have the same position in the corresponding ordering

of pins of the two components and no other pin is being blocked by routing

this net then

these pins are already in order. We only need to update the mobility

values of the left over unordered pins. If, by this choice, any pin is being

blocked then reselect that pin first.

else if A or B is a prioritized rear boundary pin then

select that pin first. If, by this choice, any pin is being blocked then

reselect that pin first.

else if If A or B is not in the components first row and the next row pin

(w.r.t current row) of both columns are the same i.e C then

select C

else

select the pin whose row number is lesser (position is higher in the

grid).

end if


Algorithm 5 Final NetOrdering Algorithm (continued)Route the selected pin (e.g A) by moving its counter Pin-A (or both in case

C is selected) towards upside in a column to reach at current row level by fol-

lowing these rules:

if First pin to move upward then

move the counter Pin-A (both in case of C) upward from the rear side

of all the pins above that, till reaching at current row level to eliminate the edge

crossing.

else if on the way any pin have R=0 or U=0 then

first we move that pin below the counter pin A (counter pin must have

R>0 and D>0). If there is more than one pin which faces this situation then the

order of the moving down pins is from the escape side to the non-escape side.

end if

if routing is not possible by selecting Pin-A and still Pin-B remians then

select Pin-B and goto Step 15

end if

if routing is not possible by selecting any pin A or B then

return false

else

update the mobility values. The value in each direction will be either

the distance between the pin and the net passing through in that direction or

connected pin whichever is lesser. Move the current variable to the next row

and goto Step 3.

end if

if eliminate all crossings by reordering pins without any problem then

this is our final net order and we will return true.

else

return false

end if

end procedure


6.2 Optimization model for Ordered Escape

In this section, we modified the Integer linear program based op-

timization model proposed in Chapter 4. We removed system con-

straints from the model because these are useless once we have final-

ized the net order. We provide graph G(V , E) as input to this model,

where V is a set of vertices. This set consists of boundary points,

intermediate points and connecting pins. All the possible edges are

in set E and the nets use these edges for escape towards the bound-

ary of the component. Based on the given constraints, the proposed

model returns another graph G′(V ′, E ′) , which shows the maximum

number of possible escaped nets, with G′(V ′, E ′) ≤ G(V , E), which

also implies that V ′ ≤ V and E ′ ≤ E . We formulate a linear pro-

gramming model that can perform escape routing of nets from a

component according to the given net order identified in the previ-

ous section. These are the sets used as input in the proposed model:

N= Set of required nets.

I = All intermediate and boundary points.

V = All intermediate points, boundary points and connecting pins.

BE= All edges at the component’s boundary.

E = All possible edges of a BGA.


The proposed model has a decision variable X(na,eij ), which is a

Boolean variable for all nets na ∈ N and for all edges eij ∈ E . If


that edge eij for a particular net na for escape routing, otherwise the


X(na,eij ) =

1 if eij edge is being used for net na

0 if eij is not being used for na


constraints of connectivity, planar graph, net order and system con-


routing designs and already explained in detail in Section-4.2.

The following set of equations 6.1 - 6.6, completely represents


the optimization model.

max .∑na∈N

∑eaj∈E

X(na,eaj ) (6.1)

subject to: ∑eij∈E & i=a

X(na,eij ) ≤ 1 ∀na ∈ N (6.2)

∑eij∈E


X(na,ejk ) ∀na ∈ N,∀j ∈ I (6.3)

X(na,eij ) + X(na,eji ) ≤ 1 ∀na ∈ N,∀eij , eji ∈ E (6.4)∑na∈N

∑eij∈E

X(na,eij ) ≤ 1 ∀j ∈ I (6.5)

∑eij∈BE

X(na,eij ).j ≤∑

ekl∈BE

X(na+1,ekl ).l ∀na ∈ N (6.6)

6.3 Evaluation

Proposed net ordering algorithm is implemented in C++ and for

detailed routing we implemented our optimization model by using

AMPL language [71]. First we validate the proposed algorithm and

optimization model in Sub-section 6.3.1 and 6.3.2 respectively. Sub-

sequently we evaluate the performance in Sub-section 6.3.3.


6.3.1 Algorithm Validation

This section varifies that the algorithm proposed in Section 6.1, gives

the optimal net order if SER has a valid routing solution. Further-

more if a particular scenario has no complete routable solution then

it return false. We perform algorithm testing for this purpose and

use BGA component as shown in Figure 6.1. Both components C1

and C2 have 6 rows from A to F and 4 columns from 1 to 4. There

are 5 connectivity pins in each component that needs escape routing

to connect with each other. To simplify the explanation, in this ex-

ample we have assumed OrthogonalCap = 1 and DiagonalCap = 2.

We considered 12 scenarios with randomly selected 5 escape pins

in each component. In the first scenario, first pin is at location B4

in C1 and location E2 in C2. Similarly we can see the location

of other pins in Figure 6.5. The net order obtained by our pro-

posed algorithm is 1,3,2,4 and 5. Then we run the same scenario

in commercially available Proteus auto router by Labcenter Elec-

tronics Ltd. The result obtained by Proteus is exactly in the same

order as obtained by our algorithm as shown in Figure 6.5. We can

see the complete validation results in Table 6.1. First column is the

scenario number, second and third columns are the pin positions in

each component respectively from Pin-1 to 5. Fourth column is the

net order obtained by the C++ program for the proposed algorithm


Figure 6.5: SER in BGA 24 1.5

and the fifth column is the net order obtained by the Proteus router.

Results validate the algorithm for all scenarios. In some cases the

algorithm returns false, which implies that complete routing for all

the nets is not possible as shown in Scenario 7 of Table 6.1. When

we run the same scenario in Proteus, we get the un-routable solution

as shown in Figure 6.6. Routing of Pin-1 from B3 of component 1

to F2 of component 2 is not possible, which validates the results.


We considered Scenario 1 of Table 6.1 for the validation of model.

The net order obtained by the proposed algorithm is 1,3,2,4,and 5.

This net order converts the SER problem into two single compo-


Table 6.1: Validation Results and Comparison With Proteus

Scenario No. C1 Pins C2 PinsNet Order

Accuracy %ageAlgorithm ProteusB4, E2, 1, 1,C3, D1, 3, 3,

1 D2, C2, 2, 2, 100%E4, B2, 4, 4,F2 E3 5 5B3, D4, 5, 5,B4, C3, 2, 2,

2 C1, F3, 1, 1, 100%E2, D2, 4, 4,D3 A3 3 3B3, D4, 5, 5,C3, C3, 1, 1,

3 C1, F3, 2, 2, 100%E2, D3, 3, 3,D3 A3 4 4B3, D2, 5, 5,C3, C3, 1, 1,

4 C1, F3, 2, 2, 100%E2, D3, 4, 4,D3 A3 3 3C2, B3, 1, 1,C1, A2, 5, 5,

5 D1, F2, 2, 2, 100%E2, E4, 4, 4,B1 D3 3 3D3, A3, 1, 1,E2, F2, 5, 5,

6 C3, C3, 3, 3, 100%C1, F3, 4, 4,B3 D4 2 2B3, D2, Routing RoutingC3, C3, of all of all

7 C1, F3, nets nets 100%E2, D3, not notD3 A3 possible possibleB3, E2, 5, 5,C3, B3, 1, 1,

8 C1, F3, 4, 4, 100%E2, C2, 2, 2,D2 A3 3 3D3, A3, 5, 5,D4, D3, 3, 3,

9 C1, C3, 1, 1, 100%D1, E3, 2, 2,D2 B3 4 4A3, E2, 1, 1,C3, D2, 3, 3,

10 D2, C2, 4, 4, 100%E3, B2, 2, 2,F2 E3 5 5D3, F2, 4, 4,C3, C2, 2, 2,

11 F2, E2, 5, 5, 100%A3, B2, 1, 1,C2 D3 3 3C2, D4, Routing RoutingF3, A1, of all of all

12 B3, E1, nets nets 100%C4, C2, not notE1 A4 possible possible


Figure 6.6: Proteus incomplete routing

nents ordered escape routing problems. This example clearly shows

that the optimization model efficiently performs ordered escape rout-

ing for PCB components based on BGA, as shown in Figure 6.7.

There are maximum 5 boundary points in the BGA component and

model chooses to route all five nets by escaping in a given order. It

is evident that this solution ensures planarity by not selecting any

vertex or edge twice. The routing of nets is exactly the same as

obtained by Proteus auto router as shown in Figure 6.5. This ex-

ample performs comprehensive validation of proposed optimization

model and ensures all constraints of connectivity, net order and pla-

nar graph.


Figure 6.7: Ordered escape routing with proposed model

6.3.3 Performance Analysis

The performance comparison in this section is to find the optimal

net order. We compared the results of our proposed mobility based

net ordering (MBNO) algorithm with the routability driven net or-

dering (RDNO) algorithm [1]. We have considered three different

scenarios of the same examples discussed in [1] for the purpose of

evaluation. In this example there are 9 rows and 10 columns for both

components, having 90 pins in total. There are 14 nets, which need

connectivity and escaping of pins for SER. Also single side escape

is permitted with OrthogonalCap equal to 2 and the DiagonalCap

equal to 3. Each scenario highlights different aspect of the proposed

algorithm as explained in respective Sub-section.


Figure 6.8: Routability driven Net ordering [1]

BGA 9x10 Default case Scenario-1

To validate, we compare the results obtained by our proposed MBNO

algorithm with the results obtained by RDNO algorithm. For the de-

fault example discussed in [1] both provided the optimal net order.

Figure 6.8 shows the output of RDNO algorithm and the net order

is: 14, 6, 2, 5, 3, 10, 11, 4, 1, 9, 7, 8, 12, 13. Whereas Figure 6.9

shows the output of the proposed algorithm and the net order is: 14,

6, 2, 5, 3, 10, 4, 11, 12, 9, 1, 13, 7, 8. We can see from results that

proposed algorithm not only provides optimal net order but also pro-

vides more compaction to the escaping nets by utilizing all escape

boundary points in a sequence, which can accommodate more nets

within the limits of SERCap.


Figure 6.9: Proposed Mobility based Net ordering

BGA 9x10 Swap pin Scenario-II

In this scenario we just swap the pin number 6 and 14 with each

other in right component of Figure 6.8, whereas rest of the things re-

main exactly the same. The net order remains the same using RDNO

algorithm but after placing net number 14 as a first net, it blocks pin

number 6 of the right component as shown in Figure 6.10 and ends

with incomplete routing. However our proposed MBNO algorithm

provides a complete routing as shown in Figure 6.11, with the fol-

lowing net order: 6, 14, 2, 5, 3, 10, 4, 11, 12, 9, 1, 13, 7, 8

BGA 9x10 Back boundary pin Scenario-III

In this scenario we just place the pin number 3 at the back boundary

of left component of Figure 6.8, whereas rest of the things remain

exactly the same in both components. The net order remains the

same using RDNO algorithm but after placing net number 14 and 6


Figure 6.10: RDNO routing for swap pin scenario

Figure 6.11: MBNO routing for swap pin scenario


Figure 6.12: RDNO routing for back boundary pin scenario

Figure 6.13: MBNO partial routing for back boundary pin scenario

as a first and second net respectively, it blocks pin number 3 of the

left component as shown in Figure 6.12 and ends with an incomplete

routing.

However our proposed MBNO algorithm first provides the partial

routing to the blocked pin i.e. pin number 3, as shown in Figure

6.13. Then the algorithm does routing for the pin number 14 and

ultimately provides optimal net order for complete routing: 14, 6, 2,

5, 10, 4, 11, 1, 9, 12, 3, 13, 8, 7


Figure 6.14: MBNO complete routing for back boundary pin scenario

Detailed routing for the given net order is shown in Figure 6.14.

We can see how efficiently proposed algorithm solves the SER prob-

lem based on the mobility values for each pin.

Varying Size BGAs Scenario-IV

The scenarios we discussed so far are variations of the same example

having two BGA components of the same size. Now we consider an-

other example having different size BGA′s. Component 1 is of size

18x9 and component 2 is of size 17x6. There are 18 nets that need

SER connectivity. We are assuming again single side escape with

OrthogonalCap equals to 1 and the DiagonalCap is 2. We can see

from Figure 6.15, that the proposed algorithm generates the optimal

net order for successful completion of SER for all the nets.

Here, we compare the results achieved by different methods dis-

cussed so far. Our proposed MBNO algorithm performed 100%


Figure 6.15: MBNO results for varying size BGA′s scenario


Table 6.2: Experiment Results and Comparison with RDNO Algorithm

Scenario C1 C2 No. ofNet Routing

MBNONo. Pins Pins Nets RDNO MBNO Routing %age

I 9x10 9x10 14 14/14 14/14 100%

II 9x10 9x10 14 Incomplete 14/14 100%

III 9x10 9x10 14 Incomplete 14/14 100%

IV 18x9 17x6 18 Incomplete 18/18 100%

routing in all of the four scenarios by generating optimal net order,

however RDNO [1] could not route all nets in Scenario-II, Scenario-

III and Scenario-IV as shown in Table 6.2. It is important to note that

manual routing of even single net left out by an automated method is

very difficult to route and is a very time consuming process requir-

ing rearranging of all the routed nets. It is also clear from the results

that based on the mobility values of each pin we have better routing

results because we are avoiding any connectivity pin blockage while

finding out the next net in the optimal net order.

6.4 Summary

This chapter proposed the use of net order, in order to solve the

SER problem in a way superior to the previous state of art methods.

We proposed a mobility based net ordering algorithm that finds the

optimal net order and converts the problem of SER into two sim-


pler problems of finding an ordered escape routing for each compo-

nent separately. Once connectivity pins escape from each compo-

nent, according to the net order obtained by the proposed algorithm,

then area routing becomes quite simple by connecting nets of both

components in an order preserving way. We validated the net or-

der obtained by our algorithm for 12 representative and randomly

generated scenarios by comparing it with the net order obtained by

Proteus auto router. We also modified our ILP optimization model

to get the detail routing results. The detailed routing results are

similar with the results obtained by Proteus auto router. As dis-

cussed in Subsection 5.3.5, the time for SER optimization model is

O(2NE ). This means if we add only one more variable, it doubles

the computation time due to exponential behaviour i.e. O(2NE+1).

Similarly by decreasing the edges we can reduce the time exponen-

tially. In our case, we are reducing the edges almost half (assum-

ing both components have equal edges). Therefore the new time is

O(2NE/2)+O(2NE/2) for ordered escape routing of both components.

This time is much lesser than O(2NE ) due to exponential reduction.

Results shows that our algorithm finds routable net order for all sce-

narios whereas previous algorithm fails to route all nets according

to their derived net order.

Chapter 7

Conclusions and Future Work

This research proposes the use of optimization models with multi-

ple routing constraints that simultaneously solves the net ordering

and net escape problem. It is hypothesized that optimization model

along with all necessary constraints can route more number of nets,

instead of solving constraints one by one. Both optimization models

prove that they can route maximum possible nets in their respective

PCB scenarios, by considering the required design rules. Compara-

tive analysis shows that the proposed optimization models performs

better than the existing routing algorithms in terms of number of nets

routed. Also the use of net ordering algorithm reduces the complex-

ity and converts the SER problem to simple ordered escape routing

problem.

125

CHAPTER 7. CONCLUSIONS AND FUTURE WORK 126

7.1 Contributions

In the first part of thesis, linear programming based optimization

model is proposed for single component ordered escape routing to

see the effect of routing constraints and ordered escaping. In the

second part, linear optimization model for SER is proposed to see

the pins connectivity between two components in some order. In

the third part, an algorithm is proposed to find the valid net order to

reduce the complexity of SER optimization model. Contributions of

this thesis are summarized below.

• Most significant contribution of this thesis is the ILP optimiza-

tion model for simultaneous escape routing problem. This model

make sure to produce optimal routing solution, if exists.

• It has also been shown that the use of system constraints(e.g

power and signal integrity) along with other necessary con-

straints of capacity and planarity, gives us optimal results. If

we do not consider design rules during routing, then either we

are violating the design or doing it manually. Therefore con-

sidering the constraints all at once gives us optimal routing so-

lution.

• Proposed flow models for multiple capacities and for different

types of pin array components and model the PCB components


as a graph with vertices and edges. This mapping of PCB rout-

ing problem into graph makes the problem easier to solve.

• Proposed Network flow based ILP optimization model with

multiple constraints for ordered escape routing. By using this

model we can get optimal routable solution in a particular order

from a single component.

• Proposed Planar Bi-Partite Graph Construction using Flow model

for SER problems. We mapped the PCB routing problem into

planar Bi-partite graph problem, which makes easier to under-

stand and solve in a planar way by providing global routing

solution.

• Net Ordering algorithm has been proposed, which is a signif-

icant improvement in reducing the complexity of simultane-

ous escape routing problem. If we get optimal net order, then

we can solve SER problem by dividing it in two halves, each

half represents ordered escape routing from a single compo-

nent. Since we are reducing the optimization model variables

to almost half of them, hence the complexity of model reduces

to many times.


7.2 Future Work

The optimization model is dependent on the branch and bound al-

gorithm of the optimization software. The algorithm can choose a

branch that might not lead to optimal result in certain cases. Also

we divided the grid into very small components, limiting the branch-

ing options. In this case, the retracting can be used by algorithm to

explore alternate branches within the permissible time budget, re-

sulting in better optimization.

The optimization model and the software that generate data for

the model run separately. There is manual step involved where data

generated by software is fed into the model using command line

interface. A software application can be developed that does the

same task automatically for ease of use.

At present, the visualization of output of the model is not gener-

ated automatically. Although this is not part of research, however it

takes time and requires expertise to visualize the generated data.

Now a days, there are different types of BGA components based

on their pin arrays. These types include, square pin array, triangle

pin array, diamond pin array and hexagonal pin array. The proposed

models in this research focus only on BGA pins forming square

shape grids, in future we can apply this research on other available


BGA grid shapes like triangle, diamond and hexagonal to see the

increase in capacity for the same size of components.

This research focuses only on the results obtained in terms of

number of routed nets. We believe that, in the presence of high per-

formance computing (HPC) servers, time is not as much important

as the routing of nets. Since manual routing of left over nets is very

tedious and time taking and also sometime we need to do rerouting

of nets to adjust the leftover nets. Although we can use jumpers or

additional PCB layers to accommodate the left over nets, however it

increases the cost and compromises the compactness of the PCB or

electronic devices. So, in future we can also apply time limit checks

to reduce the routing time without compromising the optimal solu-

tion.

Some researchers used min-cost flow solver CS2 for getting op-

timal routing results. The algorithm behind this solver works on

some heuristics to solve many problem classes in very efficient time

duration. Although the focus of this algorithm is only un-ordered es-

cape routing, however we can modify it for ordered escape routing

or SER problems to achieve optimal results within the time limits.

For SER problems, this research focuses on simultaneous escape

routing for two components on a single layer. However, in future

we can modify our proposed SER optimization model for multiple


components and for multiple layers to meet the requirement for the

state of the art PCB designs. We believe that if we improve routing

results on one layer then we can improve results on multiple layers.

Ultimately with this advancement and optimized results we can re-

duce number of layers in PCB designs and reduce the cost and size

as well for PCB industry.

As we discussed earlier that routing is of two types, escape rout-

ing and area routing. We believe that in the SER problems, escape

routing facilitates area routing because if we provide escape rout-

ing correctly in a particular order from each component, then the

only requirement is to connect the wires directly in a straight way,

without any problem. However, if we need to add length matching

constraint, then there are two options. First we can apply length

matching constraint in escape routing, as we are doing in our pro-

posed model. Secondly we can apply this constraint in area routing,

which we have not considered in our work. If we consider it in

escape routing, then it may leads to longer paths and sub-optimal

results. In the future work we can modify our optimization model

to apply length matching constraint in area routing. In this way, the

focus of escape routing would only be net ordering and we can get

optimal routing results.

Bibliography

[1] Jin-Tai Yan, Tung-Yen Sung, and Zhi-Wei Chen. Simultaneous

escape routing based on routability-driven net ordering. In SOC

Conference (SOCC), 2011 IEEE International, pages 81–86.

IEEE, 2011.

[2] Muhammet Mustafa Ozdal. Routing algorithms for high-

performance VLSI packaging. PhD thesis, University of Illi-

nois at Urbana-Champaign, 2005.

[3] Jerry C Whitaker. Microelectronics 2nd Edition, volume 14.

CRC Press, 2005.

[4] Larry A Coldren, Scott W Corzine, and Milan L Mashanovitch.

Diode lasers and photonic integrated circuits, volume 218.

John Wiley & Sons, 2012.

[5] Gabriel Marcantonio. Ball grid array (bga) integrated circuit

packages, August 18 1998. US Patent 5,796,170.

131

BIBLIOGRAPHY 132

[6] Desnnond YR Chong, BK Lim, Kenneth J Rebibis, SJ Pan,

S Krishnamoorthi, R Kapoor, Anthony Sun, and HB Tan. De-

velopment of a new improved high performance flip chip bga

package. In Electronic Components and Technology Confer-

ence, 2004. Proceedings. 54th, volume 2, pages 1174–1180.

IEEE, 2004.

[7] R Plieninger, M Dittes, and K Pressel. Modern ic packaging

trends and their reliability implications. Microelectronics Reli-

ability, 46(9):1868–1873, 2006.

[8] Nicole M Gasparini and Bidyut K Bhattacharyya. A method of

designing a group of bumps for c4 packages to maximize the

number of bumps and minimize the number of package layers.

In Electronic Components and Technology Conference, 1994.

Proceedings., 44th, pages 695–699. IEEE, 1994.

[9] Albert Titus, Bhavesh Jaiswal, and T Dishongh. Innovative

circuit board level routing designs for bga packages. Advanced

Packaging, IEEE Transactions on, 27(4):630–639, 2004.

[10] MR Garey and DS Johnson. Appendix: a list of np-complete

problems, 1979.

[11] Hua Xiang, Xiaoping Tang, and DF Wong. An algorithm for

simultaneous pin assignment and routing. In Proceedings of the

BIBLIOGRAPHY 133

2001 IEEE/ACM international conference on Computer-aided

design, pages 232–238. IEEE Press, 2001.

[12] Muhammet Mustafa Ozdal and Martin DF Wong. Simultane-

ous escape routing and layer assignment for dense pcbs. In

Proceedings of the 2004 IEEE/ACM International conference

on Computer-aided design, pages 822–829. IEEE Computer

Society, 2004.

[13] Muhammet Mustafa Ozdal and Martin DF Wong. Algorithms

for simultaneous escape routing and layer assignment of dense

pcbs. Computer-Aided Design of Integrated Circuits and Sys-

tems, IEEE Transactions on, 25(8):1510–1522, 2006.

[14] Muhammet Mustafa Ozdal, Martin DF Wong, and Philip S

Honsinger. Simultaneous escape-routing algorithms for via

minimization of high-speed boards. Computer-Aided Design

of Integrated Circuits and Systems, IEEE Transactions on,

27(1):84–95, 2008.

[15] Lijuan Luo, Tan Yan, Qiang Ma, Martin DF Wong, and

Toshiyuki Shibuya. B-escape: a simultaneous escape routing

algorithm based on boundary routing. In Proceedings of the

19th international symposium on Physical design, pages 19–

25. ACM, 2010.

BIBLIOGRAPHY 134

[16] Qiang Ma, Tan Yan, and Martin DF Wong. A negotiated con-

gestion based router for simultaneous escape routing. In Qual-

ity Electronic Design (ISQED), 2010 11th International Sym-

posium on, pages 606–610. IEEE, 2010.

[17] Hui Kong, Tan Yan, and Martin DF Wong. Optimal simultane-

ous pin assignment and escape routing for dense pcbs. In De-

sign Automation Conference (ASP-DAC), 2010 15th Asia and

South Pacific, pages 275–280. IEEE, 2010.

[18] Hank Zumbahlen et al. Linear circuit design handbook.

Newnes, 2011.

[19] Masato Tanaka and Yojiro Nakagiri. An approach to pin as-

signment in printed circuit board design. ACM SIGDA Newslet-

ter, 10(2):21–33, 1980.

[20] H Nelson Brady. An approach to topological pin assignment.

Computer-Aided Design of Integrated Circuits and Systems,

IEEE Transactions on, 3(3):250–255, 1984.

[21] Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi

Kuan, Hung-Ming Chen, and Yoji Kajitani. On routing fixed

escaped boundary pins for high speed boards. In Design, Au-

tomation & Test in Europe Conference & Exhibition (DATE),

2011, pages 1–6. IEEE, 2011.

BIBLIOGRAPHY 135

[22] Tan Yan and Martin DF Wong. Recent research develop-

ment in pcb layout. In Computer-Aided Design (ICCAD),

2010 IEEE/ACM International Conference on, pages 398–403.

IEEE, 2010.

[23] Tan Yan, Qiang Ma, and Martin DF Wong. Advances in pcb

routing. Information and Media Technologies, 7(2):535–543,

2012.

[24] Tan Yan and Martin DF Wong. A correct network flow model

for escape routing. In Design Automation Conference, 2009.

DAC’09. 46th ACM/IEEE, pages 332–335. IEEE, 2009.

[25] Qiang Ma and Martin DF Wong. Np-completeness and an ap-

proximation algorithm for rectangle escape problem with ap-

plication to pcb routing. Computer-Aided Design of Integrated

Circuits and Systems, IEEE Transactions on, 31(9):1356–

1365, 2012.

[26] Yuan-Kai Ho, Hsu-Chieh Lee, and Yao-Wen Chang. Escape

routing for staggered-pin-array pcbs. Computer-Aided De-

sign of Integrated Circuits and Systems, IEEE Transactions on,

32(9):1347–1356, 2013.

[27] Kan Wang, Sheqin Dong, Huaxi Wang, Qian Chen, and Tao

Lin. Mixed-crossing-avoided escape routing of mixed-pattern

BIBLIOGRAPHY 136

signals on staggered-pin-array pcbs. Computer-Aided Design

of Integrated Circuits and Systems, IEEE Transactions on,

33(4):571–584, 2014.

[28] Jin-Tai Yan. Length-constrained escape routing of differential

pairs. Integration, the VLSI Journal, 48:158–169, 2015.

[29] Seong-I Lei and Wai-Kei Mak. Optimizing pin assignment and

escape routing for blind-via-based pcbs. IEEE Transactions

on Computer-Aided Design of Integrated Circuits and Systems,

35(2):246–259, 2015.

[30] Hailong Yao, Tsung-Yi Ho, and Yici Cai. Pacor: practical

control-layer routing flow with length-matching constraint for

flow-based microfluidic biochips. In Proceedings of the 52nd

Annual Design Automation Conference, page 142. ACM, 2015.

[31] Ran Zhang, Tieyuan Pan, Li Zhu, and Takahiro Watanabe. A

length matching routing method for disordered pins in pcb de-

sign. In Design Automation Conference (ASP-DAC), 2015 20th

Asia and South Pacific, pages 402–407. IEEE, 2015.

[32] Jeffrey McDaniel, Zachary Zimmerman, Daniel Grissom, and

Philip Brisk. Pcb escape routing and layer minimization for

digital microfluidic biochips. IEEE Transactions on Computer-

BIBLIOGRAPHY 137

Aided Design of Integrated Circuits and Systems, 36(1):69–82,

2017.

[33] Fengxian Jiao and Sheqin Dong. Ordered escape routing for

grid pin array based on min-cost multi-commodity flow. In De-

sign Automation Conference (ASP-DAC), 2016 21st Asia and

South Pacific, pages 384–389. IEEE, 2016.

[34] Hui Kong, Qiang Ma, Tan Yan, and Martin DF Wong. An opti-

mal algorithm for finding disjoint rectangles and its application

to pcb routing. In Design Automation Conference (DAC), 2010

47th ACM/IEEE, pages 212–217. IEEE, 2010.

[35] Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, and

Yow-Tyng Nieh. Clock period minimization with minimum

delay insertion. In Design Automation Conference, 2007.

DAC’07. 44th ACM/IEEE, pages 970–975. IEEE, 2007.

[36] Shih-Hsu Huang, Guan-Yu Jhuo, and Wei-Lun Huang. Mini-

mum buffer insertions for clock period minimization. In Com-

puter Communication Control and Automation (3CA), 2010 In-

ternational Symposium on, volume 1, pages 426–429. IEEE,

2010.

[37] Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh

Chang, Yow-Tyng Nieh, and Chien-Yung Chou. Low-power

BIBLIOGRAPHY 138

timing closure methodology for ultra-low voltage designs. In

Proceedings of the International Conference on Computer-

Aided Design, pages 697–704. IEEE Press, 2013.

[38] Hui Kong, Tan Yan, Martin DF Wong, and Muhammet Mustafa

Ozdal. Optimal bus sequencing for escape routing in dense

pcbs. In Proceedings of the 2007 IEEE/ACM international

conference on Computer-aided design, pages 390–395. IEEE

Press, 2007.

[39] Tan Yan, Hui Kong, and Martin DF Wong. Optimal layer

assignment for escape routing of buses. In Proceedings of

the 2009 International Conference on Computer-Aided Design,

pages 245–248. ACM, 2009.

[40] Hui Kong, Tan Yan, and Martin DF Wong. Automatic bus plan-

ner for dense pcbs. In Proceedings of the 46th Annual Design

Automation Conference, pages 326–331. ACM, 2009.

[41] Qiang Ma, Hui Kong, Martin DF Wong, and Evangeline FY

Young. A provably good approximation algorithm for rectan-

gle escape problem with application to pcb routing. In Pro-

ceedings of the 16th Asia and South Pacific Design Automation

Conference, pages 843–848. IEEE Press, 2011.

BIBLIOGRAPHY 139

[42] Qiang Ma, Evangeline FY Young, and Martin DF Wong. An

optimal algorithm for layer assignment of bus escape routing

on pcbs. In Design Automation Conference (DAC), 2011 48th

ACM/EDAC/IEEE, pages 176–181. IEEE, 2011.

[43] Yoichi Tomioka and Atsushi Takahashi. Monotonic parallel

and orthogonal routing for single-layer ball grid array pack-

ages. In Design Automation, 2006. Asia and South Pacific Con-

ference on, pages 6–pp. IEEE, 2006.

[44] Jia-Wei Fang, Chin-Hsiung Hsu, and Yao-Wen Chang. An

integer-linear-programming-based routing algorithm for flip-

chip designs. Computer-Aided Design of Integrated Circuits

and Systems, IEEE Transactions on, 28(1):98–110, 2009.

[45] Lijuan Luo and Martin DF Wong. Ordered escape routing

based on boolean satisfiability. In Proceedings of the 2008 Asia

and South Pacific Design Automation Conference, pages 244–

249. IEEE Computer Society Press, 2008.

[46] Wen-Hao Liu, Yih-Lang Li, and Cheng-Kok Koh. A fast maze-

free routing congestion estimator with hybrid unilateral mono-

tonic routing. In Proceedings of the International Conference

on Computer-Aided Design, pages 713–719. ACM, 2012.

BIBLIOGRAPHY 140

[47] Ran Zhang and Toshio Watanabe. A parallel routing method

for fixed pins using virtual boundary. In TENCON Spring Con-

ference, 2013 IEEE, pages 99–103. IEEE, 2013.

[48] Ching-Yu Chin and Hung-Ming Chen. Simultaneous escape

routing on multiple components for dense pcbs. In Electri-

cal Design of Advanced Packaging and Systems Symposium

(EDAPS), 2013 IEEE, pages 138–141. IEEE, 2013.

[49] Abdullah Gani. Identifying false alarm for network intrusion

detection system using hybrid data mining and decision tree.

Malaysian journal of computer science, 21(2):101–115, 2008.

[50] Kemal Altinkemer, Burak Kazaz, Murat Koksalan, and Herbert

Moskowitz. Optimization of printed circuit board manufactur-

ing: Integrated modeling and algorithms. European Journal of

Operational Research, 124(2):409–421, 2000.

[51] Mircea Ancau. The optimization of printed circuit board manu-

facturing by improving the drilling process productivity. Com-

puters & Industrial Engineering, 55(2):279–294, 2008.

[52] Aakil M Caunhye, Xiaofeng Nie, and Shaligram Pokharel. Op-

timization models in emergency logistics: A literature review.

Socio-economic planning sciences, 46(1):4–13, 2012.

BIBLIOGRAPHY 141

[53] Krzysztof Walkowiak and Miroslaw Klinkowski. Joint anycast

and unicast routing for elastic optical networks: Modeling and

optimization. In Communications (ICC), 2013 IEEE Interna-

tional Conference on, pages 3909–3914. IEEE, 2013.

[54] Godfrey C Onwubolu and BV Babu. New optimization tech-

niques in engineering, volume 141. Springer, 2013.

[55] Ajay Singh. Simulation and optimization modeling for the

management of groundwater resources. ii: Combined appli-

cations. Journal of Irrigation and Drainage Engineering,

140(4):04014002, 2014.

[56] Hideki Katagiri, Qingqiang Guo, Hongwei Wu, Hiroshi

Hamori, and Kosuke Kato. A route optimization problem in

electrical pcb inspections: Pickup and delivery tsp-based for-

mulation. In Transactions on Engineering Technologies, pages

193–205. Springer, 2016.

[57] Yasser M Alginahi, Muhammad N Kabir, and Ali I Mohamed.

Optimization of high-crowd-density facilities based on discrete

event simulation. Malaysian Journal of Computer Science,

26:4, 2013.

[58] Ejaz Ahmed, Abdullah Gani, Mehdi Sookhak, Siti Hafizah

BIBLIOGRAPHY 142

Ab Hamid, and Feng Xia. Application optimization in mo-

bile cloud computing: Motivation, taxonomies, and open

challenges. Journal of Network and Computer Applications,

52:52–68, 2015.

[59] Tzong-Lin Wu, Frits Buesink, and Flavio Canavero. Overview

of signal integrity and emc design technologies on pcb: Fun-

damentals and latest progress. Electromagnetic Compatibility,

IEEE Transactions on, 55(4):624–638, 2013.

[60] Jianjiang Feng, Bipin Dhavale, Janani Chandrasekhar, Yuri

Tretiakov, and Dan Oh. System level signal and power integrity

analysis for 3200mbps ddr4 interface. In Electronic Compo-

nents and Technology Conference (ECTC), 2013 IEEE 63rd,

pages 1081–1086. IEEE, 2013.

[61] Kai Xiao, Tao Su, John Hsu, Weifeng Shu, Xiaoning Ye, and

Yuan-Liang Li. Checking pcb design electrically for pi/si is-

sues. In Electromagnetic Compatibility (EMC), 2014 IEEE In-

ternational Symposium on, pages 712–716. IEEE, 2014.

[62] Yee Chang Fei. Methodology of power integrity analysis for

high speed pcb design. In Electronic Design (ICED), 2014 2nd

International Conference on, pages 132–136. IEEE, 2014.

BIBLIOGRAPHY 143

[63] Arva Mihai Catalin and Nicu Bizon. Some aspects on model-

ing of the signal and power integrity in a pcb based on wave-

form analysis. In Electronics, Computers and Artificial Intel-

ligence (ECAI), 2015 7th International Conference on, pages

Y–27. IEEE, 2015.

[64] Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-

Ming Chen, and Yoji Kajitani. Escaped boundary pins routing

for high-speed boards. Computer-Aided Design of Integrated

Circuits and Systems, IEEE Transactions on, 32(3):381–391,

2013.

[65] Weradech Kumtong, Panuwat Danklang, and Wiroon Sribor-

rirux. Pin set sequence selection guideline routing for printed

circuit board routing. In Knowledge and Smart Technology

(KST), 2015 7th International Conference on, pages 126–130.

IEEE, 2015.

[66] Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, and Jyh-Herng

Wang. A network-flow-based rdl routing algorithmz for flip-

chip design. Computer-Aided Design of Integrated Circuits and

Systems, IEEE Transactions on, 26(8):1417–1429, 2007.

[67] Jia Wei Fang, Kuan Hsien Ho, and Yao Wen Chang. Rout-

ing for chip-package-board co-design considering differen-

BIBLIOGRAPHY 144

tial pairs. In Computer-Aided Design, 2008. ICCAD 2008.

IEEE/ACM International Conference on, pages 512–517.

IEEE, 2008.

[68] Jia-Wei Fang, Martin DF Wong, and Yao-Wen Chang. Flip-

chip routing with unified area-i/o pad assignments for package-

board co-design. In Proceedings of the 46th Annual Design

Automation Conference, pages 336–339. ACM, 2009.

[69] Xiaodong Liu, Yifan Zhang, Gary K Yeap, Chunlei Chu, Jian

Sun, and Xuan Zeng. Global routing and track assignment for

flip-chip designs. In Proceedings of the 47th Design Automa-

tion Conference, pages 90–93. ACM, 2010.

[70] Rui Shi and Chung-Kuan Cheng. Efficient escape routing

for hexagonal array of high density i/os. In Proceedings of

the 43rd annual Design Automation Conference, pages 1003–

1008. ACM, 2006.

[71] R Fourer, DM Gay, and BW Kernighan. Ampl: A modeling

language for math. programming. Duxbury Press/Brooks/Cole

Publishing, 2002.

[72] Joseph Czyzyk, Michael P Mesnier, and Jorge J More. The

neos server. Computing in Science & Engineering, 5(3):68–

75, 1998.

simultaneous escape routing (ser) with application to...

Documents