simply a logic circuit.ppt

5/20/2018 simply a logic circuit.ppt

1/72

Digital Systems: Principles and Applications, 10eBy Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss

2007 Pearson Education, Inc.

Pearson Prentice HallUpper Saddle River, NJ 07458

Figure 4-1 It is often possible to simplify a logic circuit such as that in part (a) to produce a more efficient implementation, shown in

(b).


2/72




Figure 4-2 Example 4-1.


3/72






4/72




Figure 4-4 Circuit that produces a 1 output only for the A= 0, B= 1 condition.


5/72




Figure 4-5 An AND gate with appropriate inputs can be used to produce a 1 output for a specific set of input levels.


6/72




Figure 4-6 Each set of input conditions that is to produce a HIGH output is implemented by a separate AND gate. The AND outputs are

ORed toproduce the final output.


7/72






8/72






9/72






10/72




Figure 4-10 Circuit of Figure 4-9(d) implemented using 74HC00 NAND chip.


11/72




Figure 4-11 Karnaugh maps and truth tables for (a) two, (b) three, and (c) four variables.


12/72




Figure 4-12 Examples of looping pairs of adjacent 1s.


13/72




Figure 4-13 Examples of looping groups of four 1s (quads).


14/72




Figure 4-14 Examples of looping groups of eight 1s (octets).


15/72




Figure 4-15 Examples 4-10 to 4-12.


16/72




Figure 4-16 The same K map with two equally good solutions.


17/72






18/72




Figure 4-18 Dont-care conditions should be changed to 0 or 1 to produce K-map looping that yields the simplest expression.


19/72






20/72




Figure 4-20 (a) Exclusive-OR circuit and truth table; (b) traditional XOR gate symbol; (c) IEEE/ANSI symbol for XOR gate.


21/72




Figure 4-21 (a) Exclusive-NOR circuit; (b) traditional symbol for XNOR gate; (c) IEEE/ANSI symbol.


22/72






23/72




Figure 4-23 Circuit for detecting equality of two two-bit binary numbers.


24/72




Figure 4-24 Example 4-18, showing how an XNOR gate may be used to simplify circuit implementation.


25/72




Figure 4-25 XOR gates used to implement (a) the parity generator and (b) the parity checker for an even-parity system.


26/72




Figure 4-26 Four basic gates can either enable or disable the passage of an input signal, A, under control of the logic level at control

input B.


27/72




Figure 4-27 Examples 4-21 and 4-22.


28/72






29/72




Figure 4-29 (a) Dual-in-line package (DIP); (b) top view; (c) actual silicon chip is much smaller than the protective package; (d) PLCC

package.


30/72




Figure 4-29 (continued) (a) Dual-in-line package (DIP); (b) top view; (c) actual silicon chip is much smaller than the protective

package; (d) PLCC package.


31/72




Figure 4-30 (a) TTL INVERTER circuit; (b) CMOS INVERTER circuit. Pin numbers are given in parentheses.


32/72




Figure 4-31 Logic-level input voltage ranges for (a) TTL and (b) CMOS digital ICs.


33/72




Figure 4-32 Typical logic-circuit connection diagram.


34/72




Figure 4-33 Logic diagram using schematic capture.


35/72




Figure 4-34 A logic probe is used to monitor the logic level activity at an IC pin or any other accessible point in a logic circuit.

Figure 4 35 (a) IC input internally shorted to ground; (b) IC input internally shorted to supply voltage These two types of failures force


36/72




Figure 4-35 (a) IC input internally shorted to ground; (b) IC input internally shorted to supply voltage. These two types of failures force

the inputsignal at the shorted pin to stay in the same state. (c) IC output internally shorted to ground; (d) output internally shorted to supply

voltage. These two failures do not affect signals at the IC inputs.


37/72






38/72




Figure 4-37 An IC with an internally open input will not respond to signals applied to that input pin. An internally open output will

produce anunpredictable voltage at that output pin.


39/72





h i i i ll h d h i l d i i h i f d b id i l d ll i l


40/72




Figure 4-39 When two input pins are internally shorted, the signals driving these pins are forced to be identical, and usually a signal

with threedistinct levels results.


41/72






42/72






43/72




Figure 4-42 A programmable array for selecting inputs as product terms.


44/72

Digital Systems: Principles and Applications, 10e

By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss


Pearson Prentice Hall

Upper Saddle River, NJ 07458

Figure 4-43 A PLD development system.


45/72






Figure 4-44 Combining blocks developed using different description methods.


46/72






Figure 4-45 Block diagram of a CD player.


47/72






Figure 4-46 An organizational hierarchy chart.


48/72






Figure 4-47 A timing simulation of a circuit described in HDL.


49/72






Figure 4-48 PLD development cycle flowchart.


50/72






Figure 4-49 Bit array notation.

i 4 2 i l fl f ( ) / d (b) / / S


51/72






Figure 4-52 Logical flow of (a) IF/THEN and (b) IF/THEN/ELSE constructs

Fi 4 53 L i i i i il E l 4 8


52/72






Figure 4-53 Logic circuit similar to Example 4-8.

Fi 4 56 Fl h t f lti l d i i i IF/ELSIF


53/72






Figure 4-56 Flowchart for multiple decisions using IF/ELSIF.

Fi 4 57 T t i di t i it


54/72






Figure 4-57 Temperature range indicator circuit.

Figure 4 62 A coin detector circuit for a vending machine


55/72






Figure 4-62 A coin detector circuit for a vending machine.

Figure 4 63 An AHDL coin detector


56/72






Figure 4-63 An AHDL coin detector.

Figure 4 64 A VHDL coin detector


57/72






Figure 4-64 A VHDL coin detector.

Figure 4-65 Problems 4 2 and 4 3


58/72






Figure 4-65 Problems 4-2 and 4-3.

Figure 4-66 Problem 4-8


59/72






Figure 4-66 Problem 4 8.



60/72






Figure 4 67 Problem 4 11.



61/72







Figure 4-69 Problem 4-17.


62/72









63/72






g



64/72






g



65/72






g



66/72






g



67/72








68/72








69/72






Figure 4-77 Problems 4-47, 4-48, and 4-49.


70/72








71/72








72/72

200 P Ed i I

simply a logic circuit.ppt

Documents

pearson education

eby ronald

digital systems

circuit of figure

logic circuit

final output

high output

set of input conditions