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Signal- und Power-Integrität (SPI) von Digitalen Systemen
Institut für Theoretische Elektrotechnik
A. Vogt, H.-D. Brüns, C. Schuster
ERNI Kongress 2012, Uhingen, 11.11.12
Overview
1. Introduction
2. Power Integrity
3. Signal Integrity
4. Electromagnetic Compatibility
5. Outlook
http://www.tet.tu-harburg.de
2
Overview
1. Introduction
2. Power Integrity
3. Signal Integrity
4. Electromagnetic Compatibility
5. Outlook
http://www.tet.tu-harburg.de
3
Power Plane Ground Plane
PCB
Driver Via
Receiver
A Possible Electrical Integrity Issue
http://www.tet.tu-harburg.de
4
Signal Integrity Issues: Attenuation, Reflection, Dispersion
A Possible Electrical Integrity Issue
http://www.tet.tu-harburg.de
5
Power Integrity Issues: Switching Noise, Crosstalk
A Possible Electrical Integrity Issue
http://www.tet.tu-harburg.de
6
EMC Issues: Near Field Coupling, Radiation Coupling
A Possible Electrical Integrity Issue
http://www.tet.tu-harburg.de
7
Overview
1. Introduction
2. Power Integrity
3. Signal Integrity
4. Electromagnetic Compatibility
5. Outlook
http://www.tet.tu-harburg.de
8
Problems of Power Delivery
Ideal:
• Both ICs see the same voltage U0 between their power
and ground terminals
• Independent of time and switching
IC #1 IC #2
U0
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Problems of Power Delivery
Real world:
• Finite source impedance ZPDN
• First approximation: series RL
IC #1 IC #2
U0
ZPDN
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Problems of Power Delivery
With only one IC active there is a voltage drop across ZPDN!
U0
R uIC L
iGate1, iGate2, …
Du
uIC = U0 - Du
http://www.tet.tu-harburg.de
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The goal of power integrity is to ensure an acceptable quality
of power delivery within the system, i.e. the design of an
adequate power delivery network (PDN).
This includes:
low "resistance"
low "inductance"
hierarchical decoupling
sufficient decoupling
Power Integrity
http://www.tet.tu-harburg.de
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PDN
Impedance
Frequency
Target
System
Based on the simple example from before:
The Concept of Decoupling
) largefor (
PDN
Lj
LjRZ
(R = 0.7
mW,
L = 40 nH)
R L
U0 ~ ZIC ( f )
http://www.tet.tu-harburg.de
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… we ask what a so called "decoupling" or "bypass"
capacitor might do:
The Concept of Decoupling
) largefor (1
1 2PDN
Cj
LCRCj
LjRZ
R L
U0 ~ ZIC ( f ) C
R = 0.7 mW
L = 40 nH
C = 1 mF
http://www.tet.tu-harburg.de
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The Concept of Decoupling
W m57)( 0PDN Z
R = 0.7 mW
L = 40 nH
C = 1 mF
R = 10 mW
L = 40 nH
C = 1 mF
http://www.tet.tu-harburg.de
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Heuristic explanation:
Frequency domain:
Beyond resonance frequency: the IC sees only the
impedance of the capacitor.
Time domain:
The capacitor is like a "small battery".
The Concept of Decoupling
R L
U0 ~ ZIC ( f ) C
http://www.tet.tu-harburg.de
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Ideal world: … and real world:
R is also is called the EQUIVALENT SERIES RESISTANCE
(ESR) and L the EQUIVALENT SERIES INDUCTANCE (ESL).
The Concept of Decoupling
C R L C
LC/10
C
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Power/Ground Planes
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Power/Ground Planes
Example:
11 inch
11 inch
10 mil Dielectric
Filling (er = 4)
VRM
IC
(1 inch = 2.54 cm,
1 mil = 0.001 inch)
nF11r0pp d
AC ee
Power Ground
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Inductive Capacitive
Power/Ground Planes
Input (PDN) impedance
from before (VRM + 10
decaps)
Input (PDN)
impedance
including P/G
plane
capacitance
http://www.tet.tu-harburg.de
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Power/Ground Planes
Operation usually above the first resonance frequency…
Distributed behavior!
IC
(VRM removed –
just the planes
present)
Distributed Behavior!
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Discretization for Contour Integral Method (CIM)
Full-wave discretization CIM discretization
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y
xz
y
x
z
Further Information
http://www.tet.tu-harburg.de
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IEEE Transactions on EMC 2010
Study Case
Relative dielectric permittivity εr 4.2
Relative permeability μr 1.0
Loss tangent tanδ 0.02
Plane conductivity κ (S/m) 5.8e+7
Plane thickness (mil) 1.2
Via diameter (mil) 10
Via pad diameter (mil) 20
Via keepout/antipad (mil) 36
Board dimension in inch
Observation ports
0,0
12,11
8,2
5,10
0,11
0,2
15,8
12,0 15,0
14,6
8.02,9
8.02,2
8,9
X. Duan, R. Rimolo-Donadio, H-D. Brüns, B. Archambeault, C. Schuster, “Special Session on
Power Integrity Techniques: Contour Integral Method for Rapid Computation of
Power/Ground Plane Impedance” , DesignCon 2010, Santa Clara
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1
2
Comparison to Full-Wave Simulation
The dielectric thickness is 10 mil.
0.1 1 10 100 100010
-3
10-2
10-1
100
101
102
Imp
ed
an
ce
(M
ag
nitu
de
) [ W
]
Frequency [MHz]
Z11 CIM
Z11 full-wave
Z12 CIM
Z12 full-wave
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Comparison to Measurement
The dielectric thickness is 10 mil.
0.1 1 10 100 1000-60
-40
-20
0
20
40
Frequency [MHz]
Inp
ut
Imp
ed
an
ce Z
11
(M
ag
nit
ud
e)
[dB
W]
no decaps measured
no decaps CIM
20 decaps measured
20 decaps CIM
0.1 1 10 100 1000
-60
-40
-20
0
20
40
Frequency [MHz]T
ran
sfer
Imp
ed
an
ce Z
12
(M
ag
nit
ud
e)
[dB
W]
no decaps measured
no decaps CIM
20 decaps measured
20 decaps CIM
http://www.tet.tu-harburg.de
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Electric Field Distribution @ 190MHz
Port 1 excited by 1 Watt power and port 2 terminated with 50 Ω
The dielectric thickness is 10 mil.
Full-wave CIM
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Overview
1. Introduction
2. Power Integrity
3. Signal Integrity
4. Electromagnetic Compatibility
5. Outlook
http://www.tet.tu-harburg.de
28
Signal Integrity
The goal of signal integrity is to insure an acceptable quality of
signals within the system.
This includes:
high transmission
low reflection
low crosstalk
low losses
(low power consumption)
Signal to
Noise Ratio
Frequency
Target
System
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Effects on Signal Integrity
The ideal interconnect will simply delay the signal:
Any real interconnect will additionally change timing and
amplitude:
t
Tx Rx
t
Tx Rx
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Effects on Signal Integrity
The deviations in timing and amplitude are in general called:
t
Timing jitter or simply: JITTER
Amplitude noise or simply: NOISE
http://www.tet.tu-harburg.de
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More precise definitions of jitter and noise use the EYE
DIAGRAM. For such a diagram the received bit stream is
partioned in bit periods:
and the individual
partitions overlayed
on top of each other:
Eye Diagrams
t
t
BT
Eye
Opening
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Besides S-parameters and
step response eye diagrams
are another useful method
to analyze transmission
characteristics:
Eye Diagrams
Tx
Rx
Tx
Rx
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Further Information
http://www.tet.tu-harburg.de
34
IEEE SPI 2012
Common Interconnect Problems
Insufficient
Shielding
Discontinuities
IC (Transmitter)
IC (Receiver)
Impedance
Mismatch
Insufficient Termination
We have seen that a realistic interconnect for digital signals
can suffer from many problems:
Insufficient Line Pitch and Width
http://www.tet.tu-harburg.de
35
SI Problems Inside the Motherboard
• Layer-layer inter-
connects: VIAs
• Striplines
Both „radiate“
Cross-talk
http://www.tet.tu-harburg.de
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Parallel plane modes are excited whenever a current is flowing on
a via that crosses the cavity (either signal or power/ground via):
via currents
parallel plane modes
The Physics of Vias
http://www.tet.tu-harburg.de
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Picture © TET, TUHH
Picture © IBM
Via Cross Section
Zp
Zpp
Zp
viu
vil
iiu
iil
v'il
i'iu
i'il
vi
l
l
u
u
i
ipp
i
i
i
vZ
i
v
10
1
u
u
uu
u
i
i
pi
i
i
v
Zi
v
1/1
01
'
'
l
l
ll
l
i
i
pi
i
i
v
Zi
v
'
'
1/1
01Via
Plane
Plane Cp
Cp
Zpp:
(Parallel Plate
Impedance)
Current
The Model for Vias
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Picture © IBM
Decoupling capacitor model
Cavity
representation
Cavities joined by
segmentation
techniques
R. Rimolo-Donadio et al., “Physics-based via and trace models for efficient link simulation on multilayer structures
up to 40 GHz", IEEE Trans. Microw. Theory and Techn., vol. 57, no. 8, p.p. 2072-2083, August 2009.
Zpp Ztl
Decap
Linterc.
Zpp Ztl
Decap
Linterc.
Decap
Linterc.
Cavity
representation
Stacking the Deck
S-Parameter
Matrix
Port 1 Port n
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Further Information
http://www.tet.tu-harburg.de
40
IEEE EMC Zürich 2008
MLSS – Multi-Layer Substrate Simulator
• Simulation tool for signal and power integrity issues.
http://www.tet.tu-harburg.de
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6 Vias, 4 traces case
Centered striplines at
two levels, and thru vias
in a 6 cavity stackup
Full-wave model
Mag
nit
ude
of
S1
2 [
dB
]
Frequency [GHz]
Model
FEM simulation
FIT simulation Full-wave model M
agnit
ude
of
S1
4 [
dB
]
Frequency [GHz]
Model
FEM simulation
FIT simulation
Comparison with Full-Wave Results
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• 119 vias (76 signal,
43 ground)
• 14 differential
striplines (2D)
• 6 cavities
• Terminations
Comp. time: < 3 min
Assumption
of infinite
plates
Comparison with Full-Wave Results
http://www.tet.tu-harburg.de
43 Pictures © TET, TUHH
Picture © IBM
Comparison with Measurements
Models capture the salient features of the
hardware response despite the drastic
model simplification
|S13| [dB] - FEXT |S12| [dB] - IL
Link 10 -
S3 Stripline
Link 17 - S5
Stripline
Link 10 -
S3 Stripline
Link 17 - S5
Stripline
Measurement Link 10
Measurement Link 17
Model Link 10
Model Link 17
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Overview
1. Introduction
2. Power Integrity
3. Signal Integrity
4. Electromagnetic Compatibility
5. Outlook
http://www.tet.tu-harburg.de
45
Electromagnetic Compatibility
The goal of electromagnetic compatibility is to insure
acceptable levels of electromagnetic interference (EMI) of the
system with the outside.
This includes:
EMI source control
return current control
proper shielding
proper filtering
proper SI and PI
EMI
Frequency
Target
System
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46
Sources of EMC Problems Digital Systems
Picture © TET, TUHH
Backplane
Dau
gh
terc
ard
• Switching Noise, ICs
• Cavity resonances
• Interconnects
• Differential to Common-
mode conversion
http://www.tet.tu-harburg.de
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Picture © TET, TUHH
Length mismatch Asymmetrical
ground pins
Via fields
Bends
Crosstalk
Impedance
discontinuity
There is no Truly Differential Signal
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Further Information
http://www.tet.tu-harburg.de
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IEEE EMC Symposium 2009
Development of the MoM Code CONCEPT-II
Full-wave solver suite based on the Method of Moments
Windows
http://www.tet.tu-harburg.de
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Linux
Radiation due to Cavity Resonances
• PCB: height << other dimensions
→ TM-modes
→ CIM
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• Radiated fields expressed with magnetic surface current
• CIM: no electric currents (PMC)
→ no radiation
• MoM: magnetic currents as
excitation
→ electric fields
Radiation due to Cavity Resonances
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• External ports with both MoM and CIM
Coupling to the Outside World
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Multi-Step Approach
• Interaction of a PCB with PEC scatterers
• Excited by a dipole generator in the center (1mW) of the
power plane pair
• PCB calculated with CIM, 3D interaction calculated with
MoM
http://www.tet.tu-harburg.de
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x
z
y
Excitation: 1mV
0.3 mm d
5 cm
Region for field plots
The virtual plane
for the MoM step
Multi-Step Approach – Electric Field
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Multi-Step Approach – Comparison to Full-Wave MoM
• Good correlation (outside the PCB)
• Significant speed-up:
– Full-wave MoM: 80 s/freq
– CIM/MoM: 15 s/freq
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Multi-Step Approach – Backscattering
• Induced noise voltage insignificant (less than 1%)
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0 1 2 3 4 5 6 7 8 9 100
0.5
1
1.5
2
2.5
3
3.5
Frequency [GHz]
Induced n
ois
e v
olta
ge a
t in
put port
[
V]
d = 2cm
d = 1cm
d = 0.5cm
d = 0.2cm
x
z
y
Excitation: 1mV
0.3 mm
d 5 cm
Further Information
http://www.tet.tu-harburg.de
58
IEEE EMC Europe 2012
Problem: Huge systems
• Reduce number of
unknowns
• Approximate Models
Roadmap
http://www.tet.tu-harburg.de
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Overview
1. Introduction
2. Power Integrity
3. Signal Integrity
4. Electromagnetic Compatibility
5. Outlook
http://www.tet.tu-harburg.de
60
Goals of SI, PI, and EMC
The basic goals of EMC, SI, and PI for an electrical system
are complementary to each other.
PI: insure acceptable quality
of power delivery within
SI: insure acceptable quality of
signals within
EMC: insure acceptable level
of interference with the outside
EMI
Frequency
Target
System
Frequency
SNR
Frequency
Target System
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PDS
Impedance
Target
System
Electrical Integrity
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62
Picture © TET, TUHH
Thank you for your attention!
Alexander Vogt Institut für Theoretische Elektrotechnik
Technische Universität Hamburg-Harburg
Harburger Schloßstr. 20
21079 Hamburg, Germany
http://www.tet.tu-harburg.de
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