Signal Integrity Evaluation with Full Wave Simulation Tools

Dr. An-Yu Kuo, Chief Technical OfficerOctober 2004

2

Presentation Outline

Brief Introduction of 3D full wave simulationCase Studies

A single trace over a slotted planeA single trace over a hole in a ground planeEffects of a long via stubPlacement of signal/ground viasA trace on a lossy substrateEffects of plating tails on signal integrityFull Wave Extraction of Power/Ground Planes

Q&A

3

CAD 3D Model 3D Full Wave Solver

EjHHjE

HE

ωεωµ

µε

=×∇−=×∇=⋅∇=⋅∇

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EM Fields

{ } }{])[][]([ 21 bEMKK oo ωωω =−−

S/Y/Z, Smith Chart, R/L/G/C, Z/T, TDR/TDT, W, Spice

O-Wave Automated Simulation Flow

A Single Trace over A Slotted Plane

5

Eddy Current

Displacement Current

Signal Current

Objective

Study effects of a signal trace crossing a slender slot in a ground plane (What is the return current path?)Benchmark results from different simulation tools.

2D Quasi-Static Method: Qsolve (Optimal)3D Quasi-Static Method: FastHenryImproved 3D Quasi-Static Method: PakSi-E (Optimal)3D Full-Wave Method: O-Wave (Optimal)

6

Problem Definition

5mm x 5mm square ground planeThickness = 0.025mmConductivity = 5.8e7 mho/m

Void slotLength = 4mm5 cases:Width = 0, 0.05, 0.10, 0.50, 1.00 mm

Trace: 0.1 mm above the ground planeWidth = 0.1mmThickness = 0.025 mmLength = 4mmConductivity = 5.8e7 mho/m

Dielectric Constant = 1

7

displacement current across the

gap?

Metals (0.1mm slot)

Full Wave ResultsElectrical Fields @ 1GHz

8

Full Wave ResultsElectrical Fields @ 1GHz

Displacement current due to high E field in the gap

Dielectric Material 0.1 mm slot

JDjH +=×∇ ω

9

return current due to magnetic fields

Metals (0.1mm slot)

Full Wave ResultsElectrical Fields @ 1GHz

10

Metal Current Density vs. Frequency

10KHz 10MHz 10GHz

At very low frequencies, significant return currents (eddy currents) flow along the metal edges. At higher frequencies, displacement

currents start to dominant and eddy currents diminishes.

11

Full Wave Results (Inductance)

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Freq (GHz)

L (n

H)

No Slot0.05mm0.10mm0.50mm1.00mm

The inductance solutions are extracted from O-Wave’s s-parameters with an utility tool, WB-Extract by Optimal.

A wider slot induces a higher inductance

12

Full Wave Results (TDR/TDT)

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.0 0.1 0.2 0.3 0.4 0.5 0.6

Time (ns)

Volta

ge (V

)

S11 no slotS12 no slotS11 0.1mmS12 0.1mmS11 1.0mmS12 1.0mm

The TDR/TDT curves are converted from O-Wave’s s-parameters with an utility tool, S2TDR by Optimal.

A wider slot causes a higher spike

A wider slot causes a longer delay

13

Comparison of Inductance Results @ 1 GHz

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Slot Width (mm)

L (n

H)

O-Wave (Full Wave)PakSi-E (Improved Quasi-Static)FastHenry (quasi-Static)2D No Slot

Quasi-static method over-predicts inductance

14

Discussion and Conclusions

Return currents with Optimal competitor quasi-static tools flow in metal materials only.Optimal O-Wave includes return currents in metal materials (eddy currents) and in dielectric materials (displacement current).At high frequencies (>100 MHz), the quasi-static method used by competitors over-predicts inductance by almost 50%.Displacement current plays an important role in designing tracesjumping over slots in a ground/power plane at high frequencies.PakSi-E’s improved quasi-static method provides very accurate solutions for ground planes with slots and holes.To accomplish this benchmark with competitor tools requires three different tools at a much higher cost.

Effects of Traces Over a Hole in a Ground Plane

16

Objective

Looping traces around holes is a know design practice.Many times, it is impossible to

avoid traces over holes.

Study effects of a signal trace over a hole in a ground plane

What are trade-off’s of the bends?

17

Problem Definition

5mm x 5mm square ground planeThickness = 0.025mmConductivity = 5.8e7 mho/m

Void holeDiameter = 0.0 mm, 1.0 mm

Trace: 0.1 mm above the ground planeWidth = 0.1mmThickness = 0.025 mmLength = 4mmConductivity = 5.8e7 mho/m

18

Magnetic Field

19

Results (L & C)

O-Wave (solid ground)

O-Wave (solid ground)

WB-Extract

O-Wave (Hole)

O-Wave (Hole)

20

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0 50 100 150 200 250 300 350 400 450 500

Time (ps)

Volta

ge (V

)

Near End (Solid)Far End (Solid)Near End (Hole)Far End (Hole)

Results (TDR/TDT)

Difference in delays of the two cases is not significant due to relatively constant LC product

between these two cases.

21

Results (Characteristic Impedance)

O-Wave (Solid)

The trace over a hole has a higher impedance due to its higher L and lower C.

O-Wave (Hole)

22

Discussion and Conclusions

A hole in a ground plane will cause a higher inductance and a lower capacitance for traces crossing over the hole.Traces crossing over a hole will have a higher characteristic impedance.Changes in delay for traces crossing over a hold is not as significant as the changes in characteristic impedance.Use of O-Wave together with WB-Extract can accurately quantify effects of holes in a ground plane on signal integrity of traces crossing over it.

Effects of a Long Via Stub

24

Objectives & Problem Definition

Objectives• Study effects of via stubs on high

speed signal integrity.

• Why do we need to “cut” the extra via stubs in a back-plane design?

0.2 mm wide trace, 0.5 mm pad

2.5 mm X 1.5 mm with a 0.5 mm hole

Via diameter = 0.2 mm

Dielectric Constant = 4.5

25

0.1 mm stub1 mm stub

Comparison of S-Parameter Solutions

Via stub has detrimental effects on signal integrity at high

frequencies.

Via stub is a resonator

26

Comparison of Parasitics Solutions

0

10

20

30

40

50

60

0 5 10 15 20 25 30 35Freq (GHz)

Z (o

hm)

0.1 mm

1.0 mm

0

5

10

15

20

25

0 5 10 15 20 25 30 35Freq (GHz)

T (p

s)

0.1 mm1.0 mm

0.0

0.2

0.4

0.6

0.8

1.0

1.2

0 5 10 15 20 25 30 35Freq (GHz)

L (n

H)

0.1 mm1.0 mm

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 5 10 15 20 25 30 35Freq (GHz)

C (p

F)

0.1 mm1.0 mm

Trace with a longer stub has a lower impedance.

Trace with a longer stub has a longer delay.

Trace with a longer stub has a lower inductance.

Trace with a longer stub has a higher capacitance.

27

Comparison of Near End Voltages (1)

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0 50 100 150 200 250 300 350 400 450

Time (ps)

Volta

ge (V

)

0.1 mm stub1.0 mm stub

Rise Time = 100 ps

At a slower rise time, having a long via stub may still be OK.

28

Comparison of Near End Voltages (2)

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0 50 100 150 200 250

Time (ps)

Volta

ge (V

)

0.1 mm Stub1.0 mm Stub

Rise Time = 10 ps

At a faster rise time, having a long via stub is detrimental.

29

Discussion and Conclusions

Long via stubs creates bad signal integrity at high frequenciesA longer via stub will cause higher capacitance and lower inductance, and thus, lower characteristic impedance.A 3D full wave simulation tool, such as O-Wave, is required to accurately capture the resonance due to long via stubs.Use of WB-Extract and S2TDR with O-Wave allows high speed designers to quantify effects of via stubs on signal integrity in both frequency and time domains.

Placement of Signal and Ground Vias

31

V1

Objectives & Problem Definition

Study effects of number of adjacent ground vias on signal via’s inductance.

Via Diameter = 0.3 mm

Via Pitch = 1 mm

Distance between plates = 0.8 mm

Plate thickness =0.03 mm

32

V1

Results (1 adjacent ground via)

What does this s-parameter imply?

Magnetic Field

Return current

33

V1

Results (4 adjacent ground via)

Magnetic Field

Johnson’s 4 via formula

Return currents through 4 vias

34

Actual return current pattern is a combination of a coaxial mode near the signal via and a straight line mode near the ground vias.

Return Current Path (4 adjacent ground vias)

35

V1

Results (8 adjacent ground via)

Magnetic Field

Return currents through 8 vias

36

Discussion and Conclusions

Increasing adjacent ground vias from 1 to 4 reduces the signal via inductance by 33%.Further increasing adjacent ground vias from 4 to 8 does not improve the signal via inductance.Handbook equation can only provide a rough estimate of via inductance.A 3D full wave simulation tool, such as O-Wave, is required to accurately quantify effects of number of adjacent ground vias.Use of WB-Extract with O-Wave allows high speed designers to extract electrical parasitics out of the more abstract s-parameter solutions.

A Trace on a Lossy Substrate

38

Objectives & Problem Definition

Study effects of substrate conductivity on signal integrity

Trace width = 1.6 mm

Trace length = 11.6 mm

Trace thickness = 0.2 mm

Substrate thickness = 2.1 mm

Substrate Dielectric Constant = 4.4

Substrate Conductivity = 10 mho/mm

Substrate bottom grounded

microstrip

A lossy substrate will cause the equivalent ground to move up at higher frequencies.

39

X

Y

Z

939.4

880.7

822.

763.2

704.5

645.8

587.1

528.4

469.7

411.

352.3

293.6

234.9

176.2

117.5

58.74

0.0366

V1

Output Set: O-Wave PKG ResultsContour: Total H Field (H/m)

X

Y

Z

12655.

11865.

11074.

10283.

9492.

8702.

7911.

7120.

6329.

5539.

4748.

3957.

3166.

2376.

1585.

794.

3.276

V1

Output Set: O-Wave PKG ResultsContour: Total E Field (V/m)

S & EM Fields (Dielectric Substrate)

At 0.5 mm below the trace, electrical field is still significant.

At 0.5 mm below the trace, magnetic field is quite visible.

40

L/C/Z/T Results (Lossy Substrate)

dielectric substrate

dielectric substratedielectric substrate

dielectric substrate

41

Discussion and Conclusions

Traces on a lossy (semiconductor) substrate behave quite differently from traces on a dielectric substrate.At high frequencies, lossy substrates will make penetration of magnetic fields a low shallower. As a result, inductance becomes smaller.Lossy substrates will make capacitance higher.Lossy substrate will make characteristic impedance lower.Lossy substrates effects have a very rapid transition near DC.O-Wave & WB-Extract are powerful tools for studying lossy substrate.

Effects of Plating Tails on Signal Integrity

43

Objectives & Problem Definition

Study effects of plating tails on signal integrity

Trace width = 0.2 mm

Trace length = 8 mm

Plating Tail Length = 2 mm

Trace thickness = 0.03 mm

Substrate thickness = 0.15 mm

Substrate Dielectric Constant = 4.5

Substrate bottom grounded

microstrip

44

Results : S-Parameter (no plating tail)

45

Results : S-Parameter (with plating tail)

46

Electric Field at 18 GHzwith plating tail

Plating tail is a resonator

47

Electric Field at 18 GHzwith plating tail

Plating tail is a resonator

48

Inductance Solutions

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 1 2 3 4 5 6Freq (GHz)

L (n

H)

No Plating TailWith Plating Tail

49

Capacitance Solutions

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0 1 2 3 4 5 6Freq (GHz)

C (p

F)

No Plating TailWith Plating Tail

50

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.E+00 1.E-10 2.E-10 3.E-10 4.E-10 5.E-10 6.E-10

Time (s)

Volta

ge (V

)

S11-No_TailS12-No_TailS22-No_TailS11_TailS12_TailS22_Tail

1. Identical near end curves in the no_tail case (blue and yellow)

2. Very different near end curves in the plating tail case (light blue and brown)

3. Delays are not related to driving direction in the no_tail case.

4. Delays are directional in the plating tail case.

TDR/TDT Solutions

51

Discussion and Conclusions

At low frequency, a plating tail will only add additional capacitance to the net, while inductance remains about the same.At very high frequency, a plating tail can act as a resonator and totally change the signal integrity behavior of the net.O-Wave + WB-Extract + S2TDR can be use to quantify effects of plating tails on signal integrity.

Full Wave Extraction of Power/Ground Planes

53

Fringe Inductance Models

PowerGrid’s AC analysis is industry’s first to use patent-pending Fringe Inductance ModelsLibrary of area and edge coefficients are pre-characterized and applied to complex structures

2

22

2

22

2

2

FA

FA

FAtotal

FA

FA

FAtotal

FAtotal

FAtotal

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RwR

RwR

lR

LwL

LwL

LwL

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CwCl

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×==

×+×=

×+×=

LRARRLLALLLGAGGLCACC

FAtotal

FAtotal

FAtotal

FAtotal

×+×=×+×=×+×=×+×=

AL

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w

dCF

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54

20-Port S-Parameter of a Power Plane

Freq (GHz)

| S |

(dB)

20 ports at solder bumps and solder balls

The 20-port s-parameter can be connected to the IC power grid circuit for a concurrent IC/Package dynamic IR drop analysis.

55

Impedance Curve of a Power Plane

All ports except one solder bump port open.

Impedance versus frequency curve generated by PowerGrid can be used to check ground/power plane resonance and to place decoupling capacitors.

56

Summary

Ground bounce and simultaneous switch noise issues are critical in high speed/high frequency designs.DC IR-drop is important in PCI-Express, USB, and many high power board designs.A full wave 3D tool is necessary to capture power/ground plane resonance.System tools are coming soon to link IC, package and PCB ground/power analyses together.

57

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Frequency Domain

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V+dVI+dI

R, L, C and G are matrices of parasitic parameters per unit length

58

[ ] [ ] [ ]( ) [ ] [ ]( ) 2/12/1 LjRCjGZC ωω ++= −Characteristic Impedance

Propagation Constants

[ ] [ ]( ) [ ] [ ]( )[ ] [ ][ ]2Λ=++ UULjRCjG ωω

[ ] [ ] [ ]( ) [ ] [ ]( )( ) [ ][ ][ ] 12/1 −Λ=++=Γ UULjRCjG ωω

[ ] [ ] [ ] [ ] [ ][ ] [ ] [ ] [ ] ⎟⎟⎠

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=cothcsccsccoth

CC

CC

YhYhYY

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EigenvalueProblem

Admittance Matrix

[ ] [ ] [ ] [ ]( ) [ ] [ ]( )[ ] 2/112/1LLLL YYYYYYS −+= −−S Parameter

Matrix

R,L,G,C & S,Y,Z are relatedfor Transmission Lines

Thank You Very Much!