sic power device reliability studiesneil/sic_workshop...• 3 lots / 25 parts each, no failures...
TRANSCRIPT
© 2018 Cree, Inc. All rights reserved © 2018 Cree, Inc. All rights reserved
Shadi Sabri, Daniel J. Lichtenwalner, Brett Hull, Edward Van Brunt, Don Gajewski, Dave Grider, Scott Allen, and John W. Palmour
Wolfspeed, a Cree Company; Research Triangle Park, NC 27709
SiC Power Device Reliability Studies
13th Annual SiC MOS Workshop, UMD, Aug. 16-17, 2018
© 2018 Cree, Inc. All rights reserved 2
• Packaged parts tested
• 3 lots / 25 parts each, no failures allowed (JEDEC)
• 3 lots / 77 parts each, no failures allowed (AEC-Q101)
• Typically at or near rated voltage levels, rated temperature, 1000hrs
• Automotive qualification (AEC-Q101) successful for E-Series™ 900V MOSFET and
1200V Diode
Wolfspeed Commercial parts are JEDEC and AEC Qualified
• HOWEVER, lifetime prediction requires taking parts to failure
• Use accelerated (field, temperature,…) conditions
• Extrapolate to use conditions for lifetime prediction
HTGB HTGS ESDThermal
ShockH3TRB
Gate Mechanical StructureActive Structure, Passivation, Edge
HTRB
Stressed Device Component
JEDEC Qualification Tests
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Accelerated High-Field Testing
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• High Gate Oxide Fields (VGS)
1) VT stability (PBTI/NBTI)
2) Oxide breakdown (TDDB & R-BD)
• High Drain Fields (VDS)
3) Accelerated HTRB (Vrated < VDS > Vaval)
SiC Power MOSFET Schematic
Poly Si
oxide
n-SiC
Nitrided MOS interface Wdepl & Edrift
increase with ↑VDS
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Threshold Voltage Stability (PBTI)Positive Bias Temperature Instability
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PBTI (NBTI) = Positive (Negative) Bias Temperature Instability
A threshold voltage shifting with time can change the device on-state and/or blocking characteristics
• Threshold shift (DVT) relates to interface & oxide traps [1,2]:
DVT = q*(DNox+DNIT)*[(q*Tox)/(Kox*eo)]
• VT shift of Si MOSFETs is dependent on the MOS gate electric field, temperature, and time[1,2]:
DVT = Aexp(Eox)exp(-EA/kT)tn
• SiC has an order of magnitude higher number of interface traps (NIT) than Si devices
[1] J.H. Stathis and S. Zafar, “The negative bias temperature instability in MOS devices: A review,” Microelectronics Reliability 46 (2006) pp. 270-286.
[2] D.K. Schroder, “Negative bias temperature instability: What do we understand?” Microelectronics Reliability 44 (2007) pp. 841-852.
Threshold Voltage Stability (PBTI or NBTI)
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• 900V 65mohm SiC MOSFETs -Wolfspeed C3M0065090D (150°C, +19VG (rated VG =15V))
• Log-Log plot of DVT vs PBTI stress time (worst-case scenario)
• Power law exponent ~0.19, similar to nitrided SiO2/Si
• Oxides on Si behave similarly, but with
much smaller DVT due to lower DIT levels
• Nitrided oxides on Si have a larger VT
shift than SiO2 [1]:
[1] J.H. Stathis and S. Zafar, “The negative bias
temperature instability in MOS devices: A review,”
Microelectronics Reliability 46 (2006) pp. 270-286.
Threshold Voltage Stability (PBTI) of SiC Power MOSFETs
0.01
0.1
1
1E-02 1E+00 1E+02 1E+04
DV
T(V
)
PBTI time (hrs)
Model tn, n=0.19
10-2 100 102 104
Does VT shift this much under switching operation?
VG= +19V
T= 150ºC
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• 900V 65mohm SiC MOSFETs (150°C, +19VG)
• Linear plot of VT vs stress time
• Continuous vs interrupted VGS stress
• Threshold voltage ‘relaxation’ is observed in Si devices (J.H. Stathis & S. Zafar, Microelectron. Reliab. 46 (2006))
PBTI/NBTI relaxation/switching effects
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0 80 160 240
VT
(V)
time (hrs)
Continuous Vgs
Periodic stress interruption
• Interrupted stress is closest to SiC MOSFET switching
applications; greatly reduced ∆VT observed
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• Large N-cap ramped breakdown & MOSFET TDDB
• High-voltage devices with thicker epi
TDDB Testing for Gate Oxide Lifetime Determination
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• Ramped-Breakdown at 150 °C
• Qty (750) devices, ~4mm2 area
each
• Gen 2 oxide
• Linear field model used for lifetime
extrapolation [3-5]:
is the field acceleration parameter
(nm/V)
[3] J.S. Suehle, “Ultrathin gate oxide reliability: Physical models, statistics, and characterization,” IEEE Trans. Electron Dev. 49 (2002) pp. 958-971.
[4] Y-C. Yeo, Q. Lu, and C. Hu, “MOSFET gate oxide reliability: Anode hole injection model & applications,” Inter. J. High Speed Electron. & Systems 11 (2001) pp. 849-886.
[5] H.C. Cramer, J.D. Oliver, and R.J. Porter, “Lifetime of SiNcapacitors determined from ramped and constant voltage testing,” Proc. 2006 CS MANTECH Conf., pp. 91-94.
Ramped Breakdown of large-area Ncaps
Fail time = t(0)*exp( *(Efail-
Euse))
t(0) = dt/(1-exp(- *dE)
dt, dE = ramp step time & field
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• Ramped-Breakdown at 150 °C
• Qty (750) devices, ~4mm2 area
each
• Gen 2 oxide
• Linear field model used for lifetime
extrapolation [3-5]:
is the field acceleration parameter
(nm/V)
[3] J.S. Suehle, “Ultrathin gate oxide reliability: Physical models, statistics, and characterization,” IEEE Trans. Electron Dev. 49 (2002) pp. 958-971.
[4] Y-C. Yeo, Q. Lu, and C. Hu, “MOSFET gate oxide reliability: Anode hole injection model & applications,” Inter. J. High Speed Electron. & Systems 11 (2001) pp. 849-886.
[5] H.C. Cramer, J.D. Oliver, and R.J. Porter, “Lifetime of SiNcapacitors determined from ramped and constant voltage testing,” Proc. 2006 CS MANTECH Conf., pp. 91-94.
• Good Weibull failure distributions
• field acceleration parameter () ~36
nm/V, consistent with SiO2 on silicon
Ramped Breakdown of large-area Ncaps
-7-6-5-4-3-2-1012
42 44 46 48 50 52 54 56ln
(-ln
(1-F
))
Failure Voltage (V)
Ramp Rates:0.20 V/s0.67 V/s1.67 V/s
-4
-3
-2
-1
0
1
2
3
1.00 1.05 1.10 1.15 1.20
ln(r
am
p r
ate
)
Failure Field (V/nm)
Fail time = t(0)*exp( *(Efail-
Euse))
t(0) = dt/(1-exp(- *dE)
dt, dE = ramp step time & field
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• Ramped-Breakdown lifetime extrapolation
using large Ncaps
(blue solid line)
• Constant Voltage TDDB data from
packaged 1200V 80mohm SiC Wolfspeed
MOSFETs, C2M0080120D
(circles, squares)
• Lifetime extrapolations ~agree for Ramped
& constant voltage TDDB
• TDDB median lifetime @ 20 VGS ~108 hrs
Ramped vs Constant-Voltage Breakdown
1E+01
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
1E+08
1E+09
15 20 25 30 35 40 45
Tim
e (h
rs)
Gate Voltage (V)
109
107
105
103
101
Constant-V
TDDB (points)
Ramped TDDB
extrapolation
R-BD median failure points
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• Constant Voltage TDDB data from packaged 1200V 75mohm SiC Wolfspeed
MOSFETs
• TDDB median lifetime @ 15 VGS ~5x108 hrs
Constant-Voltage Breakdown (150mm line)
Constant-V TDDB (Points)
90%
50%
10%
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Confocal/DIC Image: 10 µm thick SiC Epi
50 µm
5 µm
3.3kV SiC MOSFETs… thicker epi, rougher surface
12 nm5 µm
250 µm
30 µm thick SiC Epi
AFM Image of “pit” AFM Depth Profile
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Lifetime extracted from VBD using field acceleration ()
3.3kV SiC epi: oxide lifetime & SiC morphology
• Qty (750) devices, ~4mm2 area each• Two earliest failures do have large macroscopic defects
• Oxide lifetime still projected to be long for these parts
T1%: > 2∙108 hours
VBD
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10kV SiC epi: Failure voltage independent of surface texture
• Qty (750) devices, ~4mm2 area each• Tight failure distribution despite SiC surface roughness
Extracted capacitor failure voltages
Inset: examples of epi surface texture
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6.5 kV SiC Power MOSFET: Gate Reliability
• Entire tested population (50 parts, ~40.1mm2 each)
with a failure time >107 hours at a use voltage of 20V
8.1 mm
8.1 mm
Parametric
testing/Blocking
failures
• On wafer testing of 6.5 kV MOSFETs (~40.1mm2)
• R-Breakdown performed at 150°C and 2 V/s ramp
rate
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Accelerated High-Field HTRB Testing
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1E+01
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
1E+08
1E+09
600 1,000 1,400 1,800
Tim
e (h
rs)
Drain Voltage (V)
109
107
105
103
101
VavalVuse
• 1200V 20A G2 MOSFETs, VGS= 0 V (C2M0080120D)
• Groups of devices stressed at VDS @ 1460V, 1540V, or 1620V
• Extrapolation line gives predicted median failure time at given VDS (each data point is a median failure time)
• Failure acceleration limited by Vaval
• HTRB median lifetime @ 800 VDS ~3x107 hrs
High-temperature reverse-bias (HTRB) accelerated testing
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• 900V 20A G3 MOSFETs, VGS= 0 V (C3M0065090D)
• 60 devices stressed into weak avalanche, VDS ~1160V to ‘force’ failure
• No failures observed after 1000hrs;
• Gen3 very rugged in HTRB; even under avalanche conditions
HTRB accelerated testing: Gen3 900V MOSFET in avalanche
0
10
20
30
40
50
60
70
80
90
100
0 200 400 600 800 1000
Av
ala
nch
e C
urr
ent (μ
A)
Time (Hours)0 200 400 600 800 1000
Time (hrs)
100
80
60
40
20
0Ava
lan
che
Cu
rre
nt
(mA
)
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• E-Series™ SiC diodes & MOSFETs qualified under JEDEC standards and successfully completed automotive (AEC) qualification
• MOS threshold stability (VT), Oxide lifetime in TDDB , and Accelerated HTRBmeasurements reveal long lifetime in standard use conditions
Summary
© 2018 Cree, Inc. All rights reserved © 2018 Cree, Inc. All rights reserved
Thank you! Questions?