si4368dy

Vishay SiliconixSi4368DY

Document Number: 72704S11-0209-Rev. D, 14-Feb-11

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N-Channel Reduced Qg, Fast Switching MOSFET

FEATURES • Halogen-free According to IEC 61249-2-21

Definition • Extremely Low Qgd for Switching

Losses Improvement • TrenchFET® Gen II Power MOSFET

• 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC

APPLICATIONS • Low-Side DC/DC Conversion

- Notebook, Server, VRM Module

• Fixed Telecom

PRODUCT SUMMARY VDS (V) RDS(on) () ID (A)

300.0032 at VGS = 10 V 25

0.0036 at VGS = 4.5 V 22

S

S

D

D

D

S

G D

SO-8

5

6

7

8

Top View

2

3

4

1

Ordering Information: Si4368DY-T1-E3 (Lead (Pb)-free)Si4368DY-T1-GE3 (Lead (Pb)-free and Halogen-free)

D

G

S

N-Channel MOSFET

Notes: a. Surface mounted on 1" x 1" FR4 board.

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)Parameter Symbol 10 s Steady State Unit

Drain-Source Voltage VDS 30V

Gate-Source Voltage VGS ± 12

Continuous Drain Current (TJ = 150 °C)aTA = 25 °C

ID25 17

A

TA = 70 °C 20 13

Pulsed Drain Current (10 µs Pulse Width) IDM 70

Continuous Source Current (Diode Conduction)a IS 2.9 1.3

Avalanch Current L = 0.1 mH IAS 50

Maximum Power Dissipationa TA = 25 °CPD

3.5 1.6W

TA = 70 °C 2.2 1

Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C

THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambientat 10 s

RthJA29 35

°C/WSteady State 67 80

Maximum Junction-to-Foot (Drain) Steady State RthJF 13 16

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Notes:a. Pulse test; pulse width 300 µs, duty cycle 2 %.b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 0.6 1.8 V

Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 12 V ± 100 nA

Zero Gate Voltage Drain Current IDSSVDS = 30 V, VGS = 0 V 1

µAVDS = 30 V, VGS = 0 V, TJ = 55 °C 5

On-State Drain Currenta ID(on) VDS 5 V, VGS = 10 V 30 A

Drain-Source On-State Resistancea RDS(on) VGS = 10 V, ID = 25 A 0.0026 0.0032

VGS = 4.5 V, ID = 22 A 0.0029 0.0036

Forward Transconductancea gfs VDS = 15 V, ID = 25 A 150 S

Diode Forward Voltagea VSD IS = 2.9 A, VGS = 0 V 0.66 1.1 V

Dynamicb

Input Capacitance Ciss

VDS = 15 V, VGS = 0 V, f = 1 MHz

8340

pFOutput Capacitance Coss 850

Reverse Transfer Capacitance Crss 355

Total Gate Charge Qg

VDS = 15 V, VGS = 4.5 V, ID = 20 A

53 80

nCGate-Source Charge Qgs 17.5

Gate-Drain Charge Qgd 6.5

Gate Resistance Rg f = 1 MHz 0.8 1.2 1.8 Turn-On Delay Time td(on)

VDD = 15 V, RL = 15 ID 1 A, VGEN = 10 V, Rg = 6

25 38

ns

Rise Time tr 20 30

Turn-Off Delay Time td(off) 172 260

Fall Time tf 41 62

Source-Drain Reverse Recovery Time trr IF = 2.9 A, dI/dt = 100 A/µs 42 60

Output Characteristics

0

10

20

30

40

50

60

0 1 2 3 4 5

VGS = 10 V thru 3 V

2 V

VDS - Drain-to-Source Voltage (V)

- D

rain

Cur

rent

(A

)I D

Transfer Characteristics

0

10

20

30

40

50

60

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50

25 °C

TC = 125 °C

- 55 °C

VGS - Gate-to-Source Voltage (V)

- D

rain

Cur

rent

(A

)I D


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On-Resistance vs. Drain Current

Gate Charge

Source-Drain Diode Forward Voltage

0.000

0.001

0.002

0.003

0.004

0.005

0 10 20 30 40 50

VGS = 10 V

- O

n-R

esis

tanc

e (

)R

DS

(on)

ID - Drain Current (A)

VGS = 4.5 V

0

1

2

3

4

5

6

0 15 30 45 60 75

VDS = 15 VID = 20 A

- G

ate-

to-S

ourc

e V

olta

ge (

V)

Qg - Total Gate Charge (nC)

VG

S

1.0 1.20.1

10

60

0 0.2 0.4 0.6 0.8

TJ = 150 °C

VSD - Source-to-Drain Voltage (V)

- S

ourc

e C

urre

nt (

A)

I S

1TJ = 25 °C

Capacitance

On-Resistance vs. Junction Temperature

On-Resistance vs. Gate-to-Source Voltage

0

2000

4000

6000

8000

10000

0 5 10 15 20 25 30

Crss

VDS - Drain-to-Source Voltage (V)

C -

Cap

acita

nce

(pF

)

Coss

Ciss

0.6

0.8

1.0

1.2

1.4

1.6

- 50 - 25 0 25 50 75 100 125 150

VGS = 10 VID = 25 A

TJ - Junction Temperature (°C)

(Nor

mal

ized

)

- O

n-R

esis

tanc

e R

DS

(on)

0.000

0.002

0.004

0.006

0.008

0.010

0 2 4 6 8 10

ID = 25 A

- O

n-R

esis

tanc

e (

)R

DS

(on)

VGS - Gate-to-Source Voltage (V)

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Threshold Voltage

- 0.8

- 0.6

- 0.4

- 0.2

0.0

0.2

0.4

- 50 - 25 0 25 50 75 100 125 150

ID = 250 µA

Var

ianc

e (V

)V

GS

(th)

TJ - Temperature (°C)

Single Pulse Power

0

30

60

10

20

Pow

er (

W)

Time (s)

40

50

1 100 6001010 -110 -2

Safe Operating Area, Junction-to-Case

100

1

0.01 1 10 1000.01

10

1 s

0.1 TC = 25 °CSingle Pulse

10 ms

100 ms

DC

0.1

Limited byRDS(on)*

10 s

VDS - Drain-to-Source Voltage (V)* VGS > minimum VGS at which RDS(on) is specified

-D

rain

Cur

rent

(A)

I D

Normalized Thermal Transient Impedance, Junction-to-Ambient

10 -3 10 -2 1 10 60010 -110 -4 100

2

1

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Nor

mal

ized

Effe

ctiv

e Tr

ansi

ent

The

rmal

Impe

danc

e

1. Duty Cycle, D =

2. Per Unit Base = RthJA = 67 °C/W

3. TJM - TA = PDMZthJA(t)

t1t2

t1t2

Notes:

4. Surface Mounted

PDM


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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see www.vishay.com/ppg?72704.

Normalized Thermal Transient Impedance, Junction-to-Foot

10- 3 10- 2 1 1010- 110- 4

2

1

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Nor

mal

ized

Effe

ctiv

e T

rans

ient

The

rmal

Impe

danc

e

Vishay SiliconixPackage Information

Document Number: 7119211-Sep-06

www.vishay.com1

DIMMILLIMETERS INCHES

Min Max Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.20 0.004 0.008

B 0.35 0.51 0.014 0.020

C 0.19 0.25 0.0075 0.010

D 4.80 5.00 0.189 0.196

E 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.50 0.93 0.020 0.037

q 0° 8° 0° 8°

S 0.44 0.64 0.018 0.026

ECN: C-06527-Rev. I, 11-Sep-06DWG: 5498

431 2

568 7

HE

h x 45

C

All Leads

q 0.101 mm

0.004"LB A1

A

e

D

0.25 mm (Gage Plane)

SOIC (NARROW): 8-LEADJEDEC Part Number: MS-012

S

V I S H A Y S I L I C O N I X

TrenchFET® Power MOSFETs Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

AP

PL

ICA

TIO

N N

OT

E

Document Number: 70740 www.vishay.comRevision: 18-Jun-07 1

Wharton McDaniel

Surface-mounted LITTLE FOOT power MOSFETs useintegrated circuit and small-signal packages which havebeen been modified to provide the heat transfer capabilitiesrequired by power devices. Leadframe materials anddesign, molding compounds, and die attach materials havebeen changed, while the footprint of the packages remainsthe same.

See Application Note 826, Recommended Minimum PadPatterns With Outline Drawing Access for Vishay SiliconixMOSFETs, (http://www.vishay.com/ppg?72286), for thebasis of the pad design for a LITTLE FOOT SO-8 powerMOSFET. In converting this recommended minimum padto the pad set for a power MOSFET, designers must maketwo connections: an electrical connection and a thermalconnection, to draw heat away from the package.

In the case of the SO-8 package, the thermal connectionsare very simple. Pins 5, 6, 7, and 8 are the drain of theMOSFET for a single MOSFET package and are connectedtogether. In a dual package, pins 5 and 6 are one drain, andpins 7 and 8 are the other drain. For a small-signal device orintegrated circuit, typical connections would be made withtraces that are 0.020 inches wide. Since the drain pins servethe additional function of providing the thermal connectionto the package, this level of connection is inadequate. Thetotal cross section of the copper may be adequate to carrythe current required for the application, but it presents alarge thermal impedance. Also, heat spreads in a circularfashion from the heat source. In this case the drain pins arethe heat sources when looking at heat spread on the PCboard.

Figure 1. Single MOSFET SO-8 PadPattern With Copper Spreading

Figure 2. Dual MOSFET SO-8 Pad PatternWith Copper Spreading

The minimum recommended pad patterns for thesingle-MOSFET SO-8 with copper spreading (Figure 1) anddual-MOSFET SO-8 with copper spreading (Figure 2) showthe starting point for utilizing the board area available for theheat-spreading copper. To create this pattern, a plane ofcopper overlies the drain pins. The copper plane connectsthe drain pins electrically, but more importantly providesplanar copper to draw heat from the drain leads and start theprocess of spreading the heat so it can be dissipated into theambient air. These patterns use all the available areaunderneath the body for this purpose.

Since surface-mounted packages are small, and reflowsoldering is the most common way in which these areaffixed to the PC board, “thermal” connections from theplanar copper to the pads have not been used. Even ifadditional planar copper area is used, there should be noproblems in the soldering process. The actual solderconnections are defined by the solder mask openings. Bycombining the basic footprint with the copper plane on thedrain pins, the solder mask generation occurs automatically.

A final item to keep in mind is the width of the power traces.The absolute minimum power trace width must bedetermined by the amount of current it has to carry. Forthermal reasons, this minimum width should be at least0.020 inches. The use of wide traces connected to the drainplane provides a low impedance path for heat to move awayfrom the device.

0.0270.69

0.0781.98

0.25.07

0.1965.0

0.2887.3

0.0501.27

0.0270.69

0.0781.98

0.25.07

0.0882.25

0.2887.3

0.0501.27

0.0882.25

Application Note 826Vishay Siliconix

www.vishay.com Document Number: 7260622 Revision: 21-Jan-08

A

PP

LIC

AT

ION

NO

TE

RECOMMENDED MINIMUM PADS FOR SO-8

0.24

6

(6.2

48)

Recommended Minimum PadsDimensions in Inches/(mm)

0.172

(4.369)

0.15

2

(3.8

61)

0.04

7

(1.1

94)

0.028

(0.711)

0.050

(1.270)

0.022

(0.559)

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Revision: 02-Oct-12 1 Document Number: 91000

DisclaimerALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVERELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose orthe continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and allliability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particularpurpose, non-infringement and merchantability.

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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustainingapplications or for any other application in which the failure of the Vishay product could result in personal injury or death.Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Pleasecontact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

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Material Category PolicyVishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill thedefinitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Councilof June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm thatall the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Freerequirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make referenceto the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21conform to JEDEC JS709A standards.

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