si design guideforddr2-ddr3pcb_eng2

45
SI Design Guide for DDR2/3 PCB 46

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Page 1: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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Page 2: Si design guideforddr2-ddr3pcb_eng2

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Page 3: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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Page 4: Si design guideforddr2-ddr3pcb_eng2

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Page 5: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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Page 6: Si design guideforddr2-ddr3pcb_eng2

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Page 7: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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Page 8: Si design guideforddr2-ddr3pcb_eng2

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Page 9: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

Output Buffer

= Diff. SSTL Class1 8mA (Altera FPGA)

(Output Impedance = 25.7 Ohm)

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Page 10: Si design guideforddr2-ddr3pcb_eng2

VIH=+250mV

VIL=-250mV

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Page 11: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

473mV

VIH=+250mV

VIL=-250mV

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Page 12: Si design guideforddr2-ddr3pcb_eng2

OUT

PULLUP

PULLDOWN

logic_in

enable

inv_outV2

0

1

2

W=0.12mmP=45mmSP=0.1mm

IN

POWER

GND

OUT

inv_in

IN

POWER

GND

OUT

inv_in

0

0

V+-

Name=required

1

2

W=0.12mmP=5mmSP=0.1mm

1

2

W=0.12mmP=5mmSP=0.1mm

1

2

W=0.12mmP=10mmSP=0.1mm

1

2

W=0.12mmP=10mmSP=0.1mm

100

R26

V+-

Name=required1

VIH=+250mV

VIL=-250mV

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Page 13: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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Page 14: Si design guideforddr2-ddr3pcb_eng2

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Page 15: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

VIH=1.15V

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Page 16: Si design guideforddr2-ddr3pcb_eng2

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Page 17: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

40dB 34dB

498MHz(3rd Harmonic)

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Page 18: Si design guideforddr2-ddr3pcb_eng2

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Page 19: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

Memory Controller

I/O I/O

DDR2 Memory

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Page 20: Si design guideforddr2-ddr3pcb_eng2

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Page 21: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

ODT_Disable

ODT_150Ohmn

ODT_75Ohm

ODT_50Ohm

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Page 22: Si design guideforddr2-ddr3pcb_eng2

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Page 23: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

TL2 TL1

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Page 24: Si design guideforddr2-ddr3pcb_eng2

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Page 25: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

3. DDR2 SI Simulation Guide

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Page 26: Si design guideforddr2-ddr3pcb_eng2

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Page 27: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

Memory Controller

(BGA type)

DDR2 Memory

DQ / DM / DQS / Clock

Address / CMD / Ctrl

trace

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Page 28: Si design guideforddr2-ddr3pcb_eng2

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Page 29: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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Page 31: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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Page 33: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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Page 35: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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SI Design Guide for

DDR2/3 PCB

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SI Design Guide for

DDR2/3 PCB

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SI Design Guide for

DDR2/3 PCB

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Page 43: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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Page 44: Si design guideforddr2-ddr3pcb_eng2

4. Automatic Verification

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Page 45: Si design guideforddr2-ddr3pcb_eng2

SI Design Guide for

DDR2/3 PCB

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