si cmos for rf power applications · 2005-09-27 · si cmos for rf power applications j. a. del...
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![Page 1: Si CMOS for RF Power Applications · 2005-09-27 · Si CMOS for RF Power Applications J. A. del Alamo MIT Workshop on Advanced Technologies for Next Generation of RFIC 2005 RFIC Symposium](https://reader033.vdocuments.us/reader033/viewer/2022041915/5e691acaaa96e93e87567146/html5/thumbnails/1.jpg)
Si CMOS for RF Power Applications
J. A. del AlamoMIT
Workshop on Advanced Technologies for Next Generation of RFIC2005 RFIC Symposium June 12, 2005
Sponsors: DARPA, IBM, SRC
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RF power applications
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0
10
20
30
40
50
0.1 1 10 100 1000
Frequency [GHz]
Out
put P
ower
[dB
m]
GaAs HEMTInP HEMTSi BJTSiGe HBTGaAs / InP HBTGaAs MESFETGaN HEMTLDMOSCMOS
Power vs. frequency
Compilation of research papers from IEEE Xplore
by J. Scholvin
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Research activity by material and frequency
Compilation of research papers from IEEE Xplore by J. Scholvin
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licat
ions
per
Yea
r SiCInPGaNGaAsSilicon
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licat
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r above 27 GHz3 to 27 GHzbelow 3 GHz
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RF power technologies: 1993 vs. 2003
Compilation of research papers from IEEE Xplore by J. Scholvin
GaAs MESFET34%
InP HEMT12%
GaAs HBT12%
GaAs HEMT37% LDMOS
5%
1993
2003
SiC 3%
GaAs MESFET5%
GaN HEMT16%
InP HBT3%
InP HEMT3%
GaAs HBT16%
GaAs HEMT22%
CMOS16%
LDMOS5%
Si BJT3%
SiGe HBT10%
Silicon34%
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RF Power Figures of Merit
• PA specs:
– Frequency
– Power– Gain– Linearity– Voltage– Reliability – Power efficiency– Cost
PA
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Fundamental trade-off between voltage and frequency
scaling
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Key to power: supply voltage
0.0001
0.001
0.01
0.1
1
10
100
0.1 1 10 100
Vdd [V]
Pow
er D
ensi
ty [W
/mm
]
GaN HEMTGaAs & InP HBT
LDMOS
CMOS
GaAs MESFET
HEMT
Si BJTSiGe HBT
Compilation of research papers from IEEE Xplore by J. Scholvin
Wf
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0
20
40
60
80
100
0.1 1 10 100 1000
Frequency [GHz]
Pow
er A
dded
Effi
cien
cy [%
]GaAs/InP HBTInP HEMTGaAs HEMTGaAs MESFETCMOSSiGe HBTLDMOS
Key to frequency: efficiency
Compilation of research papers from IEEE Xplore by J. Scholvin
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The benefits of scaling
0
20
40
60
0 0.2 0.4 0.6 0.8 1Lg [µm]
Pea
k P
AE
[%]
All FETs
27 GHz < f < 50 GHz
Compilation of research papers from IEEE Xplore by J. Scholvin
scaling
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Si CMOS: a disruptive technology for RF power?
0.01
0.1
1
10
1970 1980 1990 2000 2010Year
Phy
sica
l Gat
e Le
ngth
[µm
]
III-V'sCMOSCMOS Roadmap
Gate length scaling in III-V FETs and CMOS
Compilation of research papers from IEEE Xplore
by J. Scholvin
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Si MOSFETs for RF power
0
10
20
30
40
50
0.1 1 10 100 1000
Frequency [GHz]
Out
put P
ower
[dB
m]
GaAs HEMTInP HEMTSi BJTSiGe HBTGaAs / InP HBTGaAs MESFETGaN HEMTLDMOSCMOS
1. Extending LDMOS beyond 2 GHz 2. RF power suitability of deeply scaled CMOS
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1. Extending LDMOS beyond 2 GHz
(PhD Thesis of J. Fiorenza)SourceSource
• Two critical sources of RF Loss:– Gate resistance loss: reduces power gain– Substrate loss: reduces power efficiency
Drain
Gate
Drain
Gate
LDMOSFET: Lightly-doped Drain MOSFET
n+n-n+
Pn+
Source Drain
n-
Gaten+n-n+
Pn+
Source Drain
n-
Gate
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n-
300 nm
50 nm50 nm
AlTiN
PolySiGate Oxide 20 or 30 nm
n-
300 nm
50 nm50 nm
AlTiN
PolySiGate Oxide 20 or 30 nm
Low-loss gate: Metal/Poly-Si damascene gate
Advantages:
– Implemented in the back end of process– Allows the use of Al or Cu: very low gate resistance– Self-aligned: no increase in overlap capacitance – Gate oxide undisturbed
Achieved: 0.2 ohm/sqr (>10 for polySi, ~1 for silic’d gate)
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Metal/Poly-Si Damascene Gate
3 μm
Source
Gate Drain
200 μm
Lg = 0.6 μm ft ~ 15 GHz BVoff > 18 V
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0.6 μm minimum Lg
10 mask levels
2 levels of metal
Fabricated at MIT
Test chip
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Benefit of low gate resistance: small signal
Damascene gate increases fmax, enables wide gate fingers
Source
Source
Drain
Gat
e
Wf
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Benefit of low gate resistance: large signal
High PAE with gate finger width up to 140 μm
Source
Source
Drain
Gat
e
Wf
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Low-loss substrates: SOI and high-resistivity Si
Substrate:
• Regular Si
• High-resistivity Si
Handle wafer:
• Regular Si
• High-resistivity Si
Drain
Gate
Drain
Gaten+n-n+
Pn+
Source Drain
n-
Gate
n+n-n+
P n+
Source Drain
n-
Gate
Bulk Si Thin-film SOI
Drain
Gate
Drain
Gaten+n-n+
Pn+
Source Drain
n-
Gate
n+n-n+
Pn+
Source Drain
n-
Gate
n+n-n+
P n+
Source Drain
n-
Gate
Bulk Si Thin-film SOI
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Impact of substrate
• SOI improves PAE• High-resistivity silicon improves PAE on bulk • High-resistivity silicon does not improve PAE on SOI
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Beyond 2 GHz
Low-loss substrate very important at high frequencies
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Analysis of substrate loss
Gate
Source
Drain Loss
Drain Pad
Pad Loss
• Pad Loss: • SOI effective
• HR effective on bulk Si and SOI
• Drain Loss:• SOI somehow effective
• HR very effective on bulk Si, only moderately on SOI
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Why is HRSOI Ineffective?
Drain Pad
Gate
Source
HRSOI
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
RsubRsurf
Cbox
n+pn+
Surface inversion increases drain loss on HRSOI
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Effect of substrate inversion in HRSOI-LDMOS
30
35
40
45
50
55
60
-30 -20 -10 0 10 20 30
VHS [V]
Pea
k P
AE
[%]
4.8 GHz
2.4 GHz
+- VHS
HRSOI
RFin RFout
Load-Pull Measurement
• Eliminating substrate inversion improves PAE• Most prominent at high frequencies
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Impact of inversion layer elimination
45
50
55
60
Bulk HR Bulk SOI HR SOI
Pea
k P
AE
[%]
Substrate
Enhancement due to elimination of inversion layer
f=1.9 GHz
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Impact of inversion layer elimination
30
35
40
45
50
55
60
65
2 3 4 5 6 7 8Frequency [GHz]
peak
PA
E [%
]
VHS = 5.5 V
VHS = 0 V
0
2
4
6
8
10
12
14
-10 -5 0 5 10 15 20 25Output Power [dBm]
Gai
n [d
B]
0
10
20
30
40
50
60
PA
E [%
]
f = 4.8 GHz36x40 µmVdd = 3.6 V Id = 10 mA
VHS=5.5 V
VHS=0 V
• Eliminating substrate surface effects improves performance:– Particularly prominent in LDMOS due to large drain area– Both linear and saturated performance– Most prominent at high frequencies
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0
10
20
30
40
50
0.1 1 10 100 1000
Frequency [GHz]
Out
put P
ower
[dB
m]
GaAs HEMTInP HEMTSi BJTSiGe HBTGaAs / InP HBTGaAs MESFETGaN HEMTLDMOSCMOS
Si MOSFETs for RF power
1. Extending LDMOS beyond 2 GHz 2. RF power suitability of deeply scaled CMOS
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2. RF power suitability of deeply scaled CMOS(PhD Thesis of J. Scholvin)
Attractiveness of CMOS:• System-on-Chip integration• Low cost• Low voltage• Good device models• Aggressive roadmap• Wide flavor of devices available
Suitable for:• High-volume, low cost consumer applications • Moderate frequencies (2-10 GHz)• Medium power (<100 mW)• Current: WLAN, Bluetooth, Cell-phone PA driver, WiMax/802.16
Picture from: http://www.intel.com/research/silicon/micron.htm#silicon
90 nm CMOS
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• Concerns: CMOS scaling ⇒ Vdd ↓ ⇒ Pout ↓
• Possible solutions:– Raise Vdd ⇒ impact on reliability– Use I/O devices ⇒ not really scaling
Issues of CMOS for RF power
data for IEEE published CMOS PA devices and circuits
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90 nm CMOS: there is a lot more than 90 nm devices!
• Includes devices with longer gate lengths and thicker gate oxides for I/O drivers and high V operation
• Designed RF power devices in collaboration with IBM
thick(51A)
medium(22 A)
thin (14 A)
Oxide thickness
2.51.21.0Nominal voltage [V]
xxxLg = 250 nmxxLg = 130 nm
xLg = 90 nm
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The benefits of scaling for RF
• Logic devices at optimized bias point have very high bandwidth• But… power devices at class AB bias point have much less bandwidth
0
50
100
150
200
90 nm 130 nm 250 nm
Device type
f max
(GH
z)
power device
logic device
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RF power performance ofstandard 90 nm devices
Vdd = 1 V, Id = 26 mA/mmf = 2.2 GHz48x16 µm (1 cell)8 x 48x16 (8 cell)
• 1 cell: Peak PAE = 66% at Pout = 12.5 dBm• 8 cell: Peak PAE = 59% at Pout = 20.2 dBm
0
10
20
30
40
50
60
70
-20 -10 0 10 20 30
Pout [dBm]
Gai
n [d
B],
PA
E [%
]
Gain
PAE
1 cell8 cells
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Linear performance of 90 nm CMOS
Vdd = 1 VId = 26 mA/mmfreq = 2.2 GHz8x48x16 µm
• What is PAE at a given IM3 ?– at IM3 = -35 dBc, PAE = 12% at Pout = 12 dBm
• Exceeds WCDMA PA driver specs
0
10
20
30
40
50
60
70
-20 -10 0 10 20 30
Pout [dBm]
PA
E [%
]
-100
-80
-60
-40
-20
0
IM3 [
dBc]IM3
PAE
WCDMA PA driver spec
-35 dBc
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90 nm vs. 250 nm devices at 8 GHz
• At Vdd = 1 V, 90 nm has best PAE and Pout
• 250 nm device offers highest power density at Vdd=2.5 V
0
10
20
30
40
50
60
70
0.1 1.0 10.0Vdd [V]
Pea
k P
AE
[%]
5
10
15
20
25
30
Out
put P
ower
Den
sity
[dB
m a
t 1 m
m]
Lg = 90nm, Thin OxLg = 250nm, Thick Ox
Pout
freq = 8 GHzId = 26 mA/mm
PAE
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90 nm vs. 250 nm
• 250 nm thick oxide device has higher Vds,sat⇒ compresses earlier and softer ⇒ lower Pout and peak PAE
• As Vdd ↑ impact of Vds,sat decreases
90 nm, thin oxide 250 nm, thick oxideVgs = 1V Vgs = 2.4V
0.1V steps 0.2V steps
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What about reliability?
For RF power, reliability related to ratio of:
• nominal Vdd
• to breakdown voltage
For RF power:
• 90 nm device expected to be more reliable at Vdd=1 V than 250 nm device at 2.5 V
0
1
2
3
4
5
6
90 nm 130 nm 250 nm
Device type
BV o
ff, V
nom (V
)
Vnom
BVoff
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Reliability: impact of output power
• Run device under continuous RF power conditions• Measure drop in gain over time, define MTTF as 0.2 dB drop• Power compression has huge impact on degradation
Vdd = 1.6 VId = 26 mA/mmf = 8 GHz48x16 μm
0
20
40
60
-20 -10 0 10Input Power [dBm]
Gai
n [d
B],
PA
E [%
]
Gain
PAE
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.01 0.1 1 10 100 1000Time [minutes]
Cha
nge
in G
ain
[dB
]
Pout = 17.6 dBm
17.4 dBm
17.2 dBm
16.8 dBm
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Reliability: impact of Vdd
• For same Vdd, thick oxide is more reliable– but thin oxide has better performance
• For identical lifetime, how does performance compare?
Impedances and RF power set for peak PAE
Id = 26 mA/mmfreq = 8 GHz
0.01
0.1
1
10
1 10Vdd [V]
Mea
n Ti
me
to F
ailu
re [h
ours
]
90 nmthin oxide
250 nmthick oxide
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Reliability: impact of Vdd
Impedances and RF power set for peak PAE
Id = 26 mA/mmfreq = 8 GHz
0.01
0.1
1
10
1 10Vdd [V]
Mea
n Ti
me
to F
ailu
re [h
ours
]
90 nmthin oxide
250 nmthick oxide
• 90 nm thin ox. outperforms 250 nm thick ox. for high MTTF– Low Vdd performance of 90 nm device much better than 250 nm device
PAE=58%, Pout=16.8 dBmPAE=56%, Pout=15.6 dBm
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Conclusions
• Metal-containing gates and low-loss substrates will project LDMOS to 5-6 GHz
• Deeply scaled CMOS suitable for RF power for:– Moderate power levels (~100 mW)– Very low operating voltage (~1 V and below)
• Scaling will project CMOS beyond 10 GHz
• Si-based RF power technologies will dominate many high-volume consumer applications:– WLANs, bluetooth, cellphone PA drivers, RF tags, etc
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MIT’s RF power measurement setup
– 1.8 - 18 GHz Maury ATS automatic load-pull system– 8-inch Cascade on-wafer probe station– Synthesized source with 10 W TWT-PA supplying up to 200 mW at DUT
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References
• LDMOS:– Bengtsson: MTT 2003– Fiorenza: SOI Conf. 1999; MTT-S 2001; IEDM 2002,
EDL 2001, 2003, 2005; TED 2002– Scholvin: IEDM 2003– Van der Heijden: MTT-S 2001
• 90 nm CMOS:– Ferndahl: MGWL 2003– Scholvin: IEDM 2004