si and ge nw fets, nisi-si-nisi conductor hetero-structures and manufacturing steps csaba andras...

Si and Ge NW FETs, NiSi-Si-NiSI conductor hetero-structures and manufacturing steps

Csaba Andras MoritzAssociate ProfessorUniversity of Massachusetts, [email protected]

Copyright - Csaba Andras Moritz , ECE, UMass Amherst 2

From Nanodevices to Nano Computing

Lauhon et al., Nature 420,57

Carbon Nanotubes (CNT)

Semiconductor Nanowires (NW)

NanoarrayTransistors or Diodes

Nanocircuit

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Nanocomputing


Nanowires

From Lieber, Nanoscience: Building a Big Future


Nanowires


Nanowire Materials

From Lieber, Nanoscience: Building a Big Future


Comparison of NWs and CNTs

Controlled doping of CNTs is not possible Specific growth of semiconducting and conducting tubes

is not possible These properties depend sensitively on diameter and helicity in

CNTs Semiconductor NWs overcome these limitations

Vast knowledge in the semiconductor industry Remain semiconducting independent on diameter Controlled doping demonstrated, e.g., with Boron for p-type and

Phosphorus for n-type for SiNWs Change the conductivity of SiNWs over many orders of magnitude Measured with Transmission Electron Microscopy (TEM)


P and N-type SiNW (FETs)

Yi Cui et al, The Journal of Physical Chemistry, 2000


Electron charging

Yi Cui et al, 2000


Specializing NWs

Control of composition, structure, size, doping

Diameter controlled during growth As small as 3nm

Stable electronic characteristics


FETs

PFETs and NFETs in SiNWs, GaNi NWs Both PFETs and NFETs in same material with Si and Ge

NWs and CNTs Greytak et al, American Institute for Physics, 2004 IBM Nanoscience Group lead by Davouris demonstrated CNTs


Ge based complementary FETs

Complementary doping demonstrated in Si, GaN, and now Ge Has been used to assemble inverters, bipolar

transistors and light emitting diodes Achieving p-FET and n-FET in same material was

challenging Ge has higher electron and hole mobility than Si

and both P and N type devices have been demonstrated


Synthesis of p and n-type Ge NWs

Core-shell method, doping with PH3 for N and B2H6 for P

From Greytak et al, 2004


P and N-type Ge FETs

Ge NWs with Ti S-D contacts

Vd – drain-source bias voltage, Id the current through the channel,Vg- gate voltage

Curves characteristic of MOS FETs

Yield 86%

From Greytak et al, 2004


Comparison with Si and GaN FETs

Higher on currents than in those devices Higher mobilities and smaller Vth possible

Deposition of Ge oxynitride or SiGe capping layer

Optimization of the doping procedure


Nanoarrays

Nanowires are aligned with Longmuir-Blodgett fluidic alignment

Can be packed into NW arrays


Nanoarrays


Metal/semiconductor nanowire heterostructures MW-NW contacts

Lithographically defined metal contacts with electrodes

Problem: size scale – much larger than nanoscale Cannot be used for interconnect between FETS on a

grid Integrated interconnect and contact solution

based on selective transformation of Si NWs into NiSi nanowires Yue Wu et al, Nature 2004.


Why NiSi?

Has been shown to have low resistivity (10 uOhmcm) Compatibility with Si manufacturing FET with NiSi/p-Si/NiSi junction

Si channel of 20-nm in a 10-nm diameter structure Ability to form ohmic contacts with p and n type silicon High maximum currents – 29-nm NiSi-NW would carry

1.84 mA Current density comparable to CNTs


NiSi/Si Nanowire Heterostructures

Wu et al., Nature Vol. 430, pp. 61, 2004

Deposit Ni (green) to NW (blue)

React at 550 。 C to form NiSi NW

(brown)

Etch to remove excess Ni

Lithography maskSelectively deposit NiForm NiSi segments NWs as masksForm NiSi segments on Si NWs

Si NWs


Modulation doped NWs for decoders


Very large scale integration

Nanowires assembled to form structures of 1,000 to 30,000

Assembled and interconnected

> 80% yield


Our approach:Nano circuits based on nanoarrays and FETs Why not use 2-terminal devices?

There are several approaches resembling PLA and cell-based FPGA like nanoFabrics, nanoPLA, CMOL

We are interested in building processor datapaths Need for latching etc Much higher density can be achieved even in 2-D fabrics

Even in 2-terminal arrays there is a need for signal restoration based on FETs (see nanoPLA)

We want to know what the benefits would be and what the challenges are from an architects point-of-view


Manufacturing steps for large scale 2-D computing with NW FETs (NASICs) Combination of self-assembly and nano lithography Self-assembly

Form NW array with correct doping of wires Initial metallization between crosspoints using one set of wires as the mask Create channel regions for FETs at cross-points

Nanolitography and conventional lithography Additional specialization of crosspoints with NiSi metallization Sub 10-nm imprint lithography

Stephen Chou et al, University of Minnesota, 1997 Not based on modification of chemical structure by radiation, its resolution is immune to many factors

that limit the resolution of conventional lithography, such as wave diffraction, scattering and interference in resist, and the chemistry of the resist and developer

Micro-nano interfacing selective chemical modification (Zhong et al Science 2003) Several other proposals (coded NWs radial doping, Distributed pin array, etc)

CMOS support structures

si and ge nw fets, nisi-si-nisi conductor hetero-structures and manufacturing steps csaba andras...

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