sheet 6: operational amplifiers compensation, analysis and
TRANSCRIPT
The German University in Cairo
Electronics Dept., Faculty of IET
Course: Microelectronics (ELCT 703)
Dr. Eman Azab Semester: 7th Electronics
Eng. Radwa Khairy Winter 2019
Sheet 6: Operational Amplifiers Compensation, Analysis and Design
Problem 1: A two-stage, Miller-compensated CMOS op amp has a RHP zero at 20GB, a dominant pole
due to the Miller compensation, a second pole at p2 and a mirror pole(due to current mirror
parasitic capacitance) at -3GB.
a) If GB is 1MHz, find the location of p2 corresponding to a 45ยฐ phase margin.
b) Assume that in part (a) that |p2| = 2GB and a nulling resistor is used to cancel p2.
What is the new phase margin assuming that GB = 1MHz?
c) Using the conditions of (b), what is the phase margin if CL is increased by a factor of
4?
Given: ๐๐ = ๐๐๐ฎ๐ฉ ; ๐๐๐ ; ๐๐๐ ; ๐๐๐ = โ๐๐ฎ๐ฉ
Solution:
a)
๐ด๐ฃ(๐ ) =๐ด๐ฃ๐ (1 โ
๐ ๐๐
)
(1 +๐
๐๐๐) (1 +
๐ ๐๐๐
) (1 +๐
๐๐๐)
โต ๐๐ = 180๐ + ๐โ๐๐ ๐(๐ด๐ฃ(๐บ๐ต))
๐๐ = 180๐ โ tanโ1 (๐บ๐ต
๐๐
) โ tanโ1 (๐บ๐ต
๐๐๐
) โ tanโ1 (๐บ๐ต
๐๐๐
) โ tanโ1 (๐บ๐ต
๐๐๐
)
๐๐ = 180๐ โ tanโ1 (๐บ๐ต
๐๐๐ฎ๐ฉ) โ tanโ1(๐ด๐ฃ๐) โ tanโ1 (
๐บ๐ต
๐๐๐
) โ tanโ1 (๐บ๐ต
๐๐ฎ๐ฉ)
โด ๐๐ = 180๐ โ 2.862๐ โ 90๐ โ tanโ1 (๐บ๐ต
๐๐๐
) โ 18.435๐
โต ๐๐ = 45๐
2
โด tanโ1 (๐บ๐ต
๐๐๐
) = 23.703๐
โด๐บ๐ต
๐๐๐
= 0.439
โด ๐๐๐ = 2.278๐บ๐ต
โด ๐๐๐ =1 ร 106 ร 2 ร ๐
0.439= 14.312 ๐๐๐๐/๐ ๐๐
b) Nulling resistor is used to cancel P2
โด ๐ด๐ฃ(๐ ) =๐ด๐ฃ๐
(1 +๐
๐๐๐) (1 +
๐ ๐๐๐
)
๐๐ = 180๐ โ tanโ1 (๐บ๐ต
๐๐๐
) โ tanโ1 (๐บ๐ต
๐๐๐
)
๐๐ = 180๐ โ tanโ1(๐ด๐ฃ๐) โ tanโ1 (๐บ๐ต
๐๐ฎ๐ฉ)
๐๐ = 71.565๐
c) If we increased load capacitor by factor 4
โต ๐๐๐ =๐๐6
๐ถ๐ฟ
This means that ๐๐๐ will be decreased by factor 4
โด ๐๐๐ =2๐บ๐ต
4= 0.5๐บ๐ต
3
The zero is located at P2 in part B
โด ๐ค๐ง = โ2๐บ๐ต
โด ๐ด๐ฃ(๐ ) =๐ด๐ฃ๐ (1 +
๐ ๐๐
)
(1 +๐
๐๐๐) (1 +
๐ ๐๐๐
) (1 +๐
๐๐๐)
๐๐ = 180๐ + tanโ1 (๐บ๐ต
๐๐
) โ tanโ1 (๐บ๐ต
๐๐๐
) โ tanโ1 (๐บ๐ต
๐๐๐
) โ tanโ1 (๐บ๐ต
๐๐๐
)
๐๐ = 180๐ + tanโ1 (๐บ๐ต
๐๐ฎ๐ฉ) โ tanโ1(๐ด๐ฃ๐) โ tanโ1 (
๐บ๐ต
๐. ๐๐ฎ๐ฉ) โ tanโ1 (
๐บ๐ต
๐๐ฎ๐ฉ)
๐๐ = 34.4๐
4
Problem 2:
For the two-stage op amp of Fig.1, find W1/L1, W6/L6, and Cc if GB 1 MHz, p25 GB, z
3 GB and CL 40 pF. Use the parameter values of Table1 and consider only the two-pole
model of the op amp. The bias current in M5 is 40ฮผA and in M7 is 320ฮผA.
Given:
GB 1 MHz;p25 GB, z 3 GB and CL 40 pF. Use the parameter values of
Table1 and consider only the two-pole model of the op amp. The bias current in
M5 is 40ฮผA and in M7 is 320ฮผA,๐๐๐ถ๐๐ฅ = 110๐๐ด/๐2, ๐๐๐ถ๐๐ฅ = 50๐๐ด/๐2
๐๐๐ = โ๐๐๐ = 0.7๐, ๐๐ = 0.04 ๐โ1, ๐๐ = 0.05 ๐โ1
5
Solution:
โต ๐๐๐ =๐๐6
๐ถ๐ฟ
โด ๐๐6 = 2 ร ๐ ร 5 ร 106 ร 40 ร 10โ12 = 1.257 ๐๐ด/๐
โต ๐๐6 = โ2๐พ6๐ผ๐ท6
๐ผ๐ท6 = ๐ผ๐ท7 = 320 ๐๐ด
โต ๐พ6 =๐๐6
2
2๐ผ๐ท6= 2.469 ๐๐ด/๐2
๐พ6 =๐๐๐ถ๐๐ฅ๐
๐ฟ
(๐
๐ฟ)
6=
๐พ6
๐๐๐ถ๐๐ฅ= 49.38 โ 50
โต ๐ค๐ง =๐๐6
๐ถ๐ถ
โด ๐ถ๐ถ =๐๐6
๐ค๐ง=
1.257๐
2 ร ๐ ร 3 ร 1 ร 106= 66.69 ๐๐น
โต ๐บ๐ต =๐๐1
๐ถ๐ถ
โด ๐๐1 = ๐บ๐ต ร ๐ถ๐ถ = 2 ร ๐ ร 1 ร 106 ร 66.69 ร 10โ12 = 0.419 ๐๐ด/๐
โต ๐๐1 = โ2๐พ1๐ผ๐ท1
๐ผ๐ท1 =๐ผ๐ท5
2= 20 ๐๐ด
โต ๐พ1 =๐๐1
2
2๐ผ๐ท1= 4.389 ๐๐ด/๐2
๐พ1 =๐๐๐ถ๐๐ฅ๐
๐ฟ
(๐
๐ฟ)
1=
๐พ1
๐๐๐ถ๐๐ฅ= 39.9 โ 40
6
Problem 3:
For the CMOS op amp shown, find the following quantities. Use the MOS parameters of
Table1.
1.) Slew rate (V/sec.)
2.) Positive and negative output voltage limits (all transistors remain in saturation)
3.) Positive and negative input common voltage limits (all transistors remain in
saturation)
4.) Small signal voltage gain (V/V).
5.) Unity-gain bandwidth (MHz)
6.) Power dissipation (mW). (Include the 50_A current sink)
Solution:
1.
๐๐ =๐ผ๐ท5
๐ถ๐=
50๐
5๐= 10 ๐/๐๐ ๐๐
2. The maximum output voltage when M7 is still operating in saturation
mode
๐๐๐ข๐ก,๐๐๐ฅ = ๐๐ท๐ท โ ๐๐๐ท7,๐ ๐๐ก = ๐๐ท๐ท โ โ2๐ผ๐ท7
๐พ7
7
๐๐๐ข๐ก,๐๐๐ฅ = 2.5 โ โ2 ร 250๐
50๐ ร 50= 2.0527 ๐
The minimum output voltage when M6 is still operating in saturation mode
๐๐๐ข๐ก,๐๐๐ = ๐๐๐ + ๐๐ท๐6,๐ ๐๐ก = ๐๐๐ + โ2๐ผ๐ท6
๐พ6
๐๐๐ข๐ก,๐๐๐ = โ2.5 + โ2 ร 250๐
110๐ ร 50= โ2.198 ๐
3. The maximum input voltage when M5 is still operating in saturation mode
๐๐๐,๐๐๐ฅ = ๐๐ท๐ท โ ๐๐๐บ1,๐ ๐๐ก โ ๐๐๐ท5,๐ ๐๐ก = ๐๐ท๐ท โ โ2๐ผ๐ท1
๐พ1โ |๐๐๐1| โ โ
2๐ผ๐ท5
๐พ5
๐๐๐,๐๐๐ฅ = 2.5 โ โ2 ร 25๐
50๐ ร 10โ 0.7 โ โ
2 ร 50๐
50๐ ร 10= 1.0366 ๐
The minimum input voltage when M1 is still operating in saturation mode
๐๐๐,๐๐๐ = ๐๐๐ + ๐๐บ๐3,๐ ๐๐ก โ |๐๐๐1| = ๐๐๐ + โ2๐ผ๐ท3
๐พ3โ |๐๐๐1| + ๐๐๐3
๐๐๐,๐๐๐ = โ2.5 + โ2 ร 25๐
110๐ ร 10= โ2.287 ๐
8
4.
๐ด๐ฃ๐ = ๐๐1๐ ๐๐ข๐ก1 ร ๐๐6๐ ๐๐ข๐ก2
๐ ๐๐ข๐ก1 = ๐๐๐ 2// ๐๐๐ 4 =1
(๐๐ + ๐๐)๐ผ๐ท2
= 0.444 ๐ฮฉ
๐ ๐๐ข๐ก2 = ๐๐๐ 6// ๐๐๐ 7 =1
(๐๐ + ๐๐)๐ผ๐ท7
= 44.4 ๐พฮฉ
โด ๐๐1 = โ2 ร 25๐ ร 10 ร 50๐ = 0.158 ๐๐ด/๐
โด ๐๐6 = โ2 ร 250๐ ร 50 ร 110๐ = 1.658 ๐๐ด/๐
โด ๐ด๐ฃ๐ = 0.158๐ ร 0.444๐ ร 1.658๐ ร 44.4๐พ = 5164.25
5.
๐บ๐ต =๐๐1
๐ถ๐=
0.158๐
5๐ร
1
2๐= 5.03 ๐๐ป๐ง
6.
๐๐๐๐ ๐ = 2๐๐ท๐ท(๐ผ๐ท8 + ๐ผ๐ท5 + ๐ผ๐ท7) = 1.75๐๐
9
Problem 4: A two-stage, BiCMOS op amp is shown. For the PMOS transistors, the model Parameters are
KPโ=50_A/V2, VTP = -0.7V and _P = 0.05V-1. For the NPN BJTs, the model parameters are
ฮฒF = 100, VCE(sat) = 0.2V, VA = 25V, Vt = 26mV, Is = 10fA and ฮท=1.
a) Identify which input is positive and which input is negative.
b) Find the numerical values of differential voltage gain, Av(0), GB (in Hertz), the slew
rate, SR, and the location of the RHP zero.
c) Find the numerical value of the maximum and minimum input common mode
voltages.
Given: KPโ=50_A/V2, VTP = -0.7V and _P = 0.05V-1;For the NPN BJTs, the model
parameters are๐ฝ๐น = 100, VCE(sat) = 0.2V, VA = 25V, Vt = 26mV,Is = 10fA and
ฮท=1.
Solution:
1. Since the gain of the input stage is inverting for V2 and non- inverting
for V1 and the gain of the second stage is inverting therefore V2 is the
positive(non-inverting) terminal; while V1 is the negative
(inverting)terminal
2.
๐ด๐ฃ๐ = ๐ด๐ฃ1 ร ๐ด๐ฃ2
10
๐ด๐ฃ1 = โ๐๐1๐ ๐๐ข๐ก1
โด ๐๐1 = โ2 ร 25๐ ร 10 ร 50๐ = 0.158 ๐๐ด/๐
๐ ๐๐ข๐ก1 = ๐๐๐ 2// ๐๐4 = 0.8๐ฮฉ//1๐ฮฉ = 0.44๐ฮฉ
๐ด๐ฃ2 = โ๐๐6๐ ๐๐ข๐ก2
๐ ๐๐ข๐ก2 = ๐๐๐ 7// ๐๐6 = 0.2๐ฮฉ//0.25๐ฮฉ = 0.111๐ฮฉ
โด ๐๐6 =๐ผ๐ถ6
๐๐=
100๐
26๐= 3.846 ๐๐ด/๐
โด ๐ด๐ฃ๐ = 0.158๐ ร 0.44๐ ร 3.846๐ ร 0.111๐ = 29678.5
๐บ๐ต =๐๐1
๐ถ๐=
0.158๐
5๐ร
1
2๐= 5.03 ๐๐ป๐ง
๐๐ =๐ผ๐ท5
๐ถ๐=
50๐
5๐= 10 ๐/๐๐ ๐๐
โต ๐ค๐ง =๐๐6
๐ถ๐ถ= 769.2 ๐๐๐๐/๐ ๐๐
3.
The maximum input voltage when M5 is still operating in saturation
mode
๐๐๐,๐๐๐ฅ = ๐๐ท๐ท โ ๐๐๐บ1 โ ๐๐๐ท5,๐ ๐๐ก
๐๐๐,๐๐๐ฅ = ๐๐ท๐ท โ โ2๐ผ๐ท1
๐พ1โ |๐๐๐1| โ โ
2๐ผ๐ท5
๐พ5
๐๐๐,๐๐๐ฅ = 1.5 โ โ2 ร 25๐
50๐ ร 10โ 0.7 โ โ
2 ร 50๐
50๐ ร 10= 0.0366 ๐
11
The minimum input voltage when M1 is still operating in saturation
mode
๐๐๐,๐๐๐ = ๐๐๐ + ๐๐ต๐ธ3 โ |๐๐๐1|
๐๐๐,๐๐๐ = ๐๐๐ + ๐๐๐๐ (๐ผ๐ถ3
๐ผ๐๐ ) โ |๐๐๐1|
๐๐๐,๐๐๐ = โ1.5 + (0.026 ร ๐๐ (25๐
10๐)) โ 0.7 = โ1.637 ๐
12
Problem 5: The figure below shows the internal circuit of the 741-opamp. Q11, Q12, and R5 generate a
reference bias current, IREF. Q10, Q9, and Q8 bias the input stage, which is composed of Q1 to
Q7. The second gain stage is composed of Q16 and Q17 with Q13B acting as active load. The
class AB output stage is formed by Q14 and Q20 with biasing devices Q13A, Q18, and Q19, and
an input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against
output short circuits and are normally cut off.
Given: ๐ฝ = 250, the reverse saturation current Io =10-14mA for all transistors except
Q14 and Q20 (Io14(or 20)) =3*10-14mA.
Required: (1) All the DC collector currents.
(2) Explain the operation of the SC protection circuit.
(3) Find the input resistance, output resistance and the voltage gain of the input and
second stages assuming the loading effect is neglected and the output stage is ideal
buffer. Assuming VAn =100 V and VAp=50V
(4) Draw the complete small signal model of the op-amp and find the overall gain.
(5) Find the high frequency gain of this op-amp assuming CC is the dominant
capacitance in the circuit.
(6) Find GB and SR of the 741-op-amp.
13
Solution:
1. All DC collector currents
a. For the input stage
The current source Q11 and Q10
๐ผ๐๐๐ =2๐๐ถ๐ถ โ ๐๐ต๐ธ11 โ ๐๐ธ๐ต12
๐ 5=
30 โ 1.4
39๐พ= 0.73 ๐๐ด
14
Neglecting all base currents
๐ผ๐๐๐ = ๐ผ๐ถ11 = ๐ผ๐ถ12
Q11 and Q10 form a current mirror called Widlar current mirror; so they are
matched and operating in the active region
๐๐ต๐ธ11 = ๐๐ต๐ธ10 + ๐ผ๐ถ10๐ 4
๐๐ต๐ธ11 โ ๐๐ต๐ธ10 = ๐ผ๐ถ10๐ 4
๐๐๐๐ (๐ผ๐ถ11
๐ผ๐ถ10) = ๐ผ๐ถ10๐ 4
Using trial and error we will calculate the
Collector current of Q10
๐ผ๐ถ10 = 18.4๐๐ด
Q10 and Q9 are connected in series and we
will neglect the base current of Q3 and Q4
๐ผ๐ถ10 = ๐ผ๐ถ9 = 18.4 ๐๐ด
Q8 and Q9 are a current mirror and we will neglect their bases currents
โด ๐ผ๐ถ8 = ๐ผ๐ถ9 = 18.4 ๐๐ด
For the differential amplifier Q1 and Q2 we work at the optimum DC
operating point ๐๐ผ๐ท = 0๐
๐ผ๐ถ1 = ๐ผ๐ถ2 =๐ผ๐ถ8
2= 9.2 ๐๐ด
Since all transistors have very large ๐ฝ so we can assume that
๐ผ๐ถ โ ๐ผ๐ธ
๐ผ๐ธ1 โ ๐ผ๐ถ1 = ๐ผ๐ธ3 โ ๐ผ๐ถ3
15
๐ผ๐ถ3 = ๐ผ๐ถ4 = 9.2 ๐๐ด
Q5 and Q3 are in series ; Q4 and Q6 are in series neglecting the base currents
(note that Q5 and Q6 act as a current mirror)
๐ผ๐ถ5 = ๐ผ๐ถ6 = 9.2 ๐๐ด
For Q7 we will find itโs emitter current
๐ผ๐ธ7 = ๐ผ๐ต5 + ๐ผ๐ต6 + ๐ผ๐ 3
๐ผ๐ธ7 =๐ผ๐ถ5
๐ฝ+
๐ผ๐ถ6
๐ฝ+ ๐ผ๐ 3
๐ผ๐ 3 =๐๐ต๐ธ6 + ๐ผ๐ถ6๐ 2
๐ 3=
๐๐๐๐ (๐ผ๐ถ6
๐ผ๐๐) + ๐ผ๐ถ6๐ 2
๐ 3
๐ผ๐ 3 =25๐ ร ๐๐ (
9.2๐10โ14) + 9.2๐ ร 1๐พ
50๐พ= 10.5 ๐๐ด
๐ผ๐ธ7 =9.2๐
250+
9.2๐
250+ 10.5 ๐ = 10.58 ๐๐ด
For the gain stage
Q13 is equivalent to two transistors
Each one has a part of its total collector
current
Io13B=0.75 Io
Io13A=0.25 Io
16
Q12 and Q13 form a current mirror so they have the same collector currents
โต ๐ผ๐ถ,13๐ต = 0.75๐ผ๐ถ12 = 547.5 ๐๐ด
๐ผ๐ถ17 = ๐ผ๐ถ,13๐ต = 547.5 ๐๐ด
For Q16:
๐ผ๐ธ16 = ๐ผ๐ต17 + ๐ผ๐ 9
๐ผ๐ธ16 =๐ผ๐ถ17
๐ฝ+ ๐ผ๐ 9
๐ผ๐ 9 =๐๐ต๐ธ17 + ๐ผ๐ถ17๐ 8
๐ 9=
๐๐๐๐ (๐ผ๐ถ17
๐ผ๐๐) + ๐ผ๐ถ17๐ 8
๐ 9= 13.46 ๐๐ด
โด ๐ผ๐ธ16 โ ๐ผ๐ถ16 = 15.65 ๐๐ด
For the output stage:
17
Q15, Q21, Q24, Q22 are normally off as they are turned on only when the
output node is short circuit.
Ignore the base currents for Q14 and Q20
โต ๐ผ๐ถ,13๐ด = 0.25๐ผ๐ถ12 = 182.5 ๐๐ด
๐ผ๐ถ23 = ๐ผ๐ถ,13๐ด = 182.5 ๐๐ด
๐ผ๐ถ23 = ๐ผ๐ 10 + ๐ผ๐ธ18
Assume that ๐๐ต๐ธ18 = 0.6 ๐
๐ผ๐ 10 =๐๐ต๐ธ18
๐ 10= 15๐๐ด
โด ๐ผ๐ธ18 = ๐ผ๐ถ23 โ ๐ผ๐ 10 = 167.5 ๐๐ด
โด ๐ผ๐ถ19 โ ๐ผ๐ถ13,๐ด โ ๐ผ๐ธ18 = 15๐๐ด
As for Q14 and Q20 (class AB push-pull)
Assume that ๐๐ต๐ธ14 = ๐๐ธ๐ต20
2๐๐ต๐ธ14 = ๐๐ต๐ธ18 + ๐๐ต๐ธ19
๐๐ต๐ธ14 = 0.559๐
๐ผ๐ถ14 = ๐ผ๐ถ20 = ๐ผ๐๐14๐๐ฅ๐ (๐๐ต๐ธ14
๐๐) = 154.15 ๐๐ด
2. If the output node is grounded and ๐๐ keeps increasing and with it the
base and collector currents of Q14 increases as well; thus the power
dissipated in Q14 increases so that it may damage or destroy the
transistor;
By connecting R6 and Q15 as the collector current of Q14 increases
the voltage drop across R6 increase till it turns on Q15 and thus part of
the base current of Q14 will flow through Q15 and the power
dissipation decreases;
18
Note that during the negative clock cycle R7 and Q23 will protect Q20
from damage by the same way.
3. AC analysis for the op-amp:
The input stage:
๐ ๐๐1 = ๐๐1 +๐๐3(1 + ๐ฝ1)
(1 + ๐ฝ3)+ ๐๐4 +
๐๐2(1 + ๐ฝ4)
(1 + ๐ฝ2)
19
Since Q1, Q2, Q3, Q4 have same ๐ฝ & ๐ผ๐ถ then they have same ๐๐
๐ ๐๐1 = 4๐๐1 = 2.72 ๐ฮฉ
๐ ๐๐ข๐ก1 = [๐๐4 + (1 + ๐๐4๐๐4)๐๐2
1 + ๐ฝ] //[๐๐6 + (1 + ๐๐6๐๐6)๐ 2]
โด ๐ ๐๐ข๐ก1 = 6.26 ๐ฮฉ
๐ฃ๐๐ข๐ก1 = โ2๐ฝ๐๐1๐ ๐๐ข๐ก1
โต ๐๐1 =๐ฃ๐๐
๐ ๐๐1
โด๐ฃ๐๐ข๐ก1
๐ฃ๐๐=
โ2๐ฝ๐ ๐๐ข๐ก1
4๐๐1=
โ๐๐1๐ ๐๐ข๐ก1
2= โ1151.84
Let
๐๐1๐๐ =๐๐1
2= 0.193 ๐๐ด/๐
โด ๐ด๐ฃ1 =๐ฃ๐๐ข๐ก1
๐ฃ๐๐= โ๐๐1๐๐๐ ๐๐ข๐ก1
For the second stage:
20
๐ฃ๐๐ข๐ก2 = (1 + ๐ฝ)๐๐16๐ 9
๐๐16 =๐ฃ๐๐ข๐ก1
๐๐16 + (1 + ๐ฝ)๐ 9
โด๐ฃ๐๐ข๐ก2
๐ฃ๐๐ข๐ก1=
(1 + ๐ฝ)๐ 9
๐๐16 + (1 + ๐ฝ)๐ 9
โต ๐ฃ๐๐ข๐ก = โ๐ฝ๐๐17๐ ๐๐ข๐ก2
๐๐17 =๐ฃ๐๐ข๐ก2
๐๐17 + (1 + ๐ฝ)๐ 8
โด๐ฃ๐๐ข๐ก
๐ฃ๐๐ข๐ก2=
โ๐ฝ๐ ๐๐ข๐ก2
๐๐17 + (1 + ๐ฝ)๐ 8
โด๐ฃ๐๐ข๐ก
๐ฃ๐๐ข๐ก1=
๐ฃ๐๐ข๐ก2
๐ฃ๐๐ข๐ก1ร
๐ฃ๐๐ข๐ก
๐ฃ๐๐ข๐ก2
โด ๐ด๐ฃ2 =๐ฃ๐๐ข๐ก2
๐ฃ๐๐ข๐ก1=
โ๐ฝ๐ ๐๐ข๐ก2
๐๐17 + (1 + ๐ฝ)๐ 8ร
(1 + ๐ฝ)๐ 9
๐๐16 + (1 + ๐ฝ)๐ 9
Let
๐๐2๐๐ =๐ฝ
๐๐17 + (1 + ๐ฝ)๐ 8ร
(1 + ๐ฝ)๐ 9
๐๐16 + (1 + ๐ฝ)๐ 9= 6.6 ๐๐ด/๐
๐ ๐๐ข๐ก2 = ๐๐13๐ต//[๐๐17 + (1 + ๐๐17๐๐17)๐ 8] = 78.95๐พฮฉ
โด ๐ด๐ฃ2 =๐ฃ๐๐ข๐ก2
๐ฃ๐๐ข๐ก1= โ๐๐2๐๐๐ ๐๐ข๐ก2 = โ524.52
๐ ๐๐2 = ๐๐16 + (1 + ๐ฝ)(๐ 9//(๐๐17 + (1 + ๐ฝ)๐ 8)) = 5.695 ๐ฮฉ
21
4.
The overall gain:
๐ฃ๐๐ข๐ก1 = โ๐๐1๐๐(๐ ๐๐ข๐ก1//๐ ๐๐2)๐ฃ๐๐
๐ฃ๐๐ข๐ก = โ๐๐2๐๐๐ ๐๐ข๐ก2๐ฃ๐๐ข๐ก1
โด๐ฃ๐๐ข๐ก
๐ฃ๐๐= ๐๐1๐๐๐๐2๐๐(๐ ๐๐ข๐ก1//๐ ๐๐2)๐ ๐๐ข๐ก2 = 285713.1
โด๐ฃ๐๐ข๐ก
๐ฃ๐๐ ๐๐ต
= 20๐๐๐ (๐ฃ๐๐ข๐ก
๐ฃ๐๐) = 109.12 ๐๐ต
5.
From the lectures we have
๐ด๐ฃ(๐) โ ๐ด๐ฃ๐
(1 +๐
๐ค1)
๐ค1 =1
๐ถ๐ถ๐๐2๐๐(๐ ๐๐ข๐ก1//๐ ๐๐2)๐ ๐๐ข๐ก2= 21.467 ๐๐๐/๐ ๐๐
ineqm vg 1inv 1outv1inR 1outR
+
-
2inR 12 outeqm vg 2outR outv
ineqm vg 1inv 1outv1inR 1outR
+
-
2inR 12 outeqm vg 2outR outv
CC
22
OR using Miller theorem:
๐ถ1 = ๐ถ๐ถ(1 โ ๐ด)
๐ถ2 = ๐ถ๐ถ(1 โ ๐ดโ1)
โต ๐ด =๐ฃ๐๐ข๐ก
๐ฃ๐๐ข๐ก1=
โ๐๐2๐๐๐ ๐๐ข๐ก2๐ฃ๐๐ข๐ก1
๐ฃ๐๐ข๐ก1
โด ๐ด = โ๐๐2๐๐๐ ๐๐ข๐ก2 = โ521.07
โด ๐ถ1 = 15.67 ๐๐น
โด ๐ถ2 = 30.06 ๐๐น
โด ๐ด๐ป๐น =๐ฃ๐๐ข๐ก
๐ฃ๐๐= ๐๐1๐๐๐๐2๐๐ (๐ ๐๐ข๐ก1//๐ ๐๐2//
1
๐๐ถ1) (๐ ๐๐ข๐ก2//
1
๐๐ถ2)
โด ๐ด๐ป๐น =๐ด๐๐น
(1 +๐
๐ค1) (1 +
๐๐ค2
)
Where
๐ค1 =1
๐ถ1(๐ ๐๐ข๐ก1//๐ ๐๐2)= 21.27 ๐๐๐/๐ ๐๐
๐ค2 =1
๐ถ2๐ ๐๐ข๐ก2= 4.21 ร 1023 ๐๐๐/๐ ๐๐
It is clear that ๐ค1 is the dominant pole
6.
๐บ๐ต = ๐ด๐ฃ๐๐1 = 285713.1 ร21.467
2๐โ 1 ๐๐ป๐ง
๐๐ =๐ผ๐ถ8
๐ถ๐ถ= 0.613 ๐/๐๐ ๐๐