sharing a high speed optical data transmission link with slow control stream

SHARING A HIGH SPEED OPTICAL DATA TRANSMISSION LINK WITH SLOW CONTROL STREAM

TIPP2014Amsterdam June 2-6 2014

Zhen-An LIU, Jingzhou Zhao, Dehui Sun, Trigger Lab IHEP, BeijingR. Itoh, H. Nakao, IPNS, KEK

Z.-A. LIU TIPP2014 in Amsterdam 2

• Overview of experiment data readout• Components for a high speed data transmission link(Hslink)

• Requirement of the slow control/parameter setting•Sharing Hslink with slow control in Belle II• Test results and status• Summary

Outline

2014-6-6




Outline

2014-6-6


• Fast Control• Clocks, trigger, reset,…

• Slow Control• GAS, HV,LV,….• CAMAC/VME/CPCI… crate BUS

• Gains, thresholds, Peds, window size, delay….

Tranditional Experiment Block Diagram

DetectorsWeak Elec. Signals

FE ElectronicsAmp. + Shaping

Digitizer

Trigger/Fast Control

Onl. Readout

Offline Analysis

Data Storage

Phys. Process

粒子

Slow Control

PC/Crate

2014-6-6


• FEE + DIGI near Detector• No crate for FEE, no bus anymore. • High speed data transmission link to back end readout

• FEE parameter setting is very important! BUT how?• Share with the Fast link?

Modern Experiment Block Diagram

Stand al one FEE

Fast data Li nk

Back End readout

EV Bui l der Onl i ne

Modern Experi ment Bl ock Di agram

2014-6-6




Outline

2014-6-6


General high speed link

• Single direction up link: Front to Back End •

2014-6-6

FIFO_FE

PROTOCOL&control

16bit32bi

tFrom

FEE TTC

interface

GTP

CLK_LKCLK_FE

GTP

Optical fiber

rece

iver

BL_SNDR

BL_RSVR

16bit

32bit16bit FIFO_CO

PROTOCOL&control

CLK_LK

FEE interface

COPPER interface

Nev_FE

16bit

Optical transceiver not shown




Outline

2014-6-6


General high speed link with SC

• Up and Down links• Modify the protocol parts on both sides,

• Fast&SC control in receiver side• FEE/SC control

2014-6-6

FIFO_FE

PROTOCOL&control

16bit32bi

tFrom

FEE TTC

interface

GTP

CLK_LKCLK_FE

GTP

Optical fiber

rece

iver

BL_SNDR

BL_RSVR

16bit

32bit16bit FIFO_CO

PROTOCOL&control

CLK_LK

FEE/SC interface

Fast & Slow control interface

Nev_FE

16bit

Optical transceiver not shown




Outline

2014-6-6


Belle2link in Belle II experiment• Unified high speed data readout and transmission

2014-6-6

Bellle2Link

Requirement to Belle2LinkBelle2Link is a name for global fast data readout and transmission

between Detector Front-End Electronics(FEE) and Back-End DAQ system of Belle II experiment. It features, with system simplicity and reliability, as:

1.unification in hardware design(for each detector sub-system)2.unification in firmware design(for each detector sub-system)3.provides electrical isolation 4.provides high speed transmission rate5.work at different input data rate(with different detector sub-system)6.home brew transmission protocol

d

SVD FEE

COPPER HS links

RF ClocK

CDC FEE

………PID

KLM TTC

I/F_FE

I/F_TTC

I/F_COPPER

Slow control


• Implementation of Slow Control• Parameter setting only• Unification, suitable for all

systems, not system dependent

• Easy implementation for FEE as was with Belle FINESSE

• Provide CDC implementation as an example for FEE

• Tested working with CDC

Requirement for Slow Control/parameter setting in Belle II

d

SVD FEE

COPPER HS links

RF ClocK

CDC FEE………

PIDKLM TTD

I/F_FE

I/F_TTC

I/F_COPPER

Slow control

Belle2Link: A unified fast data collection and transmission plus slow control function

2014-6-6


• Difficulties• Larger parameter data size(>128byte) needed• How to make the belle2link transparent to FEE and local buss

• New scheme has to be defined• FEE and HSLB share the address on local bus• Both FEE board and HSLB have the independent version records.

Local Bus Interface

Address Description Note

0x00-0x74 User defined

0x75 HSLB CSR

0x76 FEE FW Ver. # Mandatory

0x77 FEE HW Ver. # Mandatory

0x78 FEE Type Mandatory

0x79 Belle2link FEE FW ver. # Mandatory

0x7a HSLB Download Flag2

0x7b HSLB Download Flag1

0x7c Belle2link HSLB CPLD Ver.

0x7d Belle2link HSLB FW ver. # Mandatory

0x7e Belle2link HSLB HW ver. # Mandatory

0x7f Reserved mandatory

2014-6-6


• FEE side(Parameter Bus)• Keep the definition of local

bus of COPPER.• AB0-AB6: Local address bus.• DB0-DB7: Local data bus.• LWR: Read/write direction

indicator.• EN: ready signal.

• An indicated address 0x00 is for serial transmission

The FEE registers are are transparent to COPPER via Belle2link .

Implementation of Slow Control2014-6-6


• Receicer side (HSLB/FINESSE side)Two approaches)

• First approach• Large

stream(>128B)• Address 0X00: for

this approach• Second approach

• Large stream(<128B or individual setting )

• Address 0X01-0x74: Length up to 127B

• Address/Data meaning definition by user

Implement on FEE side

2014-6-6


Firmware Description-Structure of HSLB firmware

• Protocol• Send the slow control command after packing• Receive the package from GTP module• Check the packages and unpack them• Separate the data and transfer them to slow control module or data link module

• Data Link module• Receive the data of FEE, transmit the data and the clock to the COPPER FIFO

2014-6-6

Send after

packing


Firmware Description —Structure of Belle2lin firmware in FEE

• Protocol• Receive the package from GTP module, check the packages and unpack them, put to the

FEE slow control. Slow control send result to SC module• Transfer the data form FEE, and arbitrate the priority between slow control module and data

link module• Data Link module

• Receive the data from FEE. Pack the data

2014-6-6


Firmware Description-Structure of HSLB firmware

• Protocol• Send the slow control command after packing• Receive the package from GTP module• Check the packages and unpack them• Separate the data and transfer them to slow control module or data link module

• Data Link module• Receive the data of FEE, transmit the data and the clock to the COPPER FIFO

2014-6-6




Outline

2014-6-6


Model system--Joint test at KEK

Setup: CDC-Prototype + 16ch FEE + fiber+ HSLB +COPPER + VME crate + File server

Data from radioactive source Line rate: 3.125Gbps Data sample

3M events collected 10k events analyzed

controlled trigger rate

FPGACDC readoutFPGA

HSLRB

FPGAHSLRB

Line rate=1.5GbpsCLK_Lk=200MHz,CLK_FEE=125MHz

CLK_Lk=200MHz,CLK_CO=42.3MHzOn board reset switch

2014-6-6


Cosmic Ray test on CDC detectorCDC FEE

Test signals

and trigger

COPPER

HSLBs

Fibers

TTD

2014-6-6


Status • Slow Control/Parameter setting is part of Belle2link.• Belle2link Working Group responsible the plantation to

other systems• CDC, SVD, EMC are successful and expect no error with

other system. More tests will be made to the remaining systems.

• Installation stating next year.

2014-6-6


• Sharing HSLink with slow control makes system simple.

• As part of the Belle2link of Belle II experiment, slow control/parameter setting has been proved reliable.

• Tests with different systems shouwed that sharing HSLink with slow control is feasible basically in all case.

Many Thanks for your attention !

Summary

2014-6-6

sharing a high speed optical data transmission link with slow control stream

Documents

liu tipp2014

slow controlgas

belle iitest results

fastsc control

global fast data readout

receiver sidefeesc control

fast link

end daq system of belle