shared memory & synchronization

Upload: invasion101

Post on 04-Jun-2018

241 views

Category:

Documents


0 download

TRANSCRIPT

  • 8/13/2019 Shared Memory & Synchronization

    1/19

    Multicore Programming

    Shared Memory & Synchronization

    Tutorial 5CS 0368-3469Spring 2010

  • 8/13/2019 Shared Memory & Synchronization

    2/19

    2

    Summary

    Registers

    AtomicMRSWRegister Q.

    Consensus

    Queue Q.

    Team consensus Q.

  • 8/13/2019 Shared Memory & Synchronization

    3/19

    3 2007 Herlihy & Shavit 3

    Safe Register

    write(1001)

    Some valid value ifreads and writes do

    overlap

    read(????)

    0000 1001 1111

    $*&v

  • 8/13/2019 Shared Memory & Synchronization

    4/19

    4 2007 Herlihy & Shavit 4

    Regular Register

    write(0)

    read(1)

    write(1)

    read(0)

    Single Writer Readers return:

    Old value if no overlap (safe) Old or one of new values if overlap

  • 8/13/2019 Shared Memory & Synchronization

    5/19

    5 2007 Herlihy & Shavit 5

    Atomic Register

    write(1001)

    read(1001)

    Linearizable to sequential saferegister

    write(1010)

    read(1010)

    read(1010)

  • 8/13/2019 Shared Memory & Synchronization

    6/19

    6Art of Multiprocessor Programming 6

    Safe Boolean MRSW fromSafe Boolean SRSW

    public classSafeBoolMRSWRegisterimplementsRegister {privateSafeBoolSRSWRegister[] r =newSafeBoolSRSWRegister[N];public voidwrite booleanx) {for intj = 0; j < N; j++)r[j].write x);}public booleanread ) {inti = ThreadID.get );returnr[i].read );}}

  • 8/13/2019 Shared Memory & Synchronization

    7/19

    7

    Safe Boolean MRSW Qeustion

    True/False:

    If we replace the safe Boolean SRSWregisterswith regular Boolean SRSWregisters, then the constructionyields an regular BooleanMRSW

    register.

  • 8/13/2019 Shared Memory & Synchronization

    8/19

    8 2007 Herlihy & Shavit 8

    Safe Boolean MRSW Qeustion

    cont.

    time

    R[0]=1

    1/0read(R[1])

    1read(R[0])

    R[1]=1 R[2]=1

    0

    read(R[2])

  • 8/13/2019 Shared Memory & Synchronization

    9/19

    9

    AtomicMRSWRegister

    public classAtomicMRSWRegister implements Register {ThreadLocal lastStamp; // last timestamp writtenprivateStampedValue[][] a_table; // each entry is SRSW atomic

    publicAtomicMRSWRegister(T init, intreaders) {this.lastStamp = newThreadLocal() {

    protected LonginitialValue () { return 0; };};a_table = newStampedValue[readers][readers];StampedValue value = newStampedValue(init);for(inti = 0; i < readers; i++){

    for(intj = 0; j < readers; j++){a_table[ i ][ j ] = value;}

    }}

  • 8/13/2019 Shared Memory & Synchronization

    10/19

    10

    AtomicMRSWRegister

    publicT read() {intme = ThreadID.get();StampedValue value = a_table[me][me]; // former read

    for(inti = 0; i < a_table.length ; i++) // finds max in rowvalue = StampedValue.max(value, a_table[me][i]);

    for(inti = 0; i < a_table.length ; i++) // writes max in columna_table[i][me] = value;

    returnvalue ;}

  • 8/13/2019 Shared Memory & Synchronization

    11/19

    11

    AtomicMRSWRegister

    publicvoid write (T v){longstamp = lastStamp.get() + 1;

    lastStamp.set( stamp);// remember for next time

    StampedValue value = newStampedValue(stamp, v);

    // writes a column

    for(inti = 0; i < a_table.length ; i++)a_table [i][0] = value;}

  • 8/13/2019 Shared Memory & Synchronization

    12/19

    12 2007 Herlihy & Shavit 12

    AtomicMRSWRegister

    1:45 1234 1:45 12341:45 1234

    1:45 1234 1:45 1234

    1:45 1234

    One per thread

    1:45 1234

    1:45 1234

    1:45 1234

    1 2 3

    1

    23

  • 8/13/2019 Shared Memory & Synchronization

    13/19

    13

    AtomicMRSWRegister

    QeustionTrue/False:

    If we replace the atomicSRSWregisters with regularSRSWregisters, then the construction stillyields an atomicMRSWregister.

  • 8/13/2019 Shared Memory & Synchronization

    14/19

    14 2007 Herlihy & Shavit 14

    AtomicMRSWRegister

    Qeustion cont.

    time

    write(2:00 5678)

    read(1:45 1234)

    1:451234

    read(2:00 5678)

    In which caseits OK to read

    1234

    Yes it does, because regular registers act differently only whentwo reads are done concurrently with a write.

  • 8/13/2019 Shared Memory & Synchronization

    15/19

    15 2007 Herlihy & Shavit 15

    AtomicMRSWRegister

    Qeustion cont.

    time

    write(2:00 5678)

    read(2:00 5678)

    1:451234

    read(2:00 5678)

    In which case Bluewill complete writing2:00 5678 to its

    column

    read(1:45 1234)

  • 8/13/2019 Shared Memory & Synchronization

    16/19

    16

    AcmRegister Qeustion

    public classAcmRegister {//Atomic MRSW registersprivateBoolRegister[] b = newBoolRegister[3*N];

    public voidwrite(intx){

    boolean[] v = intToBooleanArray(x);

    for( inti=0 ; i

  • 8/13/2019 Shared Memory & Synchronization

    17/19

    17

    AcmRegister Qeustion cont.public classAcmRegister {

    public intread(){

    for( inti=0 ; i

  • 8/13/2019 Shared Memory & Synchronization

    18/19

    18

    AcmRegister Qeustion cont.

    If first == middle

    return firstElse If last == middlereturn last

    Else //writer in the middlereturn first

    http://creativecommons.org/licenses/by-sa/2.5/http://creativecommons.org/licenses/by-sa/2.5/
  • 8/13/2019 Shared Memory & Synchronization

    19/19

    19Art of MultiprocessorProgramming 19

    This work is licensed under a Creative Commons Attribution-ShareAlike 2.5 License.

    You are free:

    to Shareto copy, distribute and transmit the work

    to Remixto adapt the work

    Under the following conditions:

    Attribution. You must attribute the work to The Art ofMultiprocessor Programming (but not in any way that suggests thatthe authors endorse you or your use of the work).

    Share Alike. If you alter, transform, or build upon this work, youmay distribute the resulting work only under the same, similar or acompatible license.

    For any reuse or distribution, you must make clear to others the licenseterms of this work. The best way to do this is with a link to

    http://creativecommons.org/licenses/by-sa/3.0/.

    Any of the above conditions can be waived if you get permission fromthe copyright holder.

    Nothing in this license impairs or restricts the author's moral rights.

    http://creativecommons.org/licenses/by-sa/2.5/http://creativecommons.org/licenses/by-sa/2.5/http://creativecommons.org/licenses/by-sa/2.5/http://creativecommons.org/licenses/by-sa/2.5/http://creativecommons.org/licenses/by-sa/2.5/http://creativecommons.org/licenses/by-sa/2.5/http://creativecommons.org/licenses/by-sa/2.5/http://creativecommons.org/licenses/by-sa/2.5/http://creativecommons.org/licenses/by-sa/2.5/