Analog Integrated Circuits and Signal Processing, 24, 113±122, 2000

# 2000 Kluwer Academic Publishers. Manufactured in The Netherlands.

Settling Analysis of MOS Regulated Current Mirrors Applied toMicropower D/A Converters

J. A. DE LIMADepartment of Electrical Engineering, Universidade Estadual Paulista, FEG/DEE/UNESP, Av. Ariberto P Cunha, 333, P.O. Box 205, 12500,

Guaratingueta ± SP, Brazil

Email: delima@lexxa.com.br; delima@feg.unesp.br

Received January 27, 1998; Revised April 5, 1999; Accepted June 4, 1999

Abstract. This paper provides an insight to the trade-off between settling time and power consumption in

regulated current mirrors as building parts in micropower current-switching D/A converters. The regulation-loop

frequency characteristic is obtained and dif®culties to impose a dominant-pole condition to the resulting 2nd-order

system are evaluated. Raising pole frequencies in micropower circuits, while meeting consumption requirements,

is basically limited by parasitic capacitances. For such cases, an alternative is to impose a twin-pole condition in

which design constraints are somewhat relieved and settling slightly improved. Relationships between pole

frequencies, transistor geometry and bias are established and design guidelines for regulated current mirrors

founded. By placing loop-transistors in either weak or strong inversion, small �W/L� ratios are allowed and stray

capacitances reduced. Simulated waveforms suggest a good agreement with theory. The proposed approach

applied to the design of a micropower current-mode D/A converter improves both simulated and experimental

settling performance.

Key Words: micropower design, MOS regulated-cascode circuits, D/A converter, current mirrors

I. Introduction

Owing to its high output resistance, MOS regulated-

cascode current mirrors [1] can be employed in high-

precision analog signal processing circuits [2,3].

However, poles introduced in the transmission

characteristic by the regulation loop, unless properly

placed along the negative s-plane axis, degrade their

settling behavior when used as building parts in

current-switching circuits. The good understanding of

the regulation-loop stability becomes important in

designing such circuits where power consumption and

settling time are permanently traded off. As example,

in precision micropower current-mode D/A con-

verters, due to ®nite output resistance and capacitive

coupling, switching noise is introduced into the

summing current node during digital-code updating,

affecting the voltage across binary-weighted current

sources, and consequently, their values. Depending on

the transmission characteristic of the regulation-loop,

the settling time of the output current may be

overextended to accommodate all internal current

variations. Regulation-loop optimal bias for speed and

power dissipation has been discussed in switched-

current samplers [2]. However, in such a particular

analysis, devices operate only in strong inversion and

are not limited to micropower consumption.

This paper addresses the settling behavior of

micropower regulated-cascode current mirrors as

building blocks to high-precision D/A converters.

Stability of the 2nd-order closed-loop transfer and

conditions to impose a dominant-pole system are

evaluated. Design constraints in raising pole frequen-

cies while keeping micropower exigencies lead to

alternately imposing a twin-pole system in these cases

with some advantages such as a more relaxed ratio

between internal capacitances and a slightly faster

settling. Relationships are established between pole

frequencies and design parameters such as transistor

sizing and bias current. Since analytical models for

weak and strong inversion regions are well-estab-

lished [4], transistor operation is limited to these

regions although analysis can be easily extended to

moderate inversion [5].

II. Regulation-Loop Stability Analysis

The symbols and parameters used in the present

analysis are listed in Table 1. Some basic MOSFET

modeling for a saturated device in weak and strong

inversion [4,5] is brie¯y reviewed in Table 2, with all

voltages referred to local substrate.

The schematic of a regulated-cascode current

mirror is shown in Fig. 1 where all devices are

assumed in saturation and mismatches between M1

and Mu are neglected. Output current Iout mirrors the

input current Iu with a scaling factor K���W=L�M1=�W=L�Mu�. By imposing a current IBIAS

across transistor M2, the regulation loop composed by

M2 and M3 ideally sets the drain voltage of M1

transistor at

Weak inversion :VGS2 � VTH2 � ZUT lnID

2ZbU2T

�1a�

Strong inversion :VGS2 � VTH2

����������������������������2�1� w�IBIAS

�W=L�2mnC0ox

s�1b�

A ®xed VDS thus reduces channel-modulation

effects. Increased by the feedback loop, the low-

frequency output resistance is

rout � ro1 � ro3�1� gmb3ro1�� gm3ro3�gm2ro2 � 1�ro1

�2�

where gmb3 accounts for transistor M3 body effect. As

usually gmb3ro1 4 1, gmb3ro3 4 1 and gmb2ro2 41, it turns out

rout � ro1ro3�gmb3 � gm3gm2ro2�% gm3ro3gm2ro2ro1

�3�

so that M1 drain resistance ro1 is multiplied by the

intrinsic small-signal voltage gain gmro of transistors

M2, M3.

Analysis of the equivalent small-signal circuit

shown in Fig. 2 gives the low and medium frequency

characteristic of the regulation loop. A small-signal

source represents the voltage perturbation on M3

drain, the D/A converter current-summing node,

Table 1. List of symbols and parameters.

UT � �kT=q� [V] Thermal voltage

C0ox �F=m2� Gate-oxide capacitance per unit area

Z [-] Subthreshold slope

FF [V] Fermi potential in the substrate

g �V1=2� Body-factor

W [m] Effective channel width

L [m] Effective channel length

Cj [F] Junction capacitance per unit area

Lov [m] Gate-drain overlapping,

Lx [m] Poly-Si gate and related-diffusion

edge distance

Ilim � 2ZbU2T [A] Maximum current in weak inversion

with

w � dVTH

dVBS� g

2������������������2FF�VSB�p , for small VDS

b � �W=L�mC0ox

Cox � WLC0ox

Table 2. Basic MOSFET modeling.

Weak Inversion Strong Inversion

ID 2ZbU2T exp

VGÿZVSÿVTH

ZUT, b

2�1�w� �VGS ÿ VTH�2

for VD ÿ VS 4UT

gmID

ZUT

�������2bID

1�wq

gmb �Zÿ 1�gm wgm

Cgs=Cox expVGÿZVSÿVTH

ZUT2/3

Cgd=Cox expVGÿZVDÿVTH

ZUT& 0

Fig. 1. Regulated-cascode current mirror [1].

114 J. A. De Lima

owing to binary-word switching. Output is taken at

M1 drain so that changes on its nominal current due to

a noisy vds1 can be analyzed. As each node is at a ®nite

impedance with respect to ground, it can be

represented by a grounded capacitance Cn and

resistance Rn. Hence, a pole is established at each

node, at a frequency 1=�2pRnCn�. Capacitors C1, C2

and C3 correspond to lumped values to ground of both

intrinsic and extrinsic transistor capacitance as well as

junction capacitances on associated nodes. Applying

Kirchoff's laws in the s-domain yields

vgs3 � vg3 ÿ vout �4a�

vin � vx � vout �4b�

gm3vgs3 ÿ gmb3vout

� vx

ro3

� vout

ro1

� sC1vout �4c�

gm2vout �vg3

ro2

� sC2vg3 � 0 �4d�

After straightforward manipulation, regulation

transfer function is

F�s� � vout�s�vin�s�

� ro1�sro2C2 � 1�As2 � Bs� C

�5�

where the denominator coef®cients correspond to

A � ro1ro2ro3C1C2 �6a�

B ��ro1 � ro3�ro2C2

� ro1ro3�C1 � g0m3ro2C2� �6b�

C �ro1 � ro3

� gm3ro1ro3�gm2ro2 � 1� �6c�

and g0m3 � gm3 � gmb3 � agm3 , where a = Z in weak

inversion and a � �1� w� in strong inversion. As

normally gm2ro2 4 1 and setting a same magnitude to

both C2 and C1, it turns out g0m3ro2C2 4C1 and

gm2gm3ro1ro2ro3 4 ro1� ro3. Loop transfer is simpli-

®ed to

F�s� � C2

gm2gm3ro3

s� �1=ro2C2���C1C2�=gm2gm3�s2 � ��aC2�=gm2�s� 1

�7�

where the denominator can be decomposed as

D�s� � s2

p1p2

ÿ s1

p1

� 1

p2

� �� 1

� 1ÿ s

p1

� �1ÿ s

p2

� ��8�

Poles should be placed along the negative real s-

plane axis so that oscillation does not take place.

Thus,

D � aC2

gm2

!2

ÿ 4C1C2

gm2gm3

� 0 �9�

which imposes

gm3=gm2 � 4C1=�a2C2� �10�Assuming CGD % 0 [4], the intrinsic drain-to-gate

capacitance for a saturated transistor, lumped capaci-

tors C1 and C2 are estimated

C1 � CovM1 � CGSM2 � Cj1 �11a�

C2 � CovM2 � CGSM3 � Cj2 �11b�where CovMi and CgsMi are respectively the over-

lapping capacitance and gate-to-source capacitance of

Mi, as de®ned in Table 2, and Cji the junction

capacitance at node i. In terms of transistor geometry,

C1 and C2 can be expressed as [4]

C1 �KWuLovC0ox � CGSM2

� �KWu �W3�LxCj �12a�

C2 � W2LovC0ox � CGSM3 � �W2 �WBi�LxCj �12b�

where WBi is the channel width of the transistor

implementing the current source IBIAS.

Settling behavior of regulated current mirrors is

thus affected by the poles position on the s-plane. Two

distinct 2nd-order real-pole systems are hereafter

discussed and compared:

Fig. 2. Equivalent small-signal circuit for regulation analysis.

Settling Analysis of MOS Regulated Current Mirrors 115

1) Dominant-Pole System

Assuming p1 the dominant pole, jp1j5 jp2j and the

denominator of (7) approximates to

D�s�%1ÿ s

p1

� s2

p1p2

�13�

Straightforward identi®cation between (7) and (13)

yields

p1 � ÿgm2

aC2

�14a�

p2 � ÿagm3

C1

�14b�

Dominant-pole condition is then achieved by

imposing

gm3

gm2

4C1

a2C2

�15�

Combining (7), (14a) and (14b), the loop transfer

can be rewritten as

F�s� � 1

ro3C1

sÿ z1

�sÿ p1��sÿ p2��16�

with the zero at

z1 � ÿ1

ro2C2

�17�

Through partial-fraction expansion [6], for

jp1j5 jp2j and jp1j4 jz1j since normally

2gm2ro2=a4 1, it turns out

F1�s� �1

ro3C1

1

sÿ p2

ÿ p1

p2

1

sÿ p1

� ��18�

After some manipulation, the system response to a

unity-step input vin�s� � H�s� � 1=s yields

vout1�s� � H�s�F1�s�

� 1

ro3C1p2

1

sÿ p2

ÿ 1

sÿ p1

� ��19�

with a time-domain response

vout1�t� � ÿ1

agm3ro3

�e p2t ÿ e p2t� �20�

As expected, vout1 represents a linear combination

of two exponential terms with time constant

tr%1=jp1j and corresponds to a heavily overdamped

response �Q 5 1/2�.

2) Twin-Pole System

By imposing D = 0 in (9) one has

gm3

gm2

� 4C1

a2C2

�21�

that settles twin-poles at

p1 � p2 � ÿ2gm2

aC2

� ÿ agm3

2C1

�22�

Pole frequency is now twice as high as in the

dominant-pole case. The regulation-loop transfer is

F2�s� �1

ro3C1

sÿ z1

�sÿ p1�2�23�

or into an expanded form

F2�s� �1

ro3C1

1

sÿ p1

� p1 ÿ z1

�sÿ p1�2" #

�24�

The unity-step response corresponds to

vout2�s� �1

ro3C1

1

p1

1

sÿ p1

ÿ 1

s

� �� p1 ÿ z1

p12

�

1

sÿ 1

sÿ p1

� �� p1

�sÿ p1�2" #)

�25�

Again, jp1j4 jz1j leads to a simpli®cation

vout2�t� �1

ro3C1

1

�sÿ p1�2�26�

and a critically damped response �Q � 1/2�

vout2�t� � ÿ1

agm3ro3

2p1tep1t �27�

Fixed the pole frequency p1, comparison between

the time response of both systems suggests faster

settling in the dominant-pole case due to the presence

of factor 2p1t on (27). Since gm3=gm2 is related to

speci®ed values of Iout and IBIAS, (15) cannot always

be imposed in micropower current mirrors without

compromising power consumption or settling time.

Assuming M2 and M3 in weak inversion, leakage

mechanisms [7] determine a minimum value for IBIAS,

116 J. A. De Lima

and consequently gm2. Similarly, the mirrored current

Iout de®nes gm3. If gm3=gm2 & 1, a condition

C2 4 a2C1 is needed. Although CGS may be neglected

with respect to parasitic capacitances, further reduc-

tion of C1 is limited by layout rules and scaling factor

K. Increasing C2 through W2 to meet such a condition

would reduce the dominant pole frequency, slowing

down regulation.

As de®ned by (21), a more relaxed condition to

gm3=gm2 is allowed if a twin-pole system is imposed to

the regulation-loop transfer. In addition, as both poles

are now placed at jp1j � jp2j � 2=tr, settling will be

slightly improved with respect to a dominant-pole

system with time constant tr . This analysis is

supported by simulated results from MATLAB#.

Fig. 3 overlays unity-step time responses of single-

zero, double-pole systems with different pole place-

ment, as follows:

(a) twin-pole system �jp1j � jp2j � 2=tr�: Fa�s� �4�s� 0.05�=��s� 2��s� 2��

(b) dominant-pole system �jp1j � 1=tr�: Fb�s� �10�s� 0.05�=��s� 1��s� 10��

(c) twin-pole system �jp1j � jp2j � 1=tr�: Fc�s� �1�s� 0.05�=��s� 1��s� 1��

(d) two-pole system �jp2j > jp1j, centered at 1/tr�:Fd�s� � 0.75�s� 0.05�=��s� 0.5��s� 1.5��

where a normalized time constant tr � 1 is adopted

and DC gains are adjusted to yield identical ®nal

values [6]. As pointed out, a system with a dominant-

pole at 1=tr (b) settles faster than a two-pole system

with poles at (c) or close to 1=tr (d). However, a

system with both poles at 2=tr (a) exhibits the fastest

settling. Alternatives (a) and (b) may thus be

combined to the designing of micropower regulated

current mirrors.

III. Settling Analysis Applied to the Design ofRegulated Current-Mirrors

The results of previous section are applied to the

design of regulated current mirrors for different

current levels, complying with a double-metal,

0.7 mm CMOS process design rules. Typically, VTH

� 0.832 V, C0ox � 230 nF/cm2, Cj � 50 nF/cm2,

mn � 250 cm2=Vÿ 1sÿ 1, Lov � 0.1 mm, Lx � 2.2 mm,

g � 0.936 V1=2 and Z � 1.2. Following a voltage

perturbation at M1 drain, regulation is assumed to

occur within 5tr. Having gm3=gm2 as a parameter, the

design approach for a regulated cascode is twofold:

(i) Twin-pole system: this alternative adjusts best

when gm3=gm2 is close to unity and dif®culties to

impose C2 4 a2C1 for a given tr arise. For instance, if

Iout & IBIAS and in the nanoamp-range, for speci®ed

settling times as short as tens of nanosecond. By

keeping both M2 and M3 in weak inversion �W/L�ratios become relatively small, reducing stray capa-

citances. Fig. 4 shows a corresponding design-¯ow

diagram where in-brackets parameters are previously

de®ned. As both gm2 and gm3 are ®xed, W3 is the

determining parameter to C1 and pole frequency. For

Fig. 3. Settling behavior of different regulated systems.

Settling Analysis of MOS Regulated Current Mirrors 117

Iu � 25 nA and IBIAS � 10 nA, device sizing is listed in

Table 3.

(ii) Dominant-pole system: this condition prevails

in complementary cases, i.e., whenever speci®ed

currents Iout and IBIAS produce gm3=gm2 greater than

unity or settling time is somewhat relaxed. Proper

sizing of M2 and M3 imposes (15) and adjusts the

dominant-pole frequency. Assuming a low IBIAS to

minimize power consumption, M2 operates in weak

inversion whereas M3 is placed in strong inversion to

handle relatively high values of Iu and/or mirroring

factor K. Again, this procedure allows small values of

�W/L�, reducing internal capacitances.

The design-¯ow diagram is presented in Fig. 5

where pole-frequency ratio is represented by

M=p2=p1. Once C2 is calculated for a given tr, a

maximum value for W3 establishes the non-dominant

pole and factor M. For Iu � 250 nA and IBIAS � 20 nA,

transistor sizing is listed in Table 4, for K� 1 and K�

32. As expressed by (3), output resistance is increased

by negative feedback so that short-channel devices

can be adopted to reduce node capacitances.

A. Effect of Geometry Mismatching

A sensitivity analysis on transistor mismatching when

imposing a twin-pole condition was also realized.

Variations on channel width are assumed dominant on

evaluating (22) and departures from a nominal Wi are

accounted by a multiplying mismatch factor �1� ei�.From several analyzed combinations involving mis-

match coef®cients, eMu%� eM2% and eM3%� eMbi%

causes the largest alteration on pole frequencies.

Listed values in Table 5 correspond to percentage

deviations �e%� from unity of pole-frequency ratio M.

Diagonal zeros imply that M would not be affected by

uniform mismatching since both C1=C2 and gm2=gm3

ratios remain constant. For mismatches ei% within

+ 10%, a maximum deviation e% � 17.6% was

found.

Fig. 6 displays the settling characteristic of a

normalized twin-pole system �jp1j � jp2j � 1� in case

of (i) no geometry mismatch �e � 0� and (ii) a 25%-

relative spacing between p1 and p2 �e � 0.25�. As

similar settling occurs, one may presume that modern-

processing mismatches are not a limiting factor to the

twin-pole condition.

Fig. 4. Design-¯ow diagram for a twin-pole system current

mirror (M2 and M3 in weak inversion).

Fig. 5. Design ¯ow-diagram for a dominant-pole system current

mirror (M2 and M3 in weak and strong inversion, respectively).

Table 3. Parameters and transistor sizing for a twin-pole system. (tr

= 40 ns, Iu = 25 nA, IBIAS = 10 nA, WBi = 4.8mm, Wu = 4.8 mm).

K� 1 M1 M2 M3

W(mm) 4.8 4.0 2.9

L(mm) 12.0 2.4 2.4

K=2 W(mm) 9.6 4.0 5.8

L(mm) 12.0 2.4 2.4

Table 4. Parameters and transistor sizing for a dominant-system.

(Iu � 250 nA; IBIAS � 20 nA; IBi � 4:8mm;Wu � 4:8mm;

tr � 30ns.

K� 1 mm M1 M2 M3 M

W 4.8 3.2 4.3 34

L 12.0 1.2 1.0

K� 32 W 153.6 3.2 4.3 10

L 12.0 1.2 1.0

Table 5. Percentage deviation of M� 1 due to transistor mismatch.

eM3% � eMbi%

ÿ 10 ÿ 5 0 5 10

ÿ 10 0 4.5 8.9 13.3 17.6

eMu% ÿ 5 ÿ 4.2 0 4.3 8.5 12.6

� 0 ÿ 8.1 ÿ 4.0 0 4.1 8.1

eM2% 5 ÿ 11.6 ÿ 7.7 ÿ 3.8 0 3.9

10 ÿ 14.9 ÿ 11.1 ÿ 7.3 ÿ 3.6 0

118 J. A. De Lima

B. Design of a Micropower D/A Converter

A 6-bit micropower D/A converter employing

regulated current mirrors was designed based on the

settling-driven approach [8]. Fig. 7 shows its

simpli®ed schematic where binary-weighted currents

21Iu selected by digital code Bi, Bi � 1, . . . are

summed up to de®ne the output current Idac. By

®xing IBIAS and �W=L�2, identical drain potentials of

transistors M1i, M1i� 1,. . . are ideally set and channel-

length modulation effect reduced, providing better

accuracy between scaled currents. Switching noise is

coupled to node C during digital-code updating. For a

step-current Iu � 25 nA, current mirrors referred to

the least-signi®cant bits were sized assuming a twin-

pole system whereas a dominant-pole condition was

imposed to those generating higher currents.

Transistor sizing and parameters are listed in Table 6.

IV. Simulation Results

Simulation of designed current mirrors was carried out

with PSpice# level-3 models. For the twin-pole system

listed on Table 3, waveforms of Vout (at M1 drain) and

Iout, following a 250 mV-step perturbation at M3 drain,

are shown in Fig. 8, for K� 1 and K� 2, with a 180 ns-

settling time. Similarly, Fig. 9 displays the settling

behavior of the dominant-pole system of Table 4, for

K� 1 and K� 32, with a 60 ns-settling time. These

results validate the theoretical analysis since regula-

tion takes place within the expected 5tr and no

meaningful oscillation has been detected. Fig. 10(a)

shows the effect of switching noise in binary-weighted

currents in the D/A converter at non-optimal transistor

sizing and bias, with a resulting 60 ms settling time. As

illustrated in Fig. 10(b), this value decreases to 12 ms

by applying the settling-driven technique.

Fig. 6. Effect of transistor mismatch on twin-pole system

settling.

Fig. 7. Simpli®ed schematic of switching-current D/A converter.

Table 6. Parameter and transistor sizing of D/A converter, for

Iu � 25 nA; IBIAS � 10 nA; �W=L�2 � �4=2:4�; �W=L�u ��4:8=9:6�;WBi � 4:8mm.

Bit0* Bit1* Bit2** Bit3** Bit4** Bit5**

K 1 2 4 8 16 32

�W=L�3 3.0/2.4 6.0/2.4 1.8/1 3.6/1 5.3/1 7.1/1

tr 40 ns 40 ns 50 ns 60 ns 70 ns 80 ns

M Ð Ð 10 10 12 11

*Twin-pole system.

**Dominant-pole system.

Settling Analysis of MOS Regulated Current Mirrors 119

Fig. 8. Simulated response to perturbation of twin-pole system (a) K� 1 and (b) K� 2.

Fig. 9. Simulated response to perturbation of dominant-pole system (a) K� 1 and (b) K� 32.

Fig. 10. Effect of switching noise on output current of D/A converter with regulated current mirrors (a) non-optimal transistor sizing and

bias (b) settling-driven design approach.

120 J. A. De Lima

V. Experimental Results

Fig. 11 shows the microphotography of the designed

6-bit micropower D/A converter as part of a neural

network chip. As current IBIAS is externally deter-

mined, distinct settling characteristics can be imposed

to current-mirror regulation loops. As attempts to

probe the drain of M1 would drastically tamper with

node capacitance, observation point is taken at the

converter output. For Iu � 32 nA, Fig. 12 displays

waveforms related to MSB switching in case of (a)

dominant-pole condition @IBIAS � 14 nA and (b) non-

optimal biasing @IBIAS � 160 nA, which implies in

complex poles as de®ned by (9). As it can be seen, fast

settling is achieved in ®rst case, where proposed

approach was applied.

VI. Conclusion

A settling-driven design technique for MOS regu-

lated current mirrors as part of micropower current-

switching D/A converters was introduced. The

regulation-loop transmission characteristic was

determined and the position of poles in the resulting

2nd-order system analyzed as a function of output

current, power consumption and settling time.

Owing to parasitic capacitances, design constraints

to assure a dominant-pole, while meeting speci®ca-

tions of very-low power consumption and fast

settling, led to a twin-pole alternative whenever

gm3=gm2 approaches unity and short settling times

speci®ed. It is been also found that typical transistor

mismatches do not limit the twin-pole condition in

practice. Dominant-pole alternative prevails in

complementary cases where gm3=gm2 4 1. As

output resistance is boosted by negative feedback,

short channel lengths can be used without seriously

degrading current mirroring.

Both alternatives were applied to the synthesis of

regulated current mirrors with different scaling factors

and design-¯ow diagrams de®ned. No meaningful

oscillation in simulated waveforms suggests a good

agreement with theoretical settling behavior.

Following a 250 mV-step perturbation, a 180 ns-

regulation time was found for a twin-pole current

mirror with Iu � 25 nA, IBIAS � 10 nA and K� 1. In

case of a dominant-pole circuit, a 60 ns-settling time

for Iu � 25 nA, IBIAS � 20 nA and K� 32. By applying

the proposed technique, the simulated time-response

of a micropower D/A converter decreases from 60 to

12 ms. Fast settling was also experimentally con®rmed

at optimal biasing. Although D/A converters were

Fig. 11. D/A converter photograph.

Fig. 12. D/A converter output waveforms after MSB switching at (a) dominant-pole condition (b) non-optimal bias.

Settling Analysis of MOS Regulated Current Mirrors 121

particularly devised in this work, the settling-driven

approach can be extended to other micropower

current-switching circuits employing regulated cas-

codes.

Acknowledgment

The author would like to express his thankfulness to

Carlos Dualibe, from Universidad Catolica de

Cordoba, Argentina, on leave at the Laboratory of

Microelectronics, University Catholic of Louvain,

Belgium, for fruitful discussions and to FAPESP and

ProTem/CNPq, in Brazil, for continuous assistance on

integrated circuit research and ®nancial support on

chip fabrication.

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Current Circuits.'' IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, 43(11), 1996.

3. C. Toumazou, J. B. Hughes, and D. M. Patullo, ``A Regulated

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