serial flash controll

7/30/2019 Serial Flash Controll

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2/77

Serial Flash controller functional specification

2/77 Rev B

InformationclassifiedConfiden

tial-Donotcopy(Seelastpageforo

bligations)

15-May-2008 1.3

Sanjeev

Varshney/Parul

Agarwal

Updated the quad mode and write/erase

support (fast sequence mode).

Reorganized the document. Updated for integration guidelines.

Reorganized the document in new format,

more aligned to new spirit template.

Open points/future enhancements:

- separate clock input for the Serial Flash

controller (today it is same as the EMISS

system clock).

- Macronix memories latest mode, that is, quad

DDR mode 75 Mbits /sec) to be defined.

06-Jul-2009 2.0 Parul Agarwal

Updated document with drivers team feedback

and aligned with validation application note.

Updated the description of the SPI_CLK_DIV,

SPI_FAST_SEQ_FLASH_STA_DATA and

SPI_STATUS_WR_TIMEregisters.

07-Jul-2009 2.1 Parul Agarwal

Updated the SPI_CONFIG_DATA register with

footnote.

Added detail in the Section 4.1.9: Fast

sequence boot mode.

31-Jul-2009 2.2 Parul Agarwal Added independent SPI clock details.

17-Jun-2010 3.0 Parul Agarwal

Ported in latest spirit based template and

incorporated feedbacks received from different

people like Linux team, Validation team,

verification team.

14-Sep-2010 3.1 Shilpi JainUpdated by documentation team for

documentation style guide adherence.

24-Mar-2011 3.2 Parul Agarwal

Updated to add 32 bit address serial flash

support. Register description

SPI_FAST_SEQ_ADD_CFG is updated.

16-May-2011 3.3 Parul Agarwal Updated to add the reset state of pads to z

21-June-2011 3.4 Parul Agarwal Note added in the spi_fast_seq_data register

Date Revision Author Modification description


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Rev B 3/77

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Referenced documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 IP block name and features list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 IP block name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Features list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 IP block context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1.1 Pad connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1.2 Comms integration guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.3 Supported opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 Hardware interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Functional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Detailed functional specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Normal functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.1.1 Modes supported by the Serial Flash controller . . . . . . . . . . . . . . . . . . 14

4.1.2 Architecture of Serial Flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.3 Commands supported by different modes of the controller . . . . . . . . . . 16

4.1.4 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1.5 Fast read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1.6 Dual output (x2) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1.7 Contiguous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.8 Fast sequence mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Fast sequence mode functioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Single-page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Single-page read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Single-page write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Multiple-page sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read multiple page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Multiple-page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Chip select bit functioning for DATA phase in single- and multiple-page sequences

29
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4.1.9 Fast sequence boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Boot flow from system prospective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Fast sequence boot mode flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Registers required for the fast sequence boot mode . . . . . . . . . . . . . . . . . . . . . . . 324.1.10 Changing modes of Serial Flash controller . . . . . . . . . . . . . . . . . . . . . . 33

Fast sequence mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.2 Error conditions and error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.4 Debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.5 System requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.5.1 Memory requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.5.2 Interrupt behavior and requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.6.1 Hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.6.2 Soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.1 Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2 Clock relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3 Generated clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6 Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.1 External hardware interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7 Routers and interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1 Local interconnect (routers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.2 Point-to-point connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8 Pin group list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1 Address blocks and sub-blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1.1 Summary table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1.2 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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10 Software driver interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10.1 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10.1.1 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

11 Patents and licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Appendix A Serial Flash controller requirements . . . . . . . . . . . . . . . . . . . . . . . . 72

A.1 Performance calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

A.1.1 Contiguous mode versus normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 72

Assumptions made for the above calculations . . . . . . . . . . . . . . . . . . . . . . . . . . .72

A.1.2 Dual output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

A.1.3 Fast sequence mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

A.1.4 Performance comparison at a glance . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

A.2 Flashes supported by the Serial Flash controller . . . . . . . . . . . . . . . . . . . 73
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bligations)

1 Introduction

This document describes the Serial Flash controller module housed inside the EMI

subsystem (EMISS). The EMISS has a separate serial bus to interface with the Serial Flashdevices. The Serial Flash controller is designed to communicate with the Serial Flashdevices.

1.1 Referenced documents

Atmel Serial Flash memory, AT25F4096 datasheet

Atmel Serial Flash memory, AT25FS040 datasheet

ST Serial Flash memory, M25P40 datasheet

SST Serial Flash memory, SST25LF020A datasheet

Winbond Flash memory, W25x10 datasheet

Macronix Flash datasheet, MX25L1635D

SST Serial Flash datasheet, S71359

Winbond Serial Flash datasheet, W25X10_20_40_80b

Winbond Quad Serial Flash memory, W25Q80_16_32b

1.2 Glossary

FSM Fast sequence mode

T2 STBus Type 2Quad Quadruple mode of Serial Flash

EMISS EMI subsystem

CS Chip select of Serial Flash

DI Data in port of Serial Flash

DO Data out port of Serial Flash

Hold Hold pin of Serial Flash

WP Write protect pin of Serial Flash

I/P Input

O/P Output

BIDI Bidirectional

SPI Serial peripheral interface

Contig mode Contiguous mode

NA Not applicable


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2 IP block name and features list

2.1 IP block name

2.2 Features list

The main features of the Serial Flash controller are:

Serial Flash boot support:

x1 and x2 boot support using the legacy mode x1, x2, x4 boot support using the fast sequence boot mode

Fast sequence mode features:

Read, write and erase support

x1, x2 and x4 support for different operations

Flexibility to support any available device size

Programmable engine to support various Serial Flash devices

Variable size data transfer support

Capability to support 32 bit address Serial Flash devices

Pacing signal support to communicate with FDMA/CPU for large data transfers

Support for unaligned access Support for mode 0 (CPOL=0, CPHA=0) of the SPI protocol

Flexibility to operate serial bus on various frequencies with different system clocksusing the programmable clock division ratio

Software write protect (WP) supported

Note: x1, x2 and x4 refer to the data pad configuration of the Serial Flash. For more details, refertoSection 3.1.1: Pad connections.

Table 1. SPIRIT identification of serial_flash_controller

Vendor Library Name Version

st.com C6 serial_flash_controller 3.0


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bligations)

3 System overview

3.1 IP block context

The Serial Flash controller is integrated within the EMI subsystem (EMISS). The Figure 1shows the EMISS in a SoC context. However, the IP can also be delivered as a stand-alone.The Serial Flash controller provides seamless interface to the Serial Flash device using theSPI protocol. The Serial Flash controller is accessible to system initiators through the Type2interface of the EMISS. The main function of the Serial Flash controller is to take the STBusrequests coming from the interconnect side and convert them into serial access (SPIprotocol) to communicate with the Serial Flash devices.

Figure 1. EMISS system view

The Figure 2shows the system-level view of the Serial Flash controller embedded insidethe EMISS.

Figure 2. Serial Flash controller inside EMISS

Serial bus

EMISS

CPU

FDMA

SoC

Parallel bus

IC Padlogic

EMI

buffer

Router Padlogic Serial

WP

HOLD

DO

DI

SPI_CLOCK

CS

Serial Flash

controller

EMISS

FDMA

IC

CPU

Type2

NAND

EMI

RGV

Flash


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3.1.1 Pad connections

A typical Serial Flash can have different data bus widths in different configurations. Forexample in:

x1 pad configuration: CS; SPI_CLOCK; and unidirectional DI and DO pads are used

x2 pad configuration (dual output - legacy mode)

CS; SPI_CLOCK; one unidirectional DI pad; and one bidirectional data pad DOare used

x2 pad configuration (dual I/O - fast sequence mode)

CS; SPI_CLOCK; and two bidirectional data pads DI and DO are used

x4 pad configuration

CS; SPI_CLOCK; and four bidirectional data pads DI, DO, HOLD and WRITEPROTECT are used

These different configurations (x1, x2, x4) of Serial Flash decides the pad requirement at theSoC level. The Serial Flash controller generates six enable signals corresponding to six SPIpads. These enable signals are used to control the pad direction for all modes of the SerialFlash controller.

The enables generated by the serial flash controller drives all the spi pads in input modeduring reset. This is done to avoid driving the pads during reset. All the pads can be tristatedat SoC level on reset for the serial flash to power on and off safely. As soon as the reset isdeasserted and clock arrives the pads are put in their respective required modes. TheTable 2gives the values of the enable signals generated by the Serial Flash controller afterthe reset is over.

Table 2. Polarity of enables

The pad requirements for different type of configurations are given in the following table:

Enables Value after resetis over

Pad direction

SPI_DATA_IN_ENB 0 Input mode

SPI_DATA_OUT_EN 1 Output mode

SPI_HOLD_ENB 1 Output mode

SPI_WR_PROTECT_ENB 1 Output mode

SPI_CLK_ENB 1 Output mode

SPI_CS_ENB 1 Output mode
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Table 3. Pad requirements for different Serial Flash configurations

Pads SPI_NOT_CS SPI_CLOCK SPI_DATA_IN SPI_DATA_OUT HOLD

WRITE

PROTECT

(WP)

x1 Output pad Output pad Input pad Output padCan either be tied

appropriately at the top

level, or the Serial Flash

controller enable signals

can be used to drive

inactive value 1.

x2 (dual output -

legacy mode/FSM

mode)

Output pad Output pad Input pad Bidirectional pad

x2 (dual I/O - fast

sequence mode)Output pad Output pad

Bidirectional

padBidirectional pad

x4 Output pad Output padBidirectional

padBidirectional pad

Bidirectional

pad

Bidirectional

pad


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The Figure 3, Figure 4and Figure 6show the pad connections for x1, x2 and x4configurations of the Flash, respectively.

Figure 3. x1 pad connection

Figure 4. x2 pad connection (dual output mode)

CS

SPI_CLOCK

DI

DO

SPI_NOT_CS

SPI_CLOCK

SPI_DATA_OUTSerial

Flash

Serial Flash

controller

Padlogic

SPI_DATA_IN

CLOCK

CS

DO

DI

CS

CLOCK

DI

DO

SPI_DATA_OUT_EN

SPI_DATA_OUT

SPI_DBL_DATA_IN

SPI_DATA_IN

Serial

Flash

Serial Flash

controller

Padlogic

DO

DI

SPI_NOT_CS CS

SPI_CS_ENB

SPI_CLOCK SPI_CLOCK

SPI_CLK_ENB


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bligations)

Figure 5. x2 pad connection (dual I/O mode)

CS

CLOCK

DI

DO

SPI_NOT_CS

SPI_CLOCK

SPI_DATA_OUT_EN

SPI_DATA_OUT

SPI_DBL_DATA_IN

SPI_DATA_IN_ENB

SPI_DATA_OUT_QUAD

SPI_DATA_IN

Padlogic (SoC boundary)

Serial Flash

controller

SerialFlash

CS

SPI_CLOCK

DO

DI

SPI_CS_ENB

SPI_CLK_ENB


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Figure 6. x4 pad connection

3.1.2 Comms integration guidelines

Typically, in previous SoCs, the serial bus was shared between the comms subsystem andthe Serial Flash controller for different Serial Flash operations (mainly for write and erase).

This sharing has to be handled at the SoC level, and is outside the scope of the Serial Flashcontroller.

The Figure 7shows the example glue logic required at the SoC level for managing thecomms and the legacy mode of the Serial Flash controller. A system configuration registerbit should be used for this purpose. For booting from Serial Flash, this bit must assign theserial bus to the Serial Flash controller, by default. After booting, the software can drive thevalue of this bit as required, that is, the software programs the value of this registeraccordingly while doing transactions from the Serial Flash controller or comms.

CS

CLOCK

DI

DO

HOLD

WP

SPI_NOT_CS

SPI_CLOCK

SPI_DATA_OUT_EN

SPI_DATA_OUT

SPI_DBL_DATA_IN

SPI_DATA_IN_ENB

SPI_DATA_OUT_QUAD

SPI_DATA_IN

SPI_HOLD_ENB

SPI_HOLD_OUT

SPI_HOLD_IN

SPI_WR_PROTECT_ENB

SPI_WR_PROTECT_OUT

SPI_WR_PROTECT_IN

Padlogic (SoC boundary)

Serial Flash

controller

Serial

Flash

CS

SPI_CLOCK

DO

DI

HOLD

WP

SPI_CS_ENB

SPI_CLK_ENB


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Figure 7. Serial Flash controller legacy mode and comms multiplexing logic

3.1.3 Supported opcodesThe different opcodes supported by different modes of the Serial Flash controller areprovided in the following table:

Note: Accessing opcodes other than those mentioned above generate error conditions by settingthe INIT_R_OPC signal as high.

Serial Flash controller

EMISS

SPI_NOT_CS

SPI_CLOCK

SPI_DATA_OUT

SPI_DATA_IN

STBusPadlogic/Gluue

COMMS_CLOCK

COMMS_DATA_OUT

COMMS_DATA_INCOMMS

SPI_NOT_CS

SPI_CLOCK

SPI_DATA_OUT

SPI_DATA_IN

subsystem

System configuration register bit

EMI buffer

Table 4. Opcodes supported in different modes

Modes Boot requests FIFO requestsConfiguration

requests

Legacy modes LD 4/8/16/32 N/ALD 4

ST 4

Fast sequence mode N/ALD 4/8/16/32

ST 4/8/16/32

LD 4

ST 4

Fast sequence boot mode LD4/8/16/32 N/ALD 4

ST 4


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3.2 Hardware interfaces

The Serial Flash controller has one Type 2 RGV target interfacing with EMI buffer throughrouter. This interface is utilized by the CPU for booting and programming the Serial Flashcontroller registers to configure the IP in the required mode.

The Serial Flash controller provides two DREQs (SPI_DATA_DREQ and SPI_SEQ_DREQ)to interface with FDMA/HOST. The DREQs communicate the status of the Serial Flashcontroller. Use the SPI_DATA_DREQ signal to move the data in and out of the FIFO. Usethe SPI_SEQ_DREQ signal to program the sequence registers. Connect theSPI_DATA_DREQ and SPI_SEQ_DREQ signals with ILC to manage interrupts to the HOST.For more details, refer to Section 4.5.2: Interrupt behavior and requirements.

The Figure 8shows an example connection of DREQs with the CPU and FDMA.

Figure 8. Serial Flash controller dreq connection

3.3 Functional components

Not applicable.

Padlogic Quad

Serial

Flash

WP

HOLD

DO

DI

SPI_CLOCK

CS

EMISS

FDMA

IC

CPU

ILC3

SPI_SEQ_DREQ

SPI_DATA_DREQ

EMI

bufferRouter SPI

controller


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4 Detailed functional specification

4.1 Normal functional behavior

4.1.1 Modes supported by the Serial Flash controller

The Serial Flash controller can work in the following modes:

legacy modes

fast sequence mode (FSM)

fast sequence boot mode

After reset, the Serial Flash controller is ready to boot in the legacy normal mode. There arethree legacy modes:

normal mode

fast read mode dual output mode

The contiguous mode is present in addition to the three legacy modes. This is aperformance enhancement mode, which can be combined with any of the three legacymodes. For more details, refer to Section 4.1.7: Contiguous mode.

The Figure 9illustrates the modes of the Serial Flash controller. These modes aredescribed in detail in later sections.

Figure 9. Serial Flash controller modes

Legacy modes Fast sequence mode Fast sequence bootmode (read only)

Serial Flash controller modes

(read, write and erase)

Normal mode Fast read mode Dual output mode

(read only)


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4.1.2 Architecture of Serial Flash controller

The Serial Flash controller can be broadly divided into five blocks:

STBus interface

clock divider main controller

fast-sequence controller

padlogic

configuration block

Figure 10. Serial Flash controller architecture

The STBus interface receives STBus requests and manages responses to the interconnect.It triggers state machines of the main controller block or the fast-sequence controller block toinitiate SPI transactions. The STBus interface block also recognizes configuration requestsand forwards these requests to the configuration block.

The configuration block handles the incoming configuration requests from the interconnectside. This block provides the read/write functionality for all the configuration registers.

The main controller block is responsible for the functioning of legacy modes.

The Serial Flash controller has a configurable clock divider to tune the EMISS clock forSerial Flash devices. This divider is configured through a static signalMODE_SPI_CLK_DIV after reset, and can be programmed afterwards through theSPI_CLK_DIVregister.

The static signal MODE_SPI_CLK_DIV provided at the top level of the Serial Flashcontroller gives flexibility to different SoCs to choose any division ratio for boot. It ismandatory to tie these pins at the SoC integration level with a minimum value of divide by 8to allow booting from slow serial devices. After booting, the SPI_CLK_DIVregister can be

Main controller

Clock divider

Fast-sequence

controller

SPI_CLOCK

SPI data and enable

pins to padlogic

STBus

(RGV)

interface

MODE_SPI_CLK_DIV

Padlogic

Configuration block

Interconnect


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programmed to dynamically change the frequency. The clock division ratio for this registerranges from divide by 2 to 256 in steps of 2, that is 2, 4, 6, 8,......, 254 and 256.

The fast-sequence controller block is responsible for handling the fast sequence modeoperations. It decodes the instructions written in the fast-sequence registers and executes

them sequentially. It also has a state machine to generate control signals for the fastsequence mode. This block has a FIFO embedded inside to store data. While performingFlash writes, the data to be written to the Flash is stored in this FIFO. Similarly, during Flashread operations, the data read from the Flash is stored in this FIFO.

The padlogic block is responsible to re-time incoming and outgoing data signals to easetiming closure. This block also generates information regarding the stalling of the Flashinterface by keeping track of the FIFO status. This block also manages serial to parallelconversion and vice-versa.

4.1.3 Commands supported by different modes of the controller

The different commands supported by different modes of the Serial Flash controller are

summarized in the following table:

Table 5. Modes and features supported by the Serial Flash controller

CommandsNormal

mode

Fast read

mode

Dual

output

mode

Fast

sequence

mode

Fast

sequence

boot mode

Write enable No No No Yes Yes

Write disable No No No Yes No

Normal read(03h) Yes No No Yes Yes

Fast read (0Bh) No Yes No Yes Yes

Dual output read (3Bh) No No Yes Yes Yes

Dual I/O read (fast) No No No Yes Yes

Quad data read No No No Yes Yes

Quad I/O read (fast) No No No Yes Yes

Page program No No No Yes No

Dual data page program No No No Yes No

Quad page program No No No Yes No

Quad page program (fast) No No No Yes No

Enable quad I/O No No No Yes YesDisable quad I/O No No No Yes No

Read status register No No No Yes Yes

Write status register No No No Yes Yes

Subsector/sector/page erase No No No Yes No

Chip erase No No No Yes No

Block erase No No No Yes No


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4.1.4 Normal mode

By default, the Serial Flash controller is in the normal mode. This mode supports readaccess to the Serial Flash. This mode supports command (03h) of Serial Flash devices.

Although the opcodes supported are higher than 4 bytes, the granularity of one SPItransaction is only 4 bytes. That is, the Serial Flash controller breaks opcodes greater than4 bytes into 4 bytes access, aligned at the 4 bytes boundary. Due to this, the Serial Flashcontroller consumes 64 SPI_CLOCK cycles (32 cycles for opcode and address) for fetchingevery 4 bytes of data from the Flash. For better efficiency, this mode can be combined withcontiguous mode. For more details, refer to Section 4.1.7: Contiguous mode.

4.1.5 Fast read mode

Some Serial Flash devices support the fast read mode, that is, operations at higherfrequencies. The command (0Bh) for the fast read mode is different when compared to thenormal mode. This opcode allows reads at bit rates up to 50 MHz.

The FAST_READ bit of the SPI_MODE_SELECTregister needs to be set to configure thefast read mode. After selecting the fast read mode, the clock divider value can be adjustedto provide higher frequency of operation as defined by the Serial Flash. This mode isbeneficial in case of Serial Flash devices where the fast read mode runs at a higherfrequency when compared to the normal mode.

For better efficiency, this mode can be combined with contiguous mode. For more details,refer to Section 4.1.7: Contiguous mode.

For further details on the fast read mode, refer to the Serial Flash datasheet.

4.1.6 Dual output (x2) mode

The dual output uses a different instruction (3Bh). The data is output on the DI and DO pinsby the Flash. This mode doubles the data transfer rate as compared to the normal mode.The execution of the dual output mode is as follows:

instruction 3Bh (8 bits)

address of the required location (24 bits)

dummy bits (8 bits to provide the additional set-up time to memory)

data output by the Flash on the DI and DO pins alternatively at the falling edge of theSPI_CLOCK

Program the DUAL_OUTPUT_MODE bit of the SPI_MODE_SELECTregister to configurethe Serial Flash controller in the dual output mode.

The Figure 11 shows the command and address given by the Serial Flash controller and

data returned by the Serial Flash. Configure the Serial Flash controller in the dual outputmode with the contiguous read mode in high-speed applications where the data needs to bequickly downloaded from Flash.


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Figure 11. Dual output read mode instruction sequence

4.1.7 Contiguous mode

The contiguous mode is the performance enhancement mode. When enabled, it improvesthe performance of the Serial Flash controller for back-to-back contiguous accesses made

to Flash memory locations.To configure the IP in the contiguous mode, program the CONTIG_MODE bit of theSPI_MODE_SELECTregister. The contiguous mode is not a stand-alone mode. It must beselected in conjunction with any of the legacy modes. The possible configurations of thelegacy modes with the contiguous mode are given in the SPI_MODE_SELECTregister.

In this mode, if contiguous and back-to-back requests are made to the Serial Flashcontroller, it performs the complete read access simultaneously, thereby, saving on thecommand and address cycles for multiple requests. As a result there is no additionaloverhead of address and command cycles for every four data bytes.

The contiguous mode reads are beneficial only when STBus asserts back-to-backcontiguous Flash read requests to the Serial Flash controller. In case a non-contiguous read

or register access is made in between contiguous reads, the Serial Flash controller restartsa new SPI sequence, that is command, address and data read cycles are asserted onceagain.

The Serial Flash controller treats the STBus requests as back-to-back when the next STBusrequest arrives within 8 SPI_CLOCK cycles. Requests are contiguous when consecutiveSTBus transaction addresses are 4 bytes apart, that is, address of the nth transaction =address of (n-1) transaction + 4.

SPI_CLOCK

4 2 06

DI

CS

7 5 3 1

DO

8 bits 24 bits 8 bits DI switches to output

Dual output instruction sequence

Instruction Address Dummy bits

7 3 15

6 4 2 0 6

7

Data output from Flash


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The example waveforms of the contiguous and normal modes are given in the followingfigure:

Figure 12. Normal and contiguous mode waveform comparison

The reads from non-contiguous locations with the CONTIG_MODE bit set is slower ascompared to the normal mode. This is because the Serial Flash controller alwayspre-fetches 1 byte of data from the Serial Flash for every STBus request. This extra bytefetched is discarded as it is not required. This impacts the performance in case of non-contiguous requests. Thus, it is recommended to use normal mode when reading from thenon-contiguous locations.

SPI_CLOCK

INIT_REQ

CLOCK

000h 001h 002hINIT_ADDR(31:2)

xxxxh abcd wxyzINIT_R_DATA

SPI_VALIDNEXTCYCLE

SPI_NOT_CS

Normal mode read

SPI_CLOCK

INIT_REQ

CLOCK

SPI_VALIDNEXTCYCLE

000h 001hINIT_ADDR(31:2)

xxxxh abcdINIT_R_DATA wxyz 1234

002h 003h

SPI_NOT_CS

Normal mode with contiguous mode read

OPC[8] ADDR[24] DATA[32] OPC[8] ADDR[24] DATA[32]

64 SPI clock cycles 64 SPI clock cycles

OPC[8] ADDR[24] DATA[32+32+.......until back-to-back contiguous request arrive]


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4.1.8 Fast sequence mode

The fast sequence mode offers a flexible, software programmable engine, which may beused to perform different Serial Flash operations including read, write and erase. It also hasthe capability to perform x1, x2 and x4 Serial Flash configurations. The fast sequence modehas the flexibility to support variable size data transfers and various available device sizes. Italso supports pacing signals to communicate with FDMA/HOST for large data transfers.

The fast sequence mode has a set of instructions and operands to execute different SerialFlash operations. Software can program any intended sequence in a set of registers usingthese instructions and operands. However, the software should always program correctsequences as per the Serial Flashes supported by the Serial Flash controller. In case thesoftware programs any incorrect or invalid sequence, the Serial Flash controller does notexecute the events correctly.

Fast sequence mode functioning

The fast sequence mode enables the Serial Flash controller to execute multiplecommand/address/data sequences simultaneously based on the configuration of sequenceregisters. The Serial Flash controller executes the instructions programmed in the fastsequence mode registers one-by-one. Once the complete sequence of instructions is over,the SPI_SEQ_DREQ signal is asserted and the SPI_FAST_SEQ_STA register is updated.The software reads this information and programs a new sequence. The software mustprogram a new sequence only when the Serial Flash controller has completed the previoussequence as indicated by the SPI_FAST_SEQ_STA register.

Ensure that correct address, command and instruction sequences are programmed in thesequence registers so that the correct operation is performed on the Serial Flash. Theexample of programming sequence registers is provided in the later sections.

The fast sequence mode is selected by setting the FAST_SEQ_MODE bit of the

SPI_MODE_SELECTregister. Other fast sequence mode registers such as command,address and sequence registers must also be written as required. The operation startswhen the START_SEQ_BIT of the SPI_FAST_SEQ_CFGregister is written. TheSPI_FAST_SEQ_STA register reflects that the sequence execution is in progress and setsthe FAST_SEQ_STA bit to 1.

Note: The Serial Flash controller does not check the status of the serial device before issuing anysequence to the device. This should be managed and looked upon by the CPU/HOSTbefore programming any sequence in theSerial Flash controller. For example, if any readsequence is programmed and executed during the time when the serial device is busy inexecuting the erase/write command then the read command issued by theSerial Flashcontroller would be ignored by the Flash. Hence, it is mandatory for the CPU/HOST to checkthe status of the Flash before programming theSerial Flash controller.


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The fast sequence mode operation is based on the contents of the fast-sequence registers.The complete instruction set is enlisted in the following table:

Table 6. Instruction set of the fast sequence mode

Sequence

bitsOperand Instruction Comment

0001

0001 CMD 1Shifts the command written in the

SPI_FAST_SEQ_OPC1 register to the Flash.







0101 CMD 5 Shifts the command written in theSPI_FAST_SEQ_OPC5 register to the Flash.

0010

0001 ADD 1Shifts the address written in the

SPI_FAST_SEQ_ADD1 register to the Flash.

0010 ADD 2Shifts the address written in the

SPI_FAST_SEQ_ADD2register to the Flash.

0011

0001

(Read status register 1)

or

(Write status register 1)

STATUS_REG_DATA

Reads/writes the DATA_BYTE1 bit written in the

SPI_FAST_SEQ_FLASH_STA_DATA register to the

Flash.

0010

(Read status register 2)

Reads the DATA_BYTE2 bit written in the

SPI_FAST_SEQ_FLASH_STA_DATA register to theFlash.

0011

(Write status register 1

and 2)

Writes the DATA_BYTE1 and DATA_BYTE2 bits

written in the SPI_FAST_SEQ_FLASH_STA_DATA

register to the Flash.

0100 XXXX MODEShifts the data written in the SPI_MODE_BITS


0101 XXXX DUMMYShifts the data written in the SPI_DUMMY_BITS


01100001 DATA_WR Writes the data to the Flash.

0010 DATA_RD Reads the data from the Flash.

0111 XXXX WAITWaits for the time written in the

SPI_PROGRAM_ERASE_TIMEregister.

1000

0001 JUMP_TO_BOOTJumps to the operations written in the

SPI_QUAD_BOOT_READ_SEQ1 register.

0010 JUMP_TO_RPTJumps to the operations written in the

SPI_REPEAT_SEQ1 register.

1111 STOP STOP Last instruction to end the sequence.


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The fast sequence mode is broadly classified into two types depending upon the datatransfer size:

single-page sequence

multiple-page sequence

The page size of a typical Serial Flash is equal to 256 bytes. Use the single-page sequencefor transferring data of size less than or equal to one Serial Flash page. Use the multiple-page sequence for transferring data of size greater than one Serial Flash page. Only onetype of operation can be performed at a time. The different types of permitted operationsare:

erase

read

write

write status register

Do not club the read and write operations in one sequence because the FIFO for the data is

same for read and write. The read status register can be clubbed with the read and writesequences, but the write status register has to be an exclusive sequence.

Single-page sequence

Single-page read sequence

The single-page read sequence is meant for reading data less than or equal to 256 bytesfrom the Serial Flash. The execution of events in case of the single-page read sequence is:

The software programs read operation sequence in the sequence registers.

The software starts the sequence by writing the START_SEQ_BIT bit of theSPI_FAST_SEQ_CFG register.

The Serial Flash controller generates the SPI transaction on serial bus. On receiving appropriate command and address, the Flash starts returning data to the

Serial Flash controller.

The Serial Flash controller stores the data received from the Flash in the internal FIFO.

The Serial Flash controller asserts the SPI_DATA_DREQ signal when 256 bytes arewritten to the FIFO (SPI_DATA_DREQ must be programmed for half FIFO in case ofsingle-page transfers).

FDMA/CPU reads the data from the FIFO on receiving the SPI_SEQ_DREQ andSPI_DATA_DREQ signals.

Note: In case of Flash read, the FDMA/CPU reads data from the FIFO. In case of Flash write, theFDMA/CPU writes data in the FIFO.

Using single-page sequences, the Serial Flash controller performs the x1, x2 and x4read/write operations and erase operations.

Note: The Serial Flash controller asserts the SPI_DATA_DREQ signal when 256 bytes of data isread from the Flash and stored in the FIFO. However, the system has the flexibility to polltheSPI_FAST_SEQ_STA register to determine the data available in the FIFO. In this case, itis not mandatory to program the SPI_DATA_DREQ settings. For transferring less than 256bytes of data, the HOST/CPU can poll theSPI_FAST_SEQ_STA register and no settings ofSPI_DATA_DREQ are required. This is particularly useful in cases when DREQ signals arenot connected, and also helps in debugging.


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The dataflow of the single-page read sequence is given in Figure 13.

Figure 13. Data flow for single-page sequence

Single-page write sequence

The single-page write sequence is meant for writing data less than or equal to 256 bytes onthe Serial Flash. The execution of events in case of the single-page write sequence is:

The software programs the write operation sequence in the sequence registers.

The Serial Flash controller asserts the SPI_DATA_DREQ signal to indicate that theFIFO is empty.

The software writes the data required to be written to the Flash in the FIFO.

The software starts the sequence by writing the START_SEQ_BIT bit of theSPI_FAST_SEQ_CFG register.

The Serial Flash controller generates the SPI transaction on serial bus. On receiving appropriate command, address and data, the Flash enters into the write

cycle state.

The Serial Flash controller enters into wait state for the time programmed in theSPI_PROGRAM_ERASE_TIMEregister.

The Serial Flash controller generates the SPI_SEQ_DREQ signal when the wait time isover.

On receiving the SPI_SEQ_DREQ signal, the FDMA/CPU can program anothersequence in the sequence registers.

FIFO

FDMA/CPU


(1) FDMA/CPU initiates

sequence configuration.

(2) Controller initiates

the SPI transaction.

(3) Flash starts returning

data to the controller.

(5) Half FIFO

SPI_DATA_DREQasserted by the controller.

(4) Data received from

the Flash = 256 bytes.

SPI transactionterminated by thecontroller.

(6) FDMA/CPU fetches datafrom the FIFO after its turnaround time.

OPC + ADDR

Data = 256 bytes

CS de-asserted afterafter 256 bytes data

SPI_CLOCK

CSn

DATA_OUT

DATA_IN

Serial Flash

transfer.


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Note: In case of Flash read, the FDMA/CPU reads data from the FIFO. In case of Flash write, theFDMA/CPU writes data in the FIFO.

Using the single-page sequences, the Serial Flash controller performs the x1, x2 and x4read/write operations and erase operations.

Multiple-page sequences

Multiple-page sequences are used to support transfer size greater than 256 bytes. In thismode, the software programs the required data transfer size in theSPI_FAST_SEQ_TRANS_SIZEregister.

To execute the multiple-page sequence, program the following two set of registers:

SPI_FAST_SEQn registers for the initialization sequence

SPI_REPEAT_SEQ1 and SPI_REPEAT_SEQ2registers for the repeat sequence

It is mandatory to program both the set of registers (initialization and repeat sequenceregisters) for multiple-page operations.

Read multiple page

The Serial Flash controller starts the execution of instructions as programmed in the fast-sequence registers, and asserts the SPI_DATA_DREQ signal after 256 bytes/512 bytes ofdata is read from the Flash. This dreq assertion is dependent on the programming of theDATA_DREQ_HALF_NOT_FULL bit in the SPI_FAST_SEQ_CFGregister. The CPU/FDMAcan read the data from the FIFO once the SPI_DATA_DREQ has been asserted. If theCPU/FDMA fails to retrieve data by the time FIFO is full (512 bytes), the Serial Flashcontroller terminates the current transaction on the Serial Flash interface. The Serial Flashcontroller keeps track of the address sent to the Serial Flash. It calculates the new addressby incrementing the last address sent to the Serial Flash. Any one of the address registersSPI_FAST_SEQ_ADD1 and SPI_FAST_SEQ_ADD2can be used for sending the address

in FSM mode. This calculation is done for the register chosen in the sequence registers(depending upon the operand).

When the FDMA retrieves data from the FIFO, the Serial Flash controller issues a newtransaction using the repeat sequence registers for reading from the next memory location.The Serial Flash controller stores the subsequent data in the FIFO and asserts theSPI_DATA_DREQ signal as programmed. The Serial Flash controller breaks themultiple-page transaction into many SPI transactions depending upon the traffic on both theinterfaces.

After the chip select is de-asserted, the Serial Flash controller repeats the sequence writtenin the repeat sequence registers.

In the read multiple-page sequences, the Serial Flash controller stalls both interfaces(STBus interface and serial interface). For the STBus interface, it stops giving grant to FIFOread requests in case the FIFO is empty. For the SPI interface, it terminates the SPItransactions on serial bus by de-asserting the chip select, in case the FIFO full conditionarrives.


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The Figure 14shows a typical example of Serial Flash controller, FDMA/CPU and SerialFlash. The coordination between these components starts from the moment when theFDMA/CPU configures the Serial Flash controller for multiple-page sequence until the timewhen the FIFO is full and the Serial Flash controller stalls the serial interface by terminating

the SPI transaction.The Figure 15shows the continuation of events after the FIFO is full and the FDMAcontinues reading data from the FIFO.

Figure 14. Events until the FIFO is full in multiple-page read sequence

FIFO

FDMA/CPU


(1) FDMA/CPU initiates

sequence configuration.

(2) Controller initiates

the SPI transaction.

(3) Flash starts returning


(4) Half FIFO

SPI_DATA_DREQasserted by the controller.

(6) Flash continues returning(5) FDMA/CPU fetches datafrom the FIFO after its turnaround time.

OPC + ADDR

Data

CS de-assertion managedby the controller.

SPI_CLOCK

CSn

DATA_OUT

DATA_IN

Serial Flash


(7) FIFO full: SPI transactionterminated by the controller.


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Figure 15. Events after the FIFO is full in multiple-page read sequence

See Table 7and Table 8for an example of programming the registers for multiple-page read(quad mode).

FIFO

FDMA/CPU


(9) FDMA/CPU continues

fetching data from the FIFO.

(8) Flash transaction stalled.

(10) FIFO available: new SPI

OPC + ADDR

Data

SPI_CLOCK

CSn

DATA_OUT

DATA_IN

Serial Flash

transaction started by thecontroller.

CS assertion managed bythe controller.

New address calculated and providedby the controller

Table 7. Multiple-page read (quad mode) initialization sequence

Instruction Register CommentSequence

register

CMD 1 SPI_FAST_SEQ_OPC1

Write the write enable command opcode,

number of SPI_CLOCK cycles and number

of pads required to shift out the command to

the Flash, and set the chip select de-assert

(CS_DEASSERT) bit.

Program the

SPI_FAST_SEQ1

register.


Write the write status register commandopcode, number of SPI_CLOCK cycles and

number of pads required to shift out the

command to the Flash.

STATUS_REG_DATASPI_FAST_SEQ_FLASH

_STA_DATA

Write the data to be written to the status

register. Set the chip select de-assertion bit

(CS_DEASSERT) and number of pads

required.

JUMP SPI_REPEAT_SEQ1 Jump to the repeat sequence register.


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Multiple-page write

The multiple-page write operation is similar to the multiple-page read operation. The SerialFlash controller first executes the SPI_FAST_SEQn registers until it encounters a JUMPinstruction. By executing the SPI_FAST_SEQn registers sequence, it initializes the memory

into the desired mode. After reaching the JUMP instruction, it starts executing the repeatsequence registers.

For example in a typical Flash, the Serial Flash controller issues the write command,address and one page data to the Flash (Flash cannot write more than a page at a time).After the FIFO data has been transferred to the Flash, FIFO gets empty and theSPI_DATA_DREQ signal is asserted by the Serial Flash controller so that the FDMA/CPUwrites the consecutive data in the SPI_FAST_SEQ_DATAnregisters. After the data isshifted to the Flash, the Serial Flash controller de-asserts the chip select and executes theWAIT instruction. In this instruction, the Serial Flash controller waits for the pre-programmedwait counter to complete until the memory completes its page program time.

In the write multiple page sequences, the Serial Flash controller stalls both the interfaces

(STBus interface and serial interface). For the STBus interface, it stops giving grant to FIFOwrite requests in case the FIFO is full. For the SPI interface, it terminates the SPItransactions on serial bus by driving the chip select low, in case the FIFO_EMPTY conditionarrives. When the data for the consecutive pages is again written in FIFO, the Serial Flashcontroller repeats the repeat sequence. This time the address sent to the Serial Flash iscalculated and incremented by the Serial Flash controller itself.

The Serial Flash controller keeps on repeating the repeat sequence until the data written inthe Flash is equal to the transfer size programmed in the SPI_FAST_SEQ_TRANS_SIZEregister. Once the transfer size is done, the STOP instruction is served and the Serial Flashcontroller is ready again to receive new sequences of operation from the CPU/FDMA.

Table 8. Multiple-page read (quad read) repeat sequence

Instruction Register Comment Sequence Register

CMD 3 SPI_FAST_SEQ_OPC3Write the read command, number ofSPI_CLOCK cycles and number of pads

required to shift out the command to the

Flash.

Program the

SPI_REPEAT_SEQ1

register.

ADD 1SPI_FAST_SEQ_ADD1

SPI_FAST_SEQ_ADD_CFG

Write the starting address of the page,

number of SPI_CLOCK cycles and number

of pads required to shift out the address to

the Flash. Also, set the chip select

de-assertion

(CS_DEASSERT_FOR_ADD1) bit.

MODE SPI_MODE_BITSWrite the mode bits information in the

SPI_MODE_BITSregister.

DUMMY SPI_DUMMY_BITSWrite the dummy bits to be written to theFlash. Write the number of SPI_CLOCK

cycles and number of pads required to shift

out the dummy bits to the Flash.

DATA SPI_FAST_SEQ_DATAn Read the data from the Flash. Program the

SPI_REPEAT_SEQ2

register.STOP End operation.


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See Table 9and Table 10for an example of programming the registers for multiple-pagewrite (quad mode in winbond Flash).

Note: As mentioned in the single page write sequence, the software has to first write thesequence, and then write one page data in the FIFO and finally write the START_SEQ_BITbit of theSPI_FAST_SEQ_CFGregister.

Table 9. Multiple-page write initialization sequence (Winbond quad Flash)

Instruction Register Comment Sequence register



number of SPI_CLOCK cycles and


command to the Flash and set the chip

select de-assert (CS_DEASSERT) bit.

Program the

SPI_FAST_SEQ1

register.


Write the write status register command

opcode, number of SPI_CLOCK cycles

and number of pads required to shift out

the command to the Flash.

STATUS_REG_DATA SPI_FAST_SEQ_FLASH_STA_DATA


register. Set the chip select de-assertionbit (CS_DEASSERT) and number of pads

required.

JUMP SPI_REPEAT_SEQ1 Jump to the repeat sequence register.

Table 10. Multiple-page write repeat sequence (Winbond quad Flash)



Write the write enable command, number of

SPI_CLOCK cycles and number of pads

required to shift out the command to the Flash.

Also, set the chip select de-assertion

(CS_DEASSERT) bit.

Program the

SPI_REPEAT_SEQ1

register.


Write the page program command, number of

SPI_CLOCK cycles and number of pads


ADD 1

SPI_FAST_SEQ_ADD1

SPI_FAST_SEQ_ADD_

CFG

Write the starting address of the page, number

of SPI_CLOCK cycles and number of pads

required to shift out the address to the Flash.

Also, set the chip select de-assertion

(CS_DEASSERT_FOR_ADD1) bit.

DATA_WR SPI_FAST_SEQ_DATAn Write the data to be written to the Flash.

WAIT

SPI_PROGRAM_ERAS

E_TIME

Wait for counter to complete the Flash page

program time.Program the

SPI_REPEAT_SEQ2

register.STOP End operation.


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Chip select bit functioning for DATA phase in single- and multiple-pagesequences

The Serial Flash controller offers flexibility to configure opcode phase, address phase, modephase, data phase and dummy phase as per Serial Flash requirements. The flexibility toassert/de-assert CS after each of them has been provided to make them independent andalso to support changing protocols of different Serial Flashes. However, the last phase of asequence should always have the configuration to de-assert CS after the last phase is over.

Note: One particular transaction is the sequence of events happening during one CS assertion.

The purpose of this CS de-assert bit is to cater to future read/write protocol of Serial Flashdevices in which there can be some requirement to send some other instruction bits afterthe DATA read/write phase is complete. For example, executing the following read operationon Serial Flash requires CS configuration to be 0 during the DATA phase:

Opcode -> Address -> Dummy bits -> Data read -> Mode bits

For the above sequence, the data CS de-assertion bit must be configured to 0 so that the

CS remains asserted after the DATA phase as Mode bits are required to be send to theFlash device for completing the sequence. In this case, it is mandatory to configure theCS_DEASSERT bit of the SPI_MODE_BITSregister to 1 so that the CS gets de-assertedafter the mode phase is over.

However, if the CS is programmed to remain asserted after the last phase of the transactionis over, though the Serial Flash controller would not de-assert the CS itself, but it will go intoa hang state and the sequence would not get over. As a result, the CPU/FDMA would not beable to program the next sequence and the Serial Flash controller would not start withanother sequence and the IP would require a reset.

This bit does not provide the flexibility to keep CS asserted in between one multiple-pagedata transfer. The Serial Flash controller manages the CS assertion and de-assertion

across the multiple-page data transfer.

Figure 16. CS asserted after data phase is over

CSn

CLOCK

Opcode Address Dummy ModeDATA_OUT

DataDATA_IN


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4.1.9 Fast sequence boot mode

The fast sequence boot mode is designed to support x1, x2 and x4 booting. The advantageof fast sequence boot mode is that any Serial Flash read command can be used for bootingthrough Serial Flash. To bring the Serial Flash controller in the fast sequence boot mode,the HOST has to configure the SPI_MODE_SELECTregister and program the fastsequence boot mode registers. This programming must be included in the boot code.

The fast sequence boot mode also supports unaligned access requests, that is, theaddresses of the requests are not aligned with the opcodes issued.

Boot flow from system prospective

The system follows certain steps to boot in the fast sequence boot mode. These steps areillustrated in the following figure:

Figure 17. Booting from Serial Flash

CPU enables the CACHE.

CPU starts booting in the legacy mode.

CPU executes the cached instruction to wait

CPU programs the SPI_FAST_SEQ_CFG

Serial Flash Controller initializes the SerialFlash in the required mode.

CPU can now continue bootingfrom the Serial Flash.

CPU programs the SPI_MODE_SELECTregister to bring the Serial Flash controller

for 100 SPI_CLOCK cycles.

in the fast sequence boot mode.

register.


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Note: The Serial Flash controller does not check the status of the serial device before issuing anysequence to the device. This should be managed and looked upon by the CPU/HOSTbefore programming any sequence in the Serial Flash controller. For example, if any readsequence is programmed and executed during the time when the serial device is busy in

executing the erase/write command then the read command issued by the Serial Flashcontroller would be ignored by the Flash. Hence, it is mandatory for the CPU/HOST to checkthe status of the Flash before programming the Serial Flash controller.

Fast sequence boot mode flow

The Serial Flash controller starts the boot sequence as programmed in the fast sequencemode registers. This is done in two phases. In the first phase, the Serial Flash controllerexecutes the boot initialization sequence written in the SPI_QUAD_BOOT_SEQ_INITnregisters after the software/CPU writes the SPI_FAST_SEQ_CFGregister. When the SerialFlash controller encounters a JUMP instruction in the SPI_QUAD_BOOT_SEQ_INITnregisters, it starts the execution of sequences in the SPI_QUAD_BOOT_READ_SEQnregisters.

In the second phase, the SPI_QUAD_BOOT_READ_SEQn registers are executed as soonas the CPU asser ts a DATA read request to the Serial Flash controller. After receiving thedata read request, the Serial Flash controller executes the read sequence opcode from therespective registers. The address issued to the Flash is the address given by the CPU in theread request.

The fast sequence boot mode can also be used to boot in the x1 and x2 pad configurationsof the Serial Flash by initializing the SPI_QUAD_BOOT_SEQ_INITn registers using theJUMP command and programming the required read sequence in theQUAD_BOOT_READ_SEQ_REGn registers.

The example waveform sequence for the fast sequence boot mode is shown in Figure 18.

Figure 18. Waveforms for fast sequence boot mode

SPI_CLOCK

CSn

DATA_OUT

DATA_IN

STBus CLOCK

Initialization of(OPC, address sentby the controller)

To bring Flash inrequired mode Boot requests serviced to fetch data from Flash

Data returned bythe Flash

the Flash


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Registers required for the fast sequence boot mode

Write the SPI_MODE_SELECTregister to configure the Serial Flash controller in fastsequence boot mode. Once the Serial Flash controller is in the fast sequence boot mode,write the following registers for the fast sequence boot mode operation:

An example of programming the registers for the fast sequence boot mode in x4configuration is given in the following table:

Table 11. Fast sequence boot mode registers

Register Comment

SPI_FAST_SEQ_OPCnThese registers contain the opcodes and their configuration required for

reading the Flash in the boot mode.

SPI_FAST_SEQ_ADD_CFGThis register contains the address configuration required for sending the

address to the Flash in the boot mode.

SPI_MODE_BITS This register contains the mode bytes required by the Flash.

SPI_DUMMY_BITS This register contains the dummy bytes required by the Flash.

SPI_FAST_SEQ_FLASH_STA_DATA This register contains the status register data required by the Flash.

SPI_FAST_SEQ_CFGThis register contains the quad configuration information required by the

Serial Flash controller.

SPI_QUAD_BOOT_SEQ_INIT1and

SPI_QUAD_BOOT_SEQ_INIT2

These registers contain the initialization sequence required by the Serial

Flash controller to bring the Flash in the quad mode.

SPI_QUAD_BOOT_READ_SEQ1and

SPI_QUAD_BOOT_READ_SEQ2

These registers contain the quad read command sequence required by the

Flash.

Table 12. Boot initialization sequence for x4 configuration




number of SPI_CLK cycles and number of pads


Also, set the CS de-assert (CS_DEASSERT)

bit.

Program the

SPI_QUAD_BOOT

_SEQ_INIT1

register.


Write the write status register command

opcode, number of SPI_CLK cycles and


command to the Flash. Set the CS de-assert

(CS_DEASSERT) bit.

STATUS_REG_

DATA

SPI_FAST_SEQ_FLASH

_STA_DATA


register. Set the CS de-assert

(CS_DEASSERT) bit, number of bytes field and

other required information.

JUMPJump to the SPI_QUAD_BOOT_READ_SEQn

register operation.


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4.1.10 Changing modes of Serial Flash controller

Legacy modes

If the HOST wants to change the mode of the Serial Flash controller during the boot, it hasto wait for sufficient time (100 SPI_CLOCK cycles) after the last STBus transaction has

completed. Then the HOST can safely write into the SPI_MODE_SELECTregister tochange the mode of the Serial Flash controller.

Alternatively, after boot is over, the mode can be changed by the software by first readingthe SPI_STATUS_MODE_CHANGEregister, and then appropriately writing into theSPI_MODE_SELECTregister.

Fast sequence mode

The mode must be changed after the SPI_SEQ_DREQ signal is asserted(SPI_SEQ_DREQ = 1), that is, the last sequence execution is completed. TheSPI_STATUS_MODE_CHANGEregister has no significance in the fast sequence mode.

4.2 Error conditions and error handling

The Serial Flash controller sets the init_r_opc signal for illegal opcodes (other than thosementioned in Figure 7: Serial Flash controller legacy mode and comms multiplexing logic).Also, the behavior of the Serial Flash controller is indeterministic in case any illegalsequence is programmed in any of the configuration registers.

Table 13. Boot read sequence for x4 configuration


CMD 3 SPI_FAST_SEQ_OPC3 Write read command, number of SPI_CLKcycles and number of pads required to shift

out the command to the Flash.

Program the

SPI_QUAD_BOOT_R

EAD_SEQ1 register.

ADDR1SPI_FAST_SEQ_ADD1

SPI_FAST_SEQ_ADD_CFG

Write the number of SPI_CLOCK cycles

and number of pads required to shift out the

address to the Flash.

MODE SPI_MODE_BITS

Write the mode bits to be written to the

Flash.

Write the number of SPI_CLK cycles and


mode bits to the Flash.

DUMMY SPI_DUMMY_BITS

Write the dummy bits to be written to the

Flash. Write the number of SPI_CLK cyclesand number of pads required to shift out the

dummy bits to the Flash.

DATA_RD Read the data from the Flash. Program the

SPI_QUAD_BOOT_R

EAD_SEQ2register.STOP End sequence.


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4.3 Power saving modes

Not applicable.

4.4 Debug modes

Not applicable.

4.5 System requirements

4.5.1 Memory requirements

The configuration space allocated to the Serial Flash controller is from 0x2000 to 0x2FFF,that is, 4 Kbytes. At present, the Serial Flash controller uses only 0x2000 to 0x2500. Rest ofthe memory space is reserved. The Figure 19shows in detail the memory requirement of

the Serial Flash controller. For more information, refer to Chapter 9: Registers.


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Figure 19. Memory map of the Serial Flash controller

Normal mode registers

Reserved

SPI_FAST_SEQ_TRANS_SIZE register

SPI_FAST_SEQ_ADDn registers

SPI_FAST_SEQ_ADD_CFG register

SPI_FAST_SEQ_OPCn registers

SPI_MODE_BITS register

SPI_DUMMY_BITS register

SPI_FAST_SEQ_FLASH_STA_DATAregister

SPI_FAST_SEQn registers (n = 1 to 4)

SPI_FAST_SEQ_CFG register

SPI_FAST_SEQ_STA register

SPI_QUAD_BOOT_SEQ_INITnregisters (n = 1 to 2)

SPI_QUAD_BOOT_READ_SEQnregisters (n = 1 to 2)

SPI_PROGRAM_ERASE_TIME

SPI_REPEAT_SEQn registers

SPI_STATUS_WR_TIME register

Reserved

Fast sequence data FIFO(512 bytes)

Reserved

Fast sequence data registers

4 KB

0x0000

0x0FFF

Fast sequenceprogram andstatus registers

0x000

0x028

0x100

0x104, 0x108

0x10C

0x110 to 0x120

0x124

0x128

0x12C

0x130 to 0x13C

0x140

0x144

0x148, 0x14C

0x150, 0x154

0x158

0x15C, 0x160

0x164

0x168 to 0x2FC

0x300 to 0x4FF

0x500

0xFFF

(n = 1 to 2)


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4.5.2 Interrupt behavior and requirements

The Serial Flash controller has no interrupts. However, it has two DREQs available(SPI_SEQ_DREQ and SPI_DATA_DREQ) to communicate the status of the Serial Flashcontroller to FDMA. These DREQs can also be connected with the interrupt-level controller(ILC) to manage interrupts to the HOST. In that case, the HOST clears these interrupts withthe help of ILC. The Serial Flash controller does not clear these interrupts at the IP level.The Figure 8shows the DREQs connection with FDMA and its usage as interrupts by theCPU.

4.6 Initialization

Not applicable.

4.6.1 Hard reset

Hard reset (rst_n) is provided to reset the Serial Flash controller. It is active low. After hardreset, the IP is in the default normal boot mode.

4.6.2 Soft reset

Soft reset is available in the Serial Flash controller for resetting the fast sequence moderegisters and flushing the FIFO contents. For more details, refer to Chapter 9: Registers.

The soft reset is not applicable to legacy modes, that is, the IP remains in the fast sequencemode after the soft reset is applied. The IP does not go to the default normal boot modeafter the soft reset is applied.


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5 Clocking

The Serial Flash controller operates at 100 MHz. This clock is same as the EMISS clock.

The Serial Flash devices are clocked through the Serial Flash controller using SPI_CLOCK.This SPI_CLOCK is generated inside the Serial Flash controller by dividing the EMISS clockas defined by the clock division ratio in the SPI_CLK_DIVregister. Depending upon the typeof Flash used by the system, SPI_CLOCK can be managed by programming the suitableclock division ratio.

5.1 Frequencies

5.2 Clock relationships

The SPI_CLOCK and CLOCK are synchronous clocks.

5.3 Generated clocks

The SPI_CLOCK is a generated clock. It is generated by the clock divider inside the SerialFlash controller. The clock divider runs on the EMISS clock and the division ratio iscontrolled by the SPI_CLK_DIVregister. After reset, the mode pin (MODE_SPI_CLK_DIV)decides the division ratio. This mode pin is brought at the top so that the desired frequencycan be achieved at the SoC for booting. The generated SPI_CLOCK is used to clock theexternal Flash. It is also used by the Serial Flash controller to clock the incoming andoutgoing data to the external Flash.

Table 14. Example clock names and frequencies

Clock nameClock frequencies

Min Typical Max

CLOCK 0 100 MHz 100 MHz

SPI_CLOCK 0 50 MHz 50 MHz


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6 Bus interfaces

6.1 External hardware interfacesNot applicable.

Table 15. SPIRIT bus types for serial_flash_controllerBus type Vendor Library Name Version

T2-RGV st.com STBus T2-RGV 1.0

Table 16. SPIRIT bus interfaces of serial_flash_controller

Bus interface Bus type Role Address block name

type2 T2-RGV TARGET programming_and_data_transfer_bus


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7 Routers and interconnections

Not applicable.

7.1 Local interconnect (routers)

Not applicable.

7.2 Point-to-point connections

Not applicable.


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Pin group list Serial Flash controller functional specification

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8 Pin group list

Table 17. Port list for serial_flash_controller

Signal name I/O Timing Clock DescriptionLogical

grouping

rst_n I clock Active low reset

Systemclock I N/A

Global clock running at 100 MHz

maximum

mode_spi_clk_div I clockThis mode pin is used to select the

SPI frequency during bootStatic inputs

stnotatmel I clock0: Set for ATMEL

1: Set the default to ST Flash

init_req I early clock STBus request

STBus buffer

and router

interface

init_gnt O early clock SPI grant

init_valid O clock SPI response request

spi_validnextcycle O early clock

This signal indicates that the SPI

cycle will finish in the next cycle. It is

always the case when init_valid =

init_validnextcycle delayed by one

cycle. This signal may be useful for

the memory controllers that need

this information to change the

arbitration. For example, if the Serial

Flash controller needs the read data

bus in the next cycle, it may change

the arbitration for a read to internal

SRAM, which also needs the bus in

that cycle.

init_eop I early clock STBus end of packet (EOP)

init_r_eop O clock SPI response EOP

init_addr I early clockAddress to be accessed from

STBus

init_data I early clock Data from STBus

init_r_data O late clock Response data from IP

init_opc I early clock

Opcode describing operation

presented to the Serial Flashcontroller

init_r_opc O clock

Response opcode:

0: Success,

1: Fail

spi_cfgnotdat I early clock

It is used to indicate an access to

SPI configuration registers rather

than to an external bank


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spi_buff_bank I clock

0: Do not take control of shared

pads with comms subsystem.

1: Takes control of pad shared with

comms subsystem and releases it

only when response corresponding

to all requests have been received.

(Currently, this pin is tied at EMISS

level itself).

System

spi_not_cs O early spi_clock Chip select for Serial Flash

Pad interface

spi_clock O spi_clock Clock to Serial Flash

spi_data_out O early spi_clock Serial data to Serial Flash

spi_data_in I early spi_clock Input data from Serial Flash

spi_dbl_data_in I early spi_clock

Input port for serial data in when

configured in the dual output read

mode

spi_data_out_quad O spi_clockOne of the output data port for the

quad data mode

spi_hold_in I spi_clock Hold input from Serial Flash

spi_hold_out O spi_clock Hold output for Serial Flash

spi_wr_protect_in I spi_clock Write protect input for Serial Flash

spi_wr_protect_out O spi_clock Write protect output for Serial Flash

spi_clk_enb O clock Enable to put the spi_clock pad ininput mode during reset

Padlogic

interface (to top

glue for

multiplexing

Comms-SPI

with Flash-SPI)

spi_cs_enb O clockEnable to put the spi_not_cs pad in

input mode during reset

spi_data_out_en O early clock

Enable for deciding the polarity of

the bidirectional port at the top level

for the dual output read mode

spi_data_in_enb O clockEnable for spi_data_in the

bidirectional pad

spi_hold_enb O clockHold enable required for the HOLD

pad

spi_wr_protect_enb O clock Write protect enable required for theWP pad

spibootnotcomms O clockThis signal is used to take the

control of the pads

Table 17. Port list for serial_flash_controller (continued)


grouping


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spi_seq_dreq O clockDreq generated to indicate the end

of the programmed sequence

Pacing signals

for the fast

sequence modespi_data_dreq O clock

Dreq generated to indicate that the

FDMA/CPU must read the data from

the FIFO if it is a read operation or

write the data into the FIFO if it is a

multiple-page write operation

tst_scanenable I early clock

Test

tst_scanin I clock

tst_scanout O clock

tst_scanmode I early clock

tst_gclkenable I early clock

Table 17. Port list for serial_flash_controller (continued)


grouping


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9 Registers

9.1 Address blocks and sub-blocks

The configuration space available to the Serial Flash controller is 4 Kbytes from 0x02000 to0x02FFF. All programming registers are accessible through the Type 2 port.

9.1.1 Summary table

Table 18. SPIRIT address block programming_and_data_transfer_bus

Base address Size Address block Description

0x2000 4 K SPI SPI programming registers

Table 19. Register summary table

Address offset Register Description See

0x010 SPI_CLK_DIV Clock division register page 47

0x018 SPI_MODE_SELECT

Contiguous mode, fast read mode, dual

output mode, fast sequence mode and fast

sequence boot mode selection.

page 48

0x020 SPI_CONFIG_DATA

Configure the Serial Flash controller for

different parameters of the Serial Flash

supported

page 49

0x028 SPI_STATUS_MODE_CHANGE

Single-bit status register reflecting when

mode of SPI (in the SPI_MODE_SELECT

register) can be changed

page 50

0x100 SPI_FAST_SEQ_TRANS_SIZETotal number of bits to be read/written

from/to the Flashpage 50

0x104 SPI_FAST_SEQ_ADD1 Starting address of the memory location of

the Flash to be read or written

page 51

0x108 SPI_FAST_SEQ_ADD2 page 51

0x10C SPI_FAST_SEQ_ADD_CFGAddress configuration information required

for shifting the address in the Flashpage 52

0x110 - 0x120SPI_FAST_SEQ_OPCn

(n = 1 to 5)

Opcodes required to be

serial flash controll

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