sequential quadrature measurements for ......iii abstract sequential quadrature measurements for...
TRANSCRIPT
SEQUENTIAL QUADRATURE MEASUREMENTS FOR PLASMA
DIAGNOSTICS
by
Julio Martin-Hidalgo
A thesis submitted in partial fulfillmentof the requirements for the degree
of
MASTER OF SCIENCE
in
Electrical Engineering
Approved:
Dr. Charles M. Swenson Dr. Koushik ChakrabortyMajor Professor Committee Member
Dr. Todd Moon Dr. Mark R. McLellanCommittee Member Vice President for Research and
Dean of the School of Graduate Studies
UTAH STATE UNIVERSITYLogan, Utah
2014
ii
Copyright c© Julio Martin-Hidalgo 2014
All Rights Reserved
iii
Abstract
Sequential Quadrature Measurements for Plasma Diagnostics
by
Julio Martin-Hidalgo, Master of Science
Utah State University, 2014
Major Professor: Dr. Charles M. SwensonDepartment: Electrical and Computer Engineering
The study of the ionosphere has been very important due to its effects on terrestrial
and satellite communications. This thesis presents an introduction of the ionosphere effects,
its modeling and measurement methods that have been used along the history.
The Sweeping Impedance Probe (SIP) has proven over the years to be a reliable method
based on the radio frequency (RF) behavior of the plasma. A new SIP architecture is
presented based on the latest techniques available, using a Vector Network Analyzer (VNA)
detection and employing dynamic correction of errors with Correlated Double Sampling
(CDS) and a reference channel. The design will be detailed showing the component selection
based on their performance parameters. In this sense, several analyses have been made
to ensure that the sweep rate and accuracy requirements can be met. The testing and
calibration methodology is developed to further increase the final accuracy of the instrument.
Lastly, the main conclusions of the project are summarized and new and exciting lines
of work are presented for what is expected to be the next generation of SIP instruments.
(120 pages)
iv
Public Abstract
Sequential Quadrature Measurements for Plasma Diagnostics
by
Julio Martin-Hidalgo, Master of Science
Utah State University, 2014
Major Professor: Dr. Charles M. SwensonDepartment: Electrical and Computer Engineering
The ionosphere is the atmosphere layer characterized by its high concentration of
ionized plasma. It has a great impact on radio communications with satellites, causing
disturbances and disruptions. Therefore, it is important to understand and predict the
ionosphere characteristics.
The Sweeping Impedance Probe (SIP) is an instrument for characterizing the ionosphere
used for many decades with great success. In this thesis, a new SIP architecture design is
presented using the latest techniques and components available. The design is detailed and
analyses have been performed to ensure the required performances. The new SIP will be
flown in the Auroral Spatial Structures Probe (ASSP) sounding rocket mission in early 2015,
and it is expected it will make the most accurate measurements to date.
Lastly, the conclusions of this project are presented and future work is outlined for what
will become the next generation of SIP instruments.
v
To my family...
vi
Acknowledgments
First of all, I would like to thank Dr. Charles Swenson. Without him this thesis would
not have been possible. He is not only a great professional but also a wonderful person.
There are many people at Space Dynamics Laboratory (SDL) involved in this project who
have helped me in one way or the other, including Chad Fish, Tim Nielsen, Cameron Weston,
Wade Cox, and many others. In particular, the coaching provided by Wayne Sanderson and
Earl Pound at the beginning of the project was very helpful.
I would like to mention professors from Utah State University (USU), where I have been
able to learn many interesting and various topics, and in some cases, who have helped me
be a better engineer and researcher developing my critical thinking and improving my skills.
I would also like to thank my family who, from far away, have given me their support
and strength. Thanks to my friend, Dean, for his corrections and the good times during
these years.
Last, but not least, I am grateful to Fundacion Obra Social La Caixa for giving me the
opportunity to study here. It has been not only very educational, but also an incredible
personal experience for me.
Julio Martin-Hidalgo
vii
Contents
Page
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Public Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Ionospheric Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Plasma Physics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1 Plasma as a Dielectric Medium . . . . . . . . . . . . . . . . . . . . . 51.3.2 Capacitor Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.3 Balmain Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 RF Impedance Probe Methods . . . . . . . . . . . . . . . . . . . . . . . . . 91.4.1 Plasma Frequency Probe . . . . . . . . . . . . . . . . . . . . . . . . 101.4.2 Sweeping Impedance Probe . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 ASSP Mission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.6 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Instrument Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.1 Vector Network Analyzer Concept . . . . . . . . . . . . . . . . . . . . . . . 142.2 Sweeping Impedance Probe Requirements . . . . . . . . . . . . . . . . . . . 152.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.4 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.1 Correlated Double Sampling . . . . . . . . . . . . . . . . . . . . . . . . 212.4.2 Reference Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.4.3 Summary of Instrument Operation . . . . . . . . . . . . . . . . . . . 24
3 Design and Analyses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.1 Detailed Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Direct Digital Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . 253.1.2 RF Head . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.1.3 Detector and ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.1.4 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.1.5 Power Conditioning and Filtering . . . . . . . . . . . . . . . . . . . . 34
viii
3.2 Analyses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.2.1 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.2.2 Nonlinear Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.2.1 Loading Effect . . . . . . . . . . . . . . . . . . . . . . . . . . 413.2.2.2 Harmonic Analysis . . . . . . . . . . . . . . . . . . . . . . . . 413.2.2.3 ADC Resolution . . . . . . . . . . . . . . . . . . . . . . . . 423.2.2.4 ADC Linearity . . . . . . . . . . . . . . . . . . . . . . . . . 423.2.2.5 Other Sources of Nonlinearity . . . . . . . . . . . . . . . . 44
3.2.3 Saturation: Maximum Admittance . . . . . . . . . . . . . . . . . . . 443.2.4 Measurement Uncertainty . . . . . . . . . . . . . . . . . . . . . . . . 44
4 Calibration and Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.1 Calibration Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1.1 Error Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.1.2 Calibration Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.1.3 Calibration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2 Initial Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61A Current Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
A.1 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62A.2 Configurations Tested . . . . . . . . . . . . . . . . . . . . . . . . . . 65A.3 Final Transformer Tests . . . . . . . . . . . . . . . . . . . . . . . . . 69A.4 Hystereis and Saturation . . . . . . . . . . . . . . . . . . . . . . . . 72A.5 Shield Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
B PCB Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74C FPGA RTL Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82D Calibration Loads Characterization . . . . . . . . . . . . . . . . . . . . . . . 97E Ground Support Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
E.1 Scalar Network Analyzer . . . . . . . . . . . . . . . . . . . . . . . . 103E.2 SIP Ground Support Equipment . . . . . . . . . . . . . . . . . . . . 103
F DVD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ix
List of Tables
Table Page
3.1 SIP modules occupation on the FPGA. . . . . . . . . . . . . . . . . . . . . . 34
3.2 Power consumption of the SIP instrument. . . . . . . . . . . . . . . . . . . . 36
3.3 Measurement uncertainty of the SIP instrument. . . . . . . . . . . . . . . . 46
A.1 List of current transformer configurations tested. . . . . . . . . . . . . . . . 66
x
List of Figures
Figure Page
1.1 Ionosphere electron density vs. altitude and composing layers. . . . . . . . . 2
1.2 Global TEC real-time data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Capacitor model of an impedance probe. . . . . . . . . . . . . . . . . . . . . 7
1.4 Impedance of a small antenna in plasma. . . . . . . . . . . . . . . . . . . . . 8
1.5 ASSP main payload schematic view. . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Block diagram of the N2PK network analyzer. . . . . . . . . . . . . . . . . 15
2.2 ASSP SIP block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 SIP VNA block diagram and operation. . . . . . . . . . . . . . . . . . . . . 19
2.4 Admittance plane and calculation of the components. . . . . . . . . . . . . . 21
2.5 Measurement of complementary values (CDS) for offset cancellation. . . . . 23
2.6 Measurement of a reference admittance for phase delay and gain correction. 24
3.1 DDS output configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2 RF Head block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Mitigation of shunt capacitance with a guard. . . . . . . . . . . . . . . . . . 29
3.4 FPGA design block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 FPGA and SIP overall timing diagram. . . . . . . . . . . . . . . . . . . . . 33
3.6 Power generation and conditioning from the primary bus. . . . . . . . . . . 35
3.7 Phase noise spectrum at the DDS output. . . . . . . . . . . . . . . . . . . . 38
3.8 Phase noise spectrum at the LNA output. . . . . . . . . . . . . . . . . . . . 39
3.9 Phase noise spectrum at the ADC input. . . . . . . . . . . . . . . . . . . . . 39
3.10 CDS filter response in time and frequency domains. . . . . . . . . . . . . . . 40
xi
3.11 Phase noise spectrum reduction with the use of CDS. . . . . . . . . . . . . . 40
3.12 Loading effect on the DDS output. . . . . . . . . . . . . . . . . . . . . . . . . 41
3.13 Nonlinear error produced by harmonic mixing of the local oscillator with DDSharmonics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.14 Saturation and gain analysis of the measurement chain. . . . . . . . . . . . 44
3.15 Admittance gain and phase error as a function of the quadrature componentserrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1 Noise measurements with different configurations. . . . . . . . . . . . . . . . . 51
4.2 Offset measurements with and without CDS. . . . . . . . . . . . . . . . . . 52
4.3 Dynamic range of the instrument measuring different capacitors. . . . . . . 53
4.4 Residual error for a 4 pF capacitor measurement. . . . . . . . . . . . . . . . 54
4.5 Measurement comparison of a resonant frequency with a commercial VNA. 55
A.1 Typical circuit using a current transformer. . . . . . . . . . . . . . . . . . . 63
A.2 General model of the current transformer. . . . . . . . . . . . . . . . . . . . 63
A.3 Lumped elements model of the current transformer. . . . . . . . . . . . . . 63
A.4 Low frequency model of the current transformer. . . . . . . . . . . . . . . . 64
A.5 High frequency model of the current transformer. . . . . . . . . . . . . . . . 65
A.6 Current transformer test set-up. . . . . . . . . . . . . . . . . . . . . . . . . . 67
A.7 Normalized gain for different core geometries and sizes. . . . . . . . . . . . . 67
A.8 Normalized gain for different core materials. . . . . . . . . . . . . . . . . . . 68
A.9 Normalized gain for different turns ratio. . . . . . . . . . . . . . . . . . . . . 69
A.10 Final tests for transformer selection. . . . . . . . . . . . . . . . . . . . . . . 70
A.11 Final tests for transformers selection with detail in the operational frequencybandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A.12 Harmonics testing of the current transformer. . . . . . . . . . . . . . . . . . 72
A.13 Current transformer shield rejection test set-up. . . . . . . . . . . . . . . . . 73
xii
A.14 Rejection ratio of currents through the shield of the current transformer. . . 73
D.1 Test set-up for the calibration loads characterization. . . . . . . . . . . . . . 97
D.2 Calibration of the VNA with an SMB to N-type adapter and an N-type cal kit. 98
D.3 s1,1 magnitude and phase of the 50 Ω load. . . . . . . . . . . . . . . . . . . . 99
D.4 Impedance magnitude and phase of the 50 Ω load. . . . . . . . . . . . . . . 99
D.5 s1,1 magnitude and phase of the SHORT load. . . . . . . . . . . . . . . . . . 100
D.6 Impedance magnitude and phase of the SHORT load. . . . . . . . . . . . . 100
D.7 s1,1 magnitude and phase of the OPEN load. . . . . . . . . . . . . . . . . . . 101
D.8 Impedance magnitude and phase of the OPEN load. . . . . . . . . . . . . . . 101
D.9 s1,1 magnitude and phase of the unloaded SMB connector. . . . . . . . . . . 102
D.10 Impedance magnitude and phase of the unloaded SMB connector. . . . . . 102
E.1 SNA GSE block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
E.2 SNA GSE software interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 104
E.3 SIP GSE software interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
xiii
Acronyms
AC Alternating Current
ADC Analog-to-Digital Converter
AM Amplitude Modulation
ASSP Auroral Spatial Structures Probe
AWG American Wire Gauge
CDS Correlated Double Sampling
CSV Comma-Separated Value
CT Current Transformer
DAC Digital-to-Analog Converter
DAS Data Acquistion System
DC Direct Current
DCR Direct Conversion Receiver
DDS Direct Digital Synthesizer
DUT Device Under Test
EMI Electromagnetic Interference
FDTD Finite Difference Time Domain
FPGA Field-Programmable Gate Array
GBW Gain-Bandwidth Product
GPS Global Positioning System
GSE Ground Support Equipment
IGRF International Geomagnetic Reference Field
INL Integral Nonlinearity
LDO Low-Dropout Regulator
LNA Low-Noise Amplifier
LO Local Oscillator
LPF Low-Pass Filter
xiv
LSB Less Significant Bit
MF Major Frame
PFP Plasma Frequency Probe
PIP Plasma Impedance Probe
PLL Phase Locked Loop
RAM Random-Access Memory
RF Radio Frequency
RMS Root Mean Squared
RSS Root Sum Squared
RTL Register-Transfer Level
SDL Space Dynamics Laboratory
SF Sub Frame
SFDR Spurious-Free Dynamic Range
SIP Sweeping Impedance Probe
SNA Scalar Network Analyzer
SS Stainless Steel
SSB Single-Sideband
TCR Temperature Coefficient of Resistance
TEC Total Electron Content
TM Telemetry
UART Universal Asynchronous Receiver/Transmitter
USU Utah State University
VNA Vector Network Analyzer
1
Chapter 1
Introduction
1.1 History
When Marconi transmitted the first transatlantic radio waves in 1901, the scientific
community was astonished. It was well known that electromagnetic waves propagate in
straight lines, and the Earth’s curvature should it have made impossible this kind of long
distance transmission. Heaviside and Kennelly speculated that a layer of ionized plasma
high in the atmosphere could have been reflecting radio waves. Later in 1932, the term
ionosphere proposed by Watson-Watt was adopted.
The ionosphere is composed of ions and free electrons forming a plasma. The high-energy
ultraviolet and X-rays solar radiation are absorbed by the neutral atoms and molecules
causing them to release electrons. Due to this ionization mechanism, the plasma is quasi-
neutral, that is, the number of ions and electrons are practically the same. As will be
explained, it is often more convenient to determine the number of electrons instead of the
different ions. The fundamental parameter which defines the level of ionization is the electron
density or Total Electron Content (TEC).
The ionosphere has a great temporal and spatial variability. In altitude, the different
species and concentrations found in the atmosphere absorb different wavelength and amounts
of energy, creating layers of higher concentration as shown in Fig. 1.1 [1]. The ionosphere
extends from 70 km in altitude to thousands of km, with the electron density being zero at
the surface (total recombination). During the night, two layers named E and F are present.
During the day, the D layer appears and layer F is divided into two sublayers. In addition to
the daily cycle, differences can be also be observed with the seasons and with the solar cycle.
The spatial variability is mainly influenced by the Earth’s magnetic field (Fig. 1.2 [2]). At
low latitudes, plasma is concentrated on either side of the magnetic equator forming what
2
is known as the equatorial anomaly. Of even more importance are the solar storms which
cause disturbances in the ionosphere, or plasma bubbles which form at the bottom of the
ionosphere and float to the top leaving a turbulent wake that is impenetrable to radio waves.
Both are unpredictable with the current models.
The ionosphere has numerous effects on radio waves depending on their frequency.
Low frequency radio waves, like the one transmitted by Marconi, are bounced from the
ionosphere, while the higher frequency waves are capable of passing through. However,
they also suffer from different effects like absorption, Faraday rotation, or phase change
due to an increased electrical path. The highest frequency of radio waves that will reflect
Fig. 1.1: Ionosphere electron density vs. altitude and composing layers.
Fig. 1.2: Global TEC real-time data.
3
back to Earth when transmitted vertically is called the critical frequency of the ionosphere.
Radio waves are reflected from the ionosphere when their frequency matches the resonance
of the ionospheric plasma. This resonance is related to the local electron density so that
radio waves are reflected at different altitudes depending on their frequency, with the lower
frequencies reflected at the E layer and the higher frequencies at the F layer. Changes in
the electron density can allow radio waves to be transmitted further away (like AM radios
during the night) or be completely disrupted. In the same way, satellite communications
get affected with distortions and disruptions. The Global Positioning System (GPS) signals
must be corrected for the total electron content line-of-sight from the satellite to the receiver
to achieve high accuracy. This is done by sending signals at two or more distinct frequencies
and comparing the relative delay between them to determine the total electron content. The
GPS constellation includes a TEC instrument to account for the increased delay of the radio
waves, improving the positioning accuracy, as well as providing high redundancy to mitigate
disruptions.
Because of its practical implications on radio wave transmission and its high variability,
the ionosphere has been studied for decades with many different methods. Nowadays TEC
real-time maps are available online, but there is still a high demand for better models and
predictability. For example, the United States government spends $500 million annually
to predict and mitigate the disturbances produced by the ionosphere. One of the best
models available is GAIM-GM by Utah State University (USU) Space Weather Center,
which provides real-time information on the structure of the ionosphere based on 357 TEC
stations.
1.2 Ionospheric Measurements
After its discovery, the ionosphere was studied with the same mechanism Marconi
used to communicate over the Earth’s horizon that is, by reflecting radio waves from it.
Ionosondes operate by emitting a signal of time varying frequency to the ionosphere and
determining the propagation time of the reflected signal. With this information the virtual
height and electron density can be calculated at different altitudes. Another approach is the
4
incoherent scatter radar, measuring the reflected power scattered by the cloud of electrons
around individual ions. These techniques were later implemented in the mid 50s on satellites
making the first topside sounders (i.e. above the F layer).
While most of the current TEC data and models are developed with ground instruments,
in-situ measurements provide better accuracy and are more appropriate to measure localized
plasma anomalies, turbulences, or bubbles. Because the ionosphere minimum height is
about 70 km, the use of high altitude atmospheric balloons is impossible, reserving in-situ
measurements for sounding rockets and satellites. In fact, the first in-situ measurement
was made by error. After World War II, Americans and Soviets acquired V2 rockets and
scientists from Germany. Post war testing of the V2 rockets implemented a radio for
telemetry purposes. On some the first flights the radio signal was lost when the rockets
exceed a certain altitude and recovered again once it fell below the same altitude. It was
understood that the local ionospheric plasma was interacting with the antenna and detuning
it from the transmitter. This and other phenomena were used to study the density and
structure of the ionosphere. After those first experiments, space weather measurements
with sounding rockets became an important scientific goal. They are still in use for low
altitudes where satellites can not survive due to high atmospheric drag or during short lived
phenomena when it is difficult to get a satellite at the correct location.
Two groups of instruments have been widely used over the years for in-situ measurements
of the electron density: Langmuir probes and impedance probes. The first uses probes that
collect the free electrons and measure the Direct Current (DC) current collected by the probe
as a function of voltage. The latter are based on probes immersed in the plasma and studying
the varying electrical properties of its impedance. USU and the Space Dynamics Laboratory
(SDL) have an extensive history of over 50 years studying the ionosphere on-board sounding
rockets and small satellites [3], and are one of the pioneers of the impedance probes.
5
1.3 Plasma Physics
1.3.1 Plasma as a Dielectric Medium
In order to understand the impedance probe methods, it is convenient to first understand
the plasma properties of the ionosphere. A cold plasma with a magnetic field aligned with
the Z-axis, can be approximated as a dielectric medium with the following form for the
tensor permitivity:
←→ε r =
ε1 −iε2 0
iε2 ε1 0
0 0 ε3
, (1.1)
where
ε1 = 1 +1
ω
∑k
ω∗kω
2pk
Ω2k − ω∗
k2 , (1.2)
ε2 =1
ω
∑k
Ωk
Ω2k − ω∗
k2 , (1.3)
ε3 = 1− 1
ω
∑k
ω2pk
ω∗k
, (1.4)
ω∗ = ω − jνk, (1.5)
ω2pk =
nkq2k
ε0mk, (1.6)
Ωk =qkBomk
, (1.7)
nk, mk, qk, and νk are the density, mass, charge, and ion or electron neutral collision
frequency of the kth species, with the first species being electrons followed by various ion
species.
For frequencies between 100 kHz and 20 MHz, the ions are unmoving due to their higher
mass. Focusing on the electrons, the plasma presents several interesting natural resonant
frequencies.
6
• Plasma frequency (ωp): the natural resonant frequency of the electrons on a plasma in
the absence of a magnetic field. It is dependent on the electron density ne,
ωp =ε0me
e2ne. (1.8)
• Electron gyrofrequency (Ωk): the natural resonant frequency of the electrons under a
constant magnetic field,
Ωe =eBome
. (1.9)
1.3.2 Capacitor Model
The most common geometry used for impedance probes used short dipoles and
monopoles. These probes are electrically short, and therefore its free space impedance
is purely capacitive. As a first approach, we can consider the probe as a capacitor filled with
dielectric plasma (see Fig. 1.3). It can be shown that the impedance under this condition
follows the equation
C(θ) = C01
2[ε1(1 + cos2(θ)) + ε3 ∗ sin2(θ)], (1.10)
where θ is the angle between the probe and the magnetic field and C0 is the free space
capacitance for a cylindrical capacitor with inner radius a and outer radius b given by
C0 =2πε0L
ln( ba). (1.11)
When the probe is excited at low frequencies between 100 kHz and 20 MHz, only the
electrons are capable of moving, while the ions that are heavier than the electrons remain
static. The electron-neutron collision frequency in the altitudes of interest (E and F regions)
is only a few kHz, much lower than the cyclotron frequency and can be eliminated from the
7
r
+
-
Fig. 1.3: Capacitor model of an impedance probe.
expression. With these considerations the impedance is
Z =2
jωC0[(1 +ω2p
Ω2e−ω2 ) cos2(θ) + (1− ω2
p
ω2 ) sin2(θ)]. (1.12)
The impedance is shown in magnitude and phase in Fig. 1.4. Two resonant frequencies
are observed.
• A low impedance resonance (similar to a R-L-C series resonant circuit) at the electron
gyrofrequency.
• A high impedance resonance (similar to a R-L-C parallel resonant circuit) at the
upper-hybrid frequency. This frequency is the combination of the plasma frequency
and gyrofrequency
ω2uh = ω2
p + Ω2e. (1.13)
The electron density can be obtained by measuring the upper-hybrid frequency as
follows
ne =4πε0me
e2(f2uh − f2
c ), (1.14)
where the only unknown parameter is the electron gyrofrequency. Because it is only dependent
8
of the magnetic field, it can be calculated from magnetic field models (IGRF), or with the
use of local measurements of the magnetic field.
1.3.3 Balmain Model
The capacitor approach fails to account for the effects of the plasma on the charge
distribution on the probe surface. It is also limited to cold plasmas, but the general impedance
shape and resonant frequencies are the same as other models, and it is very intuitive. More
complex models have been developed over the years, with Balmain’s model [4] being the most
accepted and used. It treats the probe as an antenna with an assumed triangular current
distribution. The modeled impedance can be seen in Fig. 1.4, and has been validated several
times in plasma chambers as well as sounding rocket flights. The impedance expression is as
follows
Z =a
jω2πε0ε1LF 1/2[ln
L
ρ− 1− ln
a+ F 1/2
2F], (1.15)
in which F = sin2 θ + a2cos2θ and a2 = ε1/ε3.
1 1.5 2 2.5 3 3.5 4 4.5 5
102
104
106
fc
fuh
fp
Frequency [MHz]
Mag
nit
ud
e[Ω
] C0
Capacitor modelBalmain model
1 1.5 2 2.5 3 3.5 4 4.5 5
−90
−45
0
45
90
Frequency [MHz]
Ph
ase
[deg
rees
]
Fig. 1.4: Impedance of a small antenna in plasma.
9
Another approach is to numerically solve for the impedance of an antenna in a plasma.
This has been done using a Finite Difference Time Domain (FDTD) model and plasma fluid
equations [5]. One of the key observations of this model is that when near the upper hybrid
resonance the current distribution on the antenna deviates from the triangular shape as
was assumed by Balmain. The result is that the magnitude of the impedance is an order of
magnitude less than what is predicted by the analytical theories.
The impedance or radio frequency (RF) methods have several advantages over Langmuir
probes. They are loosely dependent on the rocket or spacecraft surface charge (providing an
absolute measurement), the magnetic field orientation, or the plasma temperature. Although
the free space capacitance changes with the geometry of the probe, the resonant frequencies
remain unchanged, making this kind of instruments ideal and accurate for plasma diagnostics.
The upper-hybrid frequency usually has a high quality factor, being very sharp, and the
phase crosses zero, making it very convenient and simple for instruments to track this
frequency.
One source of error of this kind of probes is the shunt capacitance that is in parallel
with the probe and sense electronics input. It is the total capacitance of the sensor geometry
that is not filled with plasma and is electrically parallel with the actual probe input. The
physical cause of the shunt capacitance are the stray capacitances of traces or wires inside
the instrument before its connection to the probe input. The result is a reduced sensitivity
to the plasma effects to be observed. It can be effectively mitigated with electrical guard
designs as will be explained in the following chapters.
1.4 RF Impedance Probe Methods
Several approaches have been used over the years for measuring the parallel resonance
of an impedance probe which is associated with the upper hybrid frequency of a plasma.
They can mainly be classified into two groups, those that sweep and measure the magnitude
of the impedance curve, and those that observe the phase change associated with the parallel
resonance.
10
1.4.1 Plasma Frequency Probe
The Plasma Frequency Probe (PFP) measures the upper-hybrid frequency by tracking
when the phase crosses zero as the resonant frequency is changed. The usual method is
some kind of analog Phase Locked Loop (PLL), although there are several variations. They
perform a wide sweep to locate the resonant frequency and then they lock in. If for any
reason the lock is lost, the search procedure is started again. It has also been implemented a
Sweeping PFP, where a continuous sweep is performed until the resonant frequency is found.
The number of steps taken in the sweep is recorded and the procedure begins again.
1.4.2 Sweeping Impedance Probe
The Sweeping Impedance Probe (SIP) excites the probe with a constant voltage, and
measures the current flowing. The method for measuring the current has been changed
over the years as new electronic components became available, and with new innovative
designs. They normally measure it in quadrature to obtain the complex impedance. Because
the measure is proportional to the admittance, they are sometimes referred as admittance
probes (and it is usually more convenient for expressing errors or saturation ranges). When
the measurement is finished, the frequency is swept over the full range, obtaining a very
detailed impedance curve. The main disadvantage is the lower sweep rate compared with
the PFP and the huge amount of telemetry required for a single sweep.
Only the variations of the impedance with respect the free space capacitance C0 are of
interest. Several techniques have been used trying to subtract C0 from the probe impedance,
obtaining a narrower range and increased sensibility. However, determining C0 is not easy
because it requires a rocket mock-up hanging in free space in the absence of any element for
many meters.
The latest SIP instruments flown are the STORMS mission [6], and the Japanese
S-520-26 [7], in 2012.
1.5 ASSP Mission
The Auroral Spatial Structures Probe (ASSP) [8] is a NASA mission intending to
11
study the energy flow around the aurora. It will consist of a sounding rocket, which ejects
six subpayloads during the flight. This will be the first mission directed by NASA with
a constellation deployed from a sounding rocket. This formation will take measurements
simultaneously providing unique spatial and temporal variations of the different magnitudes.
ASSP is scheduled to be launched in the early 2015 from Poker Flats Flight, and will measure
the ionosphere under aurora conditions from 110 km to 606 km.
The ASSP instruments are being developed and built by SDL-USU. All seven payloads
include several instruments such as electric field, magnetometer and a Langmuir probe.
Additionally, the main payload in the rocket includes a SIP and a Multi Fix-Bias Langmuir
Probe. The position of the different instruments can be seen in Fig. 1.5.
The ASSP SIP is implemented using a new architecture, intending to be more accurate
ERAU Sweeping
Langmuir Probe
SLP
USU Sweeping
Impedance Probe
(SIP)
72 in
USU Electric Field
Probe
0.50in.
Ø 2.0in.
EFP Sensor
EFP Guard
EFP Guard
UTD E-Field
Boom System
Guard
FPP Sensor
EFP Sensor 1
EFP Sensor 2
EFP Sensor 3
EFP Sensor 4
SIP Sensor
NASA Air Spring
1.0in.
19 in24.5 in
6.0 in
8.0in.
ERAU Multi Fix-
Bias (via FPP)
Langmuir Probe
called Fast
Temperature probe
(FTP)
Science (Flux MAG)
Sensor Head
USU Ground
Heater Support
ASSP Sub
Payloads
Power Cntl
USU-SDL
Main
Electronics
Power Cntl
Sweeping
Impedance
Probe
Pull Away Umbi
Internal Heating
110 to 120 C for
60 min pre-
launch
SLP Guard
1
SLP
Science Measurements
Electric Field Probe, (V12, V34)
Electric Field Spectrometer (WP1-WP16)
Floating Potential Probe (FPP)
Magnetic Field [Mres MAG] (B1x, B1y, B1z)
Magnetic Field [Flux MAG] (B2x, B2y, B2z)
Sweeping Langmuir Probe (SLP-H, SLP-L)
Fast Temperature Probe (FTP[1-5]-L – FTP[1-5]-H)
Sweeping Impedance Probe (SIP1 – SIP4)
GPS Position and Timing
NASA TM Power
SDL Mid Hinge
Boom System
Science (Mres MAG)
Magnetoresistive
Sensor Head
UTD E-Field
Boom Hinge
SIP Pre-AMP
Electric Field Wave
Power Probe uses V34
SLP Guard
Fig. 1.5: ASSP main payload schematic view.
12
and fast than the previous generations by using the latest electronic components and
techniques, and a very careful design and calibration methodology. The ASSP mission is
ideal for a SIP due to the high altitude, which will cover regions E and F.
1.6 Thesis Outline
The objective of this thesis is to present the work done and the lessons learned during
the development of the new SIP architecture.
Chapter 1 has covered the ionosphere history, past measurements, in particular the RF
methods, where an introduction of the plasma physics behind these instruments is given
for clarity. Lastly, the ASSP mission has been introduced where the SIP instrument will
be used. This chapter should give the reader a general idea of the motivation behind this
project and thesis.
The ASSP SIP overview is covered in Chapter 2, including the requirements driving
the design and the theory of operation of the instrument.
Chapter 3 details the different components and units comprising the ASSP SIP. The
different analyses during the design are presented here showing the performances achieved
compared with the requirements.
SIP testing, calibration, and performances results are presented in Chapter 4. Calibration
is a critical step during testing, based on the error model analyzed, well known calibration
loads, and a careful methodology.
In Chapter 5, the conclusions of this project are described, giving the reader a summary
of the achievements and tasks that could be improved in the future.
As part of any engineering job, multiple design files have been generated. These
are included in the different Appendices for reference. Appendix A contains the current
transformer analyses and testing. The design schematics of the different boards can be
found in Appendix B. The digital design implemented in the Field Programmable Gate
Array (FPGA) is shown in Appendix C. Appendix D includes the characterization of the
calibration loads. Software were developed to operate the test equipment and the instrument,
and they are detailed in Appendix E. All the information related to this thesis is included in
13
electronic format in the DVD attached. Its contents are described in Appendix F.
14
Chapter 2
Instrument Overview
2.1 Vector Network Analyzer Concept
The Sweeping Impedance Probe developed for the Auroral Spatial Structures Probe
sounding rocket is based on concept and designs developed by the amateur radio community
for vector network analyzers. This community has developed a variety of low-cost vector
network analyzers (VNA) and released the designs and build experiences on the Internet.
Assembled or unassembled kits for these VNAs can be purchased. These VNAs are able to
make transmission and reflection measurements from 0.05 to 60 MHz, with about 0.035 Hz
frequency resolution and over 110 dB of dynamic range. This capability spans the needs for
an impedance probe. The ASSP SIP is greatly influenced by the VNA developed by the
radio amateur with call sign N2PK and is referred to as the N2PK VNA.
The block diagram for the N2PK VNA [9] is presented in Fig. 2.1 where a Device Under
Test (DUT) is shown undergoing a simple transmission or Wheatstone type reflection bridge
measurement. The RF Direct Digital Synthesizer (DDS) block generates an RF voltage at a
0 reference phase which is applied to the input of the DUT. The output from the DUT
to the RF Detector input is a signal to be measured with a given amplitude and phase. In
addition, the RF signal at the Detector input is measured with a short length of transmission
line in place of the DUT that is assumed to have unity gain and zero phase, and with an
open at the Detector input. From these three vector measurements at a single frequency,
all DUT transmission characteristics, such as gain and phase, can be calculated [9]. In the
same way, impedance and reflection characteristics of the DUT can be measured with the
use of a reflection bridge. In this case, three accurate terminations, open, short, and load,
are used as references.
The N2PK VNA uses a narrowband direct-conversion architecture to convert the
15
Fig. 2.1: Block diagram of the N2PK network analyzer.
detected signal to DC base band through mixing. The DC voltage is dependent not only on
the magnitude of the RF voltage at its input, but also its phase relative to the RF signal
at the local oscillator (LO) input. Highly accurate measurements of this amplitude and
phase dependent DC voltage are obtained using a precision linear analog detector, a 24-bit
analog-digital converter, and precise phase control of the LO DDS. The phase information is
obtained by making two sequential DC measurements for each frequency and test condition
(reference loads and DUT). In each case, the first measurement is made with the LO at the
reference phase of 0; the second measurement is made with the LO phase shifted by 90.
This process results in the quadrature or vector components of each signal at the Detector
RF input.
2.2 Sweeping Impedance Probe Requirements
A Sweeping Impedance Probe operating in the Earth’s ionosphere has a number of
requirements that are significantly different than the N2PK VNA, which is primarily used for
measuring the performance of HF antennas and communication systems. These requirements
labeled R1 through R6 are presented below with discussion.
16
R1 The frequency of operation shall be between 1 MHz and 20 MHz and shall be pro-
grammable.
When the ionosphere is driven near the local electron cyclotron frequency significant
energy can be transferred to the plasma heating the electrons and disturbing the
medium to be probed. On previous SIP instruments the sweep range had started as
low as 0.1 MHz and strong interference was generated for all diagnostic instruments
on the sounding rocket through a process known as sheath rectification when the SIP
was at the low end of its sweep. The low end of the sweep needs to be adjusted based
on the expected cyclotron frequency of plasma to be measured.
R2 The number of sample points in a frequency sweep shall be at least 128 points.
Previous experience with impedance probes on the STORMS mission has shown that
this is a sufficient number of samples to locate the various resonances of the probe-
plasma system [6]. In general, the points are distributed linearly in two band with
higher resolution at low frequencies where the upper hybrid frequency is expected and
few points at the highest frequency ranges.
R3 The sweep rate shall be at least 10 Hz.
The sweep rate determines the along track resolution of the measurements. Given that
the plasma environment is dynamic, it is desirable to accomplish the measurement
before the underlying media changes significantly.
R4 The admittance measurement shall have an accuracy of greater that 1% in magnitude
and 1 in phase across the measurement range.
It is not essential that the SIP be extremely accurate because of the morphology of
the parallel resonance associated with the upper hybrid frequency. A small error in
magnitude or phase does not change the estimation of the frequency of this resonant
condition significantly. However, it is often desirable to obtain as noiseless and accurate
values as possible. These requirements were made base on the design capabilities and
their relative impact on other important parameters like power, size, and mass.
17
Because the SIP is actually an admittance probe, where the magnitude sensed is the
current proportional to the admittance, it is more convenient to express the accuracy
requirement or the error model in terms of the admittance instead of impedance.
However, because traditionally impedance has been used more and it is a more
intuitive magnitude, both terms will be used in the thesis.
R5 The magnitude range of the impedance measurements shall be between 100 Ω and
100 kΩ.
This is one of the driving requirements for the SIP because most network analyzers
operate relatively near a reference frequency of 50 Ω. The need to observe the high
impedance of the plasma-antenna parallel resonance drives this extended operating
range.
R6 The maximum voltage presented at the probe input shall be less than 0.5 V peak.
The ambient plasma can be driven to nonlinear states such that the simple linear
theory for the impedance of an antenna in plasma is not applicable. The desire to
drive the plasma harder to improve the signal to noise ratio for the instrument need
to be balanced by the need to not unduly perturb the plasma. This level is based on
best practices from years of impedance probe work [10].
2.3 Block Diagram
The ASSP SIP instrument is composed of the functional blocks indicated in Fig. 2.2.
The electronics are divided into two boards. The Main Board is located inside the rocket and
contains the major functionality. It includes the VNA, which produces the constant voltage
sine wave for exciting the probe, and the detector to acquire and digitize the measured
current in quadrature, coming from the RF Head. All the VNA sequencing and frequency
sweep is managed by the Controller, which is also in charge of the digital processing and
packing the values into the Telemetry (TM) format. The different electronic components
are powered from a single high-voltage bus. The Power Conditioning and Filtering stage
generates all the voltages required.
18
The second board is inside the RF Head. It is located inside the antenna boom, and
closely placed to the feed. It connects the VNA excitation voltage to the probe, while
measures the current through it. It is then amplified by a Low-Noise Amplifier (LNA), and
transmitted to the VNA for its acquisition.
2.4 Theory of Operation
The Sweeping Impedance Probe is based on the N2PK VNA, which has proven over 10
years to be very accurate and similar to commercial equipments in performance. By basing
the SIP off an existing design, it is ensured it has the required simplicity and compaction to
be implemented as part of a flight instrument. The RF Head is based on the N2PK design,
but more heavily on the experience of previous SIP instruments developed at Utah State
University. Both of them have been adapted for the SIP admittance ranges, sweep rate, and
accuracy requirements. The error model has been extensively analyzed compared with the
N2PK VNA, which relied more on prototype measurements.
The way the SIP VNA operates is indicated in Fig. 2.3. A DDS will output from one
of its channel a sine wave of the desired frequency. After removing the harmonics produced
by the DDS with the antialias filter, the signal will be ideally a pure sine wave
VRF(t) = A sin(2πf0t), (2.1)
where A is the amplitude of the sine wave, and the initial phase can be considered zero
Power Conditioning & Filtering
VNA
Controller
SIP Main Board
Power bus
TM & sync(PCM) SIP Probe
Rock
et e
xter
nal
fac
e
VRF
Vsens∝ I
RF HeadNASATM & Power
Fig. 2.2: ASSP SIP block diagram.
19
DDS
AntialiasFilter
AntialiasFilter
LPF
ADC
LO Phase
Ch. Sel.
0°
0°90°180°270°
DataN
Freq.CH 0(RF)
CH 1(LO)
Detector(mixer)
RF Head
Contr
oller
MeasuredCurrent
Fig. 2.3: SIP VNA block diagram and operation.
without loss of generality.
This voltage will be directly applied to the probe. In the RF Head a current sensing
circuit is implemented consisting of a Current Transformer (CT) and a LNA. Considering a
CT with a turn ratio of n, a burden resistor Rb, and an amplifier of gain Gamp, the incoming
signal to the VNA has the following expression:
Vsens(t) =I(t)
nRbGamp =
A|Y (f0)|RbGamp
nsin(2πf0t+ arg(Y (f0))). (2.2)
In the VNA, a second DDS channel will generate a sine wave with the same frequency and
phase as the first channel. It is multiplied with the incoming signal from the RF Head
producing the following output:
Vdet(t) = GdetVsens(t)VLO(t) = Gchain|Y (f0)|[cos(arg(Y (f0)))− cos(4πf0t+ arg(Y (f0)))],
(2.3)
where Gdet and Gchain are the detector and the measurement chain gain, respectively,
Gchain =ARbGampGdet
n. (2.4)
20
The doubled frequency signal can be easily removed with a Low-Pass Filter (LPF). The
filtered DC signal is digitized with a regular Analog-to-Digital Converter (ADC),
VADC,0 = Gchain|Y (f0)| cos(arg(Y (f0))). (2.5)
This value corresponds with the in-phase or real component of the admittance.
After that measure has been performed, the DDS second channel will shift its phase by
90,
VLO,0(t) = ALO sin(2πf0t) −→ VLO,90(t) = ALO sin(2πf0t+π
2) = ALO cos(2πf0t), (2.6)
that, when multiplied by Vsens(t) and filtered, gives the following output,
VADC,90 = Gchain|Y (f0)| sin(arg(Y (f0))), (2.7)
which is the quadrature component or imaginary part of the admittance.
Given both components the admittance can be calculated directly as
|Y (f0)| = Gchain
√V 2
ADC,0 + V 2ADC,90, (2.8)
arg(Y (f0)) = tan−1(VADC,90
VADC,0). (2.9)
This operation is similar to the calculation of the components of a vector with respect
to base vectors. A graphical representation of the admittance plane can be seen in Fig. 2.4,
where the base is formed by the LO different phases.
Compared with other SIP architectures, this method relays on two things: the use of a
digital source generator and sequential measurements. Both DDS channels must have the
exact same frequency, otherwise the ADC input will be a slowly modulated signal. Moreover,
even if we could get two signals with the same frequency, being able to shift the local
oscillator by exactly 90 at any frequency is impossible without the use of digital methods.
21
B = Im(Y)
G = Re(Y)
VADC,90
VADC,0
VLO,90
VLO,0
Y
Fig. 2.4: Admittance plane and calculation of the components.
With respect to the sequential measurements, they provide an excellent accuracy because
both values are affected by the same gains and delays. In the STORMS SIP an error of 1
or 2 was assumed in phase because the in-phase and quadrature components had different
tracks and lengths [6]. The importance of the sequential measurements will be even more
noticeable when the use of Correlated Double Sampling (CDS) and the reference channel
are explained.
From Equation (2.8) we can see that for obtaining an accurate magnitude value the
measurement chain gain must be known with very good accuracy. Even more, any drift
of this gain will ruin the instrument accuracy. As for the phase, obtained in Equation
(2.9), a simplification has been made. Any element in the measurement chain (amplifiers,
transformers, mixer) will introduce phase delays that must be corrected. Hence, a very
good calibration procedure, including temperature drifts, must be made to ensure final
performances. In the next subsections, two methods will be explained to improve the inherent
accuracy and alleviate the calibration.
2.4.1 Correlated Double Sampling
The first technique described is the Correlated Double Sampling (CDS). In general, the
measurements VADC,0 and VADC,90 will have a certain offset error from different components
22
such as the mixer, amplifiers, and the ADC. The digitized signals can be expressed more
generally as
VADC,0 = Gchain|Y (f0)| cos(arg(Y (f0)) + Voff ), (2.10)
VADC,90 = Gchain|Y (f0)| sin(arg(Y (f0)) + Voff ), (2.11)
which results in a measurement error of the calculated admittance,
|Y (f0)| = Gchain
√(VADC,0 − Voff )2 + (VADC,90 − Voff )2, (2.12)
arg(Y (f0)) = tan−1(VADC,90 + VoffVADC,0 + Voff
). (2.13)
By taking two additional measurements using LO phases of 180 and 270,
VLO,180(t) = ALO sin(2πf0t− π) −→ VADC,180 = −Gchain|Y (f0)| cos(arg(Y (f0))) + Voff ,
(2.14)
VLO,270(t) = ALO sin(2πf0t−3π
2) −→ VADC,270 = −Gchain|Y (f0)| sin(arg(Y (f0))) + Voff ,
(2.15)
two new values are obtained with a similar offset, but with the opposite value for the signal
of interest. Subtracting these new measurements from the original ones results in a value
free of offset error (see Fig. 2.5). In reality, the offset can change slightly between the
measurements, but after the CDS correction it will be much lower. The residual offset error
will be corrected by calibration. It is important to remark that the CDS technique is only
possible by acquiring sequential measurements using the same acquisition chain.
For sake of simplicity, the corrected values with CDS are defined as
VI =VADC,0 − VADC,180
2, (2.16)
VQ =VADC,90 − VADC,270
2. (2.17)
23
B
G
VADC,90
VADC,0
Y
VOff
VADC,270
VADC,180
2 Re[Y]
2 I
m[Y
]
Fig. 2.5: Measurement of complementary values (CDS) for offset cancellation.
2.4.2 Reference Channel
The use of a reference channel has been used in many of the previous SIP instruments.
Measuring the reference channel duplicates the number of measurements, but it also provides
several advantages, correcting gain errors and phase delays. The impedance is calculated as
follows:
|Y (f0)| =
√V 2I,ant + V 2
Q,ant√V 2I,ref + V 2
Q,ref
|Yref |, (2.18)
arg(Y (f0)) = tan−1(VQ,ant
VI,ant)− tan−1(
VQ,ref
VI,ref). (2.19)
In the graphical plane, shown in Fig. 2.6 for a resistive reference, it can be seen as both
measurements are affected by the same delay that can be corrected. If gain errors affect
both channels in the same way, the triangles formed by the real admittances, and the ones
affected by the gain error are similar.
While the gain and phase delay of the measurement chain can be effectively corrected,
this is only true if the reference impedance is very stable and very well known.
24
B
G
Y
Yrefθdelay
arg(Y)
Fig. 2.6: Measurement of a reference admittance for phase delay and gain correction.
2.4.3 Summary of Instrument Operation
The use of sequential measurements provide a very good inherent accuracy for the
instrument. Most of the systematic errors (offset, gain, and phase delay) and their drifts are
corrected. The residual errors can be corrected by calibration as explained in Chapter 4.
However, the main disadvantage is the sequential use of the ADC, requiring a device with
a high sampling rate. To allow a high sampling rate, the input signal cannot be filtered
without impacting the settling time. Thus, there is a trade-off between the sweeping rate and
the maximum admissible noise in the system. The noise analysis has been one of the main
concerns for the selection of components. Appropriate power distribution and grounding is
essential to obtain a reduction of the Electromagnetic Interference (EMI) noise.
There are several sources of nonlinearity errors in the system as will be explained.
Although they may be systematic, its calibration is often difficult and tedious. Therefore,
the main objective has been minimizing its influence at the source, in order to do a simpler
linear calibration.
25
Chapter 3
Design and Analyses
This chapter explains the different design decisions taken during the component selection
and their main parameters. It also presents the analyses that were performed to ensure the
final performance of the instrument.
3.1 Detailed Design
The detailed design section should provide enough insight to the reader to perform the
next SIP generation instruments based on this architecture. The order of the subsections
tries to replicate the flow of the signal from the source (DDS) up to the final destination
(ADC).
3.1.1 Direct Digital Synthesizer
The DDS must output two signals synchronized in frequency. For that matter two DDS
chips can be used with the same clock oscillator, or like in this case, a single 2-channel chip.
The DDS selected presents several advantages against others.
• It uses a serial port for configuring the DDS, that while slow, occupies less pins in the
Field-Programmable Gate Array (FPGA).
• It supports different kinds of modulations by direct action on some special pins. In
this case for the LO channel, it is very convenient for changing its phase.
• It presents a low phase noise and Spurious-Free Dynamic Range (SFDR).
It also has disadvantages like the unique voltage used, 1.8 V, or having more functionality
than needed in this application.
26
The DDS output, shown in Fig. 3.1, consists of a complementary differential current
sink, which must be converted with a balun for driving the unbalanced antenna impedance.
R147 sets the DC voltage of the outputs around 1.55 V, and R148 helps maintain the
maximum output voltage inside their compliance range (there can be problems driving a
filter with inductive input impedance).
While the use of a DDS is very convenient for frequency and phase accuracy, they have
larger phase noise and harmonics than other signal generator methods. In order to reduce
the harmonics and the digital aliases, a reconstruction filter is implemented at the output
with a frequency cut-off of 25 MHz. When the generated signal has a low frequency, not
every harmonic can be filtered. The filter is implemented with passive components to avoid
any additional noise or error. Additionally it is known that DDS produce higher harmonics
when the output frequency is a sub-multiple of the reference clock frequency, 64 MHz. In
those cases, the frequency has been slightly shifted (1 LSB introduces a shift of less than
1 Hz, negligible for the instrument operation).
Because the output of the DDS is the result of a reconstructed digital sine wave, it
follows a sinc(f0/fREF ) response. There is a small decay of 15% when the output is at
20 MHz that will be considered as part of the gain error.
IOUT
R147IOUT
1 : 1
R148
+1.8V A
LPF
Fig. 3.1: DDS output configuration.
27
3.1.2 RF Head
The RF Head block diagram can be seen in Fig. 3.2. The excitation voltage received
from the Main Board drives the antenna through a Current Transformer (CT) that senses
the current. It is converted to voltage in the secondary with a burden resistor and an
amplifier closely placed augments the signal to appropriate levels for its transmission to the
Main Board.
The reference channel is configured in the same way replacing the antenna by a fixed and
very accurate resistor. In this sense two changes have been made with respect to previous
SIP instruments.
• First, the reference impedance selected is mechanically less representative, but on the
other hand is much more accurate and stable having an initial tolerance of 0.01% and
a Temperature Coefficient of Resistance (TCR) of 20 ppm/C.
• With the exception of the CT, burden resistor, and amplifier, all the other elements of
the measurement chain are the same to the antenna channel. And all the mentioned
components have been implemented as symmetrically as possible to the antenna
channel.
• The CT for each channel are positioned perpendicular to each other, avoiding magnetic
coupling between them.
The CT analysis and testing took a fair amount of time, and all the know-how has been
compiled in Appendix A. The final configuration is a 1:5 turns ratio transformer with a
burden resistor of 50 Ω. To avoid phase differences between channels, an amplifier with very
high Gain-Bandwidth Product (GBW) has been selected. Additionally, only one signal is
sent back to the Main Board with the help of a multiplexer made from RF switches. In this
way, the uncertainty in the phase delay produced by the cable is eliminated. The amplifier is
configured in a non-inverting configuration to increase the input impedance compared with
the burden resistor. Small resistors values have been used to reduce their thermal noise.
28
Antenna Channel
ReferenceChannel
Vsens
VN
AVRF
Ch. Sel.
Fig. 3.2: RF Head block diagram.
There always exist stray capacitances between the antenna feed and ground. There
are also border effects of the antenna. Figure 3.3(a) shows the three possibilities. Stray
capacitances before the CT load the driver, but it does not produce any output on the CT.
However any current after the CT and returning through the enclosure or other ground
track, will be sensed by the CT and produce an undesirable output. All these capacitances
combined are the shunt capacitance referred in the introduction, which reduces the instrument
sensitivity. To mitigate this problem the use of a guard is implemented, where the enclosure
is grounded through the primary wire shield, which is also coupled to the CT. As seen in
Fig. 3.3(b), any current through these stray capacitances or from the antenna to the guard
return through the shield canceling its effect on the output.
The guard design has been improved over previous instruments obtaining a very enclosed
guard. At the moment of writing this thesis, a new design based on an insulated material
(green in the figure) coated with a high conductivity spray (orange in the figure) is being
studied by the mechanical team. It will provide a very good mechanical fixation for the guard
29
and the antenna, a continuous and conductive guard from the connector to the enclosure and
will ease its manufacturing. This new guard design together with a very close transformer
to the antenna connector (just a few centimeters) should reduce the shunt capacitance effect
to a minimum.
3.1.3 Detector and ADC
The detector is a Direct-Conversion Receiver (DCR) (or zero-IF receiver), consisting of
a frequency shifter by combining the current sensed with the LO signal from the DDS, both
of the same frequency. For the detector there are two possible designs.
• A frequency multiplier or linear mixer. It generates the sum and difference frequencies
with much less harmonics. The main disadvantages are that LO signal noise is present
in the output (together with its mixing with RF noise [11]) and they have less conversion
gain.
• A frequency mixer or modulator. In these kind of devices the LO input is overloaded
(a) Stray capacitances effect without guard.
(b) Stray capacitances effect with guard.
Fig. 3.3: Mitigation of shunt capacitance with a guard.
30
into a square signal and acts like a switch control for the RF signal and its opposite.
The main advantage is that it is much less sensible to the LO noise and has higher
conversion gains, but it generates multiple harmonics and intermodulation products.
For the ASSP SIP a conservative approach has been taken. The AD831 active mixer has
been selected having a high conversion gain with low harmonics. The only disadvantage is
its elevated power consumption.
The differential output of the mixer is filtered and buffered for driving the ADC.
The frequency cut-off of this filter is critical for the instrument timing. The fundamental
requirement is that it must be much lower than 2 MHz (twice the minimum frequency),
because the mixer will produce an output with the same level as the DC signal we want to
digitize. Furthermore, to reduce aliasing and limit the noise, the filter must reject frequencies
higher than 200 kHz, which is half the sampling frequency when oversampling (see Section
3.1.4). However, reducing the bandwidth increases the settling time of the filter after a
change of phase or frequency, being the major contributor to the instrument measurement
time. The final bandwidth selected is around 100 kHz, obtaining a good rejection at 2 MHz
of 25 dB. With the settling time configured to 9 ms, the value has been settled to 99.92 % of
the final value (in average of the four coadded samples).
The ADC is also a critical element of the system for determining the dynamic range. A
24-bit Delta-Sigma ADC would have been preferred but they have a very limited sampling
rate, insufficient for this application. A very accurate 16-bit ADC with a higher sampling
rate has been used.
3.1.4 Controller
The Controller is implemented in an Igloo FPGA (AGL1000V5). The main block
diagram of the digital design can be seen in Fig. 3.4.
• The Data Acquisition System (DAS) Controller acquires all the different information
to be transmitted by Telemetry (TM), it controls the SIP instrument, changing the
frequency and phase of the DDS and acquiring the ADC, and acquires houskeeping
31
information.
• The Ground Support Equipment (GSE) Interface implements a Universal Asynchronous
Receiver/Transmitter (UART) interface for on-ground debugging and testing.
• The Payload Controller modifies the acquisition modes of the DAS Controller according
to the commands received from the GSE.
• The Telemetry Matrix Former groups the information from the DAS Controller and
other information relevant to the status of the SIP instrument, and transmits it to the
NASA TM&Power unit. From this unit, some synchronization signals are received
which are used for triggering the acquisition of the telemetry.
• The Flash interface implements a counter that is incremented after each reset.
Many of the blocks have been reused from another programs, or from other ASSP units
some modifications. The DAS Controller is specific of the SIP instrument. The complete
Register-Transfer Level (RTL) diagrams can be found in Appendix C.
The general timing of the SIP acquisition can be seen in Fig. 3.5. The SIP instrument
has nine 16-bit channels allocated in each Sub Frame (SF), where the raw data of a single
frequency is transmitted. A Major Frame (MF) consists of 32 SF, and the SIP instrument
requires four complete MF to transmit a single sweep data (128 frequency points). Being
the SF period 140 µs, and the MF period 5.88 ms, this results in a maximum sweep rate of
about 42.5 Hz. Because of the huge amount of allocated data rate, it was decided to push the
design, increasing the sweep rate at the expense of reduced accuracy. The NSROC Payload
from NASA generates the timing signals indicating to the SIP Payload the beginning of
SFs and MFs. This signals are used for synchronizing and timing the SIP operations. After
the DDS initial configuration, the FPGA remains idle until the next MF. Then, it starts
acquiring each frequency values at the beginning of each SF, and stores them into a memory.
These values are transmitted in the next MF, i.e. data is delayed by one MF period but
time-tagged for further post-processing.
32
-186-0030
ASSP Main Functional
C. Weston
Top Level SIP Functional Partition
1
ASSP
DESCRIPTION
FILE NAME
ITEM
SHEET
SHT REV
TITLE
TITLE
ENGINEER
LAST MODIFIED
SPACE DYNAMICS LABORATORYUTAH STATE UNIVERSITY R ESEARCH FOUNDATION
North Logan, Utah 84341
PROGRAM
14 feb, 2014 SPSIPTOP.VSDX
NEXT ASSY.
186-0030ASSP Main Payload Top Level
DWG NO.
7 6 5 4 3 2 1
B
A
D
C
B
A
8 7 6 5 4 3 2 1
8
D
C
1 1OFTHIS DRAWING CONTAINS INFORMATION THAT IS PROPRIETARY TO SPACE DYNAMICS LABORATORY (SDL). REFERENCE USURF BP409.1
Form No. QF0423 Rev A
VHDL FILE = ASSP_MAIN_TOP.VHD
Co
mm
an
d[7
:0]
UA
RT
_P
ay_T
x_
H
UA
RT
_G
SE
_T
x_
H
UMBI
Ne
wC
oA
dd
Cnt[
1:0
]
Rst_
H
AR
st_
L
AD9958
DD
S_
Re
set_
L
DD
S_
PW
R_
DW
N
DD
S_
SC
K
FstC
lk
Rd
RcvF
IFO
_H
RcvF
E_H
WrS
IPC
onfig
_H
TMAddr[3:0]
DD
S_
SD
O[3
:0]
DD
S_
Sync_C
lk
TM
_D
ata
_H
Globals
Rst_
H
Rst_
H
Rst_
H
Payload Firmware Instruction Set
Reset Payload
Hex Command Parameters (Big-endian)
Set SIP Config
AD
C_
SC
K
AD
C_
CN
V
AD
C_S
DI
AD
C_
SD
O
AD7688
Te
lem
etr
y S
igna
ls
2
8
TM Serial Deck
TM
_G
td_C
k
TM
_L
oa
d_
L
TM
_E
na
ble
_H
TM
_W
ord
_H
TM
_F
ram
e_H
TM
_M
Fra
me_H
Flash
FL
_S
O_H
FL
_S
I_H
FL
_H
old
_L
FL
_C
S_
L
FL
_S
ck
FL
_W
P_
L
Rst_
H
FL
Com
ma
nd
[15:0
]
16
FL
Wr_
H
Flash Interface
Sweeping Impedance Probe
HK
_C
S_L
HK
_D
Clk
HK
_S
hd
n_L
HK
_B
usy_H
HK
_D
In_H
HK
_D
Ou
t_H
ADS8343
HK
(CH0)(CH1)(CH2)(CH3)
4
HK
ad
dr[
3:0
]
Te
stP
ort
[7:0
]
8
Data Acquisition System Controller
5
+V
PayID
[4:0
]
PCB S/N
UA
RT
_U
AR
T_In
va
lid_
L
UMBI UART Interface
Synchronous Serial Interface
SS
I_E
na
ble
_H
SS
I_E
na
ble
_L
+V
WrGetTM_H
RF
IV_C
trl
DD
S_
P[3
:0]
DD
S_
CS
_L
DD
S_
IO_
UP
DA
TE
0x33
0xA0 Fixed Frequency enable
2-bit CDS enable
2-bit CoAdd number of samples
32-bit fixed frequency value
Get TM data 4-bit Chunk address0xA2
Telemetry Matrix Former
Dia
gno
sticD
ata
[7:0
]
WrD
iagn
osticsD
ata
_H
SysClk
Generator
SysC
lk
Ne
wF
ixe
dF
req
[31:0
]
32
Ne
wF
ixe
dF
req
_H
Ne
wC
DS
En[1
:0]
2
Payload Controller
Fig. 3.4: FPGA design block diagram.
33
IdleInit
5.88 ms 5.88 ms 5.88 ms 5.88 ms
1 sweep: 23.52 ms
MF -1 MF 0
Data acquired in MF itransmitted in MF i+1
MF 1 MF 2 MF 3 MF 4 MF 5 MF 4 MF 5
SF 0 SF 1 SF 2 SF 3 SF 4 SF 5 SF 6 SF 30 SF 31
140 μs
Antenna
Smpl 0
Channel Reference
Phase 0° 180° 90° 270° 0° 180° 90° 270°
DDS Active frequency 4 & Load frequency 5
ADC
ADC input
Smpl 1 Smpl 2 Smpl 3
17 μs
Settling time9 μs
2.28 μs
Settling time9 μs
Smpl 0 Smpl 1 Smpl 2
2.28 μs
...
Fig. 3.5: FPGA and SIP overall timing diagram.
34
It should be noted that there is an overlap between SFs. While the ADC has sampled
the data and initiates the conversion phase, the next frequency and phase is loaded. It
should also be noted that because frequency is loaded with a serial line it requires some
time. To avoid any additional delay to the settling time, frequencies values are preloaded in
the previous SF and loaded immediately into the DDS registers at the beginning of the SF.
With the limited processing made in the FPGA, the amount of logic needed is very
limited too. In Table 3.1, it is shown a comparative of different resources between the specific
SIP modules, the complete FPGA design and the total amount provided by the FPGA.
The Random-Access Memory (RAM) blocks utilization could be optimized by delaying the
values acquisition by only two SF instead of a MF. It can be seen that the SIP digital design
does not require a high demand of the FPGA and it could be integrated together with other
instruments.
For debugging purposes, different test modes have been implemented in the FPGA
design which are only accessible through the UART. These test modes allow to establish the
VNA in a particular frequency (which in VNA is called zero-span), with/without CDS or
the amount of coadded samples.
3.1.5 Power Conditioning and Filtering
All the components mentioned previously are powered from a single high-voltage
and high-power unregulated bus. Different voltage rails are generated and conditioned
from the primary bus, as shown in Fig. 3.6, by using DC/DC converters, Low-Dropout
Regulators (LDOs), and references. The power consumption associated with each converter
is summarized in Table 3.2. The VNA dissipates around 1.3 W with 1 W coming from
the mixer. The RF Head dissipates 230 mW due to the amplifiers. The Controller and
Table 3.1: SIP modules occupation on the FPGA.Module SIP Controller Complete Design Total FPGA
Core Cells 1622 (7%) 3131 (13%) 24576
I/O pins 19 (11%) 51 (29%) 177
RAM blocks 19 (59%) 28 (87%) 32
35
housekeeping circuits take only 220 mW and all the remaining power is lost in the converters,
which are working at a very low load with low efficiency.
3.2 Analyses
Different analyses were made for the selection of components and assuring performances.
In particular, the driving requirements for the design were the impedance range, and measure-
ment uncertainty in magnitude and phase. This measurement error will be determined by
two different kind of errors, systematic and random errors. Systematic errors are comprised
by:
• Offset error: mitigated by the CDS technique. The offset voltage limits the dynamic
range of the ADC, but with enough margin it is not a critical parameter. The residual
error is difficult to predict and it will be considered only during testing and calibration.
• Gain error: mitigated by the reference channel. Like the offset error, it will be
considered later during testing and calibration.
IsolatedDC/DCconverter
LDO
SIP Electronics
Box
NASA Power
LDO
+5VD +3.3VD+1.5VD
+15VA
–15VA
IsolatedDC/DCconverter
IsolatedDC/DCconverter
– 5VA
LDO
LDO
LDORef.
+5VA
+3.3VA
+1.8VA
+2.5VA
+1.25VA
UnregulatedBus 16-24V
Ground Star Point LDORef.
Fig. 3.6: Power generation and conditioning from the primary bus.
36
Tab
le3.
2:P
ower
con
sum
pti
onof
the
SIP
inst
rum
ent.
Com
pon
ent
+1.
5VD
+3.
3VD
+5V
D+
1.2
5V
A+
2.5
VD
+1.8
VA
+3.3
VA
+5V
A-5
VA
+15V
A-1
5V
A+
VB
us
RS
422
Drv
/Rcv
16.1
GS
EP
ort
Inte
rfac
e0.
0R
eset
Cir
cuit
ry0.
0F
lash
Mem
ory
0.0
Clo
ckC
ircu
it7.
0F
PG
A8.
72.
2C
ontr
olle
r8.
718
.3
DD
S0.
483.0
Ref
eren
ceC
lock
30C
h.
Sel
.B
uff
er0.
00.0
Det
ecto
r106.0
100.0
Tem
per
ature
Sen
sor
0.3
AD
C0.
00.1
4.3
VN
A0.
40.1
83.0
0.0
110.6
100
Am
pli
fier
s22.8
22.8
Mu
ltip
lexer
0.1
RF
Hea
d0.1
22.8
22.8
Vol
tage
Mon
itor
0.1
0.1
0.1
1.7
2.5
0.3
Cu
rren
tS
ense
0.1
0.1
0.1
0.4
0.4
0.1
Mu
ltip
lexer
0.0
2.2
0.9
AD
C0.
00.0
1.5
Hou
seke
epin
g0.
10.2
1.7
0.1
4.3
3.8
Su
bto
tal
8.7
55.8
0.2
0.1
0.0
83.0
0.1
135.1
122.9
4.3
3.8
0.4
Tot
alO
utp
ut
Con
v.
8.7
65.2
65.4
0.1
0.0
83.0
0.1
226.4
122.9
4.3
3.8
Tot
alIn
pu
tC
onv.
9.4
65.2
32.1
0.1
0.1
91.0
0.1
117.1
32.6
181.8
Tot
alP
ower
3.4
WN
ote
:all
valu
esin
mA
un
less
oth
erw
ise
note
d.
37
• Nonlinearities: there are several sources of nonlinearities and each one requires a
different approach that will be explained. In particular, the loading effect will affect
the gain of the instrument for different admittance ranges.
These errors are repetitive under the same operating conditions and will be ultimately
calibrated. On the other hand random errors will be present.
• Noise: it has been properly limited by design in order to assure it does not degrade
the measurement when acquiring low signals.
• Resolution: although limited by the device used, some techniques can be used to
improve the effective resolution.
• Nonlinearities: some of the nonlinearities are not only dependent on the value being
measured but on other characteristics of the DUT or the test equipment. An example
would be the harmonic distortion.
Some of the random errors presented, like resolution or the ADC Integral Nonlinearity
(INL), are not really random but dependent on the specific component. However, they are
considered random because of its difficulty to be calibrated.
3.2.1 Noise
Because of the high sampling rate, noise was one of the main concerns, and as such,
a detailed staged analysis was performed in order to select the components. During this
analysis the noise values are provided in dBc/Hz of the Single-Sideband (SSB) noise with
respect to the fundamental (i.e. graphs represent the offset frequency with respect to the
fundamental frequency and with the relative magnitude value to the fundamental magnitude
integrated over 1 Hz bandwidth). This representation is convenient for this application
where the frequency is swept.
The phase noise of the DDS can be expressed as [12]
LDDS(f, r) =1
2r2LCLK(f) + (
r
rR)2L1/f (f, rR) + κ(r)Lfloor, (3.1)
38
where r = f0
fCLKis the ratio of the output frequency and the reference clock, and κ(r) is a
weak function of r. It has three components:
• The phase noise from the reference clock LCLK(f);
• The 1/f or flicker noise from DDS L1/f (f), which is given at a particular reference
ratio rR;
• Floor white noise of the output DAC of the DDS Lfloor.
Shown in Fig. 3.7 is the phase noise at the output of the DDS for the worst case, i.e. the
maximum output frequency. Because it is an accessible point, during testing it can be
observed the expected performance of the DDS.
The signal will be sensed by the CT and amplified by the LNA. Because of the low
signals in this stage, the noise of the components affect in great measure the total amount of
noise. Shown in Fig. 3.8 are the different contributors, including the burden resistor thermal
noise, the amplifier, and the resistors used for the amplification. As it can be observed, the
LNA used has very low floor noise (its flicker noise at low frequencies is irrelevant because
it will be rejected by the balun and mixer), and being the major contributors the thermal
noise of the amplifier resistors.
The mixer will introduce its intrinsic noise while rejecting all noise from the LO
input. Unfortunately, the datasheet does not provide the flicker noise information, and it is
something that should be checked during testing. After that, the noise from the ADC buffer
101 102 103 104 105 106 107
−160
−140
−120
−100
−80
Frequency Offset [Hz]
Magn
itu
de
[dB
c/H
z] Ref. ClockDAC
FlickerTotal Noise
Fig. 3.7: Phase noise spectrum at the DDS output.
39
101 102 103 104 105 106 107−140
−120
−100
−80
Frequency Offset [Hz]
Mag
nit
ud
e[d
Bc/
Hz] DDS Output
Burden Resistoreninninp
Other ResistorsTotal Noise
Fig. 3.8: Phase noise spectrum at the LNA output.
amplifiers (including their flicker noise) is added taking into account an increase of 3dB for
the differential path. The ADC noise is negligible according to the datasheet (0.137 LSB),
and it has not been considered. The different contributors can be seen in Fig. 3.9.
The use of CDS improves not only the offset rejection but also the flicker noise [13].
It can be considered as a digital filter with a sampling rate equal to the time difference
between phases 17 µs (see Fig. 3.10). The frequency response is a high pass-filter with a
cut-off frequency of fs/4, which in this case is 14.7 kHz. This results in a very good rejection
of the low frequency noise as seen in Fig. 3.11.
Although many sources of noise have not been considered like EMI or components noise
that is not given in the datasheet, it is expected that their contribution will be negligible.
This is the result of a very low bandwidth digitized (and further reduced by coadding) and
the use of CDS.
101 102 103 104 105 106 107−200
−150
−100
Frequency Offset [Hz]
Mag
nit
ud
e[d
Bc/
Hz] LNA Output
Mixer Noiseeninp
Total Noise
Fig. 3.9: Phase noise spectrum at the ADC input.
40
−2 2
−1
−0.5
0.5
1
n
h[n]
(a) Impulse Response
103 104 105 106
−20
−10
0
Frequency [Hz]
Magn
itu
de
[dB
]
(b) Frequency response
Fig. 3.10: CDS filter response in time and frequency domains.
101 102 103 104 105 106 107−160
−140
−120
−100
−80
Frequency Offset [Hz]
Mag
nit
ud
e[d
Bc] Without CDS
With CDS
Fig. 3.11: Phase noise spectrum reduction with the use of CDS.
41
3.2.2 Nonlinear Errors
3.2.2.1 Loading Effect
The DDS output gets loaded with the different elements shown in Fig. 3.12. Usually,
the antenna impedance is much higher than Z0 and Rb/n2, there is no loading effect and the
voltage VRF is constant and about 250 mVp. However, as its impedance lowers, the voltage
in the antenna will decrease. With 100 Ω, the voltage decreases to 200 mVp, and with 50 Ω
to only 110 mVp.
The loading effect is systematic and can be easily corrected. The main concern for the
loading effect is that only affects low antenna impedances where the most accurate calibration
loads are found. For future designs it would be interesting analyzing the convenience of
implementing a low output impedance buffer to drive the antenna and reference taking into
account the degradation of noise and harmonics.
3.2.2.2 Harmonic Analysis
The main source of harmonics is the DDS. It has a high SFDR of 65 dBc (see Fig.
3.13(a)). However, if the fundamental is located in the resonant frequency (where the
impedance is maximum) and its harmonics are located in the low impedance, they will get
amplified to higher levels. Figure 3.13(b) shows the output of the LNA superimposing the
IOUT10 mA
50Ω
RREF200 Ω
Rb/n2
≈ 2 Ω
VRF
Zant
Rb/n2
≈ 2 Ω
Fig. 3.12: Loading effect on the DDS output.
42
impedance curve. Supposing a resonant impedance of 100 kΩ and an impedance of 1 kΩ for
the harmonics, the 65 dBc margin gets reduced to only 25 dBc.
The mixer will produce a DC output of these harmonics when mixed with the LO
harmonics. The conversion gains for the different harmonics are shown in Fig. 3.13(c). With
the harmonic level at 25dBc below the fundamental and with the mixer rejection of 40dB, it
produces an output of -65dBc. Although this value is negligible, it is only achieved by the
use of the high-power mixer. With other lower power DDS and mixers, this value can get as
worse as -35dBc (1.7% in linear units), and it would require special measures to mitigate its
influence.
3.2.2.3 ADC Resolution
The ADC resolution is 16 bits, which may seem not enough for the lowest admittances.
However due to noise dithering at the ADC input, and the coadding implemented in
the Controller, the effective resolution is enhanced. Each value transmitted quadrature
component is the result of eight ADC samples, four coadded values in one phase, and another
four for the complementary phase. This results in an effective resolution of 17.5 bits. If
datarate is not the limiting factor, future designs should implement higher resolution ADC.
3.2.2.4 ADC Linearity
The main problem of the ADC that cannot be mitigated is its lack of linearity. This
ADC has a typical INL of 0.4 LSB (≈ 6 ppm). While the INL of the ADC can be potentially
calibrated it requires a very specific test set-up, and it is not practical for this kind of
instrument. Oversampling and coadding does not reduce the INL because the oversampled
values have the same INL error. However, CDS can reduce the INL by a factor of√
2,
because for this particular ADC the INL has a zero mean value and looks like white noise
(is the same consideration as it is normally made for considering the quantization error a
white noise). The ADC nonlinearity influence was discovered too late in the design process,
when the boards were already manufactured.
43
0 1 2 3 4 5 6 7 8 9 10
65dBc
Frequency [MHz]
Mag
nit
ud
e[d
Bc]
(a) Harmonic output of the DDS.
0 1 2 3 4 5 6 7 8 9 10
25dBc
Frequency [MHz]
Mag
nit
ud
e[d
Bc]
(b) Harmonic output of the LNA.
0 1 2 3 4 5 6 7 8 9 10
0dB
−41dB
−41B
−39dB
Frequency [MHz]
Mag
nit
ud
e[d
Bc]
(c) Mixer conversion gain for different harmonics.
Fig. 3.13: Nonlinear error produced by harmonic mixing of the local oscillator with DDSharmonics.
44
3.2.2.5 Other Sources of Nonlinearity
In general, all components can generate nonlinear behavior near saturation. All the
amplifiers are used with low-level signals compared to the supply voltage, and therefore
should not present any appreciable saturation effect. This however, should be taken into
account if low-power devices are used.
3.2.3 Saturation: Maximum Admittance
The different gains and voltages for the minimum impedance are shown in Fig. 3.14.
The voltage at the ADC input is ±0.7 V (for 0 and 180, respectively), which has been
properly adjusted to the ADC reference voltage of ±1.25 V. The LNA gain has been limited
to avoid saturation of the mixer RF input. A short-circuit cannot be used as an antenna
impedance because it will enter the nonlinear region generating compression on the output
signal and excessive harmonics.
3.2.4 Measurement Uncertainty
The real admittance Y will be measured with some error giving the estimation YM .
The admittance error is due to the in-phase and quadrature components errors εI and εQ as
shown in Fig. 3.15. The expression of the magnitude error in percentage is
εmag =
(|YM ||Y |
− 1
)· 100 =
(|Y + εI + jεQ|
|Y |− 1
)· 100, (3.2)
IOUT10 mAp
50 ΩRREF200 Ω
200 mVp
Zant100 Ω
2.86 mAp
570 µAp
28.6 mVp
Rb50 Ω
470 mVp 684 mVdc
Fig. 3.14: Saturation and gain analysis of the measurement chain.
45
and it can maximized for the minimum admittance and for the error aligned with the
admittance vector as in Fig. 3.15,
max(εmag) = ±
min(|Y |) +√ε2I + ε2Q
min(|Y |)− 1
· 100 = ±
√ε2I + ε2Q
min(|Y |)· 100. (3.3)
The phase error is calculated as the angle between both vectors,
εph = arg(YM )− arg(Y ), (3.4)
and the worst case is found for the minimum admittance and the errors aligned 90 to the
admittance vector (see Fig. 3.15),
max(εph) = ± tan−1
√ε2I + ε2Q
min(|Y |)≈ ±
√ε2I + ε2Q
min(|Y |). (3.5)
B
G
|Z| = 100 kΩ
±εI
±εQ
max(εph)
max(εg)
Fig. 3.15: Admittance gain and phase error as a function of the quadrature componentserrors.
46
Assuming that the in-phase and quadrature errors will have the same standard deviation,
the previous expressions can be simplified as
max(εmag) = ±√
2ε
min(|Y |)· 100, (3.6)
max(εph) = ±√
2ε
min(|Y |). (3.7)
Assuming a perfect calibration of the systematic errors (offset, gain, loading effect)
the measurement uncertainty will be limited by the random errors, noise, resolution, and
nonlinearities (see Table 3.3). This assumption is not entirely true, because the calibration
has some issues that will impact the performances. They are explained in the following
chapter.
The measurement uncertainty has been calculated to predict the compliance with the
accuracy requirements. Without taking into account the ADC, the requirements can be met
with margin because of the new architecture with great selectivity and dynamic range, and
with a very conservative selection of components. All the elements (DDS, amplifiers, mixer,
etc.) have extremely good performances at the expense of an elevated power consumption.
The ADC lack of resolution and linearity is the only design drawback, but it has been
analyzed and it should be noted and corrected for future instruments. It is believed that all
the analyses and considerations that have been collected here should prove a resourceful
guide for the next SIP instruments based on this architecture.
Table 3.3: Measurement uncertainty of the SIP instrument.Error Value
Noise ±6.76 µVResolution ±6.74 µV
INL ±10.78 µV
Total (RSS) ±14.40 µVMin. Signal (Ymin) ±478.5 µV
Magnitude Accuracy ±3.0 %Phase Accuracy ±1.7
47
Chapter 4
Calibration and Testing
In this chapter, the calibration methodology is explained, including the systematic error
model derived from the analyses and the different calibration loads available. The ASSP
SIP boards have been recently manufactured and the initial testing showing some the main
parameters are presented.
4.1 Calibration Methodology
4.1.1 Error Model
To perform the calibration the instrument error model must be defined, including all
the sources of systematic errors present. The error model is developed from the admittance
measurement expression derived in the previous chapter,
YM =VI,ant + jVQ,ant
VI,ref + jVQ,ref
1
(Rref +Rb/n2)?, (4.1)
where (Rref + Rb/n2)? is the nominal resistance of the reference channel, including the
impedance loading of the burden resistor. Using the complete expression along with the
systematic errors of the raw values,
VI,ref =Gref
|1/Yref + Zs,ref |cos(arg(1/Yref + Zs,ref)− φref) + Voff , (4.2)
VQ,ref =Gref
|1/Yref + Zs,ref |sin(− arg(1/Yref + Zs,ref)− φref) + Voff , (4.3)
VI,ant =Gant
|1/Yant + Zs,ant|cos(arg(1/Yant + Zs,ant)− φant) + Voff , (4.4)
VQ,ant =Gant
|1/Yant + Zs,ant|sin(− arg(1/Yant + Zs,ant)− φant) + Voff , (4.5)
48
where Gref , Gant are the gains for the different channels, φref , φant are the phase delays
associated with each path, and Zs,ref , Zs,ant are the impedance in series with the reference
resistor and the antenna (including the burden resistor). The first approximations are then
taken by assuming that the offset will be the same for all the measurements, and by having
the same gain and phase delay for the in-phase and quadrature components. Introducing
these expressions on the impedance measurement equation results in
YM =Gante
−jφant
(1
1/Yant+Zs,ant+ Yoff
)Grefe−jφref
(1
1/Yref+Zs,ref+ Yoff
) 1
(Rref +Rb/n2)?, (4.6)
where Yoff represents the equivalent admittance of the offset voltage. For the reference
channel the admittance selected is high enough so that the offset can be neglected. The
connection to the reference resistor is also short so Zs,ref ≈ Rb/n2. On the other hand, for
the antenna channel the ground impedance could be a source of error to be determined
during testing. Finally, the previous equation can be reduced to obtain the error model
based on the minimum number of independent parameters,
YM = εge−jφd
(1
1/Yant + Zs,ant+ Yoff
), (4.7)
where εg includes the mismatch between channel gains and the knowledge uncertainty of the
reference resistor, and φd represents the phase mismatch between channels.
The calculated error model has three complex parameters requiring three independent
measurements. A higher order model could have been obtained without making approxi-
mations. During the initial testing and characterization, it will be possible to observe if
the assumptions can be validated. Once the error parameters are determined the inverse
function can be used to correct the measured values,
Yant =1
1YM
εge−jφd
−Yoff
− Zs,ant. (4.8)
49
4.1.2 Calibration Loads
The mechanical configuration of the RF Test Head was designed in order to reuse the
calibration loads built for the STORMS mission. These loads are canned shaped similar to
the antenna allowing for easier connection to the instrument. They were also constructed
with a great range of impedances comprised by:
• Open Load;
• Short Load;
• Resistors: 50 Ω, 100 Ω, 200 Ω, 500 Ω, 1 kΩ, 2 kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 50 kΩ, 100 kΩ,
200 kΩ, 300 kΩ;
• Capacitors: 0.5 pF, 1 pF, 1.5 pF, 2 pF, 2.5 pF, 3 pF, 3.5 pF, 4 pF, 4.5 pF, 5 pF, 6 pF,
8 pF, 10 pF, 12 pF, 15 pF, 18 pF;
• Inductors: 1 µH, 2 µH, 5 µH, 10 µH, 20 µH, 50 µH, 100 µH, 200 µH, 500 µH, 1000 µH,
2000 µH;
• Resonant Circuits: 1.4 MHz, 2 MHz, 4 MHz, 6 MHz, 8 MHz, 10 MHz, 12 MHz.
The resonant circuits present a similar impedance to the plasma with different parallel
resonant frequencies.
Ideally, the calibration loads must be characterized with higher accuracy than the
instrument under calibration. Unfortunately, there is no equipment in the market that has
the required accuracy over the impedance and frequency range. For example, commercial
LCR meters have a great accuracy but only at a fixed frequency. For this project, a
commercial VNA was used and the complete measurements can be found in Appendix D.
The problem of using a VNA is that they are only accurate for resistive impedances
around the characteristic impedance Z0 (Agilent recommends using them only for 3 Ω around
Z0 for better performances). In the results, the measurement uncertainty in magnitude and
phase is shown along with the measured impedance. Because of this, only the 50 Ω load is
known with enough accuracy, around ±1 % in magnitude and ±0.7 in phase. Additionally,
50
it can be said that the OPEN load presents a high impedance (more than 3 kΩ) and the
SHORT load presents a low impedance (lower than 0.6 Ω), but the exact value is uncertain
as well as its phase. In Appendix D the problems associated with the OPEN load are
explained. Furthermore, it is discussed the convenience of not connecting any load, instead
of the OPEN load, for having a higher impedance.
4.1.3 Calibration Procedure
Given the unavailability of very well known calibration loads, the following approxima-
tions are made.
• First, assume Zs,ant is equal to Rb/n2. In either case, the ground impedance cannot
be calibrated with the calibration loads, but with the real antenna and rocket (or in
more practical terms, with an analysis or simulation).
• It is foreseen that Yoff will be very small because of a very low offset voltage after the
CDS correction. In that case, it can be simply discarded. Because the OPEN load can
not be properly characterized, the result will only be valid if the parallel is larger than
100 kΩ.
• Characterize the gain and phase mismatch with the 50 Ω load.
In principle, temperature drifts should be mostly corrected by the CDS and reference
channel. However, to improve the final accuracy it is also recommended to do a calibration
with a controlled temperature in 10 C steps.
4.2 Initial Tests
After solving some problems associated with layout errors, ADC common mode range,
obsolete parts, etc., the ASSP SIP boards were ready to be tested functionally and obtain
some of its performance parameters. The schematics of both boards are included in Appendix
B and the GSE used during the testing is described in Appendix E. Some of the solutions
adopted had a negative impact on the performances.
51
• Noise from the digital logic (specially the master clock oscillator) is coupled into the
analog plane. This will increase the total amount of noise in all frequencies.
• The reconstruction filter cut-off frequency is lower than expected (around 18 MHz),
due to the components tolerance and Q factor of the inductances.
• To solve a problem with the ADC common mode range, the low pass filter after the
mixer had to be simplified into a single pole. With this change, the image frequency
when measuring the lower frequencies (below 6 MHz) cannot be rejected completely
and this results in a higher amount of noise, and directly proportional to the signal
being measured.
In Fig. 4.1, the standard deviation noise measurements has been represented. The
CDS reduces the noise drastically because of the flicker noise filtering. On the other hand,
the coadding reduces the high-frequency noise (including the image frequency output of
the mixer). Gain at high frequencies has degraded and thus, the amount of noise increases.
Combining the CDS and coadding the total amount of noise is very reduced but higher than
expected for the reasons stated before.
In Fig. 4.2, the measurement offset has been represented. The CDS reduces in almost
2 4 6 8 10 12 14 16 18 20
0
1
2
3
·10−4
Frequency [MHz]
Ad
mit
tan
ceM
ag.
[Ω−
1]
w/out CDS & 1 coadd
w/out CDS & 2 coadd
w/out CDS & 4 coaddwith CDS & 1 coaddwith CDS & 4 coadd
Fig. 4.1: Noise measurements with different configurations.
52
an order of magnitude the total admittance offset, but it is still high enough to be considered
during the calibration. The offset in the lower frequencies is consistent with a shunt
capacitance of 0.6 pF which will need to be further investigated.
Finally to assess the capability of the instrument for measuring variations on the free
space capacitance, several capacitor loads were measured. In Fig. 4.3, three nominal loads of
1, 4, and 10 pF have been represented. As can be seen, the dynamic range of the instrument
is large enough to measure the 10 and 4 pF, but it is not enough for measuring the 1 pF
(only with averaging the capacitor curve can be distinguished).
Focusing on the 4 pF capacitor which is similar to the expected free space capacitance, a
curve fitting is performed to find the true capacitance being measured and express the error
as the residual with respect to this fitting. This has been represented in Fig. 4.4, dividing
the total error between the mean and the standard deviation. The mean deviation is due to
the lack of calibration and nonlinearity of the instrument, while the standard deviation is
purely due to the instrument noise. At low frequencies the error is primarily due to the noise
of the image frequency, and at high frequencies the loss of gain and dissimilarities between
the antenna and reference channel. It should be noted that the curves here represented
have not been calibrated in gain or phase, and therefore the mean error can potentially be
2 4 6 8 10 12 14 16 18 20
0
0.5
1
1.5
2
·10−4
Frequency [MHz]
Ad
mit
tan
ceM
ag.
[Ω−
1]]
w/out CDSwith CDS
Fig. 4.2: Offset measurements with and without CDS.
53
2 4 6 8 10 12 14 16 18 20
103
104
105
106
Frequency [MHz]
Imp
edan
ceM
ag.
[Ω]
1 pF4 pF10 pF
2 4 6 8 10 12 14 16 18 20−200
−100
0
100
200
Frequency [MHz]
Imp
edan
ceP
has
e[
]
Fig. 4.3: Dynamic range of the instrument measuring different capacitors.
54
reduced. Additionally, correcting the low-pass filter and reconstruction filter, the error curve
should be approximately flat like it is in mid-frequencies with a total error of 3% and 4 in
magnitude and phase.
Finally, a resonant circuit at 4 MHz has been measured and represented in Fig. 4.5
comparing the results with the curve obtained with a commerical VNA. Even with an error
in general higher than expected, the resonant frequency can be easily determined.
2 4 6 8 10 12 14 16 18 200
5
10
Frequency [MHz]
Mag
.E
rror
[%]
Std. Dev.Mean
2 4 6 8 10 12 14 16 18 200
2
4
6
8
Frequency [MHz]
Ph
ase
Err
or
[]
Fig. 4.4: Residual error for a 4 pF capacitor measurement.
55
2 4 6 8 10 12 14 16 18 20102.8
103
103.2
103.4
103.6
Frequency [MHz]
Mag
nit
ud
e[Ω
−1]]
SIPVNA
2 4 6 8 10 12 14 16 18 20
−80
−60
−40
−20
0
20
Frequency [MHz]
Ph
ase
[]
Fig. 4.5: Measurement comparison of a resonant frequency with a commercial VNA.
56
Chapter 5
Conclusions
In this thesis, a new SIP architecture has been outlined and analyzed. It is considered
a mature design and it can achieve the required performance metrics. The main advantages
of this architecture are the following.
• It has a high selectivity. The energy of the in-phase or quadrature component is
integrated over many cycles providing good rejection of spurious signals and noise.
The main limitation is usually found in the ADC dynamic range.
• The accuracy is enhanced by techniques like CDS or the reference channel. This
provides an inherent accuracy that can be further improved by calibration.
• An error model has been developed and some guidelines are given for the calibration.
In principle, many of the systematic errors will be corrected or limited.
• It is a compact design requiring very few components.
The design and manufacturing errors will degrade the accuracy, but they have been identified
and will be corrected in future versions. Because enough margin was taken in the impedance
range, it is anticipated that the actual antenna impedance will be accurately measured. The
ASSP mission presented a wonderful opportunity to test this new architecture by providing
very few restrictions in terms of size or power. This SIP architecture based on a VNA, along
with techniques like CDS, is very compact and provides a very good accuracy. However, for
future missions, the power consumption should be reduced, and the design optimized in
general, by for example, reducing the amount of different voltages required. If the noise level
is kept under appropriate levels, additional drivers and amplifiers are suggested to avoid
loading effect and to better adjust the dynamic range to the ADC input.
The RF Head is another block that has undergone important improvements.
57
• The reduced frequency span with respect to previous instruments has made it possible
to use a very small transformer, with an exceptional flat response and high repeatability.
• The symmetry between channels is increased, and the reference channel should be very
accurate and stable.
• The guard design has a better electrical continuity, mechanical support, and ease of
manufacturing.
Minor improvements are suggested for the next SIP. The burden resistor could be changed
for an active load [14]. In this way, the impedance loading in the primary would be negligible
and it would simplify the error model and calibration, while also improving the low frequency
response. To improve the lower cut-off frequency even further, the primary cable should
be changed to a material with lower resistivity. This will allow selecting a core magnetic
material with lower permeability, which are more stable with temperature and frequency.
Another idea to increase the symmetry between channels would be using a low gain amplifier
for each one, and a larger gain after the multiplexer.
For the calibration it is strongly recommended to use an impedance analyzer with
more calibration loads. Even if they are not capable of reaching the highest impedances, it
would allow to characterize with 1%/1 accuracy impedances between 10 and 100 kΩ loads.
Characterizing with precision capacitors and inductors would improve the knowledge of
the instrument, by observing the possible differences between the in-phase and quadrature
components. Moreover, having more calibration loads, even in the lower range, would enable
the use of more terms in the error model. In particular, a SHORT load is easy to construct
with high accuracy (ignoring the electrical length) and an effort should be made to make
possible its use inside the VNA range.
More ambitious projects include the miniaturization of this instrument for its integration
into small satellites like CubeSats. From an electrical perspective, this presents several
challenges. Low-power components must be selected and the accuracy degradation must be
assessed. However, even more challenging will be the mechanical deployment of the antenna
while maintaining a good electrical guard.
58
Even if the SIP highest advantage is providing a very accurate impedance curve,
it requires a high data rate that is not always available. There is work in progress for
implementing a digital phase locked loop. Because the frequency update is limited by the
serial line data rate, the tracking cannot be performed like that of an analog PLL. It is
proposed to implement a small span sweep centered around the parallel frequency. The raw
data must be converted to impedance values and the parallel resonance estimated in just a
few milliseconds. Therefore, it seems reasonable to perform those operations with limited
accuracy, even without calibration, while down-linking enough raw data to ground where
the parallel frequency could be calculated with higher accuracy.
Going even further, it is the intention of SDL-USU to implement a CubeSat top-side
sounder based on this same architecture. This will present many challenges and possible
projects, including the RF design of a tunable impedance matching network, the signal
post-processing for reducing the data rate or the on-ground post-processing. If successful, it
will provide invaluable data being the first top-side sounder on-board a CubeSat.
59
References
[1] SID Monitoring Station. [Online]. Available: http://sidstation.loudet.org/
[2] Space Weather Center - GAIM Global TEC. [Online]. Available: http://spaceweather.usu.edu/htm/innovations/gaim-global-tec
[3] W. G. Sanderson, “The history and dynamics of plasma impedance probe,” Master’sthesis, Utah State University, 2007.
[4] K. Balmain, “The impedance of a short dipole antenna in a magnetoplasma,” IEEETransactions on Antennas and Propagation, vol. 12, no. 5, pp. 605–617, 1964.
[5] J. Ward, C. Swenson, and C. Furse, “The impedance of a short dipole antenna in amagnetized plasma via a finite difference time domain model,” IEEE Transactions onAntennas and Propagation, vol. 53, no. 8, pp. 2711–2718, 2005.
[6] A. Hummel, “The plasma impedance probe: a quadrature sampling technique,” Master’sthesis, Utah State University, 2006.
[7] K. Endo, A. Kumamoto, H. Oya, T. Ono, and Y. Katoh, “Plasma wave turbulencedue to the wake of an ionospheric sounding rocket,” in European Geosciences UnionGeneral Assembly Conference Abstracts, vol. 15, p. 7293, April 2013.
[8] E. Stromberg, C. Swenson, and C. Fish, “Auroral spatial structures probe soundingrocket mission,” in American Geophysical Union Fall Meeting Abstracts, vol. 1, p. 1959,2011.
[9] P. Kiciak, “An HF vector network analyzer Part 1,” Technical Report, 2003. [Online].Available: http://www.n2pk.com
[10] W. Pfister, “Survey of RF impedance probes,” in Direct Aeronomic Measurements inthe Lower Ionosphere. Urbana, IL: University of Illinois Urbana, pp. 31–36, 1963.
[11] E. Rotholz, “Phase noise of mixers,” Electronics Letters, vol. 20, no. 19, pp. 786–787,Sept. 1984.
[12] T. M. Comberiate, “Phase noise and spur reduction in an array of direct digitalsynthesizers,” Master’s thesis, University of Illinois, 2010.
[13] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-ampimperfections: autozeroing, correlated double sampling, and chopper stabilization,”Proceedings of the IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996.
[14] M. Milkovic, “Current transformer with active load termination,” US Patent US3 815 012A, June, 1974.
[15] N. Kondrath and M. Kazimierczuk, “Bandwidth of current transformers,” IEEE Trans-actions on Instrumentation and Measurement, vol. 58, no. 6, pp. 2008–2016, 2009.
60
[16] “Use of ferrites in broadband transformers,” Fair-Rite Products Corp., Technical Report,2008.
[17] D. W. Knight. (2008) Current transformers: Part 1. [Online]. Available:http://www.g3ynh.info/zdocs/bridges/Xformers/part 1.html
[18] “Applying error correction to network analyzer measurements,” Agilent Technologies,Technical Report, 2002.
61
Appendices
62
Appendix A
Current Transformer
The Current Transformer (CT) has a large influence on the overall instrument perfor-
mances. It has to measure the current over a wide frequency range (1.3 decades), with very
high sensitivity (currents in the order of microamperes in the upper-hybrid frequency) while
introducing low noise. This appendix explains the different transformer cores, configurations
and decisions that were made during the design and manufacturing process.
A.1 Theory
The CT is used in the typical configuration shown in Fig. A.1, with a small burden
resistor that senses the current reflected from the primary, and with a Low Noise Amplifier
(LNA) connected to it. This together with the CT ratio 1:n assures that the impedance
insertion in the primary Rb/n2 is minimum. The CT general model [15, 16] can be seen
in Fig. A.2, where R1 and R2 are the resistive losses of the windings, L1 and L2 are the
leakage inductance of the windings, C1 and C2 are the capacitance of the windings, RC
represents the losses on the core, and LM is the magnetizing inductance of the core (where
the hysteresis and saturation can be modeled). The capacitance between windings has been
neglected because the braid of the primary wire grounded acts like a Faraday shield [17].
This model is approximated by the lumped elements model of Fig. A.3, where
R1,2 = R1 +R2/n2, (A.1)
L1,2 = L1 + L2/n2, (A.2)
C1,2 = C1 + n2C2. (A.3)
For low frequencies, the model gets simplified as shown in Fig. A.4. In general, all
inductances and capacitances present a low and high impedance, respectively, and can
63
Z
1 : n
Rb
I
Fig. A.1: Typical circuit using a current transformer.
C1
R1 L1
RC LC
1 : nR2 L2
C2 Rb
Fig. A.2: General model of the current transformer.
R1,2 L1,2
RC LC C1,2 Rb/n2
1 : n
Fig. A.3: Lumped elements model of the current transformer.
64
be ignored. However, the core inductance at low frequencies presents a low impedance
comparable to the burden resistor load, thus decreasing the sensitivity. The transfer function
is similar to a high-pass filter where the cut-off frequency is
fL =R1,2 +Rb/n
2
2πLC. (A.4)
For increasing the bandwidth in the lower frequencies the core inductance must be increased.
For example, toroidal cores have the following expression:
L =µn2A
2πr, (A.5)
where A is the cross-sectional area and r is the radius. In general, manufacturers use the AL
parameter which indicate the inductance per turn. Taking this into account, it is usually
selected a high permeability material, with big dimensions and a large number of turns. It is
also convenient to reduce the burden resistor load in the primary, and using wires with low
resistivity (mostly in the primary because the secondary impedance gets reduced by n2).
In high frequency the transformer model gets simplified as shown in Fig. A.5. The high
cut-off frequency can be calculated as
fH =1
2π√
(Rb/n2C1,2)2 + (L1,2/RC)2. (A.6)
For increasing the bandwidth in the upper frequencies, it is recommended the least number
of turns (reducing in this way all parasitic elements) and low permeability materials. These
materials have a lower permeability at low frequencies, but they extend much further in
R1,2
LC Rb/n2
1 : n
Fig. A.4: Low frequency model of the current transformer.
65
high frequencies without dropping. They also have less losses and are more stable with
temperature.
Additional requirements are having enough sensitivity, which is given by
SV =VOI
=Rbn, (A.7)
and low noise, which results in a low burden resistor. As can be seen, there exists a trade-off
between the material, number of turns, and burden resistor.
A.2 Configurations Tested
Different configurations were tested varying the core geometry (toroidal, small binocular,
or big binocular), the number of turns of the primary and secondary, the wire type, and the
burden resistor. The configurations used are summarized in Table A.1. In order to compare
the different transformers, the transfer functions have been normalized to the ideal gain (i.e.
0dB represents the gain of an ideal transformer with that configuration).
The transformers are characterized with the test set-up shown in Fig. A.6. The series
resistance is used to excite the primary with a constant current independent of the impedance
load. The input impedance of the network analyzer is used as the burden resistor.
The conclusions extracted from the tests are:
• Because the ASSP SIP transformer is situated very close to the antenna, the use of
a big impedance controlled coaxial was considered not necessary. Instead of that, a
thin shielded wire was used, allowing the employment of the binocular core. This core
presents the advantage with respect toroidal cores of very reduced leakage inductance
L1,2
RC C1,2 Rb/n2
1 : n
Fig. A.5: High frequency model of the current transformer.
66
Tab
leA
.1:
Lis
tof
curr
ent
tran
sfor
mer
con
figu
rati
ons
test
ed.
#C
ore
P/N
Geo
met
ryM
atl
n1
Pri
mar
yn
2S
econ
dar
yRb
SV
Rem
arks
1596
1000
801
Toro
idal
611
36A
WG
Tefl
on5
36A
WG
Tefl
on50
10
2286
1002
402
Bin
ocu
lar
611
36A
WG
Tefl
on5
36A
WG
Tefl
on50
10
3286
1002
402
Bin
ocu
lar
612
24A
WG
En
amel
1036
AW
GE
nam
el50
10
4286
1002
402
Bin
ocu
lar
611
24A
WG
En
amel
536
AW
GE
nam
el50
10
5286
1002
402
Bin
ocu
lar
611
28A
WG
Tefl
on5
28A
WG
Tefl
on50
10
6286
1002
402
Bin
ocu
lar
610.
518
AW
GT
eflon
328
AW
GT
eflon
508.
3
7596
1000
801
Toro
idal
611
28A
WG
Enam
el5
28A
WG
En
amel
5010
8286
1002
402
Bin
ocu
lar
611
28A
WG
En
amel
628
AW
GE
nam
el50
10
9286
1002
402
Bin
ocu
lar
611
28A
WG
En
amel
628
AW
GE
nam
el75
15
10
2873
0024
02
Bin
ocu
lar
731
28A
WG
En
amel
528
AW
GE
nam
el50
10
11
2843
0024
02
Bin
ocu
lar
431
28A
WG
En
amel
528
AW
GE
nam
el50
10
12
2873
0003
02
Bin
ocu
lar
(big
)73
124
AW
GE
nam
el5
24A
WG
En
amel
5010
13
2873
0003
02
Bin
ocu
lar
(big
)73
124
AW
GE
nam
el10
24A
WG
En
amel
5010
14
2873
0003
02
Bin
ocu
lar
(big
)73
124
AW
GE
nam
el10
24A
WG
En
amel
5010
Fir
ston
ew
ired
onop
pos
ite
sid
es
15
2873
0003
02
Bin
ocu
lar
(big
)73
124
AW
GE
nam
el+
Bra
id10
28A
WG
En
amel
5010
Sh
ield
un
con
nec
ted
16
2873
0003
02
Bin
ocu
lar
(big
)73
124
AW
GE
nam
el+
Bra
id10
28A
WG
En
amel
5010
Sh
ield
con
nec
ted
tod
rive
rgr
oun
d
17
2873
0003
02
Bin
ocu
lar
(big
)73
124
AW
GE
nam
el+
Bra
id10
28A
WG
En
amel
5010
Sh
ield
con
nec
ted
tore
ceiv
ergr
ound
18
2873
0003
02
Bin
ocu
lar
(big
)73
1C
ust
omsh
ield
edw
ire
1028
AW
GE
nam
el50
10S
hie
ldu
nco
nn
ecte
d
19
2873
0003
02
Bin
ocu
lar
(big
)73
1C
ust
omsh
ield
edw
ire
1028
AW
GE
nam
el50
10P
otte
d.
Sh
ield
un
con
nec
ted
67
PORT 1 (OUT)
PORT 2 (IN)
100Ω/1kΩ
NetworkAnalyzer
Fig. A.6: Current transformer test set-up.
(in mundane words, very little wire is not contributing to the magnetic field), with
higher AL, and it is very easy to wire allowing a high repeatability. A comparative of
toroidal and binocular cores of similar dimensions can be seen in Fig. A.7.
• The highest permeability core is preferred. Even if the permeability is reduced at high
frequencies or has more temperature degradation, to achieve a good low frequency
response is the best option. In Fig. A.8, three different materials were tested in the
same configuration, 73 with µr = 2500, 61 with µr = 125, and 43 with µr = 800.
• The burden resistor was selected to be 50Ω. It is an often convenient load to use [17],
because it is the load used by the manufacturer to provide its data, an arbitrary
5 10 15 20 25 30 35 40 45 50−20
−15
−10
−5
0
5
Frequency [MHz]
Mag
nit
ud
e[d
B]
1 (toroidal)
2 (binocular)
5 (binocular)
7 (toroidal)
Fig. A.7: Normalized gain for different core geometries and sizes.
68
105 106 107 108−10
−5
0
5
Frequency [Hz]
Gain
[dB
]
9 (61)
10 (73)
11 (43)
Fig. A.8: Normalized gain for different core materials.
length of coaxial wire and common instrumentation can be used without changing
its properties, it requires a low number of turns to have a low impedance insertion,
and it imposes a low requirement on the amplifier input impedance. In this particular
application, it also presents an adequate low thermal noise.
• The number of turns was limited to five turns in the secondary. By having this low
number of turns, the high frequency response and the sensitivity are improved. On the
other hand, the impedance insertion is high, but limited by the low burden resistor.
In Fig. A.9, it can be seen how a big turns ratio (1:6) improves the low frequency
response, but with 1:5 is enough. It was also tested with half turn in the primary
(making it similar to a toroidal), but the response was not acceptable.
• The wire selected for the primary is a custom manufactured Stainless Steel (SS)
shielded wire. Unifilar shielded wires are not very common and this wire was already in
use in other ASSP instruments. As indicated some tests were performed with enamel
coated wire with a small braid (configurations 15 to 17), but even if the electrical
properties were good, the mechanical result was much better with the shielded wire.
• For the secondary, an enamel coated wire was used. This type of wire is often referred
as magnetic wire, because it is used in transformers and motors. It presents the
69
5 10 15 20 25 30 35 40 45 50−10
−8
−6
−4
−2
0
2
Frequency [MHz]
Mag
nit
ud
e[d
B]
5 (1:5)
6 (0.5:3)
8 (1:6)
Fig. A.9: Normalized gain for different turns ratio.
advantages of having a copper core and a very thin insulation. This results in a
high conductivity and density, needing less turns than other wires. In the tests, this
advantage can be observed with respect to regular Teflon coated wire, or the custom
SS wire used in the primary. The final gauge selected, 28 AWG, was chosen from the
ones that were performing well electrically (24 and 28), and made easier the winding.
For example, a 36 AWG gauge was available, but at these frequencies the performance
was poor.
Configuration 19 is the final one. It consists of a big binocular core (2873000302), with
the custom shielded SS wire in the primary (N12-50F+00007-5), and the 28 AWG enamel
coated wire in the secondary (MW-MC5516-038). It presents a very flat frequency response
and a fair sensitivity. The transformer selected has enough space in the holes in case more
turns are considered necessary in the future. To fix the cables into a right position, the holes
are potted without affecting the electrical performances.
A.3 Final Transformer Tests
In order to improve the performances of the instrument, it is interesting to have two
similar transformers for the antenna and reference channels. Several transformers were
wired, potted, and tested with the configuration selected. The results presented in Fig. A.10,
70
and zoomed in the bandwidth of interest in Fig. A.11, show a good repeatability, and they
were used to select the more similar couple in terms magnitude and phase. In this case,
transformers 8 and 11 are quite similar and have some of the higher gain.
The primary wire resistance was measured to be about 5.7Ω and the secondary resistance
105 106 107 108
−30
−20
−10
0
10
Frequency [Hz]
Mag
nit
ud
e[d
B]
4678910111213
105 106 107 108
−20
0
20
40
60
80
100
120
140
160
Frequency [Hz]
Ph
ase
[deg
rees
]
Fig. A.10: Final tests for transformer selection.
71
2 4 6 8 10 12 14 16 18 200
5 · 10−2
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Frequency [MHz]
Mag
nit
ud
e[d
B]
4678910111213
2 4 6 8 10 12 14 16 18 20−2
−1
0
1
2
3
Frequency [MHz]
Ph
ase
[deg
rees
]
Fig. A.11: Final tests for transformers selection with detail in the operational frequencybandwidth.
72
of 0.1Ω. It would have been interesting to measure the capacitance and inductance (which
are normally not provided in the wire datasheet), to check the the expected cut-off and
resonant frequencies.
A.4 Hystereis and Saturation
Saturation and hysteresis affects the CT by producing harmonics on the secondary
output. A specific test was performed to assure that the level was acceptable. The CT
was driven with the maximum current at the minimum frequency and the secondary was
measured with a spectrum analyzer. The result can be seen in Fig. A.12, where the third
harmonic is 62 dB below the fundamental. This harmonic is in fact produced by the signal
generator (two different signal generator were used with similar results). Even if it were a
harmonic produced by the CT, it is low enough to discard any saturation degradation effects,
which was foreseen due to the low current levels, but it also discards any hysteresis problem.
A.5 Shield Rejection
The guard is only effective if the coupling between the primary core and secondary, and
the primary shield and secondary are very similar. To test this, the set-up of Fig. A.13
was used, where the same current is flown through primary and shield. In ideal conditions
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
−80
−60
−40
−20
62dB
Frequency [MHz]
Mag
nit
ud
e[d
Bm
]
Fig. A.12: Harmonics testing of the current transformer.
73
the secondary output would be zero. The result have been normalized to the output of
the secondary when only current is flowing through the primary shown in Fig. A.14. As
frequency increases, the different geometry of the core and shield are more pronounced.
However, there is still a good rejection of at least 20 dB. This means that for having a
similar output to the actual signal, the stray capacitances should be 20dB higher than the
antenna capacitance (10 times in linear units), when in fact they are much less.
PORT 1 (OUT)
PORT 2 (IN)
1kΩ
NetworkAnalyzer
Fig. A.13: Current transformer shield rejection test set-up.
2 4 6 8 10 12 14 16 18 2015
20
25
30
35
40
Frequency [MHz]
Rej
ecti
on
Rat
io[d
B]
Fig. A.14: Rejection ratio of currents through the shield of the current transformer.
74
Appendix B
PCB Schematics
(7 pages)
75
NE
XT
AS
SY
. TIT
LE
NE
XT
AS
SE
MB
LY
PR
OG
RA
M
EN
GIN
EE
R
LAS
T M
OD
IFIE
D
SC
H R
EV
DR
AW
ING
NU
MB
ER
INS
TA
NC
E N
AM
E
SC
HE
MA
TIC
NA
ME
TIT
LE
For
m N
umbe
r Q
F04
42
Rev
-
(B L
ands
cape
)
43
21
A B C D
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
Nor
th L
ogan
, Uta
h 84
341
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
INF
OR
MA
TIO
N T
HA
T IS
PR
OP
RIE
TA
RY
TO
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
(S
DL)
. R
EF
ER
EN
CE
US
UR
F B
P 4
09.1
A B C D
43
21
PA
GE
NA
ME
08/1
2/20
13S
ync
Ser
ial I
nter
face
1
DG
ND
Vbu
s_In
UA
RT
_RS
232_
GS
E_T
X
TM
_Dat
a_H
_N
TM
_Dat
a_H
_P
TM
_MF
ram
e_H
_N
TM
_MF
ram
e_H
_P
TM
_Fra
me_
H_N
TM
_Fra
me_
H_P
TM
_Wor
d_H
_N
TM
_Wor
d_H
_P
TM
_Ena
ble_
H_N
TM
_Ena
ble_
H_P
TM
_Loa
d_L_
N
TM
_Loa
d_L_
P
TM
_Gtd
_Ck_
N
TM
_Gtd
_Ck_
P
JSI2
UA
RT
_GN
D
TM
_MF
ram
e_H
_N
TM
_Dat
a_H
_N
TM
_Dat
a_H
_P
TM
_MF
ram
e_H
_P
TM
_Fra
me_
H_N
TM
_Fra
me_
H_P
TM
_Wor
d_H
_N
TM
_Wor
d_H
_P
TM
_Ena
ble_
H_N
TM
_Ena
ble_
H_P
TM
_Loa
d_L_
N
TM
_Loa
d_L_
P
TM
_Gtd
_Ck_
N
TM
_Gtd
_Ck_
P
Vbu
s_In
UA
RT
_RS
232_
Pay
_TX
UA
RT
_RS
232_
Pay
_TX
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
TM
_MF
ram
e_H
_P
TM
_MF
ram
e_H
_NT
M_F
ram
e_H
_P
TM
_Fra
me_
H_N
TM
_Wor
d_H
_P
TM
_Wor
d_H
_NT
M_E
nabl
e_H
_P
TM
_Ena
ble_
H_N
TM
_MF
ram
e_H
_N
TM
_Loa
d_L_
P
TM
_Loa
d_L_
NT
M_G
td_C
k_P
TM
_Gtd
_Ck_
N
TM
_Dat
a_H
_NT
M_D
ata_
H_N
TM
_Fra
me_
H_P
TM
_Fra
me_
H_N
TM
_Wor
d_H
_P
TM
_Wor
d_H
_NT
M_E
nabl
e_H
_P
TM
_Ena
ble_
H_N
TM
_MF
ram
e_H
_P
TM
_Loa
d_L_
P
TM
_Loa
d_L_
NT
M_G
td_C
k_P
TM
_Gtd
_Ck_
N
C5
C04
02C
102K
3RA
CT
U0.
001u
F25
V
25V
0.00
1uF
C04
02C
102K
3RA
CT
UC4
C11
C04
02C
102K
3RA
CT
U0.
001u
F25
V
25V
0.00
1uF
C04
02C
102K
3RA
CT
UC12 C3
C04
02C
102K
3RA
CT
U0.
001u
F25
V
25V
0.00
1uF
C04
02C
102K
3RA
CT
UC2
SS
I_E
nabl
e_L
SS
I_E
nabl
e_H
SS
I_E
nabl
e_L
25V
0.1u
FC
0603
C10
4K3R
AC
TU
C6
C7 C
0603
C10
4K3R
AC
TU
0.1u
F
25V
TM
_Dat
a_H
_PT
M_D
ata_
H_P
SS
I_E
nabl
e_L
SS
I_E
nabl
e_L
SS
I_E
nabl
e_L
SS
I_E
nabl
e_L
SS
I_E
nabl
e_L
422
Rec
eive
rs
422
Driv
er
Ope
n in
puts
allo
wed
Tes
t Por
t
TM
_MF
ram
e_H
TM
_Fra
me_
HT
M_W
ord_
HT
M_E
nabl
e_H
TM
_Loa
d_L
TM
_Gtd
_Ck
511o
hmR
K73
H1J
L511
0F
R13
3
511o
hmR
K73
H1J
L511
0F
R13
4
511o
hmR
K73
H1J
L511
0F
R13
5
511o
hmR
K73
H1J
L511
0F
R13
6
511o
hmR
K73
H1J
L511
0F
R13
9
511o
hmR
K73
H1J
L511
0F
R14
0
511o
hmR
K73
H1J
L511
0F
R14
1
511o
hmR
K73
H1J
L511
0F
R14
2T
PP
0T
P-1
05-0
1-05
TE
ST
PO
INT
, GR
EE
N
TP
P1
TP
-105
-01-
05T
ES
T P
OIN
T, G
RE
EN
TP
P2
TP
-105
-01-
05T
ES
T P
OIN
T, G
RE
EN
TP
P3
TP
-105
-01-
05T
ES
T P
OIN
T, G
RE
EN
TP
P4
TP
-105
-01-
05T
ES
T P
OIN
T, G
RE
EN
TP
P5
TP
-105
-01-
05T
ES
T P
OIN
T, G
RE
EN
TP
P6
TP
-105
-01-
05T
ES
T P
OIN
T, G
RE
EN
TP
P7
TP
-105
-01-
05T
ES
T P
OIN
T, G
RE
EN
Tes
tPor
t(7)
Tes
tPor
t(6)
Tes
tPor
t(5)
Tes
tPor
t(3)
Tes
tPor
t(2)
Tes
tPor
t(0)
SS
I_E
nabl
e_H
SS
I_E
nabl
e_H
SS
I_E
nabl
e_H
SS
I_E
nabl
e_H
SS
I_E
nabl
e_H
SS
I_E
nabl
e_H
TM
_Dat
a_H
TM
_Dat
a_H
TP
D7
SM
L-21
0MT
T86
21
TP
D6
SM
L-21
0MT
T86
21
TP
D5
SM
L-21
0MT
T86
21
TP
D4
SM
L-21
0MT
T86
21
TP
D3
SM
L-21
0MT
T86
21
TP
D2
SM
L-21
0MT
T86
21
TP
D1
SM
L-21
0MT
T86
21
TP
D0
SM
L-21
0MT
T86
21
Din
Rin
C1+
C1-
C2+
C2-
FO
RC
EO
FF
FO
RC
EO
N
EN
GN
DV-
V+
INV
ALI
D
Rou
t
Dou
t
VC
C
DG
ND
DG
ND
DG
ND
U4
MA
X32
21IP
W
15 13 9 10 3 7 14112166542811
C14
C06
03C
104K
3RA
CT
U0.
1uF
25V
C10
C06
03C
104K
3RA
CT
U0.
1uF
25V
25V
0.1u
F
C06
03C
104K
3RA
CT
U
C13
UA
RT
_GS
E_T
X_H
2-C
1
UA
RT
_Inv
alid
_L2-
C1
C9
C06
03C
104K
3RA
CT
U
0.1u
F
25V
UA
RT
_RS
232_
GS
E_T
X
GS
E P
ort I
nter
face
UA
RT
_RS
232_
GS
E_T
XU
AR
T_P
ay_T
X_H
UA
RT
_RS
232_
Pay
_TX
+3.3
VD
+3.3
VD
DG
ND
C1
C06
03C
104K
3RA
CT
U0.
1uF
25V
DG
ND
+3.3
VD 50
V0.
1uF
C11
1
GN
D
GN
D
GN
D
Shi
eld_
Ter
min
atio
n_T
M_D
ata
Dig
ital
Ext
erna
l
Ext
erna
lD
igita
l
Digital
External
GN
D
++
C8
TA
JD22
6K03
5R22
uF 35V
C18
6
TA
JD22
6K03
5R22
uF
35V
UA
RT
_RS
232_
Pay
_TX
100o
hmR
K73
H1J
L100
0F
R11
UA
RT
_GS
E_T
X_H
UA
RT
_Inv
alid
_L
100o
hmR
10 RK
73H
1JL1
000F
RK
73H
1JL1
000F
R5
100o
hmT
M_G
td_C
kT
M_L
oad_
LTM
_Ena
ble_
HT
M_W
ord_
HT
M_F
ram
e_H
TM
_MF
ram
e_H
100o
hmR
12
100o
hmR
9R
710
0ohm
100o
hmR
8
R6
100o
hm
C1
A2
D2
D2
A2
A2
A2
B2
A2
B2
B2
C2
B2
C2
C2
5-B
2
C2
B1
B1
B1
B1
B1
B1
B1
B1
C1
C1
C1
C1
B1
B2,
C2
B1
C2,
D3
2-C
1B
2,D
3
2-C
12-
B1
2-B
12-
B1
2-B
12-
B1
B2,
C2
C2,
D3
B2,
D3
2-C
1
2-C
1
B1
2-C
1
B1
AS
SP
SIP
Mai
n In
stru
men
t Sch
emat
ics
AS
SP
W. C
ox18
6-01
40- 6
186-
0140
Pla
ce a
ll LE
Ds
and
Tes
t poi
nts
on to
p si
deO
rder
with
7 o
n le
ft an
d 0
on r
ight
.
R4
RK
73H
2BT
TD
1210
F12
1ohm
121o
hmR
K73
H2B
TT
D12
10F
R3
R15
RK
73H
2BT
TD
1210
F12
1ohm
121o
hmR
K73
H2B
TT
D12
10F
R16 R2
RK
73H
2BT
TD
1210
F12
1ohm
121o
hmR
K73
H2B
TT
D12
10F
R1
U3
16 3 5 11 13 812415149107612
1A 1B 2A 2B 3A 3B 4A 4B G GG
ND4Y3Y2Y1Y
VC
C
AM
26LV
32ID
R
Inpu
ts d
on't
load
line
whe
n V
cc =
0V
1A 1B 2A 2B 3A 3B 4A 4B G GG
ND4Y3Y2Y1Y
VC
C
AM
26LV
32ID
R
2 1 6 7 10 9 14 15 4 12813115316
U2
4.8
Mbp
s S
erea
l Int
erfa
ce
4.8
Mbp
s S
erea
l Int
erfa
ce
U7
2 3 6 5 10 11 14 1381241597116
VC
C 1A 2A 3A 4A G G
GN
D4Z4Y3Z3Y2Z2Y1Z1Y
AM
26LV
31ID
R
+3.3
VD
+3.3
VD
+3.3
VD
+3.3
VD
+3.3
VD
+3.3
VD
JSI2
1
5747
238-
2
JSI2
2
5747
238-
2
JSI2
3
5747
238-
2
JSI2
4
5747
238-
2
JSI2
5
5747
238-
2
JSI2
6
5747
238-
2
JSI2
7
5747
238-
2
JSI2
8
5747
238-
2
JSI2
9
5747
238-
2
JSI2
10
5747
238-
2
JSI2
11
5747
238-
2
JSI2
12
5747
238-
2
JSI2
13
5747
238-
2
JSI2
14
5747
238-
2
JSI2
15
5747
238-
2
JSI2
16
5747
238-
2
JSI2
17
5747
238-
2
JSI2
18
5747
238-
2
JSI2
19
5747
238-
2
JSI2
20
5747
238-
2
JSI2
21
5747
238-
2
JSI2
22
5747
238-
2
JSI2
23
5747
238-
2
JSI2
24
5747
238-
2
JSI2
25
5747
238-
2
Digital
External
Tes
tPor
t(7)
Tes
tPor
t(6)
Tes
tPor
t(5)
Tes
tPor
t(4)
Tes
tPor
t(3)
Tes
tPor
t(2)
Tes
tPor
t(1)
Tes
tPor
t(0)
2-D
2
2-D
2
2-D
2
2-D
2
2-D
2
2-D
2
2-D
2
2-D
2
186-
0317
76
NE
XT
AS
SY
. TIT
LE
NE
XT
AS
SE
MB
LY
PR
OG
RA
M
EN
GIN
EE
R
LAS
T M
OD
IFIE
D
SC
H R
EV
DR
AW
ING
NU
MB
ER
INS
TA
NC
E N
AM
E
SC
HE
MA
TIC
NA
ME
TIT
LE
For
m N
umbe
r Q
F04
42
Rev
-
(B L
ands
cape
)
43
21
A B C D
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
Nor
th L
ogan
, Uta
h 84
341
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
INF
OR
MA
TIO
N T
HA
T IS
PR
OP
RIE
TA
RY
TO
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
(S
DL)
. R
EF
ER
EN
CE
US
UR
F B
P 4
09.1
A B C D
43
21
PA
GE
NA
ME
08/1
2/20
132
TD
I
TC
K
TM
S
TD
O
TR
ST
IO00
RS
B0/
GA
A0
IO01
RS
B0/
GA
A1
IO02
RS
B0/
GA
B0
IO03
RS
B0/
GA
B1
IO04
RS
B0/
GA
C0
IO05
RS
B0/
GA
C1
IO223NDB3
IO11
RS
B0
IO23
RS
B0
IO16
RS
B0
IO17
RS
B0
IO21
RS
B0
IO22
RS
B0
IO28
RS
B0
IO29
RS
B0
IO25
RS
B0
IO27
RS
B0
IO36
RS
B0
IO38
RS
B0
IO33
RS
B0
IO34
RS
B0
IO35
RS
B0
IO46
RS
B0
IO47
RS
B0
IO44
RS
B0
IO42
RS
B0
IO45
RS
B0
IO50
RS
B0
IO51
RS
B0
IO49
RS
B0
IO52
RS
B0
IO55
RS
B0
IO57
RS
B0
IO61
RS
B0
IO56
RS
B0
IO60
RS
B0
IO80NDB1
IO62
RS
B0
IO71
RS
B0
IO79
ND
B1
IO72
RS
B0/
GB
C0
IO73
RS
B0/
GB
C1
IO74
RS
B0/
GB
B0
IO75
RS
B0/
GB
B1
IO76
RS
B0/
GB
A0
IO77
RS
B0/
GB
A1
IO78
PD
B1/
GB
A2
IO81PDB1
IO79
PD
B1/
GB
B2
IO78
ND
B1
IO80PDB1/GBC2
IO83NPB1
IO81NDB1
IO82NSB1
IO86PPB1
IO86NPB1
IO90PPB1
IO90NPB1
IO87PDB1
IO87NDB1
IO83PPB1
IO96NPB1
IO91PPB1/GCC1
IO91NPB1/GCC0
IO92PPB1/GCB1
IO92NPB1/GCB0
IO93PPB1/GCA1
IO93NPB1/GCA0
IO94PSB1/GCA2
IO102PDB1
IO95PPB1/GCB2
IO95NPB1
IO96PPB1/GCC2
IO102NDB1
IO88PDB1
IO88NDB1
IO113NDB1/GDA0
IO100PPB1
IO100NPB1
IO107PDB1
IO107NDB1
IO106PDB1
IO106NDB1
IO111PDB1/GDC1
IO111NDB1/GDC0
IO112PPB1/GDB1
IO112NPB1/GDB0
IO113PDB1/GDA1
IO11
6RS
B2/
GD
C2
IO18
7RS
B2/
GE
A2
IO18
6RS
B2/
GE
B2/
FF
IO18
5RS
B2/
GE
C2
IO19
2NP
B3
IO18
4RS
B2
IO17
9RS
B2
IO18
3RS
B2
IO17
1RS
B2
IO17
2RS
B2
IO16
8RS
B2
IO16
5RS
B2
IO203PDB3
IO16
3RS
B2
IO16
1RS
B2
IO17
0RS
B2
IO15
9RS
B2
IO16
4RS
B2
IO15
7RS
B2
IO15
5RS
B2
IO15
1RS
B2
IO15
8RS
B2
IO14
7RS
B2
IO15
3RS
B2
IO14
9RS
B2
IO14
2RS
B2
IO13
6RS
B2
IO14
3RS
B2
IO14
1RS
B2
IO13
7RS
B2
IO13
5RS
B2
IO13
8RS
B2
IO13
4RS
B2
IO12
9RS
B2
IO13
0RS
B2
IO12
4RS
B2
IO13
1RS
B2
IO12
8RS
B2
IO12
5RS
B2
IO110NDB1
IO12
0RS
B2
IO110PDB1
IO11
5RS
B2/
GD
B2
IO11
4RS
B2/
GD
A2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GNDQ1
GNDQ2
GNDQ3
GNDQ4
GNDQ5
GNDQ6
IO18
8PD
B3/
GE
A1
IO18
8ND
B3/
GE
A0
IO18
9PD
B3/
GE
B1
IO18
9ND
B3/
GE
B0
IO19
0PP
B3/
GE
C1
IO19
0NP
B3/
GE
C0
IO19
2PP
B3
IO19
3NP
B3
IO197NSB3
IO19
4PS
B3
IO196PPB3
IO19
6NP
B3
IO203NDB3
IO202PDB3
IO19
3PP
B3
IO210PSB3
IO217PDB3
IO217NDB3F1
IO216PDB3
IO218PDB3
IO213PDB3
IO218NDB3
IO216NDB3
IO221PDB3
IO222PDB3
IO222NDB3
IO223PDB3/GAC2
IO221NDB3
IO224PDB3/GAB2
IO224NDB3
IO225PDB3/GAA2
IO225NDB3
IO204PDB3/GFC2
IO202NDB3
IO205PDB3/GFB2
IO205NDB3
IO206PSB3/GFA2
IO204NDB3
IO207PDB3/GFA1
IO209NPB3/GFC0
IO208PPB3/GFB1
IO208NPB3/GFB0
IO209PPB3/GFC1
IO207NDB3/GFA0
IO213NDB3
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCCIB0_1
VCCIB0_2
VCCIB0_3
VCCIB0_4
VCCIB1_1
VCCIB1_2
VCCIB1_3
VCCIB1_4
VCCIB2_1
VCCIB2_2
VCCIB2_3
VCCIB2_4
VCCIB3_1
VCCIB3_2
VCCIB3_3
VCCIB3_4
VMV0_1
VMV0_2
VMV1_1
VMV1_2
VMV2_1
VMV2_2
VMV3_1
VMV3_2
VCCPLF
VPUMP
VJTAG
VCOMPLF
TC
KG
ND
1
TD
O
VJT
AG
TM
S
VP
UM
PT
RS
T
PM
OD
E
TD
IG
ND
2
DG
ND
DG
ND
DG
ND
NC
GN
D
OU
TP
UT
VC
C
DG
ND
DG
ND
DG
ND
+3.3
VD
+3.3
VD
+3.3
VD
+3.3
VD
+3.3
VD
+3.3
VD
+3.3
VD
+1.5
VD
+3.3
VD
SI
SC
K
HO
LD
WP
CS
GN
DSO
VC
C
EP
DG
ND
+3.3
VD
DG
ND
DG
ND
DG
ND
+1.5
VD
+1.5
VD
DG
ND
+1.5
VD
DG
ND
DG
ND
+3.3
VD
+3.3
VD
DG
ND
+3.3
VD
DG
ND
+1.5
VD
A1
A2
GN
DY
2
Y1
VC
C
DG
ND
+3.3
VD
U1
AG
L100
0V5-
FG
256I
H4
N14
P14
J3
M5
C3
M12
P3
P12
E12
E5
C14
L5
K5
G5
F5
M11
M10
M7
M6
L12
K12
G12
F12
E11
E10
E7
E6
L10
L9
L8
L7
K11
K6
J11
J6
H11
H6
G11
G6
F10
F9
F8
F7
G2
H2
G4
H1
H3
H5
J2
K2
J1
J4
J5
L1
K1
C2
B2
C1
B1
E3
D3
D1
D2
E4
F4
F2
G3
E2
F3
E1
G1
L4
L2
K3
M2
L3
N1
M1
M3
N2
M4
N3
P2
P1
R2
R1
R15
N12
N5
D12
D5
B3
T16
T1
L11
L6
K10
K9
K8
K7
J10
J9
J8
J7
H10
H9
H8
H7
G10
G9
G8
G7
F11
F6
A16
A1
T14
R13
N13
T13
M13
R12
P11
R11
N11
T11
N10
P10
R10
T10P9
N9
R9
M9
T9
R8
T8
M8
T7
P8
N8
R7
T6 P7
T5
N7
R6
K4
P6
R5
T4
P5
T2
P4
R3
N4
R4
T3
N6
T12
N16
L13
M14
N15
M15
L14
L15
M16
L16
K14
J15
P16
G16
G15
K15
J14
K13
J12
K16
J16
H14
J13
H16
H13
H12
G13
H15
E14
F16
E16
G14
F15
F14
E15
D16
C16
F13
E13
C15
D14
B16
B15
A15
A14
A13
B13
B12
C12
D15
B14
C13
D13
D11
C11
A12
B11
A11
D10
C10
B10
A10
A9
C9
B9
E9
D9
A8
B8
D8
E8
C8
B7
C7
D7
A7
A6
B6
B5
A5
D6
C4
D4
C6
C5
B4
A4
A3
A2
P15
R16
T15
P13
R14
P1
PZ
N-1
0-A
A_J
TA
G
109
4 875
6
3
21
100K
ohm
RK
73H
1JL1
003F
R13
7
FO
X92
4B-1
0.00
0
Y3
4 3 21
0ohm
RK
73Z
1JLT
D
R27
C17
C08
05C
105K
3PA
CT
U1u
F
25V
100Kohm
RK73H1JL1003F
R18
1N58
19H
W-7
-F
D1
2 1
R23 0603RES_NA
R22 0603RES_NA
R21 0603RES_NA
R20 0603RES_NA
R19 0603RES_NA
Sys
Clk
Hol
ds F
PG
A in
res
et fo
r ap
prox
. 100
ms
Res
et C
ircui
tJT
AG
Con
nect
or
Clo
ck C
ircui
tIG
LOO
FP
GA
Load
with
firm
war
e 18
6-01
22
Pla
ce z
ero
ohm
jum
pers
in p
rope
r po
sitio
ns fo
r W
ID[4
:0]
to in
dica
te P
CB
SN
in b
inar
y.
Ser
ial N
umbe
r D
etec
tF
LAS
H M
emor
y
AT
25D
F64
1-M
WH
-Y
U12
98 2 4
13765
FL_
CS
_LF
L_W
P_L
FL_
Hol
d_L
FL_
SI_
H
FL_
SO
_H
TestPort(7)TestPort(6)TestPort(5)
TestPort(4)TestPort(3)
TestPort(2)
TestPort(1)
TestPort(0)
FL_
SI_
H
FL_
Hol
d_L
FL_
SO
_H
FL_
WP
_L
FL_
CS
_L
R47
100o
hm
R48
100o
hm
R50
100o
hm
R46
100o
hm
R49
100o
hm
FL_
Sck
FL_
SO
_H
FL_
SI_
H
FL_
WP
_L
FL_
Hol
d_L
FL_
CS
_L
FL_
Sck
0.1u
FC
0603
C10
4K3R
AC
TU
C26
R30 100ohm100ohmR29
R28 100ohm
100ohmR31
HK_ADC_DIn_H HK_ADC_DIn_H
HK_ADC_DClk HK_ADC_DClk
HK_ADC_Shdn_L HK_ADC_Shdn_L
HK_ADC_CS_L HK_ADC_CS_L
100ohmR34
R32 100ohm
100ohmR36
R33 100ohm
HK
_DO
ut_H
HK
_DO
ut_H
HK
_Bus
y_H
HK
_Bus
y_H
FL_
Sck
FL_
Sck
2.2u
F
C35
C16
C12
06C
225K
5RA
CT
U
2.2u
F50
V
C27
0.1u
F25
V0.
1uF
C06
03C
104K
3RA
CT
U
C21
C12
5
C04
02C
103K
3RA
CT
U
0.01
uF0.
01uF
C12
4C
123
0.01
uF25
V0.
01uF
C13
4
C25
C06
03C
104K
3RA
CT
U
0.1u
F0.
1uF
C32
0.1u
F
C11
2C
113
0.1u
F0.
1uF
C19
C33
0.1u
F
C24
0.1u
F0.
1uF
C30
C20
0.1u
F25
V
C11
5
C04
02C
103K
3RA
CT
U
0.01
uF0.
01uF
C11
4C
144
0.01
uF0.
01uF
C14
3C
139
0.01
uF0.
01uF
C12
2C
141
0.01
uF0.
01uF
C14
2C
117
0.01
uF25
V
0.00
1uF
C04
02C
102K
3RA
CT
U
C13
7C
136
0.00
1uF
C14
0
0.00
1uF
0.00
1uF
C13
8
0.00
1uF
C12
0C
118
0.00
1uF
C12
1
0.00
1uF
0.00
1uF
C11
9
0.00
1uF
C11
6C
132
0.00
1uF
C12
6
0.00
1uF
25V
C13
3
C04
02C
102K
3RA
CT
U
0.00
1uF
0.00
1uF
C13
5
0.00
1uF
C13
1C
128
0.00
1uF
C12
7
0.00
1uF
25V
0.00
1uF
C13
0
R25
100o
hm
100o
hmR
24S
SI_
Ena
ble_
LS
SI_
Ena
ble_
L
SS
I_E
nabl
e_H
SS
I_E
nabl
e_H
TM
_Fra
me_
H
TM
_Wor
d_H
UA
RT
_Pay
_TX
_H
UA
RT
_GS
E_T
X_H
UA
RT
_Inv
alid
_L
UA
RT
_GS
E_T
X_H
UA
RT
_Inv
alid
_L
TM
_MF
ram
e_H
TM
_Ena
ble_
H
TM
_Gtd
_Ck
TM
_Loa
d_L
R26
100o
hmT
M_D
ata_
HT
M_D
ata_
H
TM
_Ena
ble_
H
TM
_MF
ram
e_H
TM
_Fra
me_
H
TM
_Wor
d_H
TM
_Gtd
_Ck
TM
_Loa
d_L
U6
NC
7WP
14P
6X
5 6 4231
AR
st_L
AS
SP
SIP
Mai
n In
stru
men
t Sch
emat
ics
SIP
_DD
S_S
ync_
Clk
SIP
_DD
S_S
ync_
Clk
SIP
_DD
S_S
CK
SIP
_DD
S_C
S_L
SIP
_DD
S_I
O_U
pdat
e
SIP
_DD
S_R
eset
_L
SIP
_DD
S_P
WR
_DW
N
100o
hmR
53S
IP_D
DS
_SC
K
100o
hmR
54
100o
hmR
55
100o
hmR
51
100o
hmR
52S
IP_D
DS
_PW
R_D
WN
SIP
_DD
S_R
eset
_L
SIP
_DD
S_I
O_U
pdat
e
SIP
_DD
S_C
S_L
6-C2
6-C2
1-C
2
1-D
3
1-A
3
3-B
1
3-B
1
3-C4
3-C43-C4
3-C4
100o
hmR
5610
0ohm
R57
100o
hmR
58
100ohm R59
B4
SIP_DDS_P(0)
SIP_RFIV_Ctrl
SIP_ADC_SDI
SIP_ADC_SCKSIP_ADC_CNV
100ohm R35
100ohm R42
100ohm R40100ohm R38 SIP_ADC_CNV
SIP_ADC_SCK
SIP_ADC_SDI
SIP_RFIV_Ctrl
SIP_ADC_SDO SIP_ADC_SDO
R13
806
03R
ES
_NA
100o
hmR
79
PayID[4]PayID[3]PayID[2]PayID[1]PayID[0]
Pla
ce 1
k on
R??
? fo
r fli
ght
3-B
1
B4
B4
B4
B4
B4
A2
A2 A2
A2
A2
A2
3-B
1
3-B
1
3-B
2
6-C2
6-B
4
1-C
2
1-C
2
1-D
2
1-A
3
1-A
3
1-A
3
1-C
3
3-D1
6-C2
6-B
4
1-C
3
6
186-
0140
186-
0140
-
AS
SP
W. C
ox
FP
GA
DG
ND
+3.3
VD
C18
C06
03C
104K
3RA
CT
U0.
1uF
25V
25V
0.1u
FC
0603
C10
4K3R
AC
TU
C23
DG
ND
+3.3
VD
10 M
Hz
Fre
quen
cy C
lock
UA
RT
_Pay
_TX
_H
R39 100ohm
R41
100o
hm
R43
100o
hm
R45
100o
hm
C14
9C
0603
C10
4K3R
AC
TU
0.1u
F
25V
DG
ND
+3.3
VD
SIP
_DD
S_S
DO
(1)
SIP
_DD
S_S
DO
(0)
SIP
_DD
S_S
DO
(2)
SIP_DDS_SDO(3)
SIP_DDS_P(0)
SIP
_DD
S_P
(2)
SIP
_DD
S_P
(3)
SIP
_DD
S_P
(1)
HkAddr(2)
HkAddr(1)HkAddr(0)
HkAddr(3)
TestPort(0)
TestPort(1)
TestPort(2)
TestPort(3)TestPort(4)
TestPort(5)TestPort(6)TestPort(7)
3-B
1
3-B
1
3-B
1
3-B
1
1-C
1
3-B
1
6-B
16-
B1
1-C
41-
C4
3-B
1
3-B
1
3-B
1
6-B
16-
B1
1-C
41-
C4
1-C
41-
C4
1-C
41-
C4
186-
0317
77
NE
XT
AS
SY
. TIT
LE
NE
XT
AS
SE
MB
LY
PR
OG
RA
M
EN
GIN
EE
R
LAS
T M
OD
IFIE
D
SC
H R
EV
DR
AW
ING
NU
MB
ER
INS
TA
NC
E N
AM
E
SC
HE
MA
TIC
NA
ME
TIT
LE
For
m N
umbe
r Q
F04
42
Rev
-
(B L
ands
cape
)
43
21
A B C D
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
Nor
th L
ogan
, Uta
h 84
341
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
INF
OR
MA
TIO
N T
HA
T IS
PR
OP
RIE
TA
RY
TO
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
(S
DL)
. R
EF
ER
EN
CE
US
UR
F B
P 4
09.1
A B C D
43
21
PA
GE
NA
ME
308
/12/
2013
AS
SP
W. C
ox18
6-00
10
C97
0.1u
F
50V
C93
0.1u
F
50V
C91
0.1u
F
50V
C88
0.1u
F
50V
C83
C08
05C
104K
5RA
CT
U
0.1u
F
50V
AG
ND
+1.8
VA
AG
ND
+1.8
VA
C10
40.
1uF
50V
C92
0.1u
F
50V
C94
0.1u
F
50V
C98
0.1u
F
50V
C10
2C
0805
C10
4K5R
AC
TU
0.1u
F
50V
C89
0.1u
F
50V
C10
30.
1uF
50V
C85
0.1u
F
50V
C10
50.
1uF
50V
C99
0.1u
F
50V
AG
ND
+1.8
VA
C10
00.
1uF
50V
C10
60.
1uF
50V
DG
ND
C82
0.1u
F
50V
+3.3
VD
DG
ND
+3.3
VD C
159
0.1u
F
50V
25V0.01
uF
C04
02C
103K
3RA
CT
U
C16
0
+1.8
VA
R14
8
RK
73H
1JL2
4R9F
24.9
ohm
VR
FV
RF
VR
F_N
VR
F_N
VLO
VLO
_N
VLO
VLO
_N
+1.8
VA
+3.3
VD
C16
20.
001u
F
50V
C16
3
C08
05C
102J
5RA
CT
U
0.00
1uF
DG
ND
Y1
4 3 21
E/D
GN
D
OU
TP
UT
VD
D
CW
X81
3-06
4.0M
R14
5R
K73
H1J
L150
1F
R14
6
RK
73H
1JL1
501F
DG
ND
U17
2
31+ P
AD
-
AD
590J
F
AG
ND
HK
_Tem
pSen
sor_
SIP
See
CW
X8
serie
s da
tash
eet f
or
deco
uplin
g ca
paci
tor
reco
mm
ende
d ro
utin
g an
d po
sitio
ning
.
U23
57
3937 38343228
40 41 42 43
5 7 11 15 19 21 26 29 30 33 35
24 23 22
36
27
31 54 2
1
6 10 12 16 18 20 25
56443 41749 46
1413
5150 52
98
53 47485545D
VD
D1
DV
DD
2
SC
LK
CS
SD
IO_3
CH
0_O
UT
CH
0_O
UT
SD
IO_2
SD
IO_0
SD
IO_1
CH
1_O
UT
CH
1_O
UT
I/O_U
PD
AT
E
DV
DD
_I/O
DA
C_R
SE
T
PW
R_D
WN
_CT
L
MA
ST
ER
_RE
SE
T
DG
ND
1
DG
ND
2
AG
ND
7
AG
ND
6
AG
ND
5
AG
ND
4
AG
ND
3
AG
ND
2
AG
ND
1
SY
NC
_IN
SY
NC
_OU
T
SY
NC
_CLK
AV
DD
10
LOO
P_F
ILT
ER
AV
DD
13
RE
F_C
LK
RE
F_C
LK
CLK
_MO
DE
_SE
L
AV
DD
12
AV
DD
11
AV
DD
9
AV
DD
8
AV
DD
7
AV
DD
6
AV
DD
5
AV
DD
4
AV
DD
3
AV
DD
2
AV
DD
1
P3
P2
P1
P0
NC
1
NC
2
NC
3
NC
4
AV
DD
14
AV
DD
15
EP
AD
9958
BC
PZ
AG
ND
+1.8
VA
+3.3
VD
AG
ND
AG
ND
+1.8
VA
VR
F_N
VR
FV
RF
_NV
RF
VLO
_NV
LOV
LO_N
VLO
C17
0
220p
F50
V
C17
21u
F
AG
ND
C16
9
220p
F50
V
C90
270p
F
VR
Ffil
t
50V
120p
F
C17
7
50V
82pF
C18
3
50V
270p
F
C17
4
AG
ND
+5V
A
AG
ND
AG
ND
SIP
_AD
C_I
n_N
SIP
_AD
C_I
n_P
SIP
_AD
C_I
n_P
SIP
_AD
C_I
n_N
C54
1uF25
V
AG
ND
C16
4
47pF
C16
506
035A
470J
AT
2A47
pF50
V
DG
ND
HK
_Tem
pSen
sor_
SIP
U14
2 110 7 568943
IN+
IN-
SD
I
SC
K
CN
VG
ND
SD
O
VIO
RE
F
VD
D
AD
7687
BR
MZ
SIP
_AD
C_I
n_P
SIP
_AD
C_I
n_N
SIP
_AD
C_S
DI
SIP
_AD
C_S
CK
SIP
_AD
C_C
NV
AG
ND
+3.3
VD
+5V
A
SIP
_AD
C_S
DI
SIP
_AD
C_S
CK
SIP
_AD
C_C
NV
SIP
_AD
C_S
DO
SIP
_DD
S_S
CK
SIP
_DD
S_S
CK
SIP
_DD
S_R
eset
_LS
IP_D
DS
_Res
et_L
SIP
_DD
S_P
WR
_DW
NS
IP_D
DS
_PW
R_D
WN
SIP
_DD
S_I
O_U
pdat
eS
IP_D
DS
_IO
_Upd
ate
SIP
_DD
S_C
S_L
SIP
_DD
S_C
S_L
SIP
_DD
S_S
ync_
Clk
DG
ND
+3.3
VD 50
V0.
1uF
C44
50V
0.1u
FC
55
+5V
A
AG
ND
U24
16 17 18 20 2 4 13
14 76101131915851291V
P1
VP
2
VP
3
VN
1
VN
2
VN
3
AP
AN
LOP
LON
RF
P
RF
N
BIA
S
GN
D2
GN
D1
IFN
IFP
CO
M
VF
B
OU
T
AD
831A
PZ
AG
ND
AG
ND
VR
Fde
t
+5V
A
-5V
A
AG
ND
+5V
A +5V
A
DG
ND
+5V
A-5
VA
50V
0.1u
FC
179
50V
0.1u
FC
178
50V
0.1u
FC
184
50V
0.1u
FC
181
50V
0.1u
FC
185
50V
0.1u
FC
173
AG
ND
AG
ND
SIP
_AD
C_I
n_P
SIP
_AD
C_I
n_N
+3.3
VA
RF
IV_C
trl_
Buf
SIP
_RF
IV_C
trl
SIP
_RF
IV_C
trl
C52
0.1u
F
50V
+5V
A
+5V
A
AG
ND
AG
ND
+5V
A
AG
ND
C17
50.
1uF
50V
+5V
A
AG
ND
C18
00.
1uF
50V
L1
MLF
1005
LR47
K
470n
HL3 MLF
1005
DR
33K
T
330n
HL5
MLG
1005
SR
36J
360n
H
L2
MLF
1005
LR47
K
470n
HL4 MLF
1005
DR
33K
T
330n
HL6
MLG
1005
SR
36J
360n
H
+3.3
VA
AG
ND
+1.8
VA
AG
ND
186-
0140
SIP
_DD
S_P
(3)
SIP
_DD
S_P
(2)
SIP
_DD
S_P
(1)
SIP
_DD
S_P
(0)
Ref
Clk
Ref
Clk
_N
Ref
Clk
Ref
Clk
_N
Ref
Clk
Ref
Clk
_NR
efC
lk_N
Ref
Clk
Ref
Clk
Ref
Clk
_NR
efC
lkR
efC
lk_N
VR
Ffil
t_N
VR
Fde
t_N
AG
ND
+5V
A
+3.3
VA
-5V
A
J1 54
32
1
1053
378-
1
J2 54
32
1 1053
378-
1
J1
J2
JSI3
R14
9R
K73
H1J
L49R
9F49
.9oh
m
R15
0R
K73
H1J
L49R
9F49
.9oh
m
R14
7R
K73
H1J
L49R
9F
49.9
ohm
R15
2R
K73
H1J
L49R
9F
49.9
ohm
R15
1R
K73
H1J
L49R
9F49
.9oh
m
R12
606
03R
ES
_NA
C17
1
24pF
25V
C18
2
180p
F50
V
C17
6
2-D
32-
D3
2-D
32-
D3
240p
F10
0V
2-D
3
50V
120p
F
C96
50V
82pF
C86
25V
24pF
C95
B2
B2
B2
B2
B2
50V
B1,
C1
B1,
C1
C1
C1
100V
240p
F
A2
A2
C4
Iout
= 1
8.91
/ R
set
For
Rse
t = 1
.87k
->
Iout
= 1
0.1
mA
Rec
onst
ruct
ion
Filt
er
Out
put:
- 1V
pp (
open
)-
0/8V
pp (
ref.
chan
nel l
oad)
Tel
emet
ry A
DC
Gai
n fr
om R
F to
IF: 2
*pi
(diff
eren
tial)
Det
ecto
r (b
alan
ced
dem
odul
ator
)
Inpu
t: -
Max
: +10
dBm
-
Nom
: +4
dBm
(1V
pp)
Rec
onst
ruct
ion
Filt
er
+1.2
5VA
R13
2R
K73
H1J
L49R
9F
49.9
ohm
R13
1
RK
73H
1JL1
001F
1Koh
m
R12
9R
K73
H1J
L49R
9F
49.9
ohm
1Koh
m
RK
73H
1JL1
001F
R13
0
R12
4
RK
73H
1JL1
871F
1.87
Koh
m
Rec
onst
ruct
ion
Filt
er S
imul
atio
n
C10
9
C06
03C
333J
5RA
CT
U0.
033u
F
50V
50V 0.03
3uF
C06
03C
333J
5RA
CT
U
C10
7
C11
0C
0603
C15
2K5R
AC
TU
0.00
15uF 0.
0015
uF
C06
03C
152K
5RA
CT
UC10
8
9C-6
4.00
0MA
AJ-
Tis
a N
OT
AS
SE
MB
LED
part
.
R12
5R
K73
Z1J
LTD
0ohm
U25
48
132
- +A
DA
4896
-2A
RM
Z
U25
48
756
- +A
DA
4896
-2A
RM
Z
B2
B1,
C1
B1,
C1
6-C
1
180p
F
C84
C87
C4
A4
2-C
4
2-B
4
B4
2-C
4
2-C
4
2-C
42-C
4
Sig
nal G
ener
ator
(D
DS
)
T26
3 2 1
4 5 6654
123
PR
IS
EC
T1-
6T-X
65+T
273 2 1
4 5 6654
123
PR
IS
EC
T1-
6T-X
65+
T28
3 2 1
4 5 6654
123
PR
IS
EC
T1-
6T-X
65+
6S
IP
-
AS
SP
SIP
Mai
n In
stru
men
t Sch
emat
ics
64 M
Hz
Osc
illat
or
R11
610
0ohm
R11
910
0ohm
R11
810
0ohm
R11
710
0ohm
SIP
_DD
S_S
ync_
Clk
SIP
_DD
S_S
DO
(3)
SIP
_DD
S_S
DO
(2)
SIP
_DD
S_S
DO
(1)
R76
100o
hm
R12
010
0ohm
SIP
_DD
S_S
DO
(0)
SIP
_AD
C_S
DO
Digital
Analog
U15
5
6 4 2
31V
CC
A A
GN
D
BVC
CB
DIR
SN
74LV
C1T
45M
DC
KR
EP
+3.3
VD
AG
ND
C48
0.1u
F
50V
+3.3
VD
DG
ND
AG
ND
Y2
12
9C-6
4.00
0MA
AJ-
T
P2
9
1734
352-
1
P2
3
1734
352-
1
P2
1
1734
352-
1
P2
6
1734
352-
1
2-B
4
2-A
4
2-C
4
2-C
4
P2
2
1734
352-
1
P2
8
1734
352-
1
P2
7
1734
352-
1
P2
5
1734
352-
1
P2
4
1734
352-
1
50V
C15
0
10uF
C10
1
10uF
SIP
_DD
S_S
DO
(0)
SIP
_DD
S_S
DO
(1)
SIP
_DD
S_S
DO
(2)
SIP
_DD
S_S
DO
(3)
SIP
_DD
S_P
(0)
SIP
_DD
S_P
(1)
SIP
_DD
S_P
(2)
SIP
_DD
S_P
(3)
2-B
4
2-B
4
2-D
3
2-C
4
AG
ND
AG
ND
DG
ND
R15
9
RK
73Z
2ALT
D
0ohm
RF
PR
FN
$4I8
703
186-
0317
78
NE
XT
AS
SY
. TIT
LE
NE
XT
AS
SE
MB
LY
PR
OG
RA
M
EN
GIN
EE
R
LAS
T M
OD
IFIE
D
SC
H R
EV
DR
AW
ING
NU
MB
ER
INS
TA
NC
E N
AM
E
SC
HE
MA
TIC
NA
ME
TIT
LE
For
m N
umbe
r Q
F04
42
Rev
-
(B L
ands
cape
)
43
21
A B C D
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
Nor
th L
ogan
, Uta
h 84
341
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
INF
OR
MA
TIO
N T
HA
T IS
PR
OP
RIE
TA
RY
TO
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
(S
DL)
. R
EF
ER
EN
CE
US
UR
F B
P 4
09.1
A B C D
43
21
PA
GE
NA
ME
+Vin
CT
RL
-Vin
NC
CO
M
-Vou
t
+Vou
t
AG
ND
AG
ND
IN
FB
CO
MP
RE
F
GN
D
PG
ND
LX
VC
C
The
rmal
Pad
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
AG
ND
AG
ND
+3.3
VD
+1.5
VD
Vin
+
CT
RL
Vin
-V
out-
NC
2
Vou
t+
NC
1
DG
ND
10V
10uF
C12
10C
106J
8NA
CT
U
C36
PS
1
RS
3-24
15D
Z
6 87 5
132
U10
MA
X19
51E
SA
+
91 7
6325
4
8
T15
PV
A
TP
-105
-01-
02T
ES
T P
OIN
T, R
ED
GN
D2 TP
-105
-01-
04T
ES
T P
OIN
T, Y
ELL
OW
T1P
5VD T
P-1
05-0
1-05
TE
ST
PO
INT
, GR
EE
N
VB
US
1 TP
-105
-01-
06
TE
ST
PO
INT
,BLU
E
0ohm
RK
73Z
1JLT
D
R65
R70
RK
73H
1JL1
692F
16.9
Koh
mR72
RK
73H
1JL1
472F
14.7
Koh
m
L7 7440
4300
18
1.8u
H
10V
10uF
C12
10C
106J
8NA
CT
U
C42
C43
C08
05C
221K
4RA
CT
U22
0pF
16V
TE
ST
PO
INT
, GR
EE
NT
P-1
05-0
1-05
T5V
D
R73
RK
73H
1JL5
112F
51.1
Koh
m
+5V
D_I
N
±15V
A S
uppl
y
±5V
A S
uppl
y
Digital
Analog
FP
GA
Cor
e +1
.5V
D S
uppl
y
+5V
D S
uppl
y
+5V
A_I
N
C15
3C
0805
C10
5K3P
AC
TU
1uF
25V
+15V
A_I
N
C15
4
C08
05C
105K
3PA
CT
U
1uF
25V
-15V
A_I
N
+5V
D_I
N
+15V
A_I
N
-15V
A_I
N
+5V
A_I
N
PS
3
RS
3-24
05S
Z
56 8 7132
C41
C06
03C
104K
3RA
CT
U0.
1uF
25V
C38
C06
03C
104K
3RA
CT
U
0.1u
F25
V
+1.8
VA
Sup
ply
IN NC
1
NC
2
SH
DN
GN
D
BY
P
SE
NS
E
OU
T8 6 7 5
4321
LT19
62E
MS
8-1.
8#P
BF
VR
5
25V
1uF
C79
C08
05C
105K
3PA
CT
U10
uF10
V
C80
C12
10C
106J
8NA
CT
U
AG
ND
AG
ND
AG
ND
PS
2
6 87 5
132+V
in
CT
RL
-Vin
NC
CO
M
-Vou
t
+Vou
t
RS
3-24
05D
Z/H
3
AG
ND
25V
1uF
C08
05C
105K
3PA
CT
U
C16
7
AG
ND
25V
1uF
C08
05C
105K
3PA
CT
UC
166
-5V
A
+Vbu
s
+Vbu
s
+Vbu
s
186-
0140
DG
ND
DG
ND
GN
D
VIN T
AB
_OU
T
OU
T
T3P
3VD
TP
-105
-01-
05T
ES
T P
OIN
T, G
RE
EN
C40
C12
10C
106J
8NA
CT
U10
uF
10V
0ohm
RK
73Z
1JLT
D
R68
+3.3
VD
_IN 5-
D2
25V
1uF
C37
C08
05C
105K
3PA
CT
U
C39
C06
03C
104K
3RA
CT
U0.
1uF
25V
+3.3
VD
Sup
ply
3A O
utpu
t
+5V
D_I
N+5
VD
_IN
A2
VR
4
LT10
85C
M-3
.3#P
BF2 4
3 1
+5V
D_I
N
+1.8
VA
TE
ST
PO
INT
, BR
OW
N
TP
-105
-01-
01
T5N
VA
TE
ST
PO
INT
, OR
AN
GE
TP
-105
-01-
03T
1P8V
A
GN
D
GN
D
GN
D
External
Digital
++
C12
9
TA
JD22
6K03
5R22
uF 35V
C14
5
TA
JD22
6K03
5R22
uF
35V
R63 RK
73H
1JL2
0R0F
20oh
m
DG
ND
AG
ND
CG
ND
GN
D
DG
ND
1T
P-1
05-0
1-00
TE
ST
PO
INT
, BLA
CK
TE
ST
PO
INT
, BLA
CK
TP
-105
-01-
00AG
ND
1
TE
ST
PO
INT
, GR
AY
TP
-105
-01-
08CG
ND
1
TE
ST
PO
INT
, BLA
CK
TP
-105
-01-
00GN
D1
R12
308
05R
ES
_NA
R12
2R
K73
Z2A
LTD
0ohm
R12
7R
K73
Z2A
LTD
0ohm
Gro
und
Sta
r
Cha
ssis
Gro
und
Opt
ion
GN
D is
Vbu
s R
etur
nP
lace
all
test
poi
nts
on to
p si
de o
f boa
rd
Opt
ion
to c
onne
ct G
roun
dSta
r to
one
of t
he b
oard
pla
ted
thro
ugh
hole
s
Gro
undS
tar
VIN
DN
C1
GN
D1
GN
D2
DN
C2
VO
UT
AG
ND
AG
ND
AG
ND
VR
1
LT17
90A
IS6-
1.25
6 5 2134
0ohm
RK
73Z
1JLT
D
R90
25V
1uF
C08
05C
105K
3PA
CT
U
C61
+1.2
5VA
Ref
eren
ce
C59
C12
10C
106J
8NA
CT
U10
uF
10V
25V
0.1u
FC
0603
C10
4K3R
AC
TU
C63
+5V
A
+1.2
5VA
R66 RK
73H
1JL2
0R0F
20oh
m
5-C
2
5-A
3
5-B
3
5-C
3
B1
6P
ower
4
186-
0140
-
AS
SP
W. C
ox
AS
SP
SIP
Mai
n In
stru
men
t Sch
emat
ics
R15
4
RK
73Z
2ALT
D
0ohm
0ohm
RK
73Z
2ALT
D
R15
3
0ohm
RK
73Z
2ALT
D
R15
6
R15
5
RK
73Z
2ALT
D
0ohm
0ohm
RK
73Z
2ALT
D
R15
8
R15
7
RK
73Z
2ALT
D
0ohm
T15
NV
A
TP
-105
-01-
02
TE
ST
PO
INT
, RE
D
TE
ST
PO
INT
, BR
OW
N
TP
-105
-01-
01
T5P
VA
+5V
A
+3.3
VA
Sup
ply
VR
6
5
3
4 2
1IN
GN
D
BY
P
SH
DN
OU
T
LT17
61E
S5-
3.3#
TR
MP
BF
+5V
A
C81
0.01
uF25
V25V
0.01
uF
C15
2
+3.3
VA
25V
1uF
C64
C08
05C
105K
3PA
CT
U
AG
ND
10uF
10V
C58
C12
10C
106J
8NA
CT
U
AG
ND
AG
ND
DG
ND
TE
ST
PO
INT
, OR
AN
GE
TP
-105
-01-
03T
3P3V
A
VIN
DN
C1
GN
D1
GN
D2
DN
C2
VO
UT
AG
ND
AG
ND
AG
ND
VR
2
LT17
90A
IS6-
2.5
6 5 2134
T2P
5V
TE
ST
PO
INT
, WH
ITE
TP
-105
-01-
09
C62
C08
05C
105K
3PA
CT
U1u
F
25V
R89
RK
73Z
1JLT
D
0ohm+2
.5V
A R
efer
ence
C65
C06
03C
104K
3RA
CT
U0.
1uF
25V
+5V
A
+2.5
VA
TP
-105
-01-
09T
ES
T P
OIN
T, W
HIT
E
T1P
25V
R12
8R
K73
Z2A
LTD
0ohm
R87
RK
73Z
2ALT
D
0ohm
0ohm
RK
73Z
2ALT
D
R11
5
C15
5
47uF
47uFC15
1
47uFC16
1
C16
8
47uF
08/1
2/20
13
186-
0317
79
NE
XT
AS
SY
. TIT
LE
NE
XT
AS
SE
MB
LY
PR
OG
RA
M
EN
GIN
EE
R
LAS
T M
OD
IFIE
D
SC
H R
EV
DR
AW
ING
NU
MB
ER
INS
TA
NC
E N
AM
E
SC
HE
MA
TIC
NA
ME
TIT
LE
For
m N
umbe
r Q
F04
42
Rev
-
(B L
ands
cape
)
43
21
A B C D
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
Nor
th L
ogan
, Uta
h 84
341
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
INF
OR
MA
TIO
N T
HA
T IS
PR
OP
RIE
TA
RY
TO
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
(S
DL)
. R
EF
ER
EN
CE
US
UR
F B
P 4
09.1
A B C D
43
21
PA
GE
NA
ME
08/1
2/20
135
-IN
+IN
-V
OU
T
+V
-IN
+IN
-V
OU
T
+V
DG
ND
DG
ND
DG
ND
-IN
+IN
-V
OU
T
+V
-IN
+IN
-V
OU
T
+V
DG
ND
DG
ND
DG
ND
-IN
+IN
-V
OU
T
+V
-+
AG
ND
AG
ND
AG
ND
AG
ND
AG
ND
DG
ND
AG
ND
-15V
A
+15V
A
AG
ND
AG
ND
AG
ND
AG
ND
AG
ND
AG
ND
GN
D
GN
DG
ND
-IN
+IN RE
F-V
GA
IN2
GA
IN1
OU
T
+V
LT61
07M
PS
5#T
RM
PB
F
U5
5 1 2
43
R14
RK
73H
1JL4
321F
4.32
Koh
m
+Vbu
s_C
S6-
B1
U9
LT61
07M
PS
5#T
RM
PB
F
5 1 2
4310
0ohm
RK
73H
1JL1
000F
R60
+3.3
VD
_CS
6-B
1
U22
LT61
07M
PS
5#T
RM
PB
F
5 1 2
43
R11
3
RK
73H
1JL1
000F
100o
hm+5
VA
_CS
6-B
1
U8
LT61
07M
PS
5#T
RM
PB
F
5 1 2
43
R37
RK
73H
1JL1
000F
100o
hm+5
VD
_CS
6-B
1
U16
LT61
07M
PS
5#T
RM
PB
F
5 1 2
43
R85
RK
73H
1JL1
000F
100o
hm+1
5VA
_CS
6-B
1
+15V
A_I
N4-
B3
+5V
A_I
N4-
D3
+5V
D_I
N4-
A2
U20A
D86
24A
RU
Z11 4
1412 13
C50
C08
05C
105K
3PA
CT
U1u
F
25V
1uF
25V
C68
C08
05C
105K
3PA
CT
U
4.32
Koh
mR
K73
H1J
L432
1F
R10
4
C70
0.04
7uF
25V
R92
RK
73H
1JL4
021F
4.02
Koh
m
R93
RK
73H
1JL1
001F
1Koh
m
-15V
A_I
N4-
C3
-15V
A_C
S6-
B1
C08
05C
105K
3PA
CT
U
C74
25V
1uF
10K
ohm
RK
73H
1JL1
002F
R10
5
RK
73H
1JL4
992F
R78
49.9
Koh
m
40.2
Koh
mR
K73
H1J
L402
2F
R10
6
R64
10K
ohm
RK
73H
1JL1
002F
40.2
Koh
mR
K73
H1J
L402
2FR62
10K
ohm
R71
RK
73H
1JL1
002F
49.9
Koh
m
RK
73H
1JL4
992F
R69
R77
RK
73H
1JL1
822F
18.2
Koh
m
+Vbu
s_V
6-A
1+1
5VA
_V6-
A1
6-A
1+5
VD
_V6-
A1
+5V
A_V
6-A
1
+3.3
VD
_V6-
A1
R67
RK
73H
1JL1
001F
1Koh
m
Cur
rent
Sen
se
Vbu
s C
urre
nt S
ense
+3.3
VD
Cur
rent
Sen
se
+5V
A C
urre
nt S
ense
+5V
D C
urre
nt S
ense
+15V
A C
urre
nt S
ense
-15V
A C
urre
nt S
ense
G=1
0.09
Vol
tage
Mon
itors
+5V
A V
olta
ge M
onito
r
G=
-0.8
, Vou
t = 4
V
Nom
inal
: Vin
= +
15V
, Vou
t = 4
V
+15V
A V
olta
ge M
onito
rG
= 1
8.2
/ (18
.2 +
50)
= 0
.267
G=
1, V
out =
3.3
V
+3.3
VD
Vol
tage
Mon
itor
+5V
D V
olta
ge M
onito
rG
= 0.
8, V
out =
4V
G =
40k
/(40
k+10
k) =
0.8
G =
10k
/(50
k+10
k) =
0.1
667
G=
0.16
67, V
out =
4V
Vbu
s (+
16V
to 2
4V)
Vol
tage
Mon
itor
G =
4.3
2k /
49.9
= 8
6.4
Isat
@ 1
1.5A
G=+
10 (
whe
n pi
n 5
and
8 ar
e gr
ound
ed)
+Vbu
s_C
S
+3.3
VD
_IN
+5V
A_C
S
+15V
A_C
S -15V
A_C
S-1
5VA
_IN
+5V
A_V
+5V
D_V
+Vbu
s_V
+3.3
VD
_V
+15V
A_V
+3.3
VD
_IN
Vbu
s_In
25V0.1u
FC
0603
C10
4K3R
AC
TU
C76
25V
0.1u
FC
0603
C10
4K3R
AC
TU
C51
C71
C06
03C
104K
3RA
CT
U0.
1uF
25V
Vbu
s_In
R44
WS
LP12
06R
0100
FE
A
10m
ohm R61
WS
LP12
06R
0100
FE
A
10m
ohm
R86
WS
LP12
06R
0100
FE
A
10m
ohm
R88
WS
LP12
06R
0100
FE
A
10m
ohm
R11
4
WS
LP12
06R
0100
FE
A
10m
ohm
U19
LT19
90A
IS8#
PB
F
7 6 8 5 4132
+15V
A
+5V
D
+5V
A
+3.3
VD
+5V
D
+3.3
VD
+15V
A
+15V
A
-15V
A
-15V
A
+15V
A
+5V
A
+5V
A
186-
0140
+Vbu
s
GN
D
AG
ND
- +
AG
ND
R10
8
RK
73H
1JL1
003F
100K
ohm
U20 A
D86
24A
RU
Z114
132
-15V
A_V
-15V
A V
olta
ge M
onito
r
Nom
inal
: Vin
= -
15V
, Vou
t = 3
.87V
G =
3.4
8 / 1
3.48
* -
1 =
-0.
258
R11
1
RK
73H
1JL1
002F
10K
ohm
R10
9R
K73
H1J
L100
2F10
Koh
m
R11
0R
K73
H1J
L348
1F
3.48
Koh
m
R10
7
RK
73H
1JL1
002F
10K
ohm
-15V
A_V
-15V
A
-15V
A-1
5VA
+15V
A+1
5VA
R17
CS
NL2
010F
T5L
00
5moh
m
R13
RK
73H
1JL4
9R9F
49.9
ohm
+Vbu
s
10K
ohm
RK
73H
1JL1
002F
R14
4
10K
ohm
RK
73H
1JL1
002F
R14
3
10K
ohm
RK
73H
1JL1
002F
R82
10K
ohm
RK
73H
1JL1
002F
R11
2
U20
114
756
- +A
D86
24A
RU
Z
C15
6C
0805
C10
5K3P
AC
TU
1uF
25V
AG
ND
1uF
25V
C72
C08
05C
105K
3PA
CT
U
AG
ND
25V
0.1u
FC
0603
C10
4K3R
AC
TU
C75
C67
C06
03C
104K
3RA
CT
U 0.1u
F
25V
+15V
A-1
5VA
+3.3
VD
C29
C08
05C
105K
3PA
CT
U1u
F
25V
DG
ND
+5V
D
C34
C08
05C
105K
3PA
CT
U1u
F
25V
DG
ND
GN
D
C22
C08
05C
105K
3PA
CT
U1u
F
25V
+Vbu
s
G =
10k
/ 10
0 =
100
Isat
@ 5
A
G =
10k
/ 10
0 =
100
Isat
@ 5
A
G =
10k
/ 10
0 =
100
Isat
@ 5
A
4-B
2
1-A
1
AS
SP
SIP
Mai
n In
stru
men
t Sch
emat
ics
6H
K V
olta
ges/
Cur
rent
s
186-
0140
-
AS
SP
W. C
ox
- +
9 108
4 11A
D86
24A
RU
Z
U20
-15V
A
+15V
A
AG
ND
10K
ohm
RK
73H
1JL1
002FR98
40.2
Koh
mR
K73
H1J
L402
2FR97
R94
RK
73H
1JL1
003F
100K
ohm
R95
RK
73H
1JL1
002F
10K
ohm
AG
ND
-5V
A_V
-5V
A_V
-5V
A
+3.3
VA
_V6-
B1
R84
RK
73H
1JL1
001F
1Koh
m
+3.3
VA
Vol
tage
Mon
itor
G=
1, V
out =
3.3
V +3.3
VA
_V
6-B
1+1
.8V
A_V
1Koh
mR
K73
H1J
L100
1F
R12
1
G=
1, V
out =
1.8
V
+1.8
VA
Vol
tage
Mon
itor
+1.8
VA
_V
-5V
A V
olta
ge M
onito
r
+3.3
VA
+1.8
VA
G =
40
/ 50
* -1
= -
0.8
G=
0.8,
Vou
t = 4
V
10K
ohm
RK
73H
1JL1
002F
R96
C28 C04
02C
473J
8NA
CT
U0.
047u
F10V
10V
0.04
7uF
C04
02C
473J
8NA
CT
U
C31
C15 C04
02C
473J
8NA
CT
U0.
047u
F10V
C78 C04
02C
473J
8NA
CT
U0.
047u
F10V
C56 C04
02C
473J
8NA
CT
U0.
047u
F10V
AG
ND
AG
ND
AG
ND
G =
10k
/ 10
0 =
100
Isat
@ 5
A
6-B
118
6-03
17
80
NE
XT
AS
SY
. TIT
LE
NE
XT
AS
SE
MB
LY
PR
OG
RA
M
EN
GIN
EE
R
LAS
T M
OD
IFIE
D
SC
H R
EV
DR
AW
ING
NU
MB
ER
INS
TA
NC
E N
AM
E
SC
HE
MA
TIC
NA
ME
TIT
LE
For
m N
umbe
r Q
F04
42
Rev
-
(B L
ands
cape
)
43
21
A B C D
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
Nor
th L
ogan
, Uta
h 84
341
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
INF
OR
MA
TIO
N T
HA
T IS
PR
OP
RIE
TA
RY
TO
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
(S
DL)
. R
EF
ER
EN
CE
US
UR
F B
P 4
09.1
A B C D
43
21
PA
GE
NA
ME
08/1
2/20
13H
K D
igiti
zatio
n6
186-
0140
6
CH
0
CH
1
CH
2
CH
3
CO
M
VR
EF
DIN
DC
LK
SH
DN
CS
GN
D1
GN
D2
BU
SY
DO
UT
VC
C2
VC
C1
AG
ND
AG
ND
AG
ND
AG
ND
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
A0
A1
A2
A3
EN
GN
D
NC
3
NC
2
NC
1DV-
V+
AG
ND
- +
DG
ND
DG
ND
Digital
Analog
Digital
Analog
Hou
seke
epin
g A
/D
AS
SP
Hou
seke
epin
g A
/D's
AD
S83
43E
B
U18
1 9 12 13 11 101571614865432
10V
10uF
C12
10C
106J
8NA
CT
U
C57
50V
0.1u
FC
0805
C10
4K5R
AC
TU
C53
HK
_AD
C_C
S_L
HK
_AD
C_S
hdn_
LH
K_A
DC
_DC
lkH
K_A
DC
_DIn
_H
C08
05C
104K
5RA
CT
U0.
1uF
50V
C60
HK
_AD
C_D
In_H
2-A
4H
K_A
DC
_DC
lk2-
A3
HK
_AD
C_S
hdn_
L2-
A4
HK
_AD
C_C
S_L
2-A
3
C14
7
50V
0.1u
FC
0805
C10
4K5R
AC
TU
C14
8
50V
0.1u
FC
0805
C10
4K5R
AC
TU
25V
1uF
C45
25V
1uFC
46
U11
DG
406E
UI+
1 27 28 2 3 13 12181415161745678910112625242322212019
+Vbu
s_V
5-A
1+V
bus_
V
AD
8624
AR
UZ
U21
114
8109
HK
_DO
ut_H
2-B
4H
K_B
usy_
H2-
B4
RK
73H
1JL1
000F
R75
100o
hm10
0ohm
R74
RK
73H
1JL1
000F
HK
_DO
ut_H
HK
_Bus
y_H
4.64
ohm
RK
73H
1J4R
64F
R83
+Vbu
s_C
S5-
B3
+Vbu
s_C
S
HkA
ddr(
3)H
kAdd
r(2)
HkA
ddr(
1)H
kAdd
r(0)
AG
ND
AG
ND
5-A
1+1
5VA
_V+1
5VA
_V
5-B
1+5
VD
_V+5
VD
_V
5-C
1+3
.3V
D_V
+3.3
VD
_V
5-B
2-1
5VA
_V-1
5VA
_V
5-C
1+5
VA
_V+5
VA
_V
5-B
4-1
5VA
_CS
5-D
3+3
.3V
D_C
S+3
.3V
D_C
S5-
C3
+5V
D_C
S+5
VD
_CS
5-C
4+5
VA
_CS
U21
114
141213
- +A
D86
24A
RU
Z
R10
1R
K73
H1J
L432
1F
4.32
Koh
m
+15V
A_C
S+1
5VA
_CS
-15V
A_C
S+5
VA
_CS
+15V
A
-15V
A
+15V
A-1
5VA
-15V
A
+15V
A
-15V
A
+2.5
VA
+5V
A
+3.3
VD
+3.3
VD
AG
ND
HK
_Tem
pSen
sor_
SIP
HK
_Tem
pSen
sor_
SIP
R10
0
RK
73H
1JL1
001F
1Koh
mR
99
RK
73H
1JL2
551F
2.55
Koh
m
R10
3
RK
73H
1JL1
002F
10K
ohm
AG
ND
R10
2R
K73
H1J
L100
4F
1ME
Goh
m AG
ND RK
73H
1JL1
002F
R91
10K
ohm
C04
02C
473J
8NA
CT
U
C69
U13
1 2 3 54678
VC
CB
B1
B2
GN
DD
IRA2
A1
VC
CA
SN
74LV
C2T
45D
CU
R
+15V
A
AG
ND
D3
RB
876W
2
1
3
AG
ND
D2
RB
876W
2
1
3
+5V
A
+5V
A
100o
hmR
80
100o
hmR
K73
H1J
L100
0F
R81
+5V
D
DG
ND
25V
0.01
uF
C49
DG
ND
25V
0.01
uF
C47+3
.3V
D
+5V
D
AG
ND
+15V
A-1
5VA
C08
05C
104K
5RA
CT
U0.
1uF
50V
C15
8C
0805
C10
4K5R
AC
TU
0.1u
F50
V
C15
7
C73
1uF
25V
C77
1uF25
V
AG
ND
AG
ND
3-C
4
5-A
4
AS
SP
SIP
Mai
n In
stru
men
t Sch
emat
ics
186-
0140
-W
. Cox
- +
- +2 3
1
4 11A
D86
24A
RU
Z
U21
6 57
4 11A
D86
24A
RU
Z
U21
+15V
A
-15V
A
+15V
A
-15V
AA
GN
DA
GN
D
-5V
A_V
+3.3
VA
_V+1
.8V
A_V
-5V
A_V
+3.3
VA
_V+1
.8V
A_V
C66
C04
02C
473J
8NA
CT
U0.
047u
F 10V
C08
05C
104K
5RA
CT
U
0.1u
F50
VC
146
DG
ND
Digital
Analog
External
HkA
ddr(
0)H
kAdd
r(1)
HkA
ddr(
2)H
kAdd
r(3)
2-A
32-
A3
2-A
32-
A35-
D2
5-C
15-
D1
186-
0317
81
82
Appendix C
FPGA RTL Diagrams
(14 pages)
83
-X
X-X
XX
X
AS
SP
Ma
in F
unction
al
J. M
art
in-H
idalg
o
To
p L
eve
l SIP
Function
al P
art
itio
n
1
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
SIP
TO
P.V
SD
X
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Main
Paylo
ad T
op L
eve
l
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
11
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
VH
DL F
ILE
= A
SS
P_M
AIN
_T
OP
.VH
D
Command[7:0]
UART_Pay_Tx_H
UART_GSE_Tx_H
UM
BI
NewCoAddCnt[1:0]
Rst_H
ARst_L
AD
99
58
DDS_Reset_L
DDS_PWR_DWN
DDS_SCK
FstClk
RdRcvFIFO_H
RcvFE_H
WrSIPConfig_H
TM
Ad
dr[
3:0
]
DDS_SDO[3:0]
DDS_Sync_Clk
TM_Data_H
Glo
bals
Rst_H
Rst_H
Rst_H
Pay
load
Fir
mw
are
In
str
ucti
on
Se
t
Reset
Pa
ylo
ad
Hex
Co
mm
an
dP
ara
mete
rs (
Big
-en
dia
n)
Set
SIP
Config
ADC_SCK
ADC_CNV
ADC_SDI
ADC_SDO
AD
76
88
Telemetry Signals2
8
TM
Seria
l Deck
TM_Gtd_Ck
TM_Load_L
TM_Enable_H
TM_Word_H
TM_Frame_H
TM_MFrame_H
Fla
sh
FL_SO_H
FL_SI_H
FL_Hold_L
FL_CS_L
FL_Sck
FL_WP_L
Rst_H
FLCommand[15:0]
16
FLWr_H Fla
sh Inte
rfa
ce
Sw
ee
pin
g Im
pedan
ce P
robe
HK_CS_L
HK_DClk
HK_Shdn_L
HK_Busy_H
HK_DIn_H
HK_DOut_H
AD
S83
43
HK
(CH
0)(
CH
1)(
CH
2)(
CH
3) 4
HKaddr[3:0]
TestPort[7:0]
8
Data
Acq
uis
ition S
yste
m C
ontr
olle
r
5
+VPayID[4:0]
PC
B S
/N
UART_UART_Invalid_L
UM
BI U
AR
T Inte
rfa
ce
Syn
chro
no
us S
eri
al I
nte
rface
SSI_Enable_H
SSI_Enable_L
+V
WrG
etT
M_
H
RFIV_Ctrl
DDS_P[3:0]
DDS_CS_L
DDS_IO_UPDATE
0x33
0xA
0F
ixed
Fre
que
ncy
en
ab
le
2-b
it C
DS
ena
ble
2-b
it C
oA
dd
num
ber
of sam
ple
s
32
-bit fix
ed fre
quen
cy
valu
e
Ge
t T
M d
ata
4-b
it C
hun
k ad
dre
ss
0xA
2
Tele
me
try M
atr
ix F
orm
er
DiagnosticData[7:0]
WrDiagnosticsData_H
SysC
lk
Gen
era
tor
SysClk
NewFixedFreq[31:0] 32
NewFixedFreq_H
NewCDSEn[1:0]
2
Paylo
ad C
ontr
olle
r
84
-X
X-X
XX
X
AS
SP
Scie
nce
Boa
rd
J. M
art
in-H
idalg
o
Paylo
ad C
ontr
olle
r
2
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
PA
YL
OA
DC
TR
L.V
SD
X
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
12
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
VH
DL F
ILE
= s
pP
aylo
adC
trl.V
HD
CIState[2:0]
Paylo
ad C
ontr
olle
r C
om
mand
In
terp
rete
r
Next S
tate
& O
utp
ut
De
code
r
Next S
tate
& O
utp
ut
Re
gis
ters
Q
3
WA
IT_
FO
R_C
OM
MA
ND
Cle
arC
md
_H
D
Rst_
H +
AR
st_
L
RcvF
E_H
Yes
No
GE
T_
CO
MM
AN
D
Rd
RcvF
IFO
_H
D
NewCmd_H
RcvFE_H
SysClk
Para
me
ters
_H
No
WA
IT_F
OR
_P
AR
AM
ET
ER
Yes
Ne
wC
md_H
D
UM
BI U
AR
T Inte
rfa
ce
GE
T_P
AR
AM
ET
ER
RcvF
E_H
No
Yes
Rd
RcvF
IFO
_H
D
De
cP
ara
mC
nt_
HD
DecParamCnt_H
RdRcvFIFO_H
Para
me
ters
_H
No
Yes
Parameters_H
UM
BI U
AR
T Inte
rfa
ce
CO
MP
UT
E_P
AR
AM
_C
NT
No
SysClk
Cmd_D1_HNewCmd_H
Para
mC
ntD
one
_H
PA
RA
M_C
NT
_C
OM
PU
TE
D
Yes
ClearCmd_H
Rst_H
ParamCntDone_H
Regis
ter
D Q
Regis
ter
D Q ParamCntDone_H
Reset
Pa
ylo
ad
Co
mm
an
dP
ara
mete
rs
Ge
t T
M d
ata
Set
SIP
Config
4-b
it C
hun
k ad
dre
ss
SIP
Fir
mw
are
In
str
uc
tio
n S
et
Hex
0x33
0xA
0
0xA
2
All
para
me
ters
are
big
endia
n.
Fix
ed
Fre
que
ncy
en
ab
le,
32
-bit v
alu
e
2-b
it C
DS
ena
ble
2-b
it C
oA
dd
num
ber
of sam
ple
s
85
-X
X-X
XX
X
AS
SP
Scie
nce
Boa
rd
J. M
art
in-H
idalg
o
Paylo
ad C
ontr
olle
r
2
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
PA
YL
OA
DC
TR
L.V
SD
X
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
22
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
VH
DL F
ILE
= s
pP
aylo
adC
trl.V
HD
SysClk
4
Decre
men
ter
CN
T
CL
RD
EC
DA
RS
TL
D
Para
mC
nt[
3:0
]
Pap
er
Gate
10
+V
0x0
4
+V
0x1
4
+V
0x6
4
4
NewParamCnt[3:0]
S
Y
els
e2
1 .!=
0D
Para
me
ters
_HDecParamCnt_H
Co
un
ter
is inte
rpre
ted a
s a
n
un
sig
ne
d 4
-bit c
oun
t o
f th
e
nu
mbe
r of
rem
ain
ing p
ara
me
ters
.
Th
e c
oun
t can
be d
ecre
me
nte
d,
an
d d
oes n
ot
roll
over
in e
ith
er
dir
ectio
n.
SysClk
Rst_
H
ARst_L
Rcvd
Cm
d[7
:0]
8
Regis
ter
D Q
AR
ST
RS
TC
ENewCmd_D1_H
Command[7:0]
8
UM
BI U
AR
T Inte
rfa
ce
SysClk
Rst_H
ARst_L
8 8
Parameter1[7:0]
Regis
ter
D Q
AR
ST
RS
T
Rst_H
ARst_L
8 8
Parameter2[7:0]
Regis
ter
D Q
AR
ST
RS
TC
E
Rst_H
ARst_L
8 8
Parameter3[7:0]
Regis
ter
D Q
AR
ST
RS
TC
E
Rst_H
ARst_L
8 8
Parameter4[7:0]
Regis
ter
D Q
AR
ST
RS
TC
E
Rst_H
ARst_L
8 8
Parameter5[7:0]
Regis
ter
D Q
AR
ST
RS
TC
E
Rst_H
ARst_L
8 8
Parameter6[7:0]
Regis
ter
D Q
AR
ST
RS
TC
E
4 .1 DParamCnt[3:0]
4 .2 DParamCnt[3:0]
4 .3 DParamCnt[3:0]
4 .4 DParamCnt[3:0]
4 .5 DParamCnt[3:0]
4 .6 DParamCnt[3:0]
LastParam_H
Command[7:0]
Command[7:0]
Command[7:0]
Command[7:0]
Command[7:0]
Command[7:0]
ARst_L
LdParamCnt_H
Regis
ter
D Q
.
SysClk
LdParamCnt_H
NeedParam_H
.
Rst_
H
LastP
ara
m_
D1
_H
Cle
arC
md
_H
.
8
Parameter2[7:0]
8
Parameter1[7:0]
32
Pap
er
Gate
[15:8
][7
:0]
[31:0
]
NewCoAddCnt[1:0]
2
Pap
er
Gate
[1:0
]
2
Parameter5[1:0]
NewFixedFreq[31:0]
[1:0
]
DA
S C
ontr
olle
r
WrSIPConfig_H
LastParam_D1_H
.
Rst_H
8
Parameter1[7:0]
TM
Ad
dr[
3:0
] TM
Form
er
WrG
etT
M_
H
LastParam_D1_H
.
Rst_H
4
Pap
er
Gate
[3:0
]
[3:0
]
GetTM_H
SIPConfig_H
SetSIPConfig_H
SetSIPConfig_H
8
Parameter4[7:0]
8
Parameter3[7:0]
[31:2
4]
[23:1
5]
Pap
er
Gate
Parameter6[0] NewFixedFreq_H
.33
H
Rst_H
.A
0H
SetSIPConfig_H
.A
2H
GetTM_H
GetTM_H
NewCDSEn[1:0]
2
Pap
er
Gate
[1:0
]
2
Parameter5[3:2] [3:2
]
86
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
Data
Acq
uis
itio
n F
unctio
na
l Pa
rtiti
on
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
DA
SC
TR
L.V
SD
X
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
12
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
AD
S83
43
HK_CS_L
HK_DClk
HK_Shdn_L
HK_Busy_H
HK_DIn_H
HK_DOut_H
DA
S C
on
tro
l B
locks
AD
S83
43_H
K
HK_DOut[15:0]
Rst_H
SFID[4:0]HkAddr[3:0]
Com
bin
ato
rial Lo
gic
Decod
er
Co
mb
inato
rial L
og
ic D
eco
de
r
SF
ID[4
:0]
HkA
dd
r[3
:0]
0x07
0x0
0x08
0x09
0x0
A
0x0
B
0x0
C
0x0
D
0x0
E
0x0
F
0x10
0x11
0x12
0x13
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
HK
Mu
x
SFPulse_H
SysClk
DA
SCtr
l
AD
99
58
DDS_Reset_L
DDS_PWR_DWN
DDS_SCK
DDS_SDO[3:0]
DDS_Sync_Clk
ADC_SCK
ADC_CNV
ADC_SDI
ADC_SDO
AD
76
88
Sw
ee
pin
g Im
pedan
ce P
robe
RFIV_Ctrl
DDS_P[3:0]
DDS_CS_L
DDS_IO_UPDATE
Rst_H
SFPulse_H
SFID[4:0]
SIP4[31:0]
SIP3[31:0]
SIP2[31:0]
SIP1[31:0]
SIP
Ctr
l
NewFixedFreq[31:0]
NewCoAddCnt[1:0]
NewFixedFreq_H
WrSIPConfig_H
MFPulse_H
NewCDSEn[1:0]
SIPSeq[15:0]
87
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
Data
Acq
uis
itio
n F
unctio
na
l Pa
rtiti
on
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
DA
SC
TR
L.V
SD
X
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
22
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
Data
Acqu
isitio
n S
am
ple
Tim
ing D
iagra
m2
31
01
11
21
31
41
51
61
92
02
12
22
32
42
52
72
93
03
13
23
44
56
78
91
17
18
26
28
35
36
33
37
02
31
01
11
21
31
41
51
61
92
02
12
22
32
42
52
72
93
03
13
23
44
56
78
91
17
18
26
28
35
36
33
37
MF
Pu
lse
_H
SF
Puls
e_
H
HK
_D
Out[
15
:0]
14
0 u
s
SIP
Se
q[1
5:0
]
SF
ID[4
:0]
0d
0d
8d
31
d
HK
Ad
dr[
3:0
]
+V
ba
tt
1d
1d
4.4
8m
s
Note
*: du
ring
sw
eep
, co-a
ddin
g is
dis
able
d o
n D
CLP
_H
, D
CLP
_L a
nd
the
FP
P. T
he s
am
ple
d v
alu
es
are
pip
ed
into
a F
IFO
befo
re b
ein
g s
ent o
ut in
th
e T
ele
metr
y m
atr
ix. T
he s
we
eps o
ccu
r every
11
8 m
ajo
r fr
am
es.
SIP
1[3
1:0
]In
-ph
ase v
alu
e fre
quen
cy 0
In-p
hase v
alu
e fre
quen
cy 8
In-p
hase v
alu
e fre
quen
cy 3
1
SIP
1[3
1:0
]Q
uad
ratu
re v
alu
e fre
que
ncy
0Q
uad
ratu
re v
alu
e fre
que
ncy
8Q
uad
ratu
re v
alu
e fre
que
ncy
31
SIP
1[3
1:0
]In
-ph
ase r
efe
rence v
alu
e fre
quen
cy
0In
-ph
ase r
efe
rence v
alu
e fre
quen
cy
8In
-ph
ase r
efe
rence v
alu
e fre
quen
cy
31
SIP
1[3
1:0
]Q
uad
ratu
re r
efe
rence v
alu
e fre
que
ncy
0Q
uad
ratu
re r
efe
rence v
alu
e fre
que
ncy
8Q
uad
ratu
re r
efe
rence v
alu
e fre
que
ncy
31
88
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
SIP
Ctr
l F
un
ctio
nal D
iagra
m
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
SIP
CT
RL
.VS
DX
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
15
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
02
31
01
11
21
31
41
51
61
92
02
12
22
32
42
52
72
93
03
13
23
44
56
78
91
17
18
26
28
35
36
33
10
0ns
10
MH
z3
7
02
31
01
11
21
31
41
51
61
92
02
12
22
32
42
52
72
93
03
13
23
44
56
78
91
17
18
26
28
35
36
33
37
SIP
Hig
h-l
eve
l T
imin
g D
iag
ram
MF
_P
ULS
E
SF
_P
ULS
E
DD
S s
eria
l lin
e
DD
S P
ha
seP
ha
se 0
°
AD
CS
am
ple
4
Pha
se 1
80
°
RF
IV_
CT
RL
Sam
ple
1...
Pha
se 9
0°
t SE
T =
9μ
st S
AM
PL =
9.1
2μ
s
t PH
AS
E =
17
μs
13
6μ
st ID
LE =
4μ
s
If 4
th M
F r
ece
ived
, ch
an
ge
to
firs
t fr
equ
en
cy
Valu
es o
f p
rio
r M
F
Activ
ate
fre
qu
ency i &
Lo
ad
feq
ue
ncy
i+1
Sam
ple
1S
am
ple
2S
am
ple
3
t SE
T =
9μ
st S
AM
PL =
9.1
2μ
s
Pha
se 2
70
°P
ha
se 0
°P
ha
se 1
80
°P
ha
se 9
0°
Pha
se 2
70
°
Sam
ple
4...
...
...
...
...
...
TM
Fo
rmer
valu
es
89
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
SIP
Ctr
l F
un
ctio
nal D
iagra
m
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
SIP
CT
RL
.VS
DX
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
25
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
SIP_CTRL_STATE[4:0]
SIP
_C
TR
L_
FS
M
Next S
tate
& O
utp
ut
Re
gis
ters
Q
5
SYS_CLK
RS
T_
H +
AR
ST
LastPhase_H
PhaseFinished_H
SendInstr_H
No
WR
ITE
_C
ON
F_
WO
RD
Ready_H
SFPulse_H
D S
end
Instr
_H
D In
crC
onfW
ord
Cntr
_H
SmplSettled_H
ConfEnd_H
WA
IT_
CO
NF
_W
OR
D
Yes
Re
ad
y_
H
WA
IT_
FIR
ST
_S
WE
EP
Yes
J F
stM
ode
_H
J In
itSw
ee
p_
H
D S
end
IOU
pda
te_
H
D S
end
Instr
_H
D R
stP
hase
Cn
tr_
H
D R
stP
hase
Dly
_H
AC
Q_
PH
AS
E
Sm
plS
ett
led
_H
D In
itC
nv_
H
No
Yes
Pha
se
Fin
ish
ed
_H
D In
crP
ha
seC
ntr
_H
D R
stP
hase
Dly
_H
LastP
ha
se_
H
No
Yes
No
IDL
E
SF
Pu
lse
_H
No
Yes
D S
end
IOU
pda
te_
H
D S
end
Instr
_H
D R
stP
hase
Cn
tr_
H
D R
stP
hase
Dly
Cn
tr_
H
Co
nfE
nd
_H
No
Yes
MF
Puls
e_
H
Yes
No
Yes
IncrConfWordCntr_H
FstMode_H
SendIOUpdate_H
RstPhaseCntr_H
RstPhaseDly_H
IncrPhaseCntr_H
RstRWAddr_H
IncrRDAddr_H
InitCnv_H
D S
end
IOU
pda
te_
H
Re
ad
y_
HY
es
No
K F
stM
ode
_H
K I
nitS
we
ep
_H
InitSweep_H
MFPulse_H
90
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
SIP
Ctr
l F
un
ctio
nal D
iagra
m
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
SIP
CT
RL
.VS
DX
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
35
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
S
Y
015
109
62
114
1311
128
75
43
Const:00C6------h
40
4
40
ConfWord[39:0]
ConfWordCntr[3:0]
Const:01005120--h
40
Const:02A000----h
40
Const:03C00000--h
40
Const:0404000003h
40
Const:0A00000000h
40
Const:0B80000000h
40
Const:0C40000000h
40
Const:0DC0000000h
40
40
40
40
40
40
40
Const:----------h
40
S
Y
015
109
62
114
131
112
87
54
3
Const:16d
6
4
6
ConfWordNumBits[5:0]
ConfWordCntr[3:0]
66
66
66
66
66
66
66
6
Co
nf
Word
s C
oun
ter
Cn
t
RS
TA
RS
T
ARst_L
4
SysClk
Rst_H
CEIncrConfWordCntr_H
4
ConfWordCntr[3:0]
.8 d ConfEnd_H
Config
ura
tion
:
1.
CS
R:
chan
ne
l 0 e
nab
led
, chan
ne
l 1 e
nab
led
, 4
-bit s
eria
l mo
de
2.
FR
1:
4-c
han
ne
l modu
lation
, R
U/R
D d
isab
led
, S
YN
C_
CLK
dis
ab
led
3.
FR
2:
au
to-c
lear
swee
p a
nd p
hase a
ccum
ula
tor
4.
CF
R:
ph
ase m
odula
tion
5.
CF
TW
0:
1 M
Hz
(first fr
equ
ency)
6.
CW
0:
Pha
se 0
°
7.
CW
1:
Pha
se 1
80
°
8.
CW
2:
Pha
se 9
0°
9.
CW
3:
Pha
se 2
70
°
Const:----------h
Const:----------h
Const:----------h
Const:----------h
Const:----------h
Const:----------h
Const:32d
Const:24d
Const:32d
Const:40d
Const:40d
Const:40d
Const:40d
Const:40d
Const:-d
Const:-d
Const:-d
Const:-d
Const:-d
Const:-d
Const:-d
Co
nfE
nd
_H
40
ConfWord[39:0]
40
Instr[39:0]
6
ConfWordNumBits[5:0]
6
NumBits[5:0]
Const:40d
6
S
Y
01
S
Y
01
FreqData[31:0]
40
Pape
r G
ate
32
8S
Y
01
Fix
edF
req
_H
ROM_Data[31:0] 32
FixedFreq[31:0] 32
Pha
se C
ou
nte
r
Cn
t
RS
TA
RS
T
ARst_L
3
SysClk
CEIncrPhaseCntr_H
3
PhaseCntr[2:0]
.7 d LastPhase_H
.
Rst_H
RstPhaseCntr_H
AR
ST
ARst_L
8
SysClk
PhaseDlyCntr[7:0]
.89
d
SmplSettled_H
.
Rst_H
RstPhaseDlyCntr_H
.16
9d
PhaseFinished_H
88
Pha
se D
ela
y C
ou
nte
r
Cn
t
RS
T
Sett
ling t
ime
: 9 u
s
Pha
se tim
e:
17
0 u
s
Const:04h
AR
ST
16
-Bit M
FID
Co
unte
r
CN
T
CE
AS
ET
ARst_L
16
SIPSeq[15:0]
InitSweep_H
SE
T
+V
0xF
FF
F
Rst_H
SysClk
MFPulse_H
.
Regis
ter
Q
SE
TA
RS
T
ARst_L TMOutputEn_H
RS
T
Rst_H
SysClk
MFPulse_H
.
InitSweep_H
91
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
SIP
Ctr
l F
un
ctio
nal D
iagra
m
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
SIP
CT
RL
.VS
DX
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
45
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
SR
AM
Write
(12
8x19
)
Rea
d (
32
x76
)
WD
RD
WE
NR
EN
RS
T
SysClk
RAM_WD[18:0] 19
WA
DD
R
RAM_WADDR[6:0]
7
RAM_RE_L
RAM_WE_H
ARst_L
RAM_RD[75:0]
RAM_RADDR[4:0]
RA
DD
R
76
5
SysClk
Da
taV
alid_D
1_
H
Da
taV
alid_D
3_
H
SysClk
Regis
ter
D Q
.
Da
taV
alid_
D2_H
Ris
ing
ed
ge
de
tecto
r
Regis
ter
D Q
Regis
ter
D QDataValid_H
RdADCData_H
Re
ad
Add
ress C
ou
nte
r
Cn
t
RS
TA
RS
T
ARst_L
5
SysClk
CE
5
RAM_RADDR[4:0]
Rst_H
Write
Ad
dre
ss C
ou
nte
r
Cn
t
RS
TA
RS
T
ARst_L
7
SysClk
CE
7
RAM_WADDR[6:0]
Rst_H
19
1
18
19
19
Accu
mula
tor
(19
bits)
D Q
Rst
CEWrBufferCE_H
DataOut[17:0]
RAM_WD[31:0]
19
19
Pap
er
Gat
e
[37
:19
][1
8:0
]
[12
7:0
]
19
19
[75
:57
][5
6:3
8]
32
32
32
SIP1[31:0]
32Regis
ter
D Q
SIP2[31:0]
SIP3[31:0]
SIP4[31:0]
RAM_RE_L
Regis
ter
D Q
SysClk
SysClk
S
Y
10
Regis
ter
D Q
CE
SysClk
ComplPhase_H
SysClk1
9
ComplPhase_H
Rst_H
PhaseCntr[2:0]
3
Pape
r G
ate
[2:0
]
2
[2]
[1:0
]
RFIV_Ctrl
DDS_P[3:0]Pape
r G
ate
[3:0
]
[3:2
][1
:0]
2
2
Synchro
niz
er
from
FstC
lk,
de
tectin
g t
he
rise e
dge
fo
r da
ta v
alid
ation
Pha
se c
ounte
r is
de
code
d into
the
pro
file
pin
s a
nd R
FIV
_C
trl t
o s
ele
ct t
he
ap
pro
pia
te c
han
nel a
nd p
hase
.
Th
e C
DS
ca
n b
e c
on
figure
d for
each c
ha
nne
l
(an
tenn
a/r
efe
rence
) in
dep
end
en
tly.
Fo
r de
bug
purp
ose
s on
ly,
by d
efa
ult,
bo
th
chan
ne
ls a
re a
dde
d.
CE
RA
M_
RE
_D
_H
RAM_RE_L
RAM_WE_LR
egis
ter
Q
RS
TA
SE
T
ARst_L RAM_RE_L
SE
T
Rst_H
SysClk
.
..
MFPulse_H
InitSweep_H
TMOutputEn_H
SFPulse_H
Da
taO
ut[
17]
Tw
o’s
com
ple
me
nt
S
Y
10
ComplPhase_H
CDSEn[1]
CDSEn[0]
.
RdADCData_H
WrBufferCE_H
Re
gis
ter
Q
SE
TA
SE
T
ARst_L
SysClk
D
Rst_H
RAM_WE_L
.TMOutputEn_H
SFPulse_H
92
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
SIP
Ctr
l F
un
ctio
nal D
iagra
m
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
SIP
CT
RL
.VS
DX
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
55
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
ADC_SDI
ADC_SCK
ADC_CONV
ADC_SDO
InitCnv_H
CoAddCnt[1:0]
2
DataValid_H
DataOut[17:0]18
AD
CC
trl
DA
SCtr
l
DD
SC
trl
SendInstr_H
Instr[39:0] 40
NumBytes[5:0]
6
DDS_SCK
DDS_SDIO[3:0]
4
DA
SCtr
lReady_H
32
ROM_Data[31:0]
7
ROM_Addr[7:0]
AB
(A+
B) Fre
qR
OM
Const:01h
7
RAM_WADDR[7:0]
SendIOUpdate_H
2-B
it S
hift
Re
gis
ter
SO
UT
LD
SysClk
ARst_L
AR
st
2
LD
_D
AT
AS
IN
+V DDS_IO_UPDATE
DA
SC
trlP
uls
e g
ene
rato
r
to a
llow
syn
chro
niz
ation
for
SysC
lk
DDS_PWR_DWN
DA
SC
trl
DDS_CS_L
DDS_Reset_L.
Arst_L
Rst_H
NewCoAddCnt[1:0]
NewFixedFreq_H
WrS
IPC
onfig
_H
SysClk
NewFixedFreq[31:0]
23
2
Regis
ter
D Q
AS
et
CE
Regis
ter
D Q
AR
st
CE
Regis
ter
D Q
AR
st
CE
Regis
ter
D Q
AS
et
CE
ARst_L
NewCDSEn[1:0]
2
DA
SCtr
l
CoAddCnt[1:0]
FixedFreq_H
FixedFreq[31:0]
23
2
CDSEn[1:0]
2
ARst_L
ARst_L
ARst_L
93
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
SIP
DD
S S
eri
al I/
F F
un
ctio
nal D
iagra
m
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
DD
SC
TR
L.V
SD
X
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
12
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
02
31
01
11
21
31
41
51
61
92
02
12
22
32
42
52
72
93
03
13
23
44
56
78
91
17
18
26
28
35
36
33
10
0ns
10
MH
z3
7
02
31
01
11
21
31
41
51
61
92
02
12
22
32
42
52
72
93
03
13
23
44
56
78
91
17
18
26
28
35
36
33
37
DD
S S
eri
al In
terf
ace D
eta
iled
Tim
ing D
iagra
m
Sen
dIn
str
_H
Instr
[39
:0]
SysC
lk
Num
Bits[5
:0]
Instr
Le
ft[3
9:0
]
Num
BitsL
eft
[5:0
]
DD
S_
SC
K
Data
N
Data
NN
-1
Data
[38
:0]
0 0
FstM
ode
_H
DD
S_
SD
IO0
Data
[39
]D
ata
[2]
Data
[1:0
]
2
Data
[0]
1
Data
[1]
BitsL
eft
_H
RegC
E_
D_
H
0 0
Data
[0]
Data
N
Data
NN
-4
Data
[35
:0]
0D
ata
[39
:36
]D
ata
[11
:8]
Data
[7:0
]
8
Data
[3:0
]
4
Data
[7:4
]
0 0
Data
[3:0
]0
Read
y_
H
RegC
E_
H
94
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
SIP
DD
S S
eri
al I/
F F
un
ctio
nal D
iagra
m
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
DD
SC
TR
L.V
SD
X
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
22
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
40
-Bit S
hift
Re
gis
ter
Q
LD
Da
taIn
Load_H
SysClk
ARst_L
AR
st
Instr[39:0]
40
InstrLeft[39:0]
SendInstr_H
SH
4/1
FstMode_H
Bits
Le
ft C
oun
ter
Q
LD
Da
taIn
Load_H
SysClk
ARst_L
AR
st
NumBits[5:0]
DE
C4/1
FstMode_H NumBitsLeft[5:0] AB
(A>
B)
4
InstrLeft[39]
4
InstrLeft[39:36]
FstM
ode
_H
AR
st
ARst_L
4
S
Y
01
SysClk
BitsLeft_H
Regis
ter
D Q
SysClk
RegCE_D_H CE
RegCE_D_H CE
.
Re
gC
E_
H
RegCE_H
DDS_SCK
Instr[39:0] 40
NumBits[5:0]
6
DDS_SCK
DDS_SDIO[3:0]
4
4
DDS_SDIO[3:0]
Q
CE
D
Regis
ter
D
Q
SysClk
Ready_H
Ready_H
DA
SC
trl
3
NextSDIO[3:0]
Rst_H
SendInstr_H
BitsLe
ft c
oun
ter
is a
n u
nsig
ed
decre
me
nte
r.
It d
oe
s n
ot u
nde
rflo
w
Rst_H Set
AS
et
AR
st
ARst_L
Sen
dIn
str
_D
_H
SysClk
Regis
ter
D Q
.R
isin
g e
dge
de
tecto
r
Load_H
SendInstr_H
Regis
ter
D Q
SysClk
RegCE_D_H
95
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
SIP
AD
C F
unctio
na
l Dia
gra
m
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
AD
CC
TR
L.V
SD
X
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
12
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
3
D14
D2
1d
1d
2d
02
31
01
11
21
31
41
51
61
92
02
12
22
32
42
52
72
93
03
13
23
44
56
78
91
17
18
26
28
35
36
33
20
ns
50
MH
z3
7
02
31
01
11
21
31
41
51
61
92
02
12
22
32
42
52
72
93
03
13
23
44
56
78
91
17
18
26
28
35
36
33
37
AD
C_
SC
K
Mrs
Mn
tCnt[
3:0
]0
d
AD
C_
SD
O
Data
Acqu
isitio
n D
eta
iled T
imin
g D
iag
ram
(A
/D)
AD
C_
CN
V
D15
D14
80
d
Dout[
15
:0]
MS
RM
T1
0
EnA
DC
lk_
H
82
d83
d84
d85
d81
d
12
t CY
C =
2.2
6μ
s
86
d87
d11
0d
11
1d
11
2d
11
3d
11
4d
0d
11
3d
11
4d
2d
2d
1d
11
4d
0d
0d
0d
11
3d
0d
0d
0d
0d
0d
0d
0d
IncM
srm
nt2
_H
Mrs
Mn
t2C
nt[
6:0
]0
1
idle
D1
D0
0d
InitC
nv_
syn
c
tco
nv =
1.6
µs
15
16
D15
D1
La
stM
srm
nt_
H
2
16
MS
RM
T3 3
Data
Valid
_H
16
MS
RM
T4
t PU
LS
E =
30
0ns
t AC
Q =
0.6
6μ
s
0
t SM
PL =
9.1
2μ
s
96
-X
X-X
XX
X
AS
SP
Dig
ital D
esig
n
J. M
art
in-H
idalg
o
SIP
AD
C F
unctio
na
l Dia
gra
m
3
AS
SP
DE
SC
RIP
TIO
N
FIL
E N
AM
E
ITE
M
SH
EE
T
SH
T R
EV
TIT
LE
TIT
LE
EN
GIN
EE
R
LA
ST
MO
DIF
IED
SP
AC
E D
YN
AM
ICS
LA
BO
RA
TO
RY
UT
AH
ST
AT
E U
NIV
ER
SIT
Y R
ES
EA
RC
H F
OU
ND
AT
ION
No
rth L
og
an
, U
tah
843
41
PR
OG
RA
M
27
fe
b, 20
14
SP
AD
CC
TR
L.V
SD
X
NE
XT
AS
SY
. XX
-XX
XX
AS
SP
Scie
nce
Firm
ware
DW
G N
O.
76
54
32
1
B A
D C B A
87
65
43
21
8
D C
22
OF
TH
IS D
RA
WIN
G C
ON
TA
INS
IN
FO
RM
AT
ION
TH
AT
IS P
RO
PR
IET
AR
Y T
O S
PA
CE
DY
NA
MIC
S L
AB
OR
AT
OR
Y (
SD
L).
RE
FER
EN
CE
USU
RF B
P409.
1
Form
No. Q
F042
3 R
ev
A
16
-Bit S
hift
Re
gis
ter
Q
CE
Da
taIn
Regis
ter
D Q
FstClk
InitCnv_H
Regis
ter
D Q InitCnv_Sync_H
7-B
it F
irst
Sta
ge
Mea
sure
me
nt
Cou
nte
rC
nt
RS
T
Regis
ter
D Q.11
3dM
srm
ntC
nt[
7:0
]
Nb
of M
ea
sure
me
nts
Cou
nte
r
Cn
t
CE
LD
AR
ST
2
(Load when CE
is Asserted)
.81
d
ADC_CONV
Regis
ter
Q
AR
ST
IncM
srm
nt2
_H
AR
ST
ARstFst_L
ARstFst_L
7
.1 d SE
TR
ST
77
.11
4d
.82
d
77
7
EnADClk_H
2
.
ARstFst_L
ARstFst_L
IncMsrmnt2_H
IncMsrmnt2_H
RstMsrmntCnt_H
Regis
ter
Q
AR
ST
SE
TR
ST
FstClk
RstMsrmntCnt_H
LD
FstClk
InitCnv_Sync_H
Regis
ter
Q
AR
ST
FstClk
CE
ARstFst_L
D
.
ADC_SCK
. ShfDout_H
. RstMssrmntCnt_H
IncMsrmnt2_H
LastMsrmnt_H
CoAddCnt[1:0]LastMsrmnt_H
ShfDOut_H
FstClk
ARst_L
AR
st
ADC_SDO 18
2
16 A
B
(A+
B)
DataOut[17:0]
DataOut[17:0]
FstClk
18
18
18
Regis
ter
D Q
RS
TC
E
18
InitCnv_Sync_H
Dout[15:0]
DASCtrl
RstMssrmntCnt_H
16
-Bit S
hift
Re
gis
ter
SO
UT
LD
FstClk
ARstFst_L
AR
st
15
LD
_D
AT
AS
IN
+V DataValid_H
DA
SC
trl
ADC_SDI
ADC_SCK
ADC_CONV
+V
DA
SC
trl
ADC_SDO
InitCnv_H
CoAddCnt[1:0]
2
2
Synchro
niz
er
fro
m S
ysC
lk to
FstC
lk
Puls
e g
ene
rato
r
to a
llow
syn
chro
niz
ation
for
SysC
lk
.
Const:01h
Data
sam
ple
d
with
ris
ing e
dge
MsrmntCnt2[1:0]
Regis
ter
D Q
FstClk
ARst_L
Regis
ter
D Q ARstFst_L
Reset
gen
era
tor
for
the
Fst
Clk
do
main
.
Rst_H
ARST ARST
Regis
ter
Q
AR
ST
D
ARstFst_L
IncMsrmnt2_H Regis
ter
Q
AR
ST
DD
out[
15]
Th
e c
oun
ter
is o
nly
ena
ble
d
if it
is
gre
ate
r th
an 0
.
A v
alu
e 0
is id
le s
tate
97
Appendix D
Calibration Loads Characterization
To characterize the calibration loads a commercial VNA (FieldFox 44914A) was used.
The calibrations loads were connected to the VNA by using a base adapter (see Fig. D.1),
which provides an standard SMA connector on the VNA side, and an SMB and ground
connection for the can ground on the load side.
Before measuring the calibration load cans, the VNA is calibrated by using an standard
N-type connectors calibration kit with an SMB to type-N adapter (Pasternak PE9313) as
shown in Fig. D.2. Ideally, the calibration kit should have SMB connectors but these are
very rare. The introduction of the SMB to N-type adapter introduces a phase delay (the
reference plane is located at the adapter output) and could limit the effective directivity
measured [18]. Although the adapter datasheet does not provide electrical information, based
on the results of the calibration kit LOAD, with a return loss of about 70 dB, the directivity
is not limited by it. The electrical length introduced by the adapter was characterized to be
66.8 mm and it needs to be subtracted from all the calibration loads measurements. With
this correction, the measurement at the SMB connector without any load is very similar to
an OPEN.
With this set-up, all the calibration loads were measured. Apart from the instrument
Fig. D.1: Test set-up for the calibration loads characterization.
98
Reference plane
Calibration kitOPENSHORTLOAD
Fig. D.2: Calibration of the VNA with an SMB to N-type adapter and an N-type cal kit.
uncertainty, additional disturbances can be observed in the graphs. At low frequencies, the
VNA shows an abnormal response and what it seems a scale change. There is also observed
a shunt capacitance of about 3 pF that affects the measurement of high impedances, such as
resistors, low value capacitors, and inductors. The shunt capacitance seems to be associated
with the mechanical configuration. Between the measurements of the SMB without any load
and the OPEN load there is about 0.7 pF. The OPEN load has the can configuration and a
PCB without any trace. Even more, with a high resistor value 300 kΩ at high frequencies
it can be observed about 0.7 pF. It can be concluded that the parasitic capacitance of the
mechanical can and the PCB traces affect the measurements, especially for high impedances.
In the next set of figures, the measurement of the pertinent loads and the unloaded
SMB connector are presented. It can be seen that due to the nonlinear relation between the
reflection coefficient and the impedance, when the former is acquired with low uncertainty
the latter has very large uncertainty and vice versa. In the case of the 50 Ω load, shown in
Fig. D.3 and D.4, the impedance uncertainty is minimum. The SHORT load, shown in Fig.
D.5 and D.6, is a very good reflector but the impedance uncertainty is large, especially its
phase. The same happens with high impedances. Additionally, it can be observed that the
OPEN load, shown in Fig. D.7 and D.8, presents a smaller impedance than the unloaded
SMB connector, shown in Fig. D.9 and D.10.
99
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−60
−40
−20
0
Frequency [MHz]
Mag
nit
ud
e[d
B] Measured
UncertaintyNominal
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
0
100
Frequency [MHz]
Ph
ase
[deg
ree]
MeasuredUncertainty
Nominal
Fig. D.3: s1,1 magnitude and phase of the 50 Ω load.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
49
50
51
52
Frequency [MHz]
Mag
nit
ud
e[Ω
] MeasuredUncertainty
Nominal
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
0
1
2
3
Frequency [MHz]
Ph
ase
[deg
ree]
MeasuredUncertainty
Nominal
Fig. D.4: Impedance magnitude and phase of the 50 Ω load.
100
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−0.4
−0.2
0
0.2
0.4
Frequency [MHz]
Mag
nit
ud
e[d
B] Measured
UncertaintyNominal
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−200
−100
0
100
200
Frequency [MHz]
Ph
ase
[deg
ree]
MeasuredUncertainty
Nominal
Fig. D.5: s1,1 magnitude and phase of the SHORT load.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
0
0.5
1
Frequency [MHz]
Mag
nit
ud
e[Ω
] MeasuredUncertainty
Nominal
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−200
0
200
Frequency [MHz]
Ph
ase
[deg
ree]
MeasuredUncertainty
Nominal
Fig. D.6: Impedance magnitude and phase of the SHORT load.
101
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−0.4
−0.2
0
0.2
0.4
Frequency [MHz]
Mag
nit
ud
e[d
B] Measured
UncertaintyNominal
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−2
−1
0
1
2
Frequency [MHz]
Ph
ase
[deg
ree]
MeasuredUncertainty
Nominal
Fig. D.7: s1,1 magnitude and phase of the OPEN load.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
0
1
2
3·105
Frequency [MHz]
Mag
nit
ud
e[Ω
] MeasuredUncertainty
Nominal
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−200
0
200
Frequency [MHz]
Ph
ase
[deg
ree]
MeasuredUncertainty
Nominal
Fig. D.8: Impedance magnitude and phase of the OPEN load.
102
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−0.4
−0.2
0
0.2
0.4
Frequency [MHz]
Mag
nit
ud
e[d
B] Measured
UncertaintyNominal
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−2
−1
0
1
2
Frequency [MHz]
Ph
ase
[deg
ree]
MeasuredUncertainty
Nominal
Fig. D.9: s1,1 magnitude and phase of the unloaded SMB connector.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
0
2
4
6
8
·104
Frequency [MHz]
Mag
nit
ud
e[Ω
] MeasuredUncertainty
Nominal
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
·107
−200
0
200
Frequency [MHz]
Ph
ase
[deg
ree]
MeasuredUncertainty
Nominal
Fig. D.10: Impedance magnitude and phase of the unloaded SMB connector.
103
Appendix E
Ground Support Equipment
Two GSE specific software were developed during the development of the project. The
framework chosen was Labview due to its ease of programming and fast integration with
instruments controlled by GPIB.
E.1 Scalar Network Analyzer
Prior to the acquisition of the commercial VNA, a Scalar Network Analyzer (SNA) was
constructed with a signal generator and a spectrum analyzer controlled from a PC as can
be seen in Fig. E.1. The process followed is the same as with any SNA: both instruments
are initialized with the required parameters (power, IF bandwidth, span, etc.), the signal
generator is set to the minimum frequency, an appropriate settling time is waited and the
measured value by the SA is obtained. Then, the frequency is changed to the next value
and the process starts again. Because of the multiple interaction with the equipments, and
the settling time of the SA, the process requires some minutes to complete for a regular
frequency span and resolution. As indicated in the figure, the signal generators used had
a limited frequency range of operation, and for covering the complete range both of them
were used requiring a manual disconnection and connection for each measurement.
The software interface, shown in Fig. E.2, allows the configuration of the frequency span
(with linear or logarithmic sweep), averaging and exporting the results in Comma-Separated
Value (CSV) format. It is intended to emulate a real SNA interface with the most common
options.
E.2 SIP Ground Support Equipment
When using the SIP board the telemetry must be acquired by a specific GSE with
104
GPIB
Labview Control Software
DUT
Spectrum analyzerHP 8595E
9 kHz – 6.5 GHz
Signal GeneratorHP E4433B
1 MHz – 4 GHz
Signal GeneratorHP 33120A
0.1 mHz – 15 MHz
Fig. E.1: SNA GSE block diagram.
Fig. E.2: SNA GSE software interface.
105
a PCM telemetry module. Because at the time neither the GSE nor the FPGA module
were finished, a specific GSE was developed through the SIP UART. It allows configuring
the FPGA in all the test modes (fixed frequency, CDS disabled, and variable number of
coadded samples) and acquiring the measured values in small chunks. Because of the limited
buffering in the FPGA and UART data rate (115.2 kbps), the complete frequency range
has to be acquired over multiple sweeps. This does not introduce any error as long as the
load is static like in the case of the SIP. In the same manner than in the SNA, the interface
emulates a real VNA, providing real-time impedance values (without calibration) and a
table with raw values for post-processing in more specialized software.
Fig. E.3: SIP GSE software interface.
106
Appendix F
DVD Contents
The DVD attached to this thesis contains the following materials:/
thesis .................................................. LATEXfiles of this thesisfigures............................................Figures used in the thesistables........................Tables used for generating plots with PGFPlots
matlab
analyses
noise...........................................Noise analysis and figuresharmonics ..................................Harmonic analysis and figureslpffilter.........................................Low pass filter analysisaafilter ....................................Reconstruction filter analysisloading............................................Loading effect analysis
calloads................................Calibration Loads tests and analysesfpga.......................................Support files for the FPGA designtransformers................................Transformers tests and analysestests.................................................SIP tests and analyses
labview
sna...................................................SNA Labview softwaregse...............................................SIP GSE Labview software
fpga
Common....................................Common files of the ASSP FPGAsSIP
ActelDesigner.............Place-and-Route project and physical contraintsDocumentation.............................................RTL diagramsSimulation ..............................Simulation models and testbenchSynplify.................................Synthesis project and constraintsVHDL.........................................VHDL source code and cores
pcb.........................................PCB schematics, layout and part list