sequential logic - university of washington · 2014-12-14 · sequential logic autumn 2014 cse390c...
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Sequential logic
! State assignment (encoding state) in state machines " Sequential " One-hot " Output-oriented
! Communicating finite-state machines " Registers " Shift-registers " Counters
Autumn 2014 CSE390C - VII - Finite State Machines 1
Autumn 2014 CSE390C - VII - Finite State Machines 2
Can any sequential system be represented with a state diagram?
! Shift register " input value shown
on transition arcs " output values shown
within state node
100 110
111
011
101 010 000
001
1
1 1 0 1
1
1
1
0 0 0 1
0
0
0 0
D Q D Q D Q IN
OUT1 OUT2 OUT3
CLK
Shift register in Verilog
Autumn 2014 CSE390C - VII - Finite State Machines 3
module shift_register (clk, in, out);
input clk; input in; output [0:3] out;
reg [0:3] out;
initial begin out = 0; // out[0:3] = {0, 0, 0, 0}; end
always @(posedge clk) begin out = {in, out [0:2]}; end
endmodule
Autumn 2014 CSE390C - VII - Finite State Machines 4
Binary counter
! Counter " 3 flip-flops to hold state " Logic to compute next state " Much simpler state diagram -> more complex logic
! Is there a relationship between state diagram and logic needed?
D Q D Q D Q
OUT1 OUT2 OUT3
CLK
"1"
010
100
110
011 001
000
101 111
Binary counter in Verilog
module binary_counter (clk, c8, c4, c2, c1); input clk; output c8, c4, c2, c1;
reg [3:0] count;
initial begin count = 0; end
always @(posedge clk) begin count = count + 4’b0001;
end
assign c8 = count[3]; assign c4 = count[2]; assign c2 = count[1]; assign c1 = count[0];
endmodule
Autumn 2014 CSE390C - VII - Finite State Machines 5
State machine for Lab 5
! Only 4 states " Output = state
Autumn 2014 CSE390C - VII - Finite State Machines 6
010
001
101
00
reset 00
100
01
01
10
10
10
01
01
10
00
00
State assignment in Lab 5
! 8 states ! Sequential state assignments
" Number states 0 to 7 – 3 bits " Need logic to translate state
number to outputs ! One-hot
" 8 bits, one is true for each state " Need logic to translate state
number to outputs ! Output-oriented
" Exploit outputs as part of state " Easy translation to output " See previous slide
Autumn 2014 CSE390C - VII - Finite State Machines 7
ALM: adaptive logic module
! The following types of functions can be realized in a single ALM: " Two independent 4-input functions " An independent 5-input function and an independent 3-input function " A 5-input function and a 4-input function, if they share one input " Two 5-input functions, if they share two inputs " An independent 6-input function " Two 6-input functions, if they share four inputs and share function " Some 7-input functions
! An ALM also has 4 bits of memory " We’ll discuss later when we talk about
sequential logic
Autumn 2014 CSE390C - VII - Finite State Machines 8
Registers
! Collections of flip-flops with similar controls and logic " stored values somehow related (for example, form binary value) " share clock, reset, and set lines " similar logic at each stage
! Examples " shift registers " counters
Autumn 2014 CSE390C - VII - Finite State Machines 9
R S R S R S D Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT4
CLK
IN1 IN2 IN3 IN4
R S
"0"
Shift register
! Holds samples of input " store last 4 input values in sequence " 4-bit shift register:
Autumn 2014 CSE390C - VII - Finite State Machines 10
D Q D Q D Q D Q IN
OUT1 OUT2 OUT3 OUT4
CLK
Universal shift register
! Holds 4 values " serial or parallel inputs " serial or parallel outputs " permits shift left or right " shift in new values from left or right
Autumn 2014 CSE390C - VII - Finite State Machines 11
clear sets the register contents and output to 0
s1 and s0 determine the shift function
s0 s1 function 0 0 hold state 0 1 shift right 1 0 shift left 1 1 load new input
left_in left_out
right_out
clear right_in
output
input
s0 s1
clock
Design of universal shift register
! Consider one of the 4 flip-flops " new value at next clock cycle:
Autumn 2014 CSE390C - VII - Finite State Machines 12
Nth cell
D Q
CLK
Q[N-1] (left)
Q[N+1] (right) Input[N]
to N-1th cell
to N+1th cell
clear s0 s1 new value 1 – – 0 0 0 0 output 0 0 1 output value of FF to left (shift right) 0 1 0 output value of FF to right (shift left) 0 1 1 input
s0 and s1 control mux 0 1 2 3
CLEAR
Shift register application
! Parallel-to-serial conversion for serial transmission
Autumn 2014 CSE390C - VII - Finite State Machines 13
parallel inputs
parallel outputs
serial transmission
Pattern recognizer
! Combinational function of input samples " in this case, recognizing the pattern 1001 on the single input
signal
Autumn 2014 CSE390C - VII - Finite State Machines 14
D Q D Q D Q D Q IN
OUT1 OUT2 OUT3 OUT4
CLK
OUT
Counters
! Sequences through a fixed set of patterns " in this case, 1000, 0100, 0010, 0001 " if one of the patterns is its initial state (by loading or set/reset)
Autumn 2014 CSE390C - VII - Finite State Machines 15
D Q D Q D Q D Q IN
OUT1 OUT2 OUT3 OUT4
CLK
Mobius counter
! How does this counter work (assuming it starts in state 0000)?
! Counts through the sequence: " 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
! Known as Mobius (or Johnson) counter
Autumn 2014 CSE390C - VII - Finite State Machines 16
D Q D Q D Q D Q IN
OUT1 OUT2 OUT3 OUT4
CLK
Binary counter
! Logic between registers (not just multiplexer) " XOR decides when bit should be toggled " always for low-order bit,
only when first bit is true for second bit, and so on
Autumn 2014 CSE390C - VII - Finite State Machines 17
D Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT4
CLK
"1"
How fast is our counter?
! Period > TpropFF + TpropCL + TsetupFF
! Period > 3.6ns + max(TpropCL) {over all paths from Qs to Ds} + 1.8ns ! Period > 5.4ns + TpropXOR + TpropAND3 ! Frequency < 1/Period
Autumn 2014 CSE390C - VII - Finite State Machines 18
D Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT4
CLK
"1"
Autumn 2014 CSE390C - VII - Finite State Machines 19
Tug-of-War Game FSM (NOT the same as Lab #6)
! Tug of War game " 7 LEDS, 2 push buttons (LPB, RPB)
LED (3)
LED (2)
LED (1)
LED (0)
LED (6)
LED (5)
LED (4)
RESET
R R
L
R
L
R
L
R
L L
Autumn 2014 CSE390C - VII - Finite State Machines 20
Light Game FSM Verilog module Light_Game (LEDS, LPB, RPB, CLK, RESET);
input LPB ; input RPB ; input CLK ; input RESET;
output [6:0] LEDS ;
reg [6:0] position; reg left; reg right;
always @(posedge CLK) begin left <= LPB; right <= RPB; if (RESET) position <= 7'b0001000; else if ((position == 7'b0000001) || (position == 7'b1000000)) ; else if (L) position <= position << 1; else if (R) position <= position >> 1; end
endmodule
wire L, R; assign L = ~left && LPB; assign R = ~right && RPB; assign LEDS = position;
combinational logic and wires
sequential logic
LPB
left
L
positive edge detector
Do you see a problem with this game?
Activity
! Where is the problem? What is the fix?
Autumn 2014 CSE390C - VII - Finite State Machines 21
always @(posedge CLK) begin left <= LPB; right <= RPB; if (RESET) position <= 7'b0001000; else if ( (position == 7'b0000001) || (position == 7'b1000000) ) position <= position; else if (L) position <= position << 1; else if (R) position <= position >> 1;
end
always @(posedge CLK) begin // no longer biased in favor of L player left <= LPB; right <= RPB; if (RESET) position <= 7'b0001000; else if ( (position == 7'b0000001) || (position == 7'b1000000) ) position <= position; else if (L & ~R) position <= position << 1; // correct error in state diag. else if (R & ~L) position <= position >> 1; // favoring L player else position <= position; // otherwise, just hold
Lab #6
! 2 user-input FSMs for push buttons " One cycle pulse every time a button is pressed
! Tug-of-war game with a separate FSM for each LED (9 of them) " 1 center-light (lights up on reset) " 8 normal-lights (goes dark on reset)
! Victory logic " Input from first and last FSM and two buttons " If left-most light is on and left button pressed, then left wins " Similarly for right " Control HEX0 to display winner: 0 or 1, L or R, etc.
! Consider how a game ends " Do you want both push buttons still working after a player wins?
Autumn 2014 CSE390C - VII - Finite State Machines 22
Input FSM – simple shift register
Autumn 2014 CSE390C - VII - Finite State Machines 23
D Q D Q IN
OUT1 OUT2
CLK
OUT
0 10 11 00
1 0
reset 1
1
01 0 1
0
Autumn 2014 CSE390C - VII - Finite State Machines 24
machines advance in lock step initial inputs/outputs: X = 0, Y = 0
CLK
FSM1
X
FSM2
Y
A A B
C D D
FSM 1 FSM 2
X
Y
Y==1
A [1]
Y==0
B [0]
Y==0
X==1
C [0]
X==0 X==0
D [1]
X==1 X==0
Communicating finite state machines
! One machine's output is another machine's input