sequential circuits 2006 part 2 - facultypeople.ee.duke.edu/~jmorizio/ece261/classlectures/... ·...
TRANSCRIPT
![Page 1: Sequential Circuits 2006 Part 2 - Facultypeople.ee.duke.edu/~jmorizio/ece261/classlectures/... · 2006-07-28 · 3 Flip-flop insensitive to clock overlap V DD V DD M1 M3 M4 M2 M6](https://reader034.vdocuments.us/reader034/viewer/2022042414/5f2e6b986f8c1f069d07ade5/html5/thumbnails/1.jpg)
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Sequential Circuit Design: Part 2
• C2MOS Latch• Two-phase clock generators• Four-phase clocking• Pipelining and NORA-CMOS• TSPC logic
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C2MOS Logic
• Goal: Make circuit operation independent of phase overlap
• No need to worry about careful design of clock phases, clock inversions, etc
• Really ingenious design!
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Flip-flop insensitive to clock overlap
VDDVDD
M1
M3
M4
M2 M6
M8
M7
M5
CL1 CL2
X
C2MOS master-slave negative edge-triggered D flip-flop
Φ
ΦΦ
Φ
D
Φ-section Φ-section
Q
Modes of operation:1) Evaluate (Φ = 1)Φ-section acts as inverterΦ-section is in high-impedance(hold) mode
2) Roles reversed for Φ = 0
• Insensitive to clock overlap as long as clock rise and fall times are “small”
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C2MOS avoids Race ConditionsSignal propagation requires pull-up followed by pull-down, or vice versa
D
1
M1
M3
M2 M6
M7
M5
1
VDDVDD
(1-1) overlap
X
Only pull-down networks are enabled
Q D
VDDVDD
M1
M4
M2 M6
M8
M5
0 0
(0-0) overlap
X
Only pull-up networks are enabled
Q
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C2MOS avoids Race Conditions
Caution: If clock has low rise/fall times, then both pMOS and nMOS may conduct
Typically need rise/fall time at most five times clock propagation delay
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Pipelining
• Common in high-speed designs• Combinational logic (stages) separated by registers• Alternating clock phases typically used• Race may occur if clock phases overlap
F G
Reg
iste
r
Reg
iste
r
Φ1 Φ2
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Pipelined Logic using C2MOS
InF Out
VDD VDD VDD
C2C1
GC3
NORA CMOS
What are the cons traints on F and G?
(NO RAce CMOS)
Φ Φ
Φ
Φ
Φ Φ
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Example
1
VDD VDDVDD
Number o f s tatic invers ions s hould be even
Φ
Φ
Φ
Φ
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NORA CMOS
• Targets implementation of fast, pipelined datapaths using dynamic logic
• Combines C2MOS pipeline registers and np-CMOS dynamic logic functional blocks– Combinational logic can be a mixture of static and dynamic logic– Latch and logic (feeding latch) are clocked in such a way that both
are simultaneously in either evaluation or hold (precharge)– Block in evaluation during Φ=1 is a Φ-module, inverse is a Φ-
module– Φ-modules and Φ-modules alternate
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NORA CMOS ModulesVDD
VDD
PDNIn1In2In3
VDD
PUN Out
Combinational logic Latch
Φ
Φ
Φ
Φ
Φ
Φ
Φ-module
VDD
Out
VDD
PDNIn1In2In3
VDD
In4
In4
VDD
Φ
Φ-module
Φ
Φ
Φ
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NORA Logic ModulesOperation Modes
Φ-block Φ-blockLogic Latch Logic Latch
Φ = 0 Precharge Hold Evaluate EvaluateΦ = 1 Evaluate Evaluate Precharge Hold
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Doubled C2MOS Latches
• Single clock (no inverse clock is needed)
• Requires redesign of C2MOS latch
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VDD VDD
Doubled n-C2MOS latch
VDD VDD
Doubled p-C2MOS latch
ΦΦ ΦΦDQ
DQ
Φ = 1, latch in transparent, evaluate modeΦ = 0, latch in hold mode, only pull-upnetwork activeDual-stage approach: no races
Doubled C2MOS Latches
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Doubled C2MOS Latches: Advantages
• No even-inversion constraints between two latches, or between latch and a dynamic block
• Dynamic and static circuits can be mixed freely• Logic functions can be included in the n-C2MOS
or p-C2MOS latches, or placed between them• Disadvantage: More transistors per latch (six,
instead of four)
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TSPC - True Single Phase Clock Logic
VDD
Out
VDDVDD VDD
InStaticLogic
PUN
PDN
Including logic intothe latch
Inserting logic betweenlatches
Φ Φ Φ Φ
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Simplified TSPC Latch (Split-Output)
VDD VDD
ΦD
Q
A
Φ-latch
VDD VDD
ΦD
Q
Φ-latch• Reduced area• Voltage degradation at A
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Master-Slave Flip-flops
φ
VDD
D
VDD
φ
VDD
D
φ
VDD
φ
VDD
D
VDD
φ
φ
Dφ
VDD
φ
VDD
D
VDD
φ
φD
(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop
(c) Positive edge-triggered D flip-flopusing split-output latches
XY
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Two-Phase Clock Generator
• Considerations:– Drive: added buffers– Non-overlap: Two phases inverted with respect to each other– Minimum skew– Implement with NAND gates?
Φin Φ1
Φ2
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Registers with Load/Enable Inputs
C C CC
Ld
Ld
Φ1 Φ2
D Q
Multiplexedinput
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C CC
Ld Φ1
Φ2
D Q
Gated clockC
Enable
Φ
GndClock enablecircuit
Registers with Load/Enable Inputs
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Comments on Transmission Gates
(Common Misconceptions)
C
Enable
Φ
Gnd
EnabledΦ
Clock enablecircuit
Transmission gate used here as an AND gate
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Ca
b
F = abTransmission gate is not an AND gate
Ca
b
F = a+b
Cab
Transmission gate network does notserve as an OR gate
Comments on Transmission Gates
(Common Misconceptions)