semiconductor manufacturing austria final › event › 120853 › contributions › ... ·...
TRANSCRIPT
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Semiconductor Manufacturing in Austria
Rainer Minixhofer – Senior Manager R&Daustriamicrosystems AG
Topical Workshop on Electronics for Particle PhysicsVienna, Sept. 26th, 2011
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© 2010 austriamicrosystems2
Outline
Introduction, Company Overview and some History
High Voltage Technology
More than Silicon
3D IC Integration
Conclusions
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© austriamicrosystems3
Company milestones
1981 Austria Mikro Systeme (AMS) founded as joint venture by American Microsystems Inc. (AMI) and Voest Alpine (Austria)
1993 AMS goes public on Vienna exchange
2000 AMS returns to private status(major shareholder Permira Private Equity),becomes austriamicrosystems
2002 New 200 mm (8”) fab goes on-line
2004 IPO on SIX Swiss Exchange in Zurich
2006 New test facility in Asia
2011 Acquisition of Texas Advanced Optoelectronic Solutions (TAOS)
A leader in high performance analog ICs: 1,100+ employees, 6 design centers, 19 offices worldwide
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© austriamicrosystems4
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Full supply chain under one roof
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© austriamicrosystems6
Full Service Foundry
Full Service FoundryYour one-stop-shop for turn-key high performance analog IC solutions
Specialty Processes
- 180nm, 350nm, 800nm- CMOS, High-Voltage, SiGe, NVM- Automotive and medical certified- Zero defect program- Extended temperature range- Second source capabilities
Foundry Services
- MPW service with cooperation partners- Benchmark design environment- Numerous digital & analog IP-cells- Standard package assembly service- In-house mixed-signal test facility- Qualification services
More than Silicon ®
- Custom processes- 3D IC using TSVs- RGB & IR Color Coating- Extended IP portfolio- Consultancy: ESD, DFM, DFY, …- Adv. packages: WLCSP, Bumping, …
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• Design and manufacture of high performance analog ICs• Ultra-low power, high accuracy, high integration• Power Management – Sensors & Sensor Interfaces – Mobile Infotainment• Global customer base includes major OEMs• Integrated manufacturer: world class design + best-in-class manufacturing
austriamicrosystems at a glance
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High performance analog ICs
Power Management Mobile InfotainmentSensors & Sensor Interfaces
Sensors & sensor interfaces
Bus systems
Sensors & sensor interfaces
AUTOMOTIVECONSUMER & COMMUNICATIONS INDUSTRY & MEDICAL
Power management
Lighting management
Mobile infotainment
Wireless
Our business
Core expertise
Target markets
54% of revenues 201033% of revenues 2010 13% of revenues 2010
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• State-of-the-art abatement systems• Continuous energy saving and
CO2 reduction measures• Promoting FSC and MSC products
Corporate responsibility
Total CO2 Emissions (tons eq)
Environment
Stakeholder Responsibility
• Participation in UN Global Compact for good business practices• Company Code of Conduct for stakeholder relations
2005 2010
57,500
26,600
Strategic goal to become CO2 neutral as a company
- 54%
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© austriamicrosystems10
Worldwide network – design, sales, distribution
• 6 design centers: Austria, Switzerland, 2x Italy, Spain, India
• 19 sales offices, over 30 distributors worldwide Global contracts with tier 1 players
Distribution partnerships strengthened
Design centersHeadquarters & fab Sales officesDistributor coverage Test center
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Austria – famous for
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© austriamicrosystems
ViktorFranzHess
Erwin Schrödi
nger
Ludwig Boltz-mann
Leopold Gottlieb Biwald
12
But Graz was home of famous scientists too
JohannesKepler
ErnstMach
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Let‘s start with Ernst Mach
“Did you see an atom personally?”(Ernst Mach to his physics students in Vienna about 1900)
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© austriamicrosystems
Moore‘s Law
1947 (Bell Labs)
2011:
Tri-Gate(Intel 22nm):10 Million Trans./mm² 1 Billion on 100mm².
1958 (TI) invention of IC
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available in dev. intendedRev. 3/2011
Technology portfolio
Sensor technologies
Embedded NVM
800nm 350nm 180nm
• Mixed Signal CMOS
• High Perf. Analog
• RF CMOS
• BiCMOS (SiGe)
• HV CMOS
• Galvanic Isolation
CMOS
RF Technologies
HV Technologies
• Emb. EE / Flash
• OTP (Fuse)
• Through Silicon Via• Backside RDL
3D integration
• Hall
• Opto
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© 2010 austriamicrosystems16
High Voltage CMOS vs BCD Comparison
Rdson vs. BVdss for HVCMOS (blue closed symbols) and BCD (white open symbols).AMS 180nm HVCMOS shows largest BVdss range and very low Rdson
10
100
1000
-160 -120 -80 -40 0 40 80 120 160
BVdss [V]
Rsp
[mO
hm*m
m2]
0.18µm BCD (STM) 0.18µm BCD (Dongbu) 0.25µm BCD (TI) 0.25µm BCD (TSMC) 0.35µm HVCMOS (H35)0.18µm HVCMOS (XFAB) 0.18µm HVCMOS (H18) one dimensional Silicon limit 0.18µm HVCMOS (TSMC)
PFET120M
PFET50T
PFET25MPFET20T
NFET20MH
NFETI25M
NFET50MH
NFETI50M
NFETI120M
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© 2010 austriamicrosystems17
Application Areas of Power Devices
350nm/180nm HVCMOS
Current (A
)
5 10 100 1000Operating Voltage (V)
Display Electronics
Lighting Ballast
Power Converters/Power Supplies
Automotive
Telecommunication (e.g. SLIC)
5V CM
OS
20 V50 V
120 V
Motor Control
1000
100
10
Systems is partioned intocontrol chip that drives a setof discrete power SC devices Hybrid integration
Served by monolithic power ICs
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© 2010 austriamicrosystems18
• PMUs• Lighting• Supervisors &
Comparators• LDOs• DC-DC
Converters
Broad standard product portfolioPower
ManagementMobile Entertainment
Systems• Mobile Entertainment
Players• High Performance
Microcontroller
Interfaces• Display and
LED Drivers• LVDS• Industrial Bus • FlexRay /
AutomotiveBus Systems
Audio
• Audio Front-ends
• Amplifiers• Phones
(Feature/Basic)
• High Frequency • Low Frequency
Data Converters
• A/D Converters• D/A Converters• Digital
Potentiometers• Analog Switches• Data Acquisition
Front-ends
RF Products
Sensors & Sensor Interfaces
• Magnetic Rotary Encoder
• Magnetic Linear Position Encoder
• Automotive Rotary Encoder
• Metering
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© 2010 austriamicrosystems19
5V transistors
Process modularity of 350nm technology
350nm 3.3V analog/mixed signal polycide process
caps: poly& MIM
3rd and 4th metal
hi-resistive
polysilicon
SiGe BiCMOS High Voltage
poly- &Zener-fuses
Non-Volatile Memory
high sensitivity opto-process
High flexibility through modularity:
LVT transistors
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350nm vs. 180nm HV transistor comparison: 20V PMOS
AMS 350nm HVCMOS AMS/IBM 180nm HVCMOS
Additional 30% average HV area reduction by shrinking to 180nm
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© 2010 austriamicrosystems21
power metal (Cu and/or Al)
5V transistors
Process modularity of 180nm technology
180nm 1.8V silicide process
metal-metal caps
up to 7 layers of
metal
hi-resistive
polysilicon
High Voltage
OTP (eFuse)
Non-Volatile Memory
High flexibility through modularity:
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© 2010 austriamicrosystems22
180nm CMOS-HV 20V & 50V
180nm HV = 180nm RFCMOS + 2 Mask Levels(2 wells , no HV gate oxide)
Full modularity with CMOS base process, low mask countHVCMOS180nm CMOS
Low-voltage CMOS
+
+
CONFIDENTIAL RESTRICTED
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© 2010 austriamicrosystems23
Gate Module of 180nm technology
Only 180nm HV technology on the market with 3 gate oxides!
52 nm
12 nm
3.5 nm
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© 2010 austriamicrosystems24
Suite of FETs with three gate oxide thicknesses
LV fets LV fets in HV well HV asymmetric fets in HV wells
HV symmetric fets(nfet in Substrate)
VdsVgs
1.8V 5.0V 1.8V 5.0V 20V** 50V 20V 50V
1.8V(3.5nm)
nfet*pfet*
nfethvtpfethvt
nfeti*pfeti*
nfetihvtpfetihvt
nfeti20tpfet20t
nfeti50tpfet50t
5.0V(12nm)
nfetmpfetm
nfetimpfetim
nfet20mhnfeti25mpfet25m
nfeti50mpfet50m
20V(52nm)
nfeti20hpfet20h
nfeti50hpfet50h
nfet20hspfet20hs
nfet50hspfet50hs
* RF layout available ** 25V Vds for nfeti25m,pfeti25m
– Low Voltage (LV) fets for standard 1.8 and 5V CMOS– LV fets in HV well for high voltage isolation to substrate– HV asymmetric fets for High Voltage applications– 3 gate oxide thicknesses, 2 maximum drain bias choices– HV symmetric fets for specialty applications (transmission gate)
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© 2010 austriamicrosystems25
Floating Logic
3.3V
0V 3.3V
0V = PSUB
PMOS4
NMOS4
PMOS4 NMOS4 PMOSI NMOSI
B S G D D G S B B S G D D G S B PSUB
VDDF = GNDF+3.3V
GNDF
PSUB = 0V
PMOSI
NMOSI
0V … 46.7V
PSUB
DNTUB
NTUB DPTUB
Substrate Logic – 350 and 180nm Floating Logic - only in HVCMOS
• CORELIB (260 Cells) built up with PMOS4 and NMOS4
• Bulk of NMOS always PSUB
• Bulk of PMOS maximum of 3.3V
• CORELIB_HV has to be built with PMOSI and NMOS4I
• Bulk of NMOS 0V .. 46.7V
• PMOS maximum of GNDF+3.3V(max. 50V)
• Automatically generated form CORELIB
Net +2 additional alignments
3.3V
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© 2010 austriamicrosystems26
CORELIB vs. CORELIB_HV Cell LayoutCORELIB Cell CORELIB_HV Cell
NTUB
DNTUBSNTUB
RPTUB = SPTUB + DPTUBPSUB
Same Cell Size
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180nm HVCMOS metal stack options
MIM
K1 ResM2M1
M3MT
AM (4µm)
Standard CMOS layers
RF/analogadd on module
M1M2M3M4M5MT7
MT
AM Last Metal Option
M1M1M1M1M2M2M2MTM3M3MTM4MT
StandardAl wiringLevels
6543# Levels
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HV HSIM_HV Model to Hardware Results
Excellent agreement between measured results and HiSIM_HV SPICE model.Model features include:
– Surface potential iterative calculation used for an accurate description of drift region– Self-heating included– Simulation speed and accuracy is improved compared BSIM (SPICE) + subcircuit.
0,0E+00
1,0E-03
2,0E-03
3,0E-03
4,0E-03
5,0E-03
6,0E-03
7,0E-03
8,0E-03
0 5 10 15 20 25 30 35 40 45 50
VD[V]
ID[A
]
ID(VG=0.45V) ID(VG=0.60V) ID(VG=0.75V) ID(VG=0.90V) ID(VG=1.05V) ID(VG=1.20V)ID(VG=1.35V) ID(VG=1.50V) ID(VG=1.65V ID(VG=1.80V)
0,0E+00
1,0E-03
2,0E-03
3,0E-03
4,0E-03
5,0E-03
6,0E-03
0 5 10 15 20 25 30 35 40 45 50
-VD[V]
-ID[A
]ID(VG=-0.45V) ID(VG=-0.60V) ID(VG=-0.75V) ID(VG=-0.90V) ID(VG=-1.05V) ID(VG=-1.20V)ID(VG=-1.35V) ID(VG=-1.50V) ID(VG=-1.65V ID(VG=-1.80V)
Thin oxide NFET for 50V use Thin oxide PFET for 50V use
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Layout for 50V ESD Protection
4kV ESD Cell 2kV ESD Cell
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More than Moore
International Technology Roadmap of Semiconductors, ITRS 2009
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3D IC Integration3D IC integration … stacking of semiconductor wafers or chips
using TSVs to provide electrical contact between stacked layers
TSV … Through Silicon Viaelectrical contact extending through silicon
WLP … Wafer Level PackageIC packaging prior to wafer dicing
(Source: Yole Developpement, austriamicrosystems)
UBM, bumping, test
3D TSV stack
Form Factor reductionPerformance improvements
Reduced R, CReduced power consumptionIncreased speedReduced signal losses (noise)
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More than Silicon: 3D-IC integration using Through Silicon Vias
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3D technology concept
Top wafer processed up to last metal layer (chip1)
Bottom wafer including bond oxide (chip2)
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3D technology concept
top wafer thinned to 250µm
Low temperature molecular wafer bonding
edge removal of top wafer
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3D technology concept
Final Bonded wafer stack
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3D technology concept
TSV and RDL Formation
Bumped wafer
Bump on pads - standard bump technology
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3D stacking by means of TSV, BRDL and µbumps 1/3
Control and read out circuit with TSV and BRDL
sensor chips with µbumps
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control and read out circuit with TSV and BRDL
sensor chips
3D stacking by means of TSV, BRDL and µbumps 2/3
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control and read out circuit
sensor chips
3D stacking by means of TSV, BRDL and µbumps 3/3
printed circuit board
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3D special integration tools
DRIE (STS PEGASUS)
Automated Wafer Bonder (EVG GEMINI®)
Scanning Acoustic Microscope (SONIX)
Resist Coating (EVG®150 NanoSpray)STS Pegasus SONIX CSAM
EVG Gemini® EVG®150N
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TCAD environment set up
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Key TSV reliability considerationsDefect–related (extrinsic) problems
Defect screening
Defect reduction
Intrinsic reliability
Material set & construction
Layer cracking/delamination
e.g. TSV passivation integrity
Kraft IRPS/ESSDERC, Altman ISTFA, Cassidy ISTFA/IPFA/ESREF
Wafer surface
TSV sidewall
TSV base
-2000
-1500
-1000
-500
0
500
1000
1500
2000
0.00 50.00 100.00 150.00 200.00 250.00
depth (um)
stre
ss (M
Pa)
bottom topvon Mises
vertical stress
tangential stress
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new developments: gas sensors using 3D integration
Teva Nanosense 2010
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3D Integrated Photodiode ArrayDetection and processing of visible light intensity in CT-Scanners
CMOS
chip
(64 c
hann
el An
alog-
Digit
al Co
nver
ter)
Transmitted x-rays from patient
Scintillator
Green photons
270um
64 pi
xel P
hotod
iode
PCB
CMOS
chip
(64 c
hann
el An
alog-
Digit
al Co
nver
ter)
Transmitted x-rays from patient
Scintillator
Green photons
270um
64 pi
xel P
hotod
iode
PCB
NMOS PMOS
Photodiode p+
TSV
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austriamicrosystems offers a rich portfolio of technologies tailored to high performance analog applications
The high voltage technologies on the 350nm and 180nm node are ideally suitedfor SoC applications
The new 3D IC integration platform(s) provide completely new ways of sensorand multiple chip solutions.
We offer a long experience of High-Voltage CMOS/high performance analog process development and design to our customers.
Summary and Conclusions
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Some famous last words....
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Benefits
Thank you for your attention!
Acknowledgements:
Cathal CassidyHeimo Gensinger
Ingrid JonakMartin Knaipp
Günter KoppitschJochen Kraft
Franz SchrankJörg Siegert
Jordi TevaEwald Wachmann
and to FELMI-ZFEfor the excellent co-
operation