University of Montenegro

Faculty of Electrical Engineering

Course: Automated Design of Electrical Circuits and Systems

Theme: Seven segment counter 0 - 99

Mentor: Students:

Prof. dr Radovan Stojanović Olivera Nikčević 14/19Filip Živković

35/19 Budimir Anđelić 30/19

Date and place: 11/19/2019

Podgorica

Contents

Summary.....................................................................................................................................................3

Problem description....................................................................................................................................3

Hardware/software solution and simulation...............................................................................................3

Verification on board.................................................................................................................................14

Link for the video.......................................................................................................................................15

Literature...................................................................................................................................................15

Summary This is a lab project, made in MEDEL electronics lab at the University of Montenegro, with mentoring of prof. dr Radovan Stojanović. In further text, the problem is explained in details and offered an elegant solution. In addition to that, we have enclosed high level design and description of our solution, alongside with hardware and software structure. The accent is on control of a seven segment display, using a clock signal on FPGA board DE2-70.

Problem description Our job is to project the seven segment double-digit counter. We should be able to drive it with a 0.5Hz, 1Hz, 2Hz and 4Hz clock signals. Input is 50MHz clock signal from Altera board and outputs are two seven segment displays.

Hardware/software solution and simulationAs a software solution we used Altera Quartus 9.1 which is approved and tested for all FPGA and CPDL based systems. Source code was written in VHDL.

HIGH-LEVEL DESIGN

Fig. 1.0 depicts the rough scheme and simplified version of our circuit.

Fig 1.0

Short explanation in order to better understand the source code:

For the realization of this project we used four different circuits of frequency divider in order to get four clock signals( 0.5Hz, 1Hz, 2Hz, 4Hz), circuit that makes a selection of clock signal we want to use based on the states of switches p0,p1,p2,p3, counter for ones and tens and 7segment driver. The input is internal clock, coming from the board, which is divided from 50 MHz to a signals of 0.5 Hz,1Hz,2Hz,4Hz with above mentioned divider. Also we used one reset signal which is connected to a pushbutton and when the pushbutton is pressed it starts counting rising edges of input clock in order to make a new clock signal. Another input is enable signal connected to a switch. After producing four different clock signals, selection circuit makes the choise. If switch p0 is HIGH than we use 1Hz, p1 2Hz, p2 4Hz, p3 0.5Hz. Every other combination besides 1000, 0100, 0010, 0001 is treated like 1000. Then we increment counter_ones on every rising edge of new clock signal. When it becomes equal to 10 we set it back to 0 and remember that position for making new signal called “fc” which tells us when to increment a number of tens. Then we increment a counter_tens on every rising edge of “fc” signal. When it becomes equal to 10 we set it back to 0 and remember that position for making new signal called “fc1” which indicates that we counted to 99 and need to start from the beginning. Signal “fc1” is connected to led diode. The only thing left we need to make is 7segment driver. When number of ones(tens) is 0 we need to make sure that the output is "1001111" where a(a1) <= output(6); b(b1) <= output(5); c(c1) <= output(4); d(d1) <= output(3); e(e1) <= output(2); f(f1) <= output(1); g(g1) <= output(0). Same for 1,2,3,4,5,6,7,8,9. We set that h and h1 is always 0 because we don’t want a decimal points to be shown.

Source code:

---Frequency devider1hz---

library ieee;use ieee.std_logic_1164.all;entity frequency_devider isport (clock : in std_logic;reset : in bit;clock1hz : out std_logic);end frequency_devider;architecture RTL of frequency_devider issignal pulse : std_logic;signal counter : integer range 0 to 24999999 :=0;beginprocess(reset,clock)beginif(reset='0') thenpulse <='0';counter <= 0;else if rising_edge(clock) thenif(counter=24999999) then

pulse<=not(pulse);counter<=0;elsecounter<=counter+1;end if;end if;end if;end process;clock1hz<=pulse;end RTL;

---Frequency devider2hz---

library ieee;use ieee.std_logic_1164.all;entity frequency_devider2hz isport ( clock : in std_logic; reset : in bit; clock2hz : out std_logic);end frequency_devider2hz; architecture RTL of frequency_devider2hz is signal pulse :std_logic; signal counter : integer range 0 to 12499999 := 0; begin process(reset,clock) begin if(reset='0') then pulse <='0'; counter <= 0; else if rising_edge(clock) then if(counter=12499999) then pulse<=not(pulse); counter<=0; else counter<=counter+1; end if; end if; end if; end process; clock2hz<=pulse; end RTL;

---Frequency devider4hz---

library ieee;use ieee.std_logic_1164.all;entity frequency_devider4hz isport (

clock : in std_logic; reset : in bit; clock4hz : out std_logic);end frequency_devider4hz; architecture RTL of frequency_devider4hz issignal pulse : std_logic; signal counter : integer range 0 to 6249999 := 0; begin process(reset,clock) begin if(reset='0') then pulse <='0'; counter <= 0; else if rising_edge(clock) then if(counter=6249999) then pulse<=not(pulse); counter<=0; else counter<=counter+1; end if; end if; end if; end process; clock4hz<=pulse; end RTL;

---Frequency devider0.5hz---

library ieee;use ieee.std_logic_1164.all;entity frequency_devider05hz isport ( clock : in std_logic; reset : in bit; clock05hz : out std_logic);end frequency_devider05hz; architecture RTL of frequency_devider05hz issignal pulse : std_logic; signal counter : integer range 0 to 49999999 := 0; begin process(reset,clock) begin if(reset='0') then pulse <='0'; counter <= 0; else if rising_edge(clock) then if(counter=49999999) then pulse<=not(pulse); counter<=0; else counter<=counter+1;

end if; end if; end if; end process; clock05hz<=pulse; end RTL;

---Clock odabirac---

library ieee;use ieee.std_logic_1164.all;entity clock_odabirac isport(clock1hz: in std_logic;clock2hz: in std_logic;clock4hz: in std_logic;clock05hz: in std_logic;clock_new: out std_logic;p0,p1,p2,p3: in std_logic);end clock_odabirac;architecture clock_arh of clock_odabirac issignal prekidac : std_logic_vector(3 downto 0);signal clock_new1 : std_logic;beginprekidac <= p3 & p2 & p1 & p0;with prekidac selectclock_new <= clock1hz when "1000",clock2hz when "0100",clock4hz when "0010",clock05hz when "0001",clock1hz when others; end clock_arh;

---Count ones---

library ieee;use ieee.std_logic_1164.all;entity count_ones isport(clock_new: in std_logic;reset: in bit;enable : in bit;ones : out integer range 0 to 9;fc : out std_logic);end count_ones;architecture RTL of count_ones isbeginprocess(clock_new)variable brojac : integer range 0 to 9;begin if(clock_new='1' and clock_new'event) then

if (enable='1') then if(brojac<9) thenbrojac:=brojac+1;else brojac:=0;end if;end if;end if;if(brojac=0) and (enable='1') thenfc<='1';elsefc<='0';end if;ones <=brojac;end process;end RTL;

---Count tens---

library ieee;use ieee.std_logic_1164.all;entity count_tens isport(clock_new: in std_logic;reset: in bit;enable : in bit;tens : out integer range 0 to 9;fc1 : out std_logic);end count_tens;architecture RTL of count_tens isbeginprocess(clock_new)variable brojac : integer range 0 to 9;begin if(clock_new='1' and clock_new'event) thenif (enable='1') then if(brojac<9) thenbrojac:=brojac+1;else brojac:=0;end if;end if;end if;if(brojac=0) and (enable='1') thenfc1<='1';elsefc1<='0';end if;tens <=brojac;end process;end RTL;

---BCD 7seg_ones---

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity bcd_7seg_ones isport(ones: in integer range 0 to 9;a,b,c,d,e,f,g,h : OUT BIT);end bcd_7seg_ones;architecture rtl of bcd_7seg_ones isbeginprocess(ones)variable segment : bit_vector(0 to 6);begincase ones iswhen 0 => segment:="0000001";when 1 => segment:="1001111";when 2 => segment:="0010010";when 3 => segment:="0000110";when 4 => segment:="1001100";when 5 => segment:="0100100";when 6 => segment:="0100000";when 7 => segment:="0001111";when 8 => segment:="0000000";when 9 => segment:="0000100";when others => segment:="1111111";end case;a<=segment(0);b<=segment(1);c<=segment(2);d<=segment(3);e<=segment(4);f<=segment(5);g<=segment(6);h<='1';end process;end rtl;

---BCD 7seg_tens---

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity bcd_7seg_tens isport(tens: in integer range 0 to 9;

a1,b1,c1,d1,e1,f1,g1,h1 : OUT BIT);end bcd_7seg_tens;architecture rtl of bcd_7seg_tens isbeginprocess(tens)variable segment : bit_vector(0 to 6);begincase tens iswhen 0 => segment:="0000001";when 1 => segment:="1001111";when 2 => segment:="0010010";when 3 => segment:="0000110";when 4 => segment:="1001100";when 5 => segment:="0100100";when 6 => segment:="0100000";when 7 => segment:="0001111";when 8 => segment:="0000000";when 9 => segment:="0000100";when others => segment:="1111111";end case;a1<=segment(0);b1<=segment(1);c1<=segment(2);d1<=segment(3);e1<=segment(4);f1<=segment(5);g1<=segment(6);h1<='1';end process;end rtl;

---Count pack---

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;package count_pack iscomponent frequency_deviderport( clock: in std_logic;reset :in bit;clock1hz: out std_logic);end component;component frequency_devider05hzport( clock: in std_logic;reset :in bit;clock05hz: out std_logic);end component;component frequency_devider2hzport( clock: in std_logic;reset :in bit;clock2hz: out std_logic);

end component;component frequency_devider4hzport( clock: in std_logic;reset :in bit;clock4hz: out std_logic);end component;component clock_odabiracport(clock1hz: in std_logic;clock2hz: in std_logic;clock4hz: in std_logic;clock05hz: in std_logic;clock_new: out std_logic;p0,p1,p2,p3: in std_logic);end component;component count_onesport(clock_new: in std_logic;reset: in bit;enable : in bit;ones : out integer range 0 to 9;fc : out std_logic);end component;component count_tensport(clock_new: in std_logic;reset: in bit;enable : in bit;tens : out integer range 0 to 9;fc1 : out std_logic);end component;component bcd_7seg_ones port(ones: in integer range 0 to 9;a,b,c,d,e,f,g,h : OUT BIT);end component;component bcd_7seg_tensport(tens: in integer range 0 to 9;a1,b1,c1,d1,e1,f1,g1,h1 : OUT BIT);end component;end count_pack;

---Counter 99---

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;use work.count_pack.all;entity counter_99 isport( clock : in std_logic;

reset : in bit;enable :in bit;clock1hz: in std_logic;clock2hz: in std_logic;clock4hz: in std_logic;clock05hz: in std_logic;clock_new: out std_logic;p0,p1,p2,p3: in std_logic;fc,fc1: out std_logic;a,b,c,d,e,f,g,a1,b1,c1,d1,e1,f1,g1,h,h1 : out bit);end counter_99;architecture arq_count_99 of counter_99 issignal iclock1hz : std_logic;signal iclock2hz : std_logic;signal iclock4hz : std_logic;signal iclock05hz : std_logic;signal iclock_new : std_logic;signal iones : integer;signal ifc: std_logic;signal itens: integer;begindivfre:frequency_devider port map(clock=>clock, reset=>reset, clock1hz=>iclock1hz);divfre1:frequency_devider2hz port map(clock=>clock, reset=>reset, clock2hz=>iclock2hz);divfre2:frequency_devider4hz port map(clock=>clock, reset=>reset, clock4hz=>iclock4hz);divfre3:frequency_devider05hz port map(clock=>clock, reset=>reset, clock05hz=>iclock05hz);clockodab:clock_odabirac port map(p0=>p0,p1=>p1,p2=>p2,p3=>p3,clock1hz=>iclock1hz,clock2hz=>iclock2hz,clock4hz=>iclock4hz,clock05hz=>iclock05hz,clock_new=>iclock_new);countones: count_ones port map(enable=>enable,reset=>reset, clock_new=>iclock_new, fc=>ifc, ones=>iones);counttens: count_tens port map(enable=>enable,reset=>reset, clock_new=>ifc, fc1=>fc1, tens=>itens);bcdones: bcd_7seg_ones port map(ones=>iones, a=>a, b=>b, c=>c, d=>d, e=>e, f=>f, g=>g,h=>h);bcdtens: bcd_7seg_tens port map(tens=>itens, a1=>a1, b1=>b1, c1=>c1, d1=>d1, e1=>e1, f1=>f1, g1=>g1,h1=>h1);end arq_count_9

The following figure 1.1. represents Block Diagram/Schematic File

Fig. 1.1.

As a hardware solution we used FPGA board DE2-70 (Cyclone II).Signals and assigned pins : ( Fig. 1.2. and Fig. 1.3. )

Fig. 1.2.

Fig. 1.3.

Verification on board Verification was successfully done in a way described in previous paragraph. As a proof we enclose to this statement a video, which was made in MEDEL electronics lab.

Link for the videohttps://youtu.be/fCMkQW_dfCA

Literature [1] Radovan D. Stojanovic AUTOMATIZOVANO PROJEKTOVANJE DIGITALNIH SISTEMA (VHDL i FPGA) [2] DE2-70 User manual version 1.08