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SOLUTIONS - SEMESTER ONE - 2007

MODULE: Digital Circuits and Systems (EE201)

COURSE: B.Eng. in Info and Communications EngineeringB.Eng. in Mechatronic EngineeringB.Eng. in Electronic EngineeringB.Eng. in Digital Media Engineering

YEARS: 2 (two) and 3 (three)

EXAMINERS: Mr. David Bermingham

Dr. R. MillarDr. F. DevittDr. F. Owens

TIME ALLOWED: 2 hours

INSTRUCTIONS: Answer FOUR questions. All questions carry equal marks

___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester One - 2006/2007

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QUESTION 1

A) Design a sequential logic circuit that except two inputs, X0 and X1, and has a single output Z which is 1 most of the time. If the input bits decrement from 11 to 00 the output Z becomes 0 for one clock. Use J-F flip-flops

State CodingPresent State Code

A 0 0B 0 1C 1 0D 1 1

Need two flip-flops, JKA and JKB.

State TablePresent

StateNext State Output

X0 X1 X0 X1 X0 X1 X0 X1 X0 X1

X0 X1

X0 X1

X0 X1

00 01 10 11 00 01 10 1100

A A A B 1 1 1 1

01

A A C A 1 1 1 1

10

A D A A 1 1 1 1

11

A A A A 0 1 1 1


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Excitation TableQA QB X0 X1 Q’A Q’B JA KA JB KB Z0 0 00 0 0 0 X 0 X 10 0 01 0 0 0 X 0 X 10 0 10 0 0 0 X 0 X 10 0 11 0 1 0 X 1 X 10 1 00 0 0 0 X X 1 10 1 01 0 0 0 X X 1 10 1 10 1 0 1 X X 1 10 1 11 0 0 0 X X 1 11 0 00 0 0 X 1 0 X 11 0 01 1 1 X 0 1 X 11 0 10 0 0 X 1 0 X 11 0 11 0 0 X 1 0 X 11 1 00 0 0 X 1 X 1 01 1 01 0 0 X 1 X 1 11 1 10 0 0 X 1 X 1 11 1 11 0 0 X 1 X 1 1

JAX0X1\ QA QB 00 01 11 10

00 0 0 X X01 0 0 X X11 0 0 X X

10 0 1 X X

JA =X0./X1.QB

KA

X0X1\ QA QB

00

01 11 10

00 X X 1 101 X X 1 0

11 X X 1 110 X X 1 1

KA= QB + X0 + /X1(K-map omitting one grouping)___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester One - 2006/2007

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JB

X0X1\ QA QB 00 01 11 1000 0 X X 0

01 0 X X 111 1 X X 010 0 X X 0

JB =|X0.X1.Qa + X0.X1.|Qa

KB

X0X1\ QA QB 00 01 11 1000 X 1 X 101 X 1 X 111 X 1 X 110 X 1 X 1

KB = 1

Z

X0X1\ QA QB 00 01 11 1000 1 1 0 101 1 1 1 111 1 1 1 110 1 1 1 1

Z = X0 + X1 + /QB + /QA

Implementation required (17 Marks)

(b) Given the following state table, table I. Describe how the number of flip-flops needed to implement this sequential circuit could be reduced.

PresentState

Next State OutputX=0 X=1 X=0 X=1

A A B 0 0

B A C 0 0

C D E 0 0

D E C 0 1

E E F 0 1


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F D E 0 0

States C and F are equivalent. Replace F with C and remove state F.

PresentState


A A B 0 0

B A C 0 0

C D E 0 0

D E C 0 1

E E C 0 1

States D and E are now equivalent. Replace E with D and remove state E.

PresentState


A A B 0 0

B A C 0 0

C D D 0 0

D D C 0 1

We have saved 1 flip-flop since only need 2 flip-flops now instead of 3 with original state table.

(8 Marks)

QUESTION 2a) What is the advantage of using Hamming code over single parity bit?

Describes the steps needed when encoding and transmitting an M-bit data string using Hamming code.


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Unlike single parity bit, Hamming Code allows single data errors to be both detected and corrected. With single parity bits, single errors can only be detected.

Steps to Encode and Transmit1) Count number of data bits to be sent.2) Determine number of parity bits needed from

i.3) Using either ODD or EVEN parity, calculate the parity bits based on

the locations each parity bit checks4) Place the parity bits in their Hamming locations between the data bits

to form a Hamming sequence.5) Transmit the Hamming Sequence.

(9 marks)

b) Encode using Hamming code the following data, briefly indicating the steps taken: (Assume even parity used)(i) 1010(ii) 10011101

(i) 10104 data bits => 2P = P + 4 +1Requirement holds if P= 3. Need 3 Parity bits:

Required Hamming SequenceP1 P2 D3 P4 D5 D6 D7? ? 1 ? 0 0 1

P1 checks P1, D3, D5, D7P2 checks P2, D3, D6, D7 P4 checks P4, D5, D6, D7

Using Even ParityP1 -> P1, 1, 0, 0 => P1 = 1P2 -> P2, 1, 1, 0 => P2 = 0P4 -> P4, 0, 1, 0 => P4 = 1

Hamming Sequence = 1011010(4 Marks)

(i) 100111018 data bits => 2P = P + 8 +1Requirement holds if P= 4. Need 4 Parity bits:

Required Hamming SequenceP1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12? ? 1 ? 0 0 1 ? 1 1 0 1


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P1 checks P1, D3, D5, D7, D9, D11P2 checks P2, D3, D6, D7, D10, D11 P4 checks P4, D5, D6, D7, D12P8 checks P8, D9, D10, D11, D12

Even Parity Used again…P1 -> P1, 1, 0, 1, 1, 0 => P1 = 1P2 -> P2, 1, 0, 1, 1, 0 => P2 = 1P4 -> P4, 0, 0, 1, 1 => P4 = 0P8 -> P8, 1, 1, 0, 1 => P8 = 1

Hamming Sequence = 111000111101 (4 Marks)c) Detect errors (if any) and extract the corrected binary data from the

following Hamming codes: (Assume odd parity used) (i) 0110101(ii) 1011011

(i) Received code: 0110101Received bit count is 7 bits, N =7

Determine number of parity bits used in transmission2P = N +1 => 3 party bits used

P1 P2 D3 P4 D5 D6 D70 1 1 0 1 0 1

C1 checks P1, D3, D5, D7C2 checks P2, D3, D6, D7C4 checks P4, D5, D6, D7

Odd Parity Used:C1 -> 0, 1, 1, 1 -> C1 = 0C2 -> 1, 1, 0, 1 -> C2 = 0C4 -> 0, 1, 0, 1 -> C4 = 1

Error is in bit 1002 or bit position 4 of data sequence. Parity bit is corrupted

=> Original data sequence: 1101(4 Marks)

(ii) Received code: 1011011Received bit count is 7 bits, N =7

Determine number of parity bits used in transmission2P = N +1 => 3 party bits used

P1 P2 D3 P4 D5 D6 D71 0 1 1 0 1 1


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C1 checks P1, D3, D5, D7C2 checks P2, D3, D6, D7C4 checks P4, D5, D6, D7

Odd Parity Used:C1 -> 1, 1, 0, 1 -> C1 = 0C2 -> 0, 1, 1, 1 -> C2 = 0C4 -> 1, 0, 1, 1 -> C4 = 0

No Error in data=> Original data sequence: 1011

(4 Marks)

Question 3

a) Using a 4-bit RCA Adder, a 4-bit 4:1 Multiplexer, and an 8-bit latch and any logic gates you need to design a 4-bit ALU which can perform the following operations:

ALU Control Signals ALU OutputBit 0 Bit 1

0 0 A plus B0 1 A minus B1 0 A AND B1 1 A XOR B

Highlight the critical path of your ALU.

When the En line is high a new value is latched into the ALU.When Bit1 of the control signal is high, the B input is inverted in the 4-bit XOR gates and the carry in bit is set high.___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester One - 2006/2007

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When B1 is zero, the B input is unchanged and normal 4-bit addition is performed. The output multiplexer selected which result to select.The critical path(red path) is from the latch output, through the XOR gates, the Adder and the output mux.

(12 Marks)

b) Using any additional circuitry. Describe how your ALU could be fitted with an Accumulator (ACC). The Accumulator should allow ALU results to be used as input B of the ALU.

Requires, additional 4-bit register plus 2:1 Mux with new control line to select between the Accumulator or new input.

(5 Marks)___________________________________________________________________________________________EE201 - Digital Circuits and Systems - Semester One - 2006/2007

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c) Show in detail the sequence of both the ALU control signals AND the ACC you would need to perform the following piece of code: ((3+5) & 9) ^ 12), Where: & denotes logic AND, ^ denotes the XOR operationList the partial outputs from each operation.

Step 1: A = 3, B = 5, Control Bits = 00, BnACC=1, Enable = 1 Partial Result = 8(1000

Step 2: A = 9, B = X, Control Bits = 10, Enable = 1, BnACC=0 Partial Result = 8(1000

Step 3: A = 12, B = X, Control Bits = 11, Enable = 1, BnACC=0 Partial Result = 4(0100)

(8 Marks)

Question 4

a) Describe a transparent NAND D-type latch.

Transparent NAND D-type latch is comprised of an inverted S-R flipflop with an additional pair of NAND gates at the input. Using a NAND design, an active high D-type latch can be built using only 4 NAND gates.

The inverted SR flipflop has the following truth table

When the Enable line is zero, /S = /R = 1 and the inverting SR flipflop retains its previous value. When the enable line is high, the value of data line D is latched into the flipflop.

(8 Marks)


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/S /R Q’0 0 X0 1 11 0 01 1 Q

E D /S /R Q’0 0 1 1 No Change0 1 1 1 No Change1 0 1 0 01 1 0 1 1

b) Using 2 D-type latches and 2 NAND gates, Design a rising edge triggered D flipflop. How would this be converted to respond to a falling clock edge?

Using 2 D-type transparent latches and 2 NOT gates we can create an edge triggered flipflop which can be used in synchronous circuits.

The red boxes outline the 2 D-type latches. The first drives the input of the second D-type latch. When the clock is 0 the first D-type latch is ON, with the value of D latched into the inverted SR flipflop. As the clock goes high, the first D-type latch switches OFF and the second D-type latch is enabled. The output of latch 1 propagates through the second flipflop to the output. When the clock goes low again the value of D is retained until the next clock edge.The circuit can be made to respond to falling clock edges by removing the leftmost inverter from the circuit.

(5 Marks)

c) Design a 16-word by 1-bit RAM using 4-word by 1-bit latches and any additional logic gates you need.


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Design Signals: Data-In (1-bits), Data-Out (1-bits), Address Lines (4-bits), Read/Write control signal.

Each 4-word by single bit memory has 2 address lines, a chip-select and read/write control signals. The address lines allow the 4 bits to be addressed. The least significant address bits are connected to the 2 RAM select lines, with the most significant address bits used to generate a 4-bit decoded value which can be used to control the chip select lines.When the address line is “0000”, the address decoder decodes the input 00 to “1000”, enabling the first RAM element. If R/W=1, the data on DataIn will be written to memory location 0.

The address decoder can be implement using 4 2-input AND gates and 2 inverters.

(12 Marks)Question 5

a) Define VOH, VOL, VIH, VIL

VIH => Min voltage at input which can be ‘read’ as a 1(high)VIL => Max voltage at input which can be ‘read’ as a 0(low)VOH => Min voltage at output which allows a 1(high)VOL => Max voltage at output which can be ‘read’ as a 0(low)

(8 Marks)

b) Describe totem pole output configurations when applied to TTL circuits. Briefly compare and contrast this configuration with open collector TTL outputs

Totem pole outputs use two transistors at the output to ensure proper TTL levels.

A TTL NAND gate using totem pole outputs is shown above, the diodes Q3 and Q4 provide totem-pole functionality. Both transistors cannot be ON at the same time, allowing current to be sourced from +5V or providing a means of sinking current from the next stage.When compared to Open-Collector configurations:


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Totem-pole allows faster switching as the resistor is the limiting factors in open collector TTL circuits.

Unlike open-collector which can only sink current, totem pole allows both current to be sourced and sunk.

However, totem pole output cannot be used for data-busing as the output current requirements of 2 bussed totem pole outputs would greatly exceed TTL requirements,

o IOH = @30 mA for totem poleo TTL limits IOH(max) = 16mA

(8 Marks)

c) Outline the three components of power consumption in a CMOS circuit

1) Short-Circuit Power: During a change in state of the input, there is a short period where both PMOS and NMOS transistors are on. Creating a very short period where Vdd is shorted to ground.

2) Static Power: Due to leakage when circuit is not changing. Static power is comprised of 1) Gate->Source leakage and 2) source-drain leakage.

3) Dynamic Power: The major component of CMOS power dissipation, dynamic power consumption relates to the charging and discharging of the gate load capacitance. Dynamic power is determined by the switching frequency of the CMOS device and is the dominant component of CMOS power consumption.

(9 Marks)


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