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1 Databook 1.. .1 1 1 Local Bus VU Graphies Controller 1 OTt-G87 1 1 l, 1 1 1 ,1 1 1 r . 1

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Page 1: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 Databook

1

1 1 1

Local Bus VU Graphies Controller 1 OTt-G871middot

1 1 l

1 1 1

1

1 1 r

1

(

OTI-087X Addendum to the Databook

1 1 1

1 This Addendum describes changes to the OTI-087 February 1993 databook for OTI-087X parts The OTI-087X currently does not support the RAS only refresh DRAM 2608 type DRAM and integrated feature connector support

~ Description 1 Disregard the reference to RAS only refresh in the feature liste This is currently

not supported

8 Disregard CASOn CAS1n CAS2n and CAS3n signaIs on the Operational Block Diagram

13 This MD interface is not supported with this OTI-087 revision

i l 16 Disregard CASOn CAS1n CAS2n and CAS3n signaIs on the Memory Mapping

i Configuration

1 25 EPDATA should be DCn under the OU-087 (LB386486) co1urnn

28 Pin 99 on OTI-087 (LB 386486) should be DCn

37 Extended Register 8 bits 6 10 should be as below AIso pin 99 does not apply

Bits 6 1 0 Pin 19 Pin 20 101 EPCLK EPDATA 110 EPCLK EPDATA

Bit 7 Reserved

60 See attached for new Local Bus Schematics

r--- - -(--

31194

OTI-087 Drivers List

ution s ~RS

~AD262 x ~AD 910111112 x x x x x x x x x hadc 1020 x x x x x mce4041 x x x ~odeII x x 132x254360 =wode III x x 132x254360

331 x x x x 12320x x x 132x2543 12322 x x x x 132x254360 123 3031 x x x x resolution dependent 140 x 21 x x x D4S x x x ua 1l x ua 20 x x x x lCAD60 x x x x x lCADl386 60 x x x x x ~TSR x x x x 132x2543608Ox60 lPerfect SO x lPerfect S1 x x x x 132x254360

lowa31 x x x x x x x x x x x x x x x x lowaNf 31 x x x x x x x x

=se resolutioDS are oDly IUpported by 00-087 due to the requirement of 2Mbytes ofvideo memory

~

-

~~ ~

- -----___- ---~--

(

t-

~ middot

1 1 1 1 1 1 1 J 1 1 1 1 1 1 1 l 1

Prefa~e

The information eontained in this document has been carefully checked and is be1ieved to be reliable However Oak Technology Incmakes no guarantee or warranty conceming the saidinformationand shaH not be responsible for any 10ss or damage of whatever nature resulting from the use of or relianee upon it Oak Teehnology Ine does not guarantee that the use of any information eontained herein will not infringe upon the patent or other rights of third parties and no patent or other Iicense is implied hereby

This document does not in any way extend Oak Technology Ines warranty on any produet beyond that set forth in its standard terms and conditions of sale Oak Technology Ine reserves the rightto make changes in the produets or specifications or both presented in this publication at any time and without notice

Life Support Applications

Oak Technology Ine produets are not intended for use as critical eomponents in life support appliances deviees or systems in which the failure of an Oak Technology Ine product to perform eould reasonably he expeeted to result in personal injury

February 1993

--

(

)

1

11

Table of Contents

Description bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 1

Supported Screen Formats 2 Software Driver Support 2 Interface Descriptions 3 Feature Descriptions 5

Block Diagrams and Features bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 7

System Black Diagram 7 011-087 Operational Blod Diagram 8 011-087 on 486 Local Bus 9 011-087 on 386DX Local Bus 10 Memory Interface Diagrams 11 Memory Mapping Configuration 16

1111 1

Pin Descriptions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 11

AT-Bus Interfacebullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull17 Local Bus Interface 19 Clock Interface 20 CRT and Color Palette Interface 21 Video Memory Interface 22 EEPROM Interface 23 Power amp Ground 23 Pin Out Cross Reference for OTI-087 in Different COnfigurations 24 Pin Diagrams 26

111 1 11

OTI-087 Register Definitions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 29

Configuration Registers On-087 Extended Regiumlsters _

29 31

OTI-08 AC Timing and DC middotParameters _ 47

Video Memory Cycle Timing _ 47

[

Video ROM Cycle Timing 48 Video Pixel Timing Video DAC va Timing Video VO Access Timing _

_ _bullbull_

49 51

_bullbull52 Local Bus Interface Timing _ 53 DUM Interface Timing amp Memory Refresh TImicircngbullbullbullbullbullbull_ _bullbullbullbullbull_ 55 OC Specification _ _ _ _bullbull~bull 51

1

1

~ -t bull

Package Oudines 58

Example Schematics ~ ~ 60

VR5A Iocal Bus ISA Bus

60 66

shy ~

1 Overvlew

bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

Ycs Yel Yel Ycs

2561lt 2561lt 2561lt 2561lt

NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

Yel Yes

512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

lM lM

Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

lt t)p

011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

- ~~ ~ 07-

ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

shy

SYSTEM BUS

OTl-06S VIDEO AND

MEMORY CLOCK

SOURCE

lt shy5D170]DATA BUS (7-0)

SDI156]DATA BUS (15-8) )f( vJ

SA[190]ADOIlESS BUS~ v

~ CONTROL

VLCK i CStLO

CStL1

J CSEL2

J CSEL3

MCLK

~ANALOG MONITOR (ANAlOG RGB)

1

i 24-BIT DIRECT COLOR

PALETTE DAC j

li l li

c 9- 0 U t=

~ t~ Cl liA

PCLK

BLANKnOn-087 LOCAL BUS VGA

GRAPIDCS HampVSYNC

-

CONTROllER

99 agrave9lo - B~ 0i~~ ~ ~

1I~lI

~ ~~ Cl ~ ~0lt1( if 8

DISPLAY MEMORY

1

1 1

1--shy

shy1-- shy

1 bull

(OTI-o~7 OperationaI Block Dlagram

INTERNAL DATA BUS

lt==

CRTC shy-CONTROLLER

~

Reglster gt

~ATTRIBUTE 7~ CONTROlLER

J Data

RWReglster

~

cache

Bltblt AssIst HW

GRAPHICS CONTROLLER lt===shy

~ 12 i

C UumlC

i Data-lt ~ 0 19

li)

euml gt~ Data flFO~

8 ct

u J FIFO Control

Reglster ~

SA23O] MA9 Cadte

L Tas 1shy7

SEQUENŒR

shy shy

M16njSRDY IOCHRDY

AEN RfSHn MRDn MWRn 1016n HLDA

ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

BD6jCPUBHEn BD7jCPURESET

SDI150] CINTn

ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

~

shy

-~

- ~

~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

~ sectI~ i~~

Il~~ 2~

il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

0[70) D7O)

11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

OEn D

X icirc A1ll2)If

J~

SAlll2)

V BUFfE aBUFFElB

DlIl Note4 mJ)A iClOEn i

ATSAlZZ11ATSDl158)

IIIs ca

G s

Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

)J

1 5 ~ ft 3~ ~I~

91

a~ ~j 22

~

BSI6n l

(

Z

PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

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JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

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u_ln

L

u

L

ua o La 0

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I

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LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

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087C021093-oo1

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Page 2: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

(

OTI-087X Addendum to the Databook

1 1 1

1 This Addendum describes changes to the OTI-087 February 1993 databook for OTI-087X parts The OTI-087X currently does not support the RAS only refresh DRAM 2608 type DRAM and integrated feature connector support

~ Description 1 Disregard the reference to RAS only refresh in the feature liste This is currently

not supported

8 Disregard CASOn CAS1n CAS2n and CAS3n signaIs on the Operational Block Diagram

13 This MD interface is not supported with this OTI-087 revision

i l 16 Disregard CASOn CAS1n CAS2n and CAS3n signaIs on the Memory Mapping

i Configuration

1 25 EPDATA should be DCn under the OU-087 (LB386486) co1urnn

28 Pin 99 on OTI-087 (LB 386486) should be DCn

37 Extended Register 8 bits 6 10 should be as below AIso pin 99 does not apply

Bits 6 1 0 Pin 19 Pin 20 101 EPCLK EPDATA 110 EPCLK EPDATA

Bit 7 Reserved

60 See attached for new Local Bus Schematics

r--- - -(--

31194

OTI-087 Drivers List

ution s ~RS

~AD262 x ~AD 910111112 x x x x x x x x x hadc 1020 x x x x x mce4041 x x x ~odeII x x 132x254360 =wode III x x 132x254360

331 x x x x 12320x x x 132x2543 12322 x x x x 132x254360 123 3031 x x x x resolution dependent 140 x 21 x x x D4S x x x ua 1l x ua 20 x x x x lCAD60 x x x x x lCADl386 60 x x x x x ~TSR x x x x 132x2543608Ox60 lPerfect SO x lPerfect S1 x x x x 132x254360

lowa31 x x x x x x x x x x x x x x x x lowaNf 31 x x x x x x x x

=se resolutioDS are oDly IUpported by 00-087 due to the requirement of 2Mbytes ofvideo memory

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1 1 1 1 1 1 1 J 1 1 1 1 1 1 1 l 1

Prefa~e

The information eontained in this document has been carefully checked and is be1ieved to be reliable However Oak Technology Incmakes no guarantee or warranty conceming the saidinformationand shaH not be responsible for any 10ss or damage of whatever nature resulting from the use of or relianee upon it Oak Teehnology Ine does not guarantee that the use of any information eontained herein will not infringe upon the patent or other rights of third parties and no patent or other Iicense is implied hereby

This document does not in any way extend Oak Technology Ines warranty on any produet beyond that set forth in its standard terms and conditions of sale Oak Technology Ine reserves the rightto make changes in the produets or specifications or both presented in this publication at any time and without notice

Life Support Applications

Oak Technology Ine produets are not intended for use as critical eomponents in life support appliances deviees or systems in which the failure of an Oak Technology Ine product to perform eould reasonably he expeeted to result in personal injury

February 1993

--

(

)

1

11

Table of Contents

Description bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 1

Supported Screen Formats 2 Software Driver Support 2 Interface Descriptions 3 Feature Descriptions 5

Block Diagrams and Features bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 7

System Black Diagram 7 011-087 Operational Blod Diagram 8 011-087 on 486 Local Bus 9 011-087 on 386DX Local Bus 10 Memory Interface Diagrams 11 Memory Mapping Configuration 16

1111 1

Pin Descriptions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 11

AT-Bus Interfacebullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull17 Local Bus Interface 19 Clock Interface 20 CRT and Color Palette Interface 21 Video Memory Interface 22 EEPROM Interface 23 Power amp Ground 23 Pin Out Cross Reference for OTI-087 in Different COnfigurations 24 Pin Diagrams 26

111 1 11

OTI-087 Register Definitions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 29

Configuration Registers On-087 Extended Regiumlsters _

29 31

OTI-08 AC Timing and DC middotParameters _ 47

Video Memory Cycle Timing _ 47

[

Video ROM Cycle Timing 48 Video Pixel Timing Video DAC va Timing Video VO Access Timing _

_ _bullbull_

49 51

_bullbull52 Local Bus Interface Timing _ 53 DUM Interface Timing amp Memory Refresh TImicircngbullbullbullbullbullbull_ _bullbullbullbullbull_ 55 OC Specification _ _ _ _bullbull~bull 51

1

1

~ -t bull

Package Oudines 58

Example Schematics ~ ~ 60

VR5A Iocal Bus ISA Bus

60 66

shy ~

1 Overvlew

bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

Ycs Yel Yel Ycs

2561lt 2561lt 2561lt 2561lt

NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

Yel Yes

512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

lM lM

Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

lt t)p

011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

- ~~ ~ 07-

ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

shy

SYSTEM BUS

OTl-06S VIDEO AND

MEMORY CLOCK

SOURCE

lt shy5D170]DATA BUS (7-0)

SDI156]DATA BUS (15-8) )f( vJ

SA[190]ADOIlESS BUS~ v

~ CONTROL

VLCK i CStLO

CStL1

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MCLK

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1

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GRAPIDCS HampVSYNC

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BD4jCPUAO BDSjCPUA1

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DACWRn PROCLKROMENn

VCLK MClK

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Page 8

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PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

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u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

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LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

~ccedil ~C

t-C-28-~C-Z-7-~-C-2-lC2 teI2r-1I~lt1ar-Tltln4Ihe15o-JJe2bteJ2I-JC8--1SC32--kC5-2--~C53 ~ li 22Ufiuml 2U~22uroZ2UF ~lUF1ii IlIr1ii lUr1iilUrlOluF19middot1UF1O lUlf lUF1l lUCID lU

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I ~

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(

OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

- - - - - - - - - - - -

bullbull

1

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

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Page 3: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

OTI-087X Addendum to the Databook

1 1 1

1 This Addendum describes changes to the OTI-087 February 1993 databook for OTI-087X parts The OTI-087X currently does not support the RAS only refresh DRAM 2608 type DRAM and integrated feature connector support

~ Description 1 Disregard the reference to RAS only refresh in the feature liste This is currently

not supported

8 Disregard CASOn CAS1n CAS2n and CAS3n signaIs on the Operational Block Diagram

13 This MD interface is not supported with this OTI-087 revision

i l 16 Disregard CASOn CAS1n CAS2n and CAS3n signaIs on the Memory Mapping

i Configuration

1 25 EPDATA should be DCn under the OU-087 (LB386486) co1urnn

28 Pin 99 on OTI-087 (LB 386486) should be DCn

37 Extended Register 8 bits 6 10 should be as below AIso pin 99 does not apply

Bits 6 1 0 Pin 19 Pin 20 101 EPCLK EPDATA 110 EPCLK EPDATA

Bit 7 Reserved

60 See attached for new Local Bus Schematics

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OTI-087 Drivers List

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lowa31 x x x x x x x x x x x x x x x x lowaNf 31 x x x x x x x x

=se resolutioDS are oDly IUpported by 00-087 due to the requirement of 2Mbytes ofvideo memory

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1 1 1 1 1 1 1 J 1 1 1 1 1 1 1 l 1

Prefa~e

The information eontained in this document has been carefully checked and is be1ieved to be reliable However Oak Technology Incmakes no guarantee or warranty conceming the saidinformationand shaH not be responsible for any 10ss or damage of whatever nature resulting from the use of or relianee upon it Oak Teehnology Ine does not guarantee that the use of any information eontained herein will not infringe upon the patent or other rights of third parties and no patent or other Iicense is implied hereby

This document does not in any way extend Oak Technology Ines warranty on any produet beyond that set forth in its standard terms and conditions of sale Oak Technology Ine reserves the rightto make changes in the produets or specifications or both presented in this publication at any time and without notice

Life Support Applications

Oak Technology Ine produets are not intended for use as critical eomponents in life support appliances deviees or systems in which the failure of an Oak Technology Ine product to perform eould reasonably he expeeted to result in personal injury

February 1993

--

(

)

1

11

Table of Contents

Description bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 1

Supported Screen Formats 2 Software Driver Support 2 Interface Descriptions 3 Feature Descriptions 5

Block Diagrams and Features bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 7

System Black Diagram 7 011-087 Operational Blod Diagram 8 011-087 on 486 Local Bus 9 011-087 on 386DX Local Bus 10 Memory Interface Diagrams 11 Memory Mapping Configuration 16

1111 1

Pin Descriptions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 11

AT-Bus Interfacebullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull17 Local Bus Interface 19 Clock Interface 20 CRT and Color Palette Interface 21 Video Memory Interface 22 EEPROM Interface 23 Power amp Ground 23 Pin Out Cross Reference for OTI-087 in Different COnfigurations 24 Pin Diagrams 26

111 1 11

OTI-087 Register Definitions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 29

Configuration Registers On-087 Extended Regiumlsters _

29 31

OTI-08 AC Timing and DC middotParameters _ 47

Video Memory Cycle Timing _ 47

[

Video ROM Cycle Timing 48 Video Pixel Timing Video DAC va Timing Video VO Access Timing _

_ _bullbull_

49 51

_bullbull52 Local Bus Interface Timing _ 53 DUM Interface Timing amp Memory Refresh TImicircngbullbullbullbullbullbull_ _bullbullbullbullbull_ 55 OC Specification _ _ _ _bullbull~bull 51

1

1

~ -t bull

Package Oudines 58

Example Schematics ~ ~ 60

VR5A Iocal Bus ISA Bus

60 66

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bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

Ycs Yel Yel Ycs

2561lt 2561lt 2561lt 2561lt

NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

Yel Yes

512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

lM lM

Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

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011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

- ~~ ~ 07-

ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

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SYSTEM BUS

OTl-06S VIDEO AND

MEMORY CLOCK

SOURCE

lt shy5D170]DATA BUS (7-0)

SDI156]DATA BUS (15-8) )f( vJ

SA[190]ADOIlESS BUS~ v

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VLCK i CStLO

CStL1

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GRAPIDCS HampVSYNC

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ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

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-~

- ~

~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

~ sectI~ i~~

Il~~ 2~

il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

0[70) D7O)

11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

OEn D

X icirc A1ll2)If

J~

SAlll2)

V BUFfE aBUFFElB

DlIl Note4 mJ)A iClOEn i

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IIIs ca

G s

Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

)J

1 5 ~ ft 3~ ~I~

91

a~ ~j 22

~

BSI6n l

(

Z

PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Prefa~e

The information eontained in this document has been carefully checked and is be1ieved to be reliable However Oak Technology Incmakes no guarantee or warranty conceming the saidinformationand shaH not be responsible for any 10ss or damage of whatever nature resulting from the use of or relianee upon it Oak Teehnology Ine does not guarantee that the use of any information eontained herein will not infringe upon the patent or other rights of third parties and no patent or other Iicense is implied hereby

This document does not in any way extend Oak Technology Ines warranty on any produet beyond that set forth in its standard terms and conditions of sale Oak Technology Ine reserves the rightto make changes in the produets or specifications or both presented in this publication at any time and without notice

Life Support Applications

Oak Technology Ine produets are not intended for use as critical eomponents in life support appliances deviees or systems in which the failure of an Oak Technology Ine product to perform eould reasonably he expeeted to result in personal injury

February 1993

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1

11

Table of Contents

Description bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 1

Supported Screen Formats 2 Software Driver Support 2 Interface Descriptions 3 Feature Descriptions 5

Block Diagrams and Features bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 7

System Black Diagram 7 011-087 Operational Blod Diagram 8 011-087 on 486 Local Bus 9 011-087 on 386DX Local Bus 10 Memory Interface Diagrams 11 Memory Mapping Configuration 16

1111 1

Pin Descriptions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 11

AT-Bus Interfacebullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull17 Local Bus Interface 19 Clock Interface 20 CRT and Color Palette Interface 21 Video Memory Interface 22 EEPROM Interface 23 Power amp Ground 23 Pin Out Cross Reference for OTI-087 in Different COnfigurations 24 Pin Diagrams 26

111 1 11

OTI-087 Register Definitions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 29

Configuration Registers On-087 Extended Regiumlsters _

29 31

OTI-08 AC Timing and DC middotParameters _ 47

Video Memory Cycle Timing _ 47

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Video ROM Cycle Timing 48 Video Pixel Timing Video DAC va Timing Video VO Access Timing _

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49 51

_bullbull52 Local Bus Interface Timing _ 53 DUM Interface Timing amp Memory Refresh TImicircngbullbullbullbullbullbull_ _bullbullbullbullbull_ 55 OC Specification _ _ _ _bullbull~bull 51

1

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VR5A Iocal Bus ISA Bus

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bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

Ycs Yel Yel Ycs

2561lt 2561lt 2561lt 2561lt

NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

Yel Yes

512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

lM lM

Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

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middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

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011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

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1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

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ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

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OTI-oS7 Block Diagrams

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~ATTRIBUTE 7~ CONTROlLER

J Data

RWReglster

~

cache

Bltblt AssIst HW

GRAPHICS CONTROLLER lt===shy

~ 12 i

C UumlC

i Data-lt ~ 0 19

li)

euml gt~ Data flFO~

8 ct

u J FIFO Control

Reglster ~

SA23O] MA9 Cadte

L Tas 1shy7

SEQUENŒR

shy shy

M16njSRDY IOCHRDY

AEN RfSHn MRDn MWRn 1016n HLDA

ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

BD6jCPUBHEn BD7jCPURESET

SDI150] CINTn

ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

~

shy

-~

- ~

~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

~ sectI~ i~~

Il~~ 2~

il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

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11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

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SAlll2)

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Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

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1 5 ~ ft 3~ ~I~

91

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PAL Atgt Al BHEn

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DAC DIPSWlTOl

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RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

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001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 5: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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Prefa~e

The information eontained in this document has been carefully checked and is be1ieved to be reliable However Oak Technology Incmakes no guarantee or warranty conceming the saidinformationand shaH not be responsible for any 10ss or damage of whatever nature resulting from the use of or relianee upon it Oak Teehnology Ine does not guarantee that the use of any information eontained herein will not infringe upon the patent or other rights of third parties and no patent or other Iicense is implied hereby

This document does not in any way extend Oak Technology Ines warranty on any produet beyond that set forth in its standard terms and conditions of sale Oak Technology Ine reserves the rightto make changes in the produets or specifications or both presented in this publication at any time and without notice

Life Support Applications

Oak Technology Ine produets are not intended for use as critical eomponents in life support appliances deviees or systems in which the failure of an Oak Technology Ine product to perform eould reasonably he expeeted to result in personal injury

February 1993

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1

11

Table of Contents

Description bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 1

Supported Screen Formats 2 Software Driver Support 2 Interface Descriptions 3 Feature Descriptions 5

Block Diagrams and Features bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 7

System Black Diagram 7 011-087 Operational Blod Diagram 8 011-087 on 486 Local Bus 9 011-087 on 386DX Local Bus 10 Memory Interface Diagrams 11 Memory Mapping Configuration 16

1111 1

Pin Descriptions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 11

AT-Bus Interfacebullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull17 Local Bus Interface 19 Clock Interface 20 CRT and Color Palette Interface 21 Video Memory Interface 22 EEPROM Interface 23 Power amp Ground 23 Pin Out Cross Reference for OTI-087 in Different COnfigurations 24 Pin Diagrams 26

111 1 11

OTI-087 Register Definitions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 29

Configuration Registers On-087 Extended Regiumlsters _

29 31

OTI-08 AC Timing and DC middotParameters _ 47

Video Memory Cycle Timing _ 47

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Video ROM Cycle Timing 48 Video Pixel Timing Video DAC va Timing Video VO Access Timing _

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49 51

_bullbull52 Local Bus Interface Timing _ 53 DUM Interface Timing amp Memory Refresh TImicircngbullbullbullbullbullbull_ _bullbullbullbullbull_ 55 OC Specification _ _ _ _bullbull~bull 51

1

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Package Oudines 58

Example Schematics ~ ~ 60

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bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

Ycs Yel Yel Ycs

2561lt 2561lt 2561lt 2561lt

NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

Yel Yes

512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

lM lM

Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

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011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

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ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

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OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

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99 agrave9lo - B~ 0i~~ ~ ~

1I~lI

~ ~~ Cl ~ ~0lt1( if 8

DISPLAY MEMORY

1

1 1

1--shy

shy1-- shy

1 bull

(OTI-o~7 OperationaI Block Dlagram

INTERNAL DATA BUS

lt==

CRTC shy-CONTROLLER

~

Reglster gt

~ATTRIBUTE 7~ CONTROlLER

J Data

RWReglster

~

cache

Bltblt AssIst HW

GRAPHICS CONTROLLER lt===shy

~ 12 i

C UumlC

i Data-lt ~ 0 19

li)

euml gt~ Data flFO~

8 ct

u J FIFO Control

Reglster ~

SA23O] MA9 Cadte

L Tas 1shy7

SEQUENŒR

shy shy

M16njSRDY IOCHRDY

AEN RfSHn MRDn MWRn 1016n HLDA

ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

BD6jCPUBHEn BD7jCPURESET

SDI150] CINTn

ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

~

shy

-~

- ~

~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

~ sectI~ i~~

Il~~ 2~

il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

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11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

OEn D

X icirc A1ll2)If

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SAlll2)

V BUFfE aBUFFElB

DlIl Note4 mJ)A iClOEn i

ATSAlZZ11ATSDl158)

IIIs ca

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Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

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1 5 ~ ft 3~ ~I~

91

a~ ~j 22

~

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Z

PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

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Page 6: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

~ middot

1 1 1 1 1 1 1 J 1 1 1 1 1 1 1 l 1

Prefa~e

The information eontained in this document has been carefully checked and is be1ieved to be reliable However Oak Technology Incmakes no guarantee or warranty conceming the saidinformationand shaH not be responsible for any 10ss or damage of whatever nature resulting from the use of or relianee upon it Oak Teehnology Ine does not guarantee that the use of any information eontained herein will not infringe upon the patent or other rights of third parties and no patent or other Iicense is implied hereby

This document does not in any way extend Oak Technology Ines warranty on any produet beyond that set forth in its standard terms and conditions of sale Oak Technology Ine reserves the rightto make changes in the produets or specifications or both presented in this publication at any time and without notice

Life Support Applications

Oak Technology Ine produets are not intended for use as critical eomponents in life support appliances deviees or systems in which the failure of an Oak Technology Ine product to perform eould reasonably he expeeted to result in personal injury

February 1993

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(

)

1

11

Table of Contents

Description bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 1

Supported Screen Formats 2 Software Driver Support 2 Interface Descriptions 3 Feature Descriptions 5

Block Diagrams and Features bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 7

System Black Diagram 7 011-087 Operational Blod Diagram 8 011-087 on 486 Local Bus 9 011-087 on 386DX Local Bus 10 Memory Interface Diagrams 11 Memory Mapping Configuration 16

1111 1

Pin Descriptions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 11

AT-Bus Interfacebullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull17 Local Bus Interface 19 Clock Interface 20 CRT and Color Palette Interface 21 Video Memory Interface 22 EEPROM Interface 23 Power amp Ground 23 Pin Out Cross Reference for OTI-087 in Different COnfigurations 24 Pin Diagrams 26

111 1 11

OTI-087 Register Definitions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 29

Configuration Registers On-087 Extended Regiumlsters _

29 31

OTI-08 AC Timing and DC middotParameters _ 47

Video Memory Cycle Timing _ 47

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Video ROM Cycle Timing 48 Video Pixel Timing Video DAC va Timing Video VO Access Timing _

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49 51

_bullbull52 Local Bus Interface Timing _ 53 DUM Interface Timing amp Memory Refresh TImicircngbullbullbullbullbullbull_ _bullbullbullbullbull_ 55 OC Specification _ _ _ _bullbull~bull 51

1

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Package Oudines 58

Example Schematics ~ ~ 60

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bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

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NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

Yel Yes

512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

lM lM

Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

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011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

- ~~ ~ 07-

ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

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SYSTEM BUS

OTl-06S VIDEO AND

MEMORY CLOCK

SOURCE

lt shy5D170]DATA BUS (7-0)

SDI156]DATA BUS (15-8) )f( vJ

SA[190]ADOIlESS BUS~ v

~ CONTROL

VLCK i CStLO

CStL1

J CSEL2

J CSEL3

MCLK

~ANALOG MONITOR (ANAlOG RGB)

1

i 24-BIT DIRECT COLOR

PALETTE DAC j

li l li

c 9- 0 U t=

~ t~ Cl liA

PCLK

BLANKnOn-087 LOCAL BUS VGA

GRAPIDCS HampVSYNC

-

CONTROllER

99 agrave9lo - B~ 0i~~ ~ ~

1I~lI

~ ~~ Cl ~ ~0lt1( if 8

DISPLAY MEMORY

1

1 1

1--shy

shy1-- shy

1 bull

(OTI-o~7 OperationaI Block Dlagram

INTERNAL DATA BUS

lt==

CRTC shy-CONTROLLER

~

Reglster gt

~ATTRIBUTE 7~ CONTROlLER

J Data

RWReglster

~

cache

Bltblt AssIst HW

GRAPHICS CONTROLLER lt===shy

~ 12 i

C UumlC

i Data-lt ~ 0 19

li)

euml gt~ Data flFO~

8 ct

u J FIFO Control

Reglster ~

SA23O] MA9 Cadte

L Tas 1shy7

SEQUENŒR

shy shy

M16njSRDY IOCHRDY

AEN RfSHn MRDn MWRn 1016n HLDA

ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

BD6jCPUBHEn BD7jCPURESET

SDI150] CINTn

ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

~

shy

-~

- ~

~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

~ sectI~ i~~

Il~~ 2~

il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

0[70) D7O)

11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

OEn D

X icirc A1ll2)If

J~

SAlll2)

V BUFfE aBUFFElB

DlIl Note4 mJ)A iClOEn i

ATSAlZZ11ATSDl158)

IIIs ca

G s

Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

)J

1 5 ~ ft 3~ ~I~

91

a~ ~j 22

~

BSI6n l

(

Z

PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

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Page 7: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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11

Table of Contents

Description bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 1

Supported Screen Formats 2 Software Driver Support 2 Interface Descriptions 3 Feature Descriptions 5

Block Diagrams and Features bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 7

System Black Diagram 7 011-087 Operational Blod Diagram 8 011-087 on 486 Local Bus 9 011-087 on 386DX Local Bus 10 Memory Interface Diagrams 11 Memory Mapping Configuration 16

1111 1

Pin Descriptions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 11

AT-Bus Interfacebullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull17 Local Bus Interface 19 Clock Interface 20 CRT and Color Palette Interface 21 Video Memory Interface 22 EEPROM Interface 23 Power amp Ground 23 Pin Out Cross Reference for OTI-087 in Different COnfigurations 24 Pin Diagrams 26

111 1 11

OTI-087 Register Definitions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 29

Configuration Registers On-087 Extended Regiumlsters _

29 31

OTI-08 AC Timing and DC middotParameters _ 47

Video Memory Cycle Timing _ 47

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Video ROM Cycle Timing 48 Video Pixel Timing Video DAC va Timing Video VO Access Timing _

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49 51

_bullbull52 Local Bus Interface Timing _ 53 DUM Interface Timing amp Memory Refresh TImicircngbullbullbullbullbullbull_ _bullbullbullbullbull_ 55 OC Specification _ _ _ _bullbull~bull 51

1

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bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

Ycs Yel Yel Ycs

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NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

Yel Yes

512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

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Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

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middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

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011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

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1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

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ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

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OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

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PCLK

BLANKnOn-087 LOCAL BUS VGA

GRAPIDCS HampVSYNC

-

CONTROllER

99 agrave9lo - B~ 0i~~ ~ ~

1I~lI

~ ~~ Cl ~ ~0lt1( if 8

DISPLAY MEMORY

1

1 1

1--shy

shy1-- shy

1 bull

(OTI-o~7 OperationaI Block Dlagram

INTERNAL DATA BUS

lt==

CRTC shy-CONTROLLER

~

Reglster gt

~ATTRIBUTE 7~ CONTROlLER

J Data

RWReglster

~

cache

Bltblt AssIst HW

GRAPHICS CONTROLLER lt===shy

~ 12 i

C UumlC

i Data-lt ~ 0 19

li)

euml gt~ Data flFO~

8 ct

u J FIFO Control

Reglster ~

SA23O] MA9 Cadte

L Tas 1shy7

SEQUENŒR

shy shy

M16njSRDY IOCHRDY

AEN RfSHn MRDn MWRn 1016n HLDA

ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

BD6jCPUBHEn BD7jCPURESET

SDI150] CINTn

ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

~

shy

-~

- ~

~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

~ sectI~ i~~

Il~~ 2~

il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

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11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

OEn D

X icirc A1ll2)If

J~

SAlll2)

V BUFfE aBUFFElB

DlIl Note4 mJ)A iClOEn i

ATSAlZZ11ATSDl158)

IIIs ca

G s

Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

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1 5 ~ ft 3~ ~I~

91

a~ ~j 22

~

BSI6n l

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Z

PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

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Page 8: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1

11

Table of Contents

Description bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 1

Supported Screen Formats 2 Software Driver Support 2 Interface Descriptions 3 Feature Descriptions 5

Block Diagrams and Features bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 7

System Black Diagram 7 011-087 Operational Blod Diagram 8 011-087 on 486 Local Bus 9 011-087 on 386DX Local Bus 10 Memory Interface Diagrams 11 Memory Mapping Configuration 16

1111 1

Pin Descriptions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 11

AT-Bus Interfacebullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull17 Local Bus Interface 19 Clock Interface 20 CRT and Color Palette Interface 21 Video Memory Interface 22 EEPROM Interface 23 Power amp Ground 23 Pin Out Cross Reference for OTI-087 in Different COnfigurations 24 Pin Diagrams 26

111 1 11

OTI-087 Register Definitions bullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbullbull 29

Configuration Registers On-087 Extended Regiumlsters _

29 31

OTI-08 AC Timing and DC middotParameters _ 47

Video Memory Cycle Timing _ 47

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Video ROM Cycle Timing 48 Video Pixel Timing Video DAC va Timing Video VO Access Timing _

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49 51

_bullbull52 Local Bus Interface Timing _ 53 DUM Interface Timing amp Memory Refresh TImicircngbullbullbullbullbullbull_ _bullbullbullbullbull_ 55 OC Specification _ _ _ _bullbull~bull 51

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Example Schematics ~ ~ 60

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bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

Ycs Yel Yel Ycs

2561lt 2561lt 2561lt 2561lt

NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

Yel Yes

512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

lM lM

Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

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011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

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1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

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ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

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OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

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INTERNAL DATA BUS

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CRTC shy-CONTROLLER

~

Reglster gt

~ATTRIBUTE 7~ CONTROlLER

J Data

RWReglster

~

cache

Bltblt AssIst HW

GRAPHICS CONTROLLER lt===shy

~ 12 i

C UumlC

i Data-lt ~ 0 19

li)

euml gt~ Data flFO~

8 ct

u J FIFO Control

Reglster ~

SA23O] MA9 Cadte

L Tas 1shy7

SEQUENŒR

shy shy

M16njSRDY IOCHRDY

AEN RfSHn MRDn MWRn 1016n HLDA

ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

BD6jCPUBHEn BD7jCPURESET

SDI150] CINTn

ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

~

shy

-~

- ~

~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

~ sectI~ i~~

Il~~ 2~

il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

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11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

OEn D

X icirc A1ll2)If

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SAlll2)

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ATSAlZZ11ATSDl158)

IIIs ca

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Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

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1 5 ~ ft 3~ ~I~

91

a~ ~j 22

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PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 9: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

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Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

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mA NIA Standard

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25175 40000 40000

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800 x 600 1280 x 1024

32K 256

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100 x 375 160 x 64

78000 78000

3750 4875

60 87

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5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

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011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

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ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

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OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

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1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

0[70) D7O)

11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

OEn D

X icirc A1ll2)If

J~

SAlll2)

V BUFfE aBUFFElB

DlIl Note4 mJ)A iClOEn i

ATSAlZZ11ATSDl158)

IIIs ca

G s

Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

)J

1 5 ~ ft 3~ ~I~

91

a~ ~j 22

~

BSI6n l

(

Z

PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

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u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

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LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

~ccedil ~C

t-C-28-~C-Z-7-~-C-2-lC2 teI2r-1I~lt1ar-Tltln4Ihe15o-JJe2bteJ2I-JC8--1SC32--kC5-2--~C53 ~ li 22Ufiuml 2U~22uroZ2UF ~lUF1ii IlIr1ii lUr1iilUrlOluF19middot1UF1O lUlf lUF1l lUCID lU

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CD

I ~

~

(

OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

- - - - - - - - - - - -

bullbull

1

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Page 10: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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1 Overvlew

bull OTI-087 LOCAL BUS VGA CONTROLLER 1

Description

1 The OTI-087 is a highly integrated single chip Local Bus VGA Controller compatible with the mM VGA standard The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being

1 capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality Especial1y attractive for

1 motherboard applications the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies

1 Features

1 bull IBM VGA compatible graphies controller with resolutions up to

1024x768 256 colors Non-Interlaced

1280x1024 256 colors Interlaced

640x480 168 million colors (24-bit)

middot1 bull 100 Hardware and BIOS compatible with IBMs VGA

1 bull Supports up to 2 MBytes of memory

2 4 or 8 64K X 16 DRAMs 2 4 8 or 16 256K X 4 DRAMs

1 2 or 4 256K X 16 DRAMs 2 or 4 S12KX 8 DRAMs

bull Hardware cursor (64x64 2 bitspixel)

bull Integrated feature connector support

1 bull Write cache for high speed local bus implementation

bull Read cache optimizes memory bandwidth usage

bull Integrated zero wait state AT bus performance

1 bull Supports 8 16 or 32-bit memory interface with fast page operation

bull Supports CAS before RAS and RAS only refresh

1 bull Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays

bull Up to 80 MHz maximum video dock rate

bull Complete linear addressability in protected mode

1 bull Packed pixel format for 256 color modes

bull Foregroundbackground color expansion registers for fast tat output

1 bull 16-bit graphies latch for truc 16-bit operations in pIanu modes

bull Special 256 color pattern and fi11 modes incrcase performance

bull Supports 132 column tat

bull bull Integratcd bus interface for PC(YJAT and local bus implcmentations

bull Supports portrait monitors

bull Truc 16-bit 10 readwritc operations

bull EEPROM support provides switchless contigurations 1

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

Ycs Yel Yel Ycs

2561lt 2561lt 2561lt 2561lt

NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

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512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

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Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

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011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

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1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

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ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

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OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

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of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

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JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

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u_ln

L

u

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I

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LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 11: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

Supported Screen Formats ( J The OTI-087 not onir supports aU standard IBM VGA modes but the fol1owing extended modes as well

Non- Video Mmk lzh 12h

Resolution 640 x 480 640x 480

~ 16 16

E2nt 8x 16 8x 16

Alpha Format 80x30 80x30

pot Clk(Mfkl 2S175 31500

H-frccedilg(KHz) 3150 3786

V-fuq(Rz) 60 72

Intccedilrlaced Ylaquo Yel

Msmmx 256K 2561lt

mA NIA Standard

4Eh 4Fh SOho

80x60 132 x 60 132 x 25

16 16 16

8x8 8x8 8x 14

80x 60 132x60 132 x25

25175 40000 40000

3150 3150 3150

60 60 70

Ycs Yel Ycs

2561lt 2561lt 2561lt

NIA NIA NIA

51h 52h 52h 52h

132 x 43 800 x 600 800 x 600 800 x 600

16 16 16 16

8x8 8 x 16 8x 16 8x 16

132x 43 100 x 375 100 x 375middot 100 x 375

40000 36000 40000 50000

3150 3516 3788 4808

70 56 60 72

Ycs Yel Yel Ycs

2561lt 2561lt 2561lt 2561lt

NIA MfgGL MfgGL Standard

53h 640 x 480 256 8x 16 80x 30 25175 3150 60 Ycs 512K NIA 53h 640 x 480 256 8x 16 80x 3If 31500 3786 72 Yes 512K Standard 54h S4h

800 x 600 800 x 600

256 256

8 x 16 8 x 16

100 x 375 100 375

36000 40000

3516 3788

56 60

Yel Yes

512K 512K

Mfg GL MfgGL

54h 800 x 600 256 8 x 16 100 x 375 50000 4808 72 Ycs 512K Standard 55h 1024 x 768 4 8 x 16 128 x 48 44900 3552 87 No 256K NIA 55h 1024 x 768 4 8 x 16 128 x 48 65000 4836 60 Ycs 2561lt MfgGL S5h 1024 x 768 4 8 x 16 128x 48 78000 5669 70 Yes 2561lt Standard 55h 1024 x 768 4 8x 16 128 x 48 78000 5804 72 Yes 256K NIA S6h 1024 x 768 16 8x 16 128 x 48 44900 3552 87 No 512K NIA 56h 1024 x 768 16 8x 16 128 x 48 65000 4836 60 Yes 512K MfgGL 56h 1024 x 768 16 8 x 16 128 x 48 78000 5669 70 Ye5 512K Standard 56h 1024 x 768 16 8x 16 128 x 48 78000 5804 72 Yes 512K NIA 57h 768 x 1024 16 8x 16 96x 64 44900 46n 87 No 512K NIA 57h 768 x 1024 16 8x 16 96x 64 65000 5974 55 Yel 512K NIA 58h 1280 x 1024 16 8x 16 160x 64 78000 4875 87 No lM NIA 59hZ 1024 x 768 256 8x 16 128 x 48 44900 3552 87 No lM NIA 59h 1024 x 768 256 8 x 16 128 x 48 65000 4836 60 Yu lM Mfg GL 59h 1024 x 768 256 8x 16 128 x 48 78000 5669 70 Ycs lM Standard S9h 1024 x 768 256 8 x 16 128 x 48 78000 5804 72 Yu lM NIA 5MZ 640 x 480 64K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SM 640x 480 64K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SBh 640x 400 32K64K 8x 16 80x 2S 50000 3150 70 Yes 512K NIA 5Chz 640x 480 32K 8x 16 80x 30 50000 3150 60 Ycs lM NIA SCh 640 X 480 32K 8x 16 80x 30 63000 3786 72 Ycs lM Standard SDh SEh

800 x 600 1280 x 1024

32K 256

8x 16 8x 16

100 x 375 160 x 64

78000 78000

3750 4875

60 87

Ycs No

lM lM

Mfg Gl NIA

5Th 640 x 480 168M 8x 16 80x 30 78000 3155 60 Ycs lM NIA 60h 800 600 64K 8 16 100 375 78000 3750 60 Ycs lM Mfg GL 61h 640 400 256 8x 16 80x25 25175 3150 70 Ycs 2561lt NIA

Software Driver Support

Oak Technology was the first graphies company to promote the importance of the hardware-software driver relationship Thus Oak is committed to providing customers with the most powerful software drivers Oaks software driver support inc1udes the fastest drivers available for popular applications including

AutoCAD OS2 UNIX (ISC amp SCO) AutoShade OS2 Presentation Manager OrCAD CADvance VersaCAD EasyCADF~tCAD GEM VESA BIQS Extensions Microsoft Windows Lotus 1-2-3Symphony WordPerfectjDrawPerfectPlmPerfect Wordstar P-eAD Ventura

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

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011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

- ~~ ~ 07-

ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

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Page 12

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MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

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CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

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0 (PS c D E F _ - 803 lS 1l04cPUAO

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bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

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ua o La 0

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Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

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NOTEI

AND

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ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

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---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

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5TR081 AUDO 5D1Ccedil H5YNC

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10 1110 r~ e A 1

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AD DO HA AD DO ~AO DO Al Dl Al Dl Al Dl A2 D2 A2 D2 A2 D2 AJ D3 A3 D3 A3 D3 A4 A4 AS AS A6 A6 Al Al AB AB

RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

RAS CAS WE

~ SOJ 4n6-70

A 1

AD DO Al Dl A2 D2 A3 D3 A4 AS A6 Al AB

RAS CAS WE OE

SOJ 42i6-70

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Qll

$ 1 MB

Il c 10K

1

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MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

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--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 12: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

Overview 1 Display Memory Interface

1 The On-087 supports 64Kx16 256Kx4 256Kx16 and 512Kx8 DRAM devices The On-D87 provides aU the necessary control signaIs and address and data tines to access the video memory in page mode The control

1 signaIs can be programmed to optimize memory cycles for a given memory type and speed for a specifie memory clock The maximum video buffer size is 2Mbytes when used with 256Kx4 256Kx16 or 512Kx8 DRAMs and IMbyte when used with 64Kx16 DRAMs Minimum configuration is 256Kbytes when used with 64Kx16 or 256Kx4 DRAMs and IMbyte when used with 512KxS or 256Kx16 DRAM The video buffer can be

1 addressed through either a programmable Iinear address range above lM or through the conventional video address (AOOOa to BFFFFH) using the segment registers

1 Clock Interface

Up to 16 external video clock frequencies can be se1ected by four programmable dock select pins Video clock frequencies up to SO MHz can be supported When implemented with the 011-068 Dual Clock Generator the On-DS7 can select sixteen pixel clock frequencies providing support for both conventional and flicker-free VESA vertical refresh rates without any hardware switches The 011-068 also supports three memory clock frequencies which can be selected through hardware configuration to optimize performance with a wide variety

1 of DRAM types and speeds

l

middot1 System Bus Interface The system bus of the On-oS7 can be conneeted to the PC system in three different configurations on-board local bus add-on local bus and on-board AT bus The On-087 can also be connected to the AT bus The

1 mode of operation is defined by the Configuration Register 1 status set through the MD[70] bus during reset time

1 System Configuration Bit 2 Bitl Local Bus o 0 Local Bus Add-on o 1

1 On-board AT 1 0 Add-onAT 1 1

1 Local Bus Interface In Local Bus configuration the On-D87 can interface to the 80286 80386SX 80386DX and 80486 CPUs

1 Configuration of the OTI-D87 for the proper CPU local bus is accomplished through the ADSn pin and the Configuration Regina 2 as detailed in the table be1ow Configuration Regista 2 is set through the MD[158] bus during reset

1 Local Bus Mode AI2SJ1 llitl ~ 80286 Local Bus 0 0 0

1 S0386SX Local Bus 1 0 0 80386DX Local Bus 1 0 1 80486 Local Bus 1 1 0

To ensure the above detectIumlon scheme will operate properly a weak puIl-down resistor should he conneaed to the ADSn pin of the OTI~87 Since the 80286 processor does not have AOSn this signal should remain low during reset in 80286 designs For proper operation in 80386 and 80486 processor designs this signal will he reset high

lt t)p

011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

- ~~ ~ 07-

ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

shy

SYSTEM BUS

OTl-06S VIDEO AND

MEMORY CLOCK

SOURCE

lt shy5D170]DATA BUS (7-0)

SDI156]DATA BUS (15-8) )f( vJ

SA[190]ADOIlESS BUS~ v

~ CONTROL

VLCK i CStLO

CStL1

J CSEL2

J CSEL3

MCLK

~ANALOG MONITOR (ANAlOG RGB)

1

i 24-BIT DIRECT COLOR

PALETTE DAC j

li l li

c 9- 0 U t=

~ t~ Cl liA

PCLK

BLANKnOn-087 LOCAL BUS VGA

GRAPIDCS HampVSYNC

-

CONTROllER

99 agrave9lo - B~ 0i~~ ~ ~

1I~lI

~ ~~ Cl ~ ~0lt1( if 8

DISPLAY MEMORY

1

1 1

1--shy

shy1-- shy

1 bull

(OTI-o~7 OperationaI Block Dlagram

INTERNAL DATA BUS

lt==

CRTC shy-CONTROLLER

~

Reglster gt

~ATTRIBUTE 7~ CONTROlLER

J Data

RWReglster

~

cache

Bltblt AssIst HW

GRAPHICS CONTROLLER lt===shy

~ 12 i

C UumlC

i Data-lt ~ 0 19

li)

euml gt~ Data flFO~

8 ct

u J FIFO Control

Reglster ~

SA23O] MA9 Cadte

L Tas 1shy7

SEQUENŒR

shy shy

M16njSRDY IOCHRDY

AEN RfSHn MRDn MWRn 1016n HLDA

ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

BD6jCPUBHEn BD7jCPURESET

SDI150] CINTn

ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

~

shy

-~

- ~

~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

~ sectI~ i~~

Il~~ 2~

il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

0[70) D7O)

11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

OEn D

X icirc A1ll2)If

J~

SAlll2)

V BUFfE aBUFFElB

DlIl Note4 mJ)A iClOEn i

ATSAlZZ11ATSDl158)

IIIs ca

G s

Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

)J

1 5 ~ ft 3~ ~I~

91

a~ ~j 22

~

BSI6n l

(

Z

PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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00

r--80

1098 (2790)

-- --0

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1 40

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---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

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011-087 VESA Local Bus Schematlcs

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 13: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

lt t)p

011-087 Local Bus with 80286 and S0386SX Processors

The local b~s interface of the OTI-DS7 provides an optimal implementation for S0286 and 80386SX designs which use Oak Technologys On-D20 system chipset An implementation of the On-D87 with the On-D20 requires no externallogic for local bus interface

The video space of the OTI-D870n-D20 local bus video system is defined by the VIDEO1 register (port 1F index 5) When any one of the video segments in this register is enabled the OTI-D20 system chipset gene~ ates a video cycle to the external bus and terminates the CPU cycle If the video segments are disabled the local bus On-DS7 will terrninate the CPU cycle Graphies Register 3DFH Index 6 only affects the access to video memory and has no effect on the generation of SRDY At system boot-up time the system will scan for the presence of any off-board memory which occupies the AOOOO-BFFFFH range If off-board video memory is detected the VIDEOl register (present in both the On-D20 system chipset and the On-D87) will be proshygrammed so that the local bus system responds to aIl the mernory in AOOOO-BFFFF

H excluding the enabled

segments in the VIDEOl register

The On-D87 supports 16-bit zero-wait-state CPU memory operations through the CPU local bus The onshy087 uniquely employs both a read cache and a write cache to achieve zero-wait-state rnernory operations for local bus speeds up to 33 MHz During the CPU rnemory cycle the On-DS7 interprets the status Hnes (WRn and DCn) and the address CA19-CA17 (101H) gated with the VIDEOl register to generate a local bus memory cycle If the requested data is already inside the OTI-087 read cache during a rnernory read SRDY is returned in the next CPU clock thus a zero-wait-state memory cycle Otherwise SRDY is not returned until the data is read from the video memory and driven out to the bus For writes to video memory a rnemory write request is stored inside the write cache and SRDY is returned in the next CPU clock for a zero-wait-state memory cycle ( If either the write cache is full or the write address does not share the same cache page as the previous write then SRDY is not returned until the data is aetually written to the video memory

The On-087 supports 16-bit IIO access and 8-bit memory access for DMA and MASTER cycles During a DMA or MASfER cycle the On-D87 receives 10 and memory commands from the AT-bus and transfers data to the local SD bus as if it were a 16-bit device In this case both SD[70] and SD[158] are driven with the same data During IIO cycles the On-D87 receives commands from the AT-bus and transfers data on the local bus The system chipset is responsible for routing the address and data to and from the AT-bus

80386DX and 80486 Local Bus

This section refers to the 80386DXS0486 block diagrams following this section The On-D87 requires four buffers (ABEF in the diagram) and 1 PAL to interface with the 80386DX CPU Two additional buffers (CD in the diagram) are required to interface with the 80486 CPU The PAL is used to decode the upper address of the CPU and generate the CPU address 01 and the CPUBHEn signal for the On-DS7 The AB buffers are used to interface the On-D87 data bus to AT-data bus while the CDEF buffers are used to interface the onshy0amp7 data bus to the CPU data bus

During 10 DMA or MASfER cycles the On-D87 receives bus commands from the AT-bus During a CPU memory cycle the On-D87 will use the CPUAOAlBHEn signals to execute the cycle The LBSELn signal is the protocol between the system chipset and the On-D87 to determine ownership of the current memory cycle If the current memory cycle belongs to the On-DS7 address space the On-DS7 forces the LBSELn signallow L at the beginning ofT2 and terminates the cycle with SRDY If the current memory cycle does not be10ng to the On-D87 address space the system chipset should terminate the cycle In 80386DX and S0486 configura-

Page 4

1

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

- ~~ ~ 07-

ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

shy

SYSTEM BUS

OTl-06S VIDEO AND

MEMORY CLOCK

SOURCE

lt shy5D170]DATA BUS (7-0)

SDI156]DATA BUS (15-8) )f( vJ

SA[190]ADOIlESS BUS~ v

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J CSEL3

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1

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~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

~ sectI~ i~~

Il~~ 2~

il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

0[70) D7O)

11 JI

1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

l

AT BUS

agrave

l shy)

L- OEn D

X 1 l D[158) ) BUFFEIlE

V lt

OEn D

1 l 0[701

BUFFU F~ ~ L-

OEn D

X icirc A1ll2)If

J~

SAlll2)

V BUFfE aBUFFElB

DlIl Note4 mJ)A iClOEn i

ATSAlZZ11ATSDl158)

IIIs ca

G s

Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

lOi i ~ lOt~z~a2i~~~I~

)J

1 5 ~ ft 3~ ~I~

91

a~ ~j 22

~

BSI6n l

(

Z

PAL Atgt Al BHEn

Al8 SIl231

DAC DIPSWlTOl

-~ puu-uPjDOW-WIn

RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 14: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

shy

1 Overvlew

tions there are two reset signaIs connected to the OTI-087 The RSET signal is connected to the system reset and the CPURESET is connect to the CPU reset The On-087 uses the CPURESET signal to synchronize the

1 internaI clock and uses the RSET signal to reset the 011-087 If the system chipset does not drive a valid address to the CPU bus during DMA or MASIER cydes then more buffers are necessary to route the address ta the CPU bus Buffer G in 80386DX80486 block diagrams illustrate this implementation

1 Summary of Performance Features

1 The 011-087 implements aIl of the standard state-of-the-art features for high speed frame-buffer graphies controllers These standard features include independent memory and pixel docks support for high refresh displays highly integrated bus interfaces and true 16-bit IjO readwrite operations In addition the 011-087

1 implements several next generation features which advance the state-of-the-art in graphies frame-buffer technolshyogy

11

Hlgh Speed Local Bus

The On-087 is one of the first PC graphies controllers designed from the ground up for motherboard archishytectures implementing direct CPU interfaces to the video controller The local control signals of the OTI-087 provide accelerated system to video memory transfers Timing overhead is also reduced To take advantage of the high transfer rates the 011-087 implements the most features of any frame-buffer controller for assisting

J CPU-based graphies operations

Hardware Cursor

1 The Hardware Cursor (He) increases the overall graphies performance by reducing the need for the CPU to redraw the cursor during each update Also the image under the cursor does not have to be updated by

111 1

software when the cursor is moved Lastly the cursor appears continuously and is more responsive

Wrlte Cache

When writing ta the 011-087 bath data and address are latched from the system bus and the zero-wait-state signal is activated unless the cache is full When implemented in the AT-bus configuration the 011-087 will exhibit zero-wait-state performance in lower resolutioncolor and planar modes In higher resolution the percentage of zero-wait cycles will decrease for packed pixel modes with increasing bus speed resolution color depth and vertical refresh

Read Cache

The read cache of the 011-087 was designed to accelerate bitblt funetions When executing block moves often

11

the next operation requires a read from an adjacent memory location In this case the desired data will be in the read cache and the operation can execute without waiting for a memory cycle

Llnear Addressablllty

In extended video modes where more than 256Kbytes of video buffer are required the video driver must perform segment checking and address ca1culation to detennine a given pixe1s location in video memory At programmable addresses above 1 Mbyte the On-087 provides linear memory mapping thereby diminating segment checking Linear addressing speeds aIl functions when running applications in proteeted-mode

1

1

- ~~ ~ 07-

ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

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SYSTEM BUS

OTl-06S VIDEO AND

MEMORY CLOCK

SOURCE

lt shy5D170]DATA BUS (7-0)

SDI156]DATA BUS (15-8) )f( vJ

SA[190]ADOIlESS BUS~ v

~ CONTROL

VLCK i CStLO

CStL1

J CSEL2

J CSEL3

MCLK

~ANALOG MONITOR (ANAlOG RGB)

1

i 24-BIT DIRECT COLOR

PALETTE DAC j

li l li

c 9- 0 U t=

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PCLK

BLANKnOn-087 LOCAL BUS VGA

GRAPIDCS HampVSYNC

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CONTROllER

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DISPLAY MEMORY

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INTERNAL DATA BUS

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CRTC shy-CONTROLLER

~

Reglster gt

~ATTRIBUTE 7~ CONTROlLER

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RWReglster

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cache

Bltblt AssIst HW

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u J FIFO Control

Reglster ~

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SEQUENŒR

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ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

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MAO 1[80] MA23[80]

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MD Interface for 512Kx 8 DRAMs (

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CASAn CASn MA231801MA9 A90)

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Page 12

1

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OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

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WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

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MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

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MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

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1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

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1

-11 1 1 1

1 1 1 1 1 1 1

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1 1 1 1 1 1

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RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

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MAO 118 1] MA23181] ~OI31241512741

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CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

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RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

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64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

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011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

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Page 62

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v 6 10 _v v ltIv V ~ ~vv V

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~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

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CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

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Pl B19 A1B B19 A19

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Pl Pl Pl~1I10

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856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

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VI 824 AH

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vec Q lU 1 lin An Pl 1131 AU 13

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 15: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

- ~~ ~ 07-

ForegroundBackground Color Expansion ( In packed pixe1 modes the output of simple text becomes more cumbersome To reduce the number of individual memory operations required the OTI()87 contains foregroundbackground co1or expansion registers which a110w eight consecutive bytes to be expanded from one byte containing the foreground or background bits A pixel masking capability is also imp1emented to he able to 1eave specified pixels unshychanged This a1so speeds masked bitb1t funetions

256 Color Patterns and FUis

For packed pixel modes the OTI-087 provides a pattern register for defining patterns and expanding the color information from either OTI-087 registers or CPU data This al10ws fast pattern fill

16-bit Graphies Latch

Most currently availab1e VGA controUers on1y allow for byte operations in many cases The OTI()87 as with previous generations of Oak VGA controllers provides true 16-hit move operations in all situations Relative te other VGA control1ers this is particularly useful for pattern bIts and source copy bitblts where MOVSW instructions can replace MOVSB instructions

EEPROM Support

In a VGA-based video system certain configuration information must be available to the video BIOS It is eommon practice on many video adapter boards to use jumpers or switches to provide the proper settings These switch settings can cause confusion for the consumer To simplify the situation the On-087 provides support for a seriaI EEPROM which stores the specifie configuration information The configuration is done through software eliminating a11 jumpers and switches

80 Mbytesec Video

Fixed dock rates to 80 MHz allow the OTI()87 to offer vertical refresh rates at 1024x768 that exceed the VESA standard of 70 Hz for high vertical refresh displays Depending on the capabilities of the monitor the OTIshy087 can support up to 1024x768 with 256 colors at a 76 Hz vertical screen refresh

Page 6

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

shy

SYSTEM BUS

OTl-06S VIDEO AND

MEMORY CLOCK

SOURCE

lt shy5D170]DATA BUS (7-0)

SDI156]DATA BUS (15-8) )f( vJ

SA[190]ADOIlESS BUS~ v

~ CONTROL

VLCK i CStLO

CStL1

J CSEL2

J CSEL3

MCLK

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1

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Page 8

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1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

-7 DlltDIli 14 - HLDA

OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

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u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

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LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

~ccedil ~C

t-C-28-~C-Z-7-~-C-2-lC2 teI2r-1I~lt1ar-Tltln4Ihe15o-JJe2bteJ2I-JC8--1SC32--kC5-2--~C53 ~ li 22Ufiuml 2U~22uroZ2UF ~lUF1ii IlIr1ii lUr1iilUrlOluF19middot1UF1O lUlf lUF1l lUCID lU

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I ~

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(

OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

- - - - - - - - - - - -

bullbull

1

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 16: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 1 1 1 1 1middot 1 1 1 1 1 1 1 1 ~

1

OTI-oS7 Block Diagrams

OTI-Q87 System Block Diagram

shy

SYSTEM BUS

OTl-06S VIDEO AND

MEMORY CLOCK

SOURCE

lt shy5D170]DATA BUS (7-0)

SDI156]DATA BUS (15-8) )f( vJ

SA[190]ADOIlESS BUS~ v

~ CONTROL

VLCK i CStLO

CStL1

J CSEL2

J CSEL3

MCLK

~ANALOG MONITOR (ANAlOG RGB)

1

i 24-BIT DIRECT COLOR

PALETTE DAC j

li l li

c 9- 0 U t=

~ t~ Cl liA

PCLK

BLANKnOn-087 LOCAL BUS VGA

GRAPIDCS HampVSYNC

-

CONTROllER

99 agrave9lo - B~ 0i~~ ~ ~

1I~lI

~ ~~ Cl ~ ~0lt1( if 8

DISPLAY MEMORY

1

1 1

1--shy

shy1-- shy

1 bull

(OTI-o~7 OperationaI Block Dlagram

INTERNAL DATA BUS

lt==

CRTC shy-CONTROLLER

~

Reglster gt

~ATTRIBUTE 7~ CONTROlLER

J Data

RWReglster

~

cache

Bltblt AssIst HW

GRAPHICS CONTROLLER lt===shy

~ 12 i

C UumlC

i Data-lt ~ 0 19

li)

euml gt~ Data flFO~

8 ct

u J FIFO Control

Reglster ~

SA23O] MA9 Cadte

L Tas 1shy7

SEQUENŒR

shy shy

M16njSRDY IOCHRDY

AEN RfSHn MRDn MWRn 1016n HLDA

ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

BD6jCPUBHEn BD7jCPURESET

SDI150] CINTn

ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

~

shy

-~

- ~

~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

~ CPUAI ~

CPUBHEn

DACWRn DACROn

SDHOEn

~50[1581

SOI7DI 1(

SDLOEn DIa

ltCAl231

ATOEHn

ATOEln -

middot~i~i~f~~ii J

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il lft QQ

1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

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1 1 1 1 1

1

1 BUFfE A

DIIl4 - OEn

1 ATSq7O

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AT BUS

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X 1 l D[158) ) BUFFEIlE

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1 l 0[701

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SAlll2)

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Note 11 bullbullr G He4ecl ODIy If dao sy__ dalpset clMt fOIIte Net tlaese tas DAlAMMter cycles

1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

ATOEHn

ATOEln --

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Icirc

BUFfER E

v )

OEn

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D

1 k 1

Memory ) OEn D

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AT BUS

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P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

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bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

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HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

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POePS 16 17

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Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

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04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

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H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

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l vcc

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C41 22~F ~C4 ~50

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87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

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1- ~

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Vcc

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Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

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Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Pl Pl Pl~1I10

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936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

- - - - - - - - - - - -

bullbull

1

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RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

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Qll

$ 1 MB

Il c 10K

1

D lDK ~ Rn

shy i--lDK

2

Il ~

11 lOIlt 10il lOK -rOM

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MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

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--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 17: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 bull

(OTI-o~7 OperationaI Block Dlagram

INTERNAL DATA BUS

lt==

CRTC shy-CONTROLLER

~

Reglster gt

~ATTRIBUTE 7~ CONTROlLER

J Data

RWReglster

~

cache

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~ 12 i

C UumlC

i Data-lt ~ 0 19

li)

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8 ct

u J FIFO Control

Reglster ~

SA23O] MA9 Cadte

L Tas 1shy7

SEQUENŒR

shy shy

M16njSRDY IOCHRDY

AEN RfSHn MRDn MWRn 1016n HLDA

ALEADSn RSET

ZEROWSnjDCn BHEn IORn

IOWn SAI230]

BDOjATOELn BD1DIR

BD2jSDLOEn BD3jSDHOEn

BD4jCPUAO BDSjCPUA1

BD6jCPUBHEn BD7jCPURESET

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ENVGAWRn DACROn

DACWRn PROCLKROMENn

VCLK MClK

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shy

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~

~

~

BUS ~ INTEIlFACE ~

LOGIC ~

amp CONfiG

CONTROL REGISTER

lt ~

~ - ~

~

HSYNc VSYNC BLANKn

P[70]

PCLK

MDI310]

MA01[80) MA23[80]

RASLn RASHn CASAnWEn

WEAnCASOn WEBnCASl Il WKnCAS2n WEDnCAS3n

Page 8

1 OTI-6S7 Block Dlagrams

~ ~

PAL l BH~3~)

V I) r Al ~ All-Al3 BHEn

Al8 ~ - HLDA

A D[3124)8UiFER C

K

OEn 0

r 1 A 012316)

BUFFER tgt K

bull -OTI087 on 486 Loca18us

LBSEln L8SEln

SIlDYO SRDYO SIlDYI SIlDYJ

ADSn ADSn

Den Den

on-os7 Rn WItn aURESET

aURESEf HLOA

MAsrUryHLDA

~ CPUAO

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CPUBHEn

DACWRn DACROn

SDHOEn

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SOI7DI 1(

SDLOEn DIa

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ATOEHn

ATOEln -

middot~i~i~f~~ii J

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1 BSl6n l

1 1 1 SAU)

DIPSWlTCHDAC WRn-c1- PUUUPDO~- RDn ~ v

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11 JI

1 1 1 1 1

1

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1 ATSq7O

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ATSAlZZ11ATSDl158)

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1

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

Agrave

SOI581 lt1

50701 lt l

SDLOlD DIR

CA232 k

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ATOEln --

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1 5 ~ ft 3~ ~I~

91

a~ ~j 22

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PAL Atgt Al BHEn

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DAC DIPSWlTOl

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RDn D[7~1 07~1

l

Icirc

BUFfER E

v )

OEn

D(701BUFfU F

lL1lHEr(3~1

f ~ A31-Al3

F- 1[ HLDA

001581

~

D

1 k 1

Memory ) OEn D

i ~ Icirce4- g If 1221

SAl2Z2Igt J

IUFfUQIUFfU bullIUFfEllA

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OEIl ClOEIl -f

ATSA(UlATSOIt58)AYS0(701

AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

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Page 62

-------------- -- _-

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v 6 10 _v v ltIv V ~ ~vv V

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CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

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Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Pl Pl Pl~1I10

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936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

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856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 18: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

bull 1 bull ~ bull ~ bull

c vi~ ~~~gt~~~ i~

OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

11J111 1 111 l 1

- bull _ ~ ~~ bull- bullbull ~ - ~- bull Tl7- ~ - _

MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

DQl150] rt llASn CASn AI80] WELn WEHn

MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

r

bull ~ l ~

1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

-_ 1 1

1

-11 1 1 1

1 1 1 1 1 1 1

--~

1 1 1 1 1 1

n

MOr23 161183OJ DQU50J rO

RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

WEIn WEBn WEHnOTl~87

OEn MAPOlf CAS~ __~eumlA~----

MAO 118 1] MA23181] ~OI31241512741

OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

CAS__~eumlASn --shyMDI3124151274] DQII50] r5

RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

(

64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

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JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

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u_ln

L

u

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I

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LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

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RAS

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 19: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

OTI-087 on 386DX Local Bus bull

LBSElrl IIIUA

SRDYO SRDYO

SRDYI ~rM

ADSn ADSn OTI()S7 DCn

00-

WRn WRn

CPURESET CPURESET

MASTERJvHLDA HLDA

~ CPUAO

~ CPUAI

~ CPUIlHEn

DA DACRD

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SDLOlD DIR

CA232 k

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ATOEln --

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AT BUS

Notll 1 Baffer G as aeedn ollly If dle syRe dalpset does IlOt lOllie Net dlad slpaIs cl DMAMuter cycles

P2pl0

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

)f - ------1 RASn rHI

1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

1WEn 1 __ 11

MAPI

)f---------1 RASn rt3

1 1 1 1 1 1

1 1 1 1 1 1 1 ~

1

MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

1

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OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

RASHn ltASnWEn WEn

MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

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MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

RASHn CASAn

MA011801 RASLn WEAn RASHn wren CASAn

f OEn

WEAn WEBn WEen MD31 24151274] WEDn RASln

CASAn

MA73 80 WEBn

MDI310] WEOn - OEn

MD31 24151274] RASHn CASAn

MA73[8O] WEBn WEDn

f OEn

DQlISO] rO RASn CASn Al80] WELn WEHn

MAPOl

DQllS0] r1 llASn CASn AI80] WELn WEHn

MA PO 1

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MAP23

DQl150] r3 llASn CASn Al80] WELn WEHn

MAP23

Page 14middotmiddot

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1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

1 _--~

1 --r31

1 11 1 1

1 1 1 1 1

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1

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1 1 1 1 1 1 1

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RASLn ~ RASn CASAn CASn

MAOHSl1 A[7O]WEAn

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OQrt50] rIRASLn ~ RASn CASAn

CASnRASin MA23IS11

A[7OJRASHn WEAn ~ WElnCASAn WEBn WEHnCASBn MAP23OEn

CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

RASnWWn tAltA CASn UltnUAoIl A170]

WUn ~ WEln WEOn

bull WEHnMOl31OJ OEn MAPOf

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RASHn RASn CASAn CASn

MA23 81 A(70)WECn Min WEDn WEHn

MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

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64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Page 66

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apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 20: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 OTI-087 Block Dlagrams

1 MD[2320] 1 1

CASn CASn l

1 WEAn

l8O] l8O] 1 WECn

WEn 1

of Ofn 1

-tMAPO(t) f--_J

RASHn gtr-shy - ---- RASHn ----- shy 1 llASn r91 ----- shy

MD[74] MD[31 28] shy rt 1 DQ[3O 1 RASn RASn 1 CASn CASn

1 WEBn l8O A[8O 1 WEDn

WEn 1

of OEn 1 - 0Fn

MAP2(3) f-_-I

RASHn )f shy -- shy -- RASHn ----- shy 1 llASn rto 1 ----- shy

MD[118] shy MD[1916] shyr2

1 DQ[3O] 1

~ 1 ~ RASn RASn CASn CASn

1 WEAn ~

l8O] l8O] 1 WECn

WFn 1

i Ofn 1 - Ofn MAPO(t)

__1

RASHn gt[_ - - - RASHn ----- shy 1 RASn rUI ----- shy

MD[1512] r3

1 MDI2724] DQ[3O] r5DQ[3O] 1

RASn RASn 1

RASn

CASn CASn CASn

1 WEBn l8O] A[8O] w~n

AlSO] WEn 1 WEn1

1 - OEn__1 MAP3

RASHn ~r--------- ------ RASn r14 1

DQl3O] r6 RASn CASn l8O WEn Ofn

MAPI

)f -------1 llASn t5r

DQ[3O] r7 RASn CASn l8O WEn

__1 MAP3

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1 DQ[3O] r4 1

1RASn 1 1 1

CASn l8O] 1

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1 1 1 1 1 1

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MD Interface for 256K x 4 DRAMs RASHn ~~

------ RASn r81 MD[30]

OTI-087

MAO 1[80] MA23[80]

RASLn RASHn CASAn

WfAn WEBn WECn WEDn -

MD[jSO] MD[3116] 1shy

DQ[3O] rO RASn RASn

Ofn

f MAP2(3

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

MA231801MA9 A[90] WEOn Wfn

- OEIl MAP3

Page 12

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OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

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CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

MD(3t 24151274J DQ[150] r3

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MA23 801 A[80] CAStn CASn CAS3n CASHn

MAP23f OEn

1

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MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

WEAn wrenOTI-087 - OEn

MA01[8O) MA23180] MD731611 830]

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CASAn

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MDI310] WEOn - OEn

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MAPOl

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MA PO 1

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Page 14middotmiddot

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1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

1 CASBn

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MAP23OEn

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

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64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

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1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 21: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

MD Interface for 512Kx 8 DRAMs (

MDIII 830) shyDQ[7O] 10

RASLn RASn CASAn CASn

MAO 1I801MA9 A90)WEAn Wfn

OTIQ87 OEn MAPO

f MAI9]MAOII80] MA(9)MA23180) MDI2316] DQ[7O] rl

RASLn RASn CASAn CASn

MA01[801MA9 -0 A90)RASLn WECn WfnCASAn

MAP - OEn

WEAn WEBn WECn M0I1S12741

DQ[7O] r1WEDn RASLn RASn

CASAn CASn MA231801MA9 A90)

WEBn WfnMD[31O)

MAP2 - OEn

MD3124) DQ[7O) r3RASLn RASn CASAn CASn

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Page 12

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OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

OQ[t50) rORASln RASn

WEn WEnMAOt 80] A[80)

CASOn CASlnCAS2n

1 CASHnOTI~87 - OEn MAPOl

MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

WEn WEn MAOt (80] A[80]RASIn CASOn CASnRASHn CAS2n CASHnWEn - OEn MAPOl

CASOn CAS1n CAS2n MD[3124151274J

OQ[1S0] rCAS3n IlASln RASn WEn WEn

MA23fS01 A[80] CAStn CASnMD[310) CAS3n CASHn- OEn MAP23

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MA23 801 A[80] CAStn CASn CAS3n CASHn

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MD[73161183O) RASln

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CASAn

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1 OTI()87 Block Dlagrams

MD lnterface for 64K x 16 DRAMs

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CAS__~eumlASn----WEAn WEBn Mor23161183OJ DQII50] r4WECn RASHn

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OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

RASHn MA9

NC Ne rO1 r8-18

CASAn MEn

rO1 rO123 rO1 r0-1S

WEAn rO rO1 rO rO2810 CASOn MAPOl MAPO1 MAPO1 MAPO

WEBn r1 r23 r1 r13911 CASln MAP23 MAP23 MAP23 MAPZ

WECn CAS2n

Ne Ne Ne r461214 MAP1

WEDn CAS3n

Ne Ne Ne r571315 MAP3

MA01 MA01 (OJ MA01 (0) MA01 fOl MA01 (O rOll

CASBn

MAl3 [0)

MAl3 (0) MAl3 [0) MAl3 fOl MAZ3 [0]

256Kx16 (2 or 4) MD32

MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

r13 (WEWCASLn)

MAPl

rO2 (WEHnCASHn)

MAP1

r13 (WEHnCASHn)

MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

MD32

MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

Not Applicable

Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

rO MAPO

r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

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64Kx16 (24 or 8)

MD32

MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

lJ Ne

Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

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1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 22: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1

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OTl-087 Block Dlagrams

MD ~nterface (260) for 256K x 16 DRAMs

1 MD[231611 8301shy

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MA0180) MA23[8O) MD[23161183O]

1 OQ[150) r1RASHn RASn

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OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

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MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

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MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

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MD[2316 11 830

MD[3124 1S1274

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Not Applicable

Not Applicable

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rO1

r23

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rO2 (WEWCASLn)

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MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

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MD1512 74

MDI2316

MD[3124

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Not Applicable

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rO123

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r2 MAP1

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r20 (2) (46)

MDI2316 rO (2) (46)

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MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

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r4567

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rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

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r2367 CASSn

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Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

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Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

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1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

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PagelS

1

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01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

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Page 23: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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MD Interface (270) for 256K x 16 DRAMs (

MD[73161183O) RASln

CASAn MAOl [80]

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MA01[8O) MA23180] MD731611 830]

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OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

MD16 MD16 MD32

MAPO MDI11 830 MDI11 830] MDI11 830 r20 rO r20 (108)

MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

RAS Ln rOl rO123 rO1 rO123 4567

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rO1 rO123 rO1 r0-1S

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MD[11 830 r20 (2)

MDI2316 rO (2)

MD(1S12 74] r1 (3)

MD[3124] r1 (3)

MD[2316 11 830

MDI3124 1S1274

MD[2316 11 830

MD[3124 1S1274

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Not Applicable

Not Applicable

Not Applicable

rO1

r23

rO123

rO2 (WEWCASLn)

MAPO

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MAP3

MA01 (0)

MAl3 (0)

512Kx8 (4)

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MDI11 830 r20

MDI2316 r2

MD[1S12 74 r1

MD[3124] r3

MDI11 830

MD1512 74

MDI2316

MD[3124

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Not Applicable

Not Applicable

Not Applicable

rO123

rO123

rO123

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r1 MAP2

r2 MAP1

r3 MAP3

MAO1 [O

MAl3 [O

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MDI11 830

r20 (2) (46)

MDI2316 rO (2) (46)

MDI1S12 74] r1 (3) (57)

MD[3124 r1 (3) (57)

MD(2316 11 830

MD[3124 1S1274

MD(2316 11 830]

MD(3124 151274

MD[2316 11 830

MD(3124 (151274J

MD(2316 11830

MDI3124 151274

rO123

r4567

rO145

rO246 (WELn) MAPO

r1357 (WELn) MAP2

rO246 (WEHn) MAP1

r1357 (WEHn) MAP3

r2367 CASSn

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Page 16

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1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

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Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

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1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

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PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 24: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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Memory Mapplng Configuration

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RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

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Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

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1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

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1

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01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

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10

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IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

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Page 62

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 25: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

OTl-oS7 MappingConfiguratlon

Memory Mapplng Configuration

256Kx4 256Kx4 5UKx8 256Kx4 (2) (4) (2) (8 or 16)

MD8

MDI30] rO

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MAPI MD(30 rO MD(11 830 r20

MDI11 830] rO

MD(2316 r64 (1412)

MAP2 MD(74 r1 MDI1S12 74] MD[1S12 74 MD(1S12 74 r31 r1 r31 (119)

MAP3 MD[74] r1 MD[1S12 74] r31

MD[1S12 74 r1

MDI3124 r7S (1513)

RAMO (8)

MD(30] MD[30 MD[11 830 MD[30

RAM1 (9)

MD[74] MDI74 MD[1512 74 MD(74

RAM2 (10)

Not Applicable MD[118 Not Applicable MD(11S

RAM3 (11 )

Not Applicable MDI1512 Not Applicable MD(1S12

RAM4 (12)

Not Applicable Not Applicable Not Applicable MD(1916

RAM5 (13)

Not Applicable Not Applicable Not Applicable MD[2724]

RAM6 (14)

Not Applicable Not Applicable Not Applicable MDI2320

RAM7 (15)

Not Applicable Not Applicable Not Applicable MD(3128

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Page 16

middot - ~ -

1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

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Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

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1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

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01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

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10

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10

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IO

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DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

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Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

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B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Page 26: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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1 OTlo087 Pin Description i PIN DESCRIPTION

AT-BUS INTERFACE

1 This section describes the AT-Bus interface signaIs of the On-087 when implemented in an add-on card configuration either on an adapter card or on the motherboard For information on the system bus interface for local bus implementations see the next section

1 Pin Pin Pin Name Jt Type Description

1 5D[158] 4642 VO SYSfEM DATA BUS 158 4038

1 5D[70] 8581 VO SYSTEM DATA BUS 70 7775

1 5A[160] 6762 l LATCHED SYSTEM ADDRESS BITS 160 For add-on 6050 card configuration these are the latched system address bits 160

1 1 IA[2317] 7468 l UNLATCHED SYSŒM ADDRESS BITS 2317 For add-on configuration

these are the unlatched system address bits 23-17 These bits are decoded to generate M16n Address bits 1917 are latched by ALE to generate 5A[1917]

M16n 78 VO 16-BIT MEMORY This signal is an active low open drain output signal used to indicate to the system that the present cycle is a l~bit data transfer to video memory The signal is derived from the decoding of lA17 through LA23 -

1 1 IOCHRDY 79 0 IIO CHANNEL READY This signal is an active high open drain output

that signaIs to the processor that it is ready for memory access This signal is used to add wait states to the AT-bus timing during video memory access

1 AEN 86 l ADDRESS ENABLE This signal is used by the On-087 to qualify the video

IIO access from the CPU When it is active high the DMA controller has control of the address bus data bus and command lines

RFSHn 87 1 REFRESH This signal is used by the on-C87 to qualify the video memory1 access and the IIO access from the CPU An active low signal indicates a system memory refresh cycle

1 MRDn 88 1 MEMORY REAn This is an active low memory read strobe asserted during memory read cycles

1 MWRn 89 1 MEMORY WRITE This is an active low memorywrite strobe asserted

during memory write cycles r 1

Page 11

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Pin Jt 90

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DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

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1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

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01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

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10

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DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

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1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

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Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

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OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

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EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

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1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

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1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

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Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

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Page 24

1

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bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

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Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

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---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

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CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

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ltt0 YL-tlUI SOS1214 SOli S07

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HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

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Page 62

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AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

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CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

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87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

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---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

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Page 66

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RAS

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MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

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AD DO Al Dl A2 D2 A3 D3 A4 AS A6 Al AB

RAS CAS WE OE

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MAP0 Cr0 )

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JI MAP2 (ri)

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CONFIGURATION SETTING

MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

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RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

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087C021093-oo1

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Page 27: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

7~~ lt~~ gt~

Pin lliIM CINTn i

Pin Jt 90

Pin ~ a

DescriptiQn CRT INTERRUPT REQUEST An interrupt request is generagraveted when vertical retrace occurs if it is enabled by bit 5 in the Vertical Retrace End register It is an active lQW Qpen cQllectQr Qutput

(

1016n 91 a 16-BIT 10 This active lQw Qpen drain Qutput signal is used tQ indicate tQ the systemthat the present data transfer is a 16-bit Va cycle It is derived from an address decode

MASTERn 92 1 MASTERn This pin indicates that the current cycle is a master cycle when the controHer is in add-on cQnfiguration It enables the lA address to pass through during master cycle

ALE 93 1 ADDRESS LATCH ENABLE This pin is used to latch a valid address from the microprocessor in add-on configuration

ROMENL 95 VA ROM LOW BYTE ENABLE This active low signal enables the low byte of BIaS data tQ the CPU data bus in 16-bit BIaS configuration In 8-bit BIaS configuration this pin is not used

RSET 97 1 RESET This is an active high system reset signal This input signal will reset the VGA controller and initialize the configuration register based on the logic level Qn MD[1501 pins at PQwer-up reset In a local bus configuration with Oak Technologys system logic chipsets this pin is connected to system reset and is used to determine the processor clock phase

ENVGA 98 1 VGA ENABLE In non-Iocal bus configurations this pin acts as the address select for the cQntroUer The seleeted address range includes the VGA address space color palette register address space video memory space and the VGA BIaS space The address select condition is enabled by register 3C3H bit 0 and register 102H bit O

ZEROWSn 99 VA ZERO WAIT STATE This pin is used to indicate the cucrent cycle is a zero wait state AT-bus cycle

BHEn 100 1 BYTE HIGH ENABLE This active low input indicates that there is valid data on the 5D[1581 bus This signal and SA(O] together indicate to the on-087 whether an 8-bit or 16-bit cycle is heing executed br the system

10Rn 101 1 10 READ This is an active low VO rcad strabe asserted during 10 read cycles

IOWn 102 1 IO WRITE This is an active law VO write strobe asserted during VO write cycles

l f

PagelS

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

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1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

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(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 28: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1

amp1

01-087 Pin Description

LOCAL BUS INTERFACE

1 1 1 1 1 1 1 1 1 1 1 1 1 1 [

1

Pin i

Name CA[2317]

CA[160]

ADSn

PROCLK

WRn

DCn

HLDA

ATOEHn

ATOELn

DIR

SDLOEn

SDHOEn

Pin if 7468

6762 6050

93

95

98

99

92

47

10

11

12

13

Pin ~

1

l

l

10

l

10

l

o

10

IO

IO

If0

DescriptiQn CPU ADDRESS BITS 2317

CPU ADDRESS BITS 160 FQr 80386SX IQcal bus these pins can be cQnnected directly tQ the CPU address bus FQr 8038680486 IQcal bus cQnfiguratiQns CA[162] shQuld be CQnnected tQ CPU address bits [162] and CA[10] shQuld be cQnnected tQ SA[10] Qf the AT bus

ADDRESS STATUS This input from the CPU indicates when a valid address is Qn the bus

PROCESSOR CLOCK The proceSSQr dQck input samples the CPU status and address This is a IX dQck fQr 486 CPUs and a 2X dQck fQr 386 CPUs

WRITEREAD This input frQm the CPU distinguishes between write and read cycles

DATACONTROL This input from the CPU distinguishes between data cycles and cQntrol cycles

HOLD ACKNOWLEDGE This CPU input indicates a DMA Qr Master cycle

AT-BUS HIGH BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus high byte data This pin is used with 80386DX80486 local bus cQnfiguratiQns See 80386DX80486 local bus diagrams for details

AT BUS LOW BYTE DATA ENABLE This is an active IQW Qutput enable signal fQr AT-bus IQW byte data This pin is used with 80386DX80486 IQcal bus configuration See 80386DX80486 local bus diagrams for details

DATA DIRECTION CONTROL This signal contraIs the direction of the data buffer between either the AT-bus or the CPU IQcal bus and the VGA bus A IQgical high directs data intQ the VGA and a IQgicallQW provides data output tQ the AT or CPU bus This pin is used with 80386DX80486 local bus configurations See 80386D)CcedilI80486 local bus diagrams for details

SYSTEM DATA LOW OurPlIT ENABLE This active low signal is used to enable the low word data buffer from the CPU bus to the VGA bus This signal is used with 80386DX80486 local bus configurations See 80386DX 80486 local bus diagrams for details

SYSIEM DATA HIGH OlITPlIT ENABLE This active low signal is used to enable the high ward data buffer from the CPU bus ta the VGA bus This signal is used with 80486 local bus configuration See the 80486 local bus diagram for details

Paie 19

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 29: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

(Pin Pin Pin lliJM i Jt ~ Description CPUAO 14 va CPU ADDRESS BIT O This is the translated CPU address bit 0 that is

generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DJCcedill80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUAI 15 va CPU ADDRESS BIT 1 This is the translated CPU address bit 1 that is generated from the 4 byte enables of the CPU by implementing an external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPUBHEn 16 10 CPU BYTE HIGH ENABLE This active low input is the translated byte high enab1e generated from the 4 byte enables of the CPU by the external PAL This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

CPURESET 17 va CPU RESET This is the reset signal synchronized with the CPU clock It is used by the YGA controller ta determine the correct sampling phase

GAlO 19 1 GATE AlO This signal is used only with local bus configuration

SRDYI 20 1 SYSTEM READY INPUT This input from the system chipset indicates the termination of a cycle This signal is used with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

LBSELn 23 0 LOCAL BUS SELECf This active low signal indicates ta 80386DX or 80486 system controller chipsets that the cucrent cycle is a video local bus cycle and that the chipset should not respond to the CPU This signal aIso indicates ta the CPU that the current cycle is a 16-bit cycle This signal is used only with 80386DX80486 local bus configurations See 80386DX80486 local bus diagrams for details

SRDY 78 VO SYSTEM READY This tri-state active low output indicates the termination of a CPU bus cycle For chipsets with separate SRDYI and SRDYO this signal is sampled by the system controller chipset to indicate the aetual termination of the bus cycle This signal is driven high for one-half of the PROCLK before being tri-stated at the end of a cycle

CLOCK INTERFACE Pin Pin Pin ~ ~ Description yeult 106 1 VIDEO CLOCK This is the master input pixel clock

MCLK 107 1 MEMORY CLOCK This is the input clock used for memory timing l] CSEL[O) lOS 0 CLOCK SELEcr UNE O Clock select lines are used to select the appropriate

pixel clock frequency This pin can he programmed through registet 3DFH index 6 or register 3~

Page 20

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

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Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

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OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

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EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

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1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

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Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

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Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

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Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

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M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

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Page2S

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1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

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(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

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Page 62

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v 6 10 _v v ltIv V ~ ~vv V

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Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Pl Pl Pl~1I10

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856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

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vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

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~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 30: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1

OT-o87 Pin Description

1 Pin Pin Pin

~ Ji Type DescriptiQn GSEL[l] 104 0 CLOCK SELECf UNE 1 CIQck select lines are used tQ select the appropriate

pixel dQck frequency This pin can be prQgrammed through register 3DF index 6 Qr register 3C2 bull H

H

1 1 CSEL[2] 103 10 CLOCK SELECf UNE 2 CIQck select lines are used to select the appropriate

pixel dQck frequency This pin can be programmed through register 3DF index 6 H

1 CSEt[3] 18 0 CLOCK SELECf UNE 3 Clock select lines are used tQ select the apprQpriate

pixel clQck frequency This pin can be prQgrammed through register 3DFH

index 6

1middot CRY AND COLOR PALETIE INTERFACE

1 Pin Pin Pin Name ~ DescriptiQn P[70] 3330 0 PIXEL DATA This is the 8-bit pixel data bus (bits 7-0) This output bus

2825 interfaces tQ an external palette chip fQr color mapping during CRY display

1 VSYNC 34 0 VERTICAL SYNC This signal provides the vertical synchrQnization pulses for the display monitor The polarily of the pulse is determined by bit 7 of the Miscellaneous Output Register

1 1 HSYNC 35 0 HORIZONTAL SYNC This signal provides the horizontal synchronization

pulses for the display monitor The polarily of the pulse is determined bybit 6 of the MiscellaneQus Output Register

1 BIANKn 36 0 BlANK This active low output signal provides blanking to the color palette

ta blank the pixel data fQr the display monitor

PCLK 37 0 PIXEL CWCK The pixel dock output latches the pixel data P7-PO ta the

1 color palette The dock rate is seleeted by the dock select pins for the current video mode

1 DACRDn 48 0 COLOR PALETTE REAn This active low JlO read signal is generated for reading external color palette registers

1 DACWRn 49 0 COLOR PALETTE WRITE This active low IIO write signal is generated for writing to external color palette registers

1 BD[70 1710 JlO AUXILIARY DATA BUS 70 In add-on card mode this bus is the high byte data (bits 7-0) of the VGA BIOS in 16-bit BIOS configuration or the single byte data in 8-bit BIOS configuration In 80386DX80486 local bus configu-Icirc

~ rations BD[70] are used as misce11aneous signals ta control the data routing iii to and from the VGA bus the AT-bus and the CPU local bus

l1ft7~~ lt~_

~J

J

Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

Pap22 1

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 31: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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Pin Pin Pin (fuM Jt ~ Description EPCLK 19 l ENABLE PCLK This active high input is used to enable the PCUlt output

EPDATA 20 l ENABLE PDATA This active high input is used to enablethe PDATA

MXPCLK 23 0 MUX CLOCK For 24-bit color mode support with a color palette that requires a 24-bit bus this dock signal is used as the PCUlt for latching PDATA to a bank of external data latches

SWSENSE 24 l SWITCH SENSE This input signal is used to auto-detect the monitor type

VIDEO MEMORY INTERFACE Pin Pin Pin Name Jt ~ Description MAucircl[81] P4131 MEMORY ADDRESS MAPS 0 1 Memory address for maps 01 bits 81

129126 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMsmiddot

MA23[8l] 115108 MEMORY ADDRESS MAPS 2 3 Memory address for maps 23 bits 81 for 256KxXX and 512Kx8 DRAMs bits 70 for 64Kx16 DRAMs

RASLn 120 0 ROW ADDRESS STROBE LOW This active low output signal connects to the first 1 MByte of256KxXX DRAMs the first 512Kbytes of 64Kx16 DRAMs and aU banks of 512Kx8 DRAMs

RASHn 125 0 ROW ADDRESS STROBE HIGH This active low output signal MA9 eonneets to the second 1 MByte of 256KxXX DRAMs or the second

512Kbytes of 64Kx16 DRAMs For 512Kx8 DRAMs this pin is memory address bit 9 and should be eonnected to aIl maps and aIl banks of 512Kx8 DRAMs

CASAnj 123 0 COLUMN ADDRESS STROBFWRITE ENABLE This active lowoutput WEn signal conneets to an video memory maps and to aIl banks of 256KxXX

CASAn conneets to aIl video maps of 512Kx8 but only to maps O 1 of aIl banks of 64Iltx16 DRAMs

WEAn 118 0 WRITE ENABLE ACOLUMN ADDRESS STROBE O This active 10w write CASOn enab1e signal connects to memory maps 0 and 1 in 16-bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 0 in 32-bit MD configuration

WEBn 119 0 WRITE ENABLE BCOLUMN ADDRESS STROBE 1 This active low write CASl enab1e signal connects to memory maps 2 and 3 in 16--bit MD configurations

(4 - 256Kx4 2 - 512K(8) and is the WIIumlte enablecolumn address strobe for memory map 2 in 32-bit MD configuration

1l WECn 116 0 WRITE ENABLE CjCOLUMN ADDRESS STROBE 2 This active low write CAS2n enablecolumn address strobe signal connects to memory map 1 in 32-bit MD

configuration

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OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

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EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

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1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

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Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

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Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

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Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

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(OTI-087 LB 386486 Pin Dlagram

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M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

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Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

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U14 R29 ~Ol( A

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CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

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Page 62

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Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Pl Pl Pl~1I10

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936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

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~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 32: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1

or ~

OTI-087 Pin Description shy1 Pin Pin Pin

1 Name i Jt ~ DescriptiQn WEDnl 117 0 WRITE ENABLE DCOLUMN ADDRESS STROBE 3 This active low write CAS3n enablecQlumn address strobe signal CQnnects tQ memQry map 3 in 32-bit MD

cQnfiguration

1 1 MAOl[OV 124 0 MAP 01 MEMORY ADDRESS BIT O Memory address bit 0 fQr maps 01

CASBn in 256KxXX and 512Kx8 DRAM configuratiQns This signal is CASBn fQr maps l 3 in 64Kx16 DRAM configurations

1 MA23[0] 122 0 MAP 23 MEMORY ADDRESS BIT O This signal is memory address bit 0

fQr maps 23 in 256KxXX and 512Kx8 DRAM cQnfiguration

1 MD[310] 92 10 MEMORY DATA This is the memQry data bus bits 31-0 MD[150] are also

160153 used fQr the cQnfiguratiQn register during hardware reset MD[70] 152145 cQrrespond to bits 70 of ConfiguratiQn Register 1 and MD[158] 143142 correspond to bits 70 of ConfiguratiQn Register 2 See Memory

1 140135 Mapping table and block diagrams for further details

EEPROM INTERFACE

1 Pin Pin Pin

1 Name Jt ~ Description EEPCSn 47 0 EEPROM CHIP SELECT This signal is used to enable the serial EEPROM

for read and write operations C~~L

1 EEPSK 103 0 EEPROM SHIFf CLOCK This dock cm be toggled through register 3DFH

index 18Hbull

Leshy

EEPWD 104 0 EEPROM WRITE DATA Data can be written to the EEPROM through the

1 __67 data bit in the register 3DFH index 18Hbull

7vC

1 EEPRD 105 10 EEPROM REAn DATA Data can be read frQm the EEPROM through the

data read bit in the register 3DFH index 18H

POWER L GRODND

1 Pin Pin Pin DescriptiQn~ W

VSSOO l EXTERNAL GROUND

1 VSSOlVSS02 2941

1 VSS03VSS04 SOUl VSS05~VSS06 130144

VSSIO 22 INTERNAL GROUND VSSIl 96r VDDO 21 EXTERNAL amp INTERNAt POWER VDD1VDD2 6194

1 VDD3 141

Pagc23

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

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CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

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0 (PS c D E F _ - 803 lS 1l04cPUAO

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bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

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Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

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1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

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P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

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53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

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---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

~ccedil ~C

t-C-28-~C-Z-7-~-C-2-lC2 teI2r-1I~lt1ar-Tltln4Ihe15o-JJe2bteJ2I-JC8--1SC32--kC5-2--~C53 ~ li 22Ufiuml 2U~22uroZ2UF ~lUF1ii IlIr1ii lUr1iilUrlOluF19middot1UF1O lUlf lUF1l lUCID lU

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

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RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

RAS CAS WE

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AD DO Al Dl A2 D2 A3 D3 A4 AS A6 Al AB

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$ 1 MB

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MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

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RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

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--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 33: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

~ ~ ~~

Pin Out Cross Reference for OTI-087 ln Different Configurations (

Pin

1 92 10 11 12 13 14 lS 16 17 18 19 20 21 22 23 24 33302825 29 34 35 36 37 46424038 41 47 48 49 5150 67626052 7468 61 85817775 78 79 80 86 87 88 89 90 91 92

011-087 (ISA Add-on) VSSOO MO[3124] BOIO] BOln BOI2] BOI3] BO[4] BOIS] BOI6] BOI7] CSELI3] EPCLK EPOATA VOOO VSSIO MXPCLK SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn OACWRn SA[10] SAI162] LA[2317] V001 SO[70) M16n IOCHRDY VSS03 AEN RFSHn MROn MWRn CINTn 1016n MASTERn

011-087 (Oak LB) VSSOO MOI3124] BOrO] BOIt] BOI2] BOl3] BO[4] BOIS] BOI6] BO[l] CSEL[3] EPCLKGA20 EPOATA VOOO VSSIO LBSELn SWSENSE P[10] VSS01 VSYNC HSYNC BLANKn PCLK 50[158] VSS02 EEPCSn DACROn DACWRn CA[10] CA[162] CAI2317] VOD1 SO[70) SRDY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

011-087 (LB 386486) VSSOO MOI3t24] ATOELn DlR SOLOEn SOHOEn CPUAO CPUAl CPUBHEn EEPCSn CSELI3] EPCLK SROYI VOOO VSSIO LBSELn SWSENSE P[70] VSSOl VSYNC HSYNC BLANKn PCLK 50[1581 VSS02 ATOEHn DACROn DACWRn SA[10] CA[162] CAI2317] VOD1 5D[70) SROY IOCHRDY VSS03 AEN RFSHn MRDn MWRn CINTn 1016n HLDA

l ~

J

Page 24

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

~

~

1

J

1f i

(OTI-087 LB 386486 Pin Dlagram

gm~~$~~~~~g~~~~~~OQ~~~~~~~~~~~~~~~~~~~~~1 - - - ~ - - - - - - - - -- - - - - ~20VSSOO RASLn

M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

~~Q~~~~$~~~~~I~lmi~~81~lle~~~~~~~~~i

Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

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u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

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LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

~ccedil ~C

t-C-28-~C-Z-7-~-C-2-lC2 teI2r-1I~lt1ar-Tltln4Ihe15o-JJe2bteJ2I-JC8--1SC32--kC5-2--~C53 ~ li 22Ufiuml 2U~22uroZ2UF ~lUF1ii IlIr1ii lUr1iilUrlOluF19middot1UF1O lUlf lUF1l lUCID lU

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I ~

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(

OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

- - - - - - - - - - - -

bullbull

1

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Page 34: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1

~ - ~ bullbull 1middot bull bullbull 1- bull ~

bull OTlo087 Pin Description

1 1 1 1 1 1 1 ~

1 1 1 1 1 1 1 bull

Pin

93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 115108122 116 117 118 119 120 121 123 134131 129126 124

125 130

OTl-087 (ISA Add-on) ALE VDD2 ROMENln VSSI1 RSET ENVGA ZEROWSn BHEn JORn JOWn CSEll2] CSElll] CSElIOI VClK MCLK MA231801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01[811

MAOIIOJ CASBn RASHnMA9 VSSOS

152145143 MDI150I 142140 135 141 VOD3 144 VSS06 160153 MO[23161

OTI-087 (Oak LB) ADSn VDD2 PROCLK VSSI1 RSET WRn DCn BHEn JORn IOWn CSEL[2] CSELI1] CSELlO] VCLK MClK MA23[801 WECn WEDn WEAn WEBn RASln VSS04 CASAn MA01181]

MAOHO] CASBn RASHnMA9 VSS05 MDI150

VOD3 VSS06 MDl2316]

OTI-087 (LB 386486) ADSn VDD2 PROCLK VSSJ1 RSET WRn EPDATA BHEn IORn IOWn CSEL[2] CSEL1] CSELlO] VCLK MClK MA23l80] WECn WEDn WEAn WEBn RASLn VSS04 CASAn MA01l81]

MAOllO] CASBn RASHnMA9 VSS05 MDl150]

VDD3 VSS06 MDl2316]

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

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Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

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(OTI-087 LB 386486 Pin Dlagram

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M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

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Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

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Page 66

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apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 35: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

OTI-087 ISA Add-on Pin Dlagram

VSSOO MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31

BOO BD1 B02 BD3 BD4 605 BD6 B07

CSEl3 EPClK

EPDATA VDDO VSSIO

MXPClK SWSENSE

PO P1 P2 P3

VSS01 P4 P5 P6 P7

VSYNC HSYNC

BlANKn PClK

S08 SD9

SD10

1 120 AASln 2 119 WEBn 3 118 WEAn 4 117 WEDn 5 116 WEen 6 7

115 114

MA23[8] MA23[7]

8 113 MA23[6] 9 112 MA23[5] 10 111 MA23[4] 11 110 MA23[3] 12 109 MA23(2) 13 108 MA23(1) 14 107 MelK 15 106 VClK 16 105 CSElO 17 104 CSEl1 18 103 CSEl2 19 102 10Wn 20 101 10Rn 21 100 SHEn 22 99 ZEROWSn 23 98 ENVGA 24 97 RSET 25 96 VSSI1 26 95 ROMENlnmiddot

a ~ VDD2 28 93 AlE 29 92 MASTERn

30 91 1016n 31 90 CINTn 32 89 MWRn

~ ~ MRDn

M ~ RFSHn ~ ~ AEN ~ ~ SD7 ~ M sce ~ ~ SD5 39 82 S04

40 81 SD3

~~~~~~~~i~g~~~8~8Iioga~II~112~~~~~~~~~i

Page 26

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

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(OTI-087 LB 386486 Pin Dlagram

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M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

S07BLANKn ~ S0637 84PCLK SOS~ 83S08 S04~ ~S09 S03~ 81S010

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Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 36: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1

OTI()S7 Pin DescriptionJ

III

1 1 1 1 1 1

1 1 1 1 1 1 1

on-qS7 Oak LB Pin Diagram

VSSOO MD24 MD25 M026 MD27 MD28 MD29 M030 M031

BOO B01 BD2 BD3 BD4 BOS B06 B07

CSEL3 EPCLKlGA20

EPOATA VODO VSSIO

LBSELn SWSENSE

PO Pl P2 P3

VSSOl P4 P5 PB P7

VSYNC HSYNC

BlANKn PCLK

S08 S09

SOlO

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 B6 85 84 83 82

RASLn WEBn WEAA WEDn WECn MA23[8] MA23[7] MA23(6] MA23(5] MA23[4] MA23[3] MA23(2] MA23(1) MCLK VCLK CSELO CSEL1 CSEL2 10Wn 10Rn BHEn OCn WRn RSET VSSI1 PROCLK V002 AOS HL DA 1016n CINTn MWRn MRDn RFSHn AEN S07 S06 S05 S04 SD3

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(OTI-087 LB 386486 Pin Dlagram

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M024 2 119 WEBnM025 3 118 WEArM026 4 117 WEOn M027 5 116 WECn M028 6 115 MA23[8)M029 7 114 MA23[7JM030 8 113 MA236]MD31 9 112 MA23[SJ

ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

LBSELn ~ ~ WRn SWSENSE ~ ~ RSET

PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

VSS01 HLDA~ ~

P4 ~ 91 1016n P5 ~ ~ CINTn P6 ~ ~ MWRn

MROnP7 ~ VSYNC 34 87 RFSHn HSYNC AEN~ ~

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Page2S

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

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1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

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3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 37: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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(OTI-087 LB 386486 Pin Dlagram

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ATOELn 10 111 MA23[4]DIR 11 110 MA23[3J

SOLDEn 12 109 MA2312J SOHOEn ~ 1~ MA23[1J

CPUAO 14 107 MCLK CPUA1 15 106 VCLK

CPUBHEn 16 105 CSELO EEPCSn 17 104 csa1

CSEL3 18 103 CSEL2 EPCLK ~ 1~ IOWn ( SROVi 20 101 IORn VDOO 21 100 BHEn VSSIO 22 99 EPOATA

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PO ~ 96 VSS1 P1 ~ 95 PROCLK P2 ~ 94 VD02 P3 ~ 93 AaSn

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Page2S

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1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

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- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

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1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

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3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 38: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

__

1 OTI-087 Reglster Definitions OTI-qS7 Reglster Definitions

1 Refer to on-067 databook or IBM technical reference for VGA register definition AlI registers are in hexadecimal format Local bus related registers fol1ow

1 Local Bus Related Reglsters

1F Video memory range control reglster Index = 5 W

1 llli Description

1 o VMSO EnDis video memory AOOOO bull AFFFF (64K) 1 VMS1 EnDis video memory BOOOO - BOFFF (4K) 2 VMS2 EnDis video memory BlOOO - B3FFF (16K) 3 VMS3 EnDis video memory B4000 bull B7FFF (16K) 4 VMS4 EnDis video memory B8000 bull BBFFF (16K)

1middot 5 VMS5 EnDis video memory BCOOO - BFFFF (16K) 7-6 Reserved

Default IF

1 Adapter CardfMotherboard Configuration

J There are twa sets of registers that control the IBM VGA products One register set controls access ta the onshyboard system VGA and the other register set controls access to the add-on VGA These registers are used ta enable or disable the appropriate VGA interface The on-087 chip contains both add-on and on-board

1 registers The registers that control on-board operation aIso reside in the system chipset or on the motherboard The addresses for both register sets are

1 Add-on YGA mode 46E8 control (in On-087) 0102 enablejdisable (in On-087)

1 1 On-board VGA mode 03C3 enab1ejdisable (in On-087)

0094 control (in DTI-087 and system chip) 0102 enabledisable (in 011-087)

Add-On Mode Configuration

1 In order for the 011-)87 to properly function in the add-on mode the following initialization sequence is

1 recommended This example assumes no BIaS ROM paging

46E8 lt- 10 Enable access to location 0102 in VGA chip

0102 lt- 01 Enable VGA chip

46E8 lt- 08 Activate readwrite access to VGA interface

1 Once in this mode 46E8 bit 3 may be cleared to disallow access or may be set to permit access to theYGA interface registers However if 102 in the VGA chip is not loadelt with a l 46E8 bit 3 hagraves no effect and the VGA interface registers will not respond to read or write commands

1 ft 4A

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

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1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

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3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

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Page 39: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

- -

Registers 46E8 and 102 are descrihed below ( 46~8 w

This is a write-only register This register serves as the Power on Setup (POS) equivalent on Micro Channel Architecture (MCA) machines Bit Description 2-0 Reserved 3 VGA Golor Palette and Video RAM access control

Bit 3 Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

(normal operational mode) 4 This bit sets the current state of the On-087 in add-on mode

Bil4 Description o Add-on card is in the ACflVE state (this is the normal mode of

operation for the add-on mode) 1 Add-on card is in the SETUP state This permits a software utility

to enable or disable access to the On-087 chip 7-5 Reserved

102

Bit Description o VGA Color Palette and Video RAM access control

lfuO Description o Disable readwrite access to VGAColor PalettejVideo RAM 1 Enable readwrite access to VGAColor PalettejVideo RAM

7-1 Reserved

On-Board Mode Configuration When the On-087 is configured to operate on a system motherboard the ENVGA pin or register 3C3 in conjunction with registers 94102 controls access to the 011-087 To access the On-087 chip ENVGA should be asserted or register 3C3 bit 0 set to 1 Register 102 bit 0 should also be set to 1 To access register 102 in on-board configuration OTI-D87s register 94 bit 5 should be written with a O The definition of register 94 inside On-D87 is given be1ow

~ W This is a write onlr register Bit Description 4Q Reserved 5 VGA Color Palette and Video RAM access control

IlliS Descriptiagraven o Disable readwrite access to VGAColor PalettcVVideo RAM

Enable write to register 102 1 Enable readwrite access to YGAColor PaletteVideo RAMe

Disable write to register 102 7-6 Reserved

Page 30

1 y ~ gt

OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

1

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1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

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3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

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3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

~ccedil ~C

t-C-28-~C-Z-7-~-C-2-lC2 teI2r-1I~lt1ar-Tltln4Ihe15o-JJe2bteJ2I-JC8--1SC32--kC5-2--~C53 ~ li 22Ufiuml 2U~22uroZ2UF ~lUF1ii IlIr1ii lUr1iilUrlOluF19middot1UF1O lUlf lUF1l lUCID lU

~c lc tClr1te17lJc1eacute~P-cln9r-lC3flb-LCuib-~eJ2~r-te2alc22

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1

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CD

I ~

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OTI-087 Trile Color ISA-Bus Schematlcs

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Page 40: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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OTI-087 Reglster Definitions

3DF Oak Test Reglster Index =3 RfW

1 1 1 1 1 1 1

1 1 1 1 1 1 1

Hit Description 2-0 Test mode - These bits define the test modes of the controller

Bits 2=0 000 001 010 011 100 101

110 111

3 Reserved 4 Cache Flush

Bit 4 o 1

Test mode Test CRTC Reserved Test waveform RAM Reserved Reserved Scan Test Attribute Controller This bit forces the font data and

attribute data ta he replaced by the system data bus 158 and 70 respectively in text mode In graphie mode this bit replaces the AFA data with system data bus 158 Reserved Reserved

Description Normal operation Flush the write cache immediate1y after a write commando

5 VSYNC Test This bit will cause the V-sync ta toggle when it is changed from 1 ta 0 or from 0 to 1

6 10 write test bit ~

o 1

7 Enable test mode Bit 7

o 1

Dcfault 0

Description Normal operation 10 test mode - In this mode an 10 write command is not clocked by MCLK Bit 6 must he 0 during normal operation

Description Normal operation Enable global test modes Bit 7 must be 0 during normal operamiddot tian

3Df Local Bus Control Reglster Index =4

Bit Description o First write wait state

JiitQ Description o No additional wait state for the first write cycle (the first write

cycle is a memory write cycle when the write cache is empty) 1 One wait state is insertelt into the first write cycle This bit

should he tumed on when the OTI-087 is operated with 20 MHz 80286 CPU or 40 MHz or higher frequency 80386 and 80486 CPU

Pageacute 33

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1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

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3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

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3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

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Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

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OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

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(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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1098 (2790)

-- --0

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1 40

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---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

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011-087 VESA Local Bus Schematlcs

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Page 62

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Page 66

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2

Il ~

11 lOIlt 10il lOK -rOM

Ii7

CONFIGURATION SETTING

MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

CI i en g ~

1 1raquon li)

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

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087C021093-oo1

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(

Page 41: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

--- -------- ----------

]~ ~ lt

1 (Write hit wait state Bit 1 DescriptiQn

o NQ additiQnal wait state fQr writehit cycle (a write hit cycle is a write cycle which shares the same cache page address With the previQus write)

1 One wait state is inserted into each local bus write hit cycle This bit shQuld be turned on when the controller is operated with 40 MHz Qr higher frequency 80386 and 80486 CPUs

2 Read hit wait state Bit 2 DescriptiQn

o No additiQnal wait state fQr read hit cycle (a read hit cycle is a read cycle in which the CQntent Qf the read already exists in the read cache)

1 One wait state is inserted into each local bus read hit cycle This bit shQuld be turned Qn when the controller is operated with 40 MHz or higher frequency 80386 and 80486 CPUs

3 80486 Minimum wait state lliU DescriptiQn

o Zero-wait-state 80486 IQcal bus 1 Minimum l-wait-state 80486 local bus This bit has no effect Qn

configurations other than 80486 local bus 4 Turbo local bus interface

Bit 4 Description o Normal local bus operation (On-087 Rev A and On-087 Rev B) 1 Enable this bit fQr faster local bus performance

7-4 Reserved Default F

3DF Video Memory Mapplng Reglster Index = 5 RfW Bit Description

0 Enable Oak address mapping BitJl Description

o VGA memory mapping at AOOOO and B8000 as dietated by Graphie register 6

1 Oak memQry mapping as dietated by bit 2 and 3 of this register 1 DMA access disable

mu DescriptiQn o NQrmaI operation 1 Disable DMA access tQ video memQry This bit is used when the

011-087 linear address range is ta be higher than 16 Mbytes 3-2 MemQry address aperture select These bits define the memQry address aperture fQr

which the OTI)87 will respond These bits have no effect if bit 0 - O Bits 32 Memocr address aperture

00 xOOOO()x3FFFF 256K aperture 01 x~x7FFFF SUK aperture t 10 xOOOOO-xFFFFF lM aperture Il xOOOucircO-lFFFlF 2M aperture

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

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PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

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Page 62

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Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Pl Pl Pl~1I10

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9~0- Pl~818

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856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

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vec Q lU 1 lin An Pl 1131 AU 13

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ISA BUS Pl

Pl

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~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 42: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

~ i- -

OTI-G87 Reglster Definitions

1 1 7-4 These bits define the starting address range for the On-087

Bits 7-4 Start address 0000 000000 - only VGA memory mapping (AOOO(BFFFF)

0001 100000-

iiii FO~OOcircO For 2 Mbyte aperture the starting address has to be multiple of2 Mbyte1 Default 0

1 3DF ClockSeIect Reglster Index = 6 RfW

1 Illi Description 3-0 Video Clock Select The state of these 4 bits are reflected in the pins CSEL[30] Bits

1-0 of this register are the images of bits 3-2 of register 3C2 Bit 2 of this register is

l the image of bit 5 of extended register D See frequency table for more details This

1 frequency table refleets On-068 only Future Oak dock chips may have different frequencies

Frequency Table for OTI-068

- CSEL3 CSEL2 CSEl1 CSELO ClOCK (MHz)

o o 0 0 252

o o 0 1 283

o o 1 0 650

o o 1 1 449

1 o 1 0 0 283

o 1 0 1 360

1 o 1 1 0 400

o 1 1 1 360

1

o 0 0 252

1 o 0 1 283

1 o 1 0 780

1 o 1 1 650

11

1 1 0 0 630 1 0 1 720

1 1

1 1 0 4001 1 1 1 1 500

1 7-4 Reserved Software reset must be executed each rime this register is updated

Default 0

1

shy

3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 43: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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3DF Configuration Reglster 1 Index = 7 R ( llli DescriptiQn o BIOS path width selectiQn

llitQ Description o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROMs)

2-1 Bus Modes These bits define the bus configuration Qf the cQntroller FQr different types of lQcal bus configurations see ConfiguratiQn Register 2 bits 1 and O

Bits 21 Bus MQdes 00 Local bus MQtherboard When this mode is selected the On-087

must be enabled through pQrt 94102 and 3C3 This mQde also disables ROM decoding at COOOO

01 Local bus Add-on When this mQde is selected the On-087 must be enabled through pQrt 46E8102 and enables ROM decoding at COOOO

10 Motherboard AT-bus configuration In this cQnfiguration the on-087 is enabled through 94102 and either 3C3 Qr ENVGA and dQes not respond to COOOO

11 Add-on card AT-bus configuratiQn In this configuration the On-087 is enabled through 46E8102 and responds to COOOO

4-3 DRAM type These bits define the type of DRAM used Bits 43 DRAM Type

00 64Kx16 01 Reserved ( 10 256~

11 512Kx8 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0)

Bitj DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA

6 IIO write sampling dock speed IOWn frQm the AT-bus is internally sampled with MCLK thus it is important to indicate tQ the IIO controller the MCLK speed

lfuj Description o MCLK gt- 44 MHz 1 MCLK lt44 MHz

7 CPU Clock select Bit1 Description

o Normal system dock lX dock for 386 IX dock for 486 1 VL-Bus CPU dock IX dock for 386

Bit 2 and bit 7 of this register in combination with bits 10 of Configuration Register 2 are used to enable the EEPROM function for capable 3864861ocal bus configurations

Inder-7 Index-8 Bit Z 2 Bit 1 0 fln1Z Description

x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386486 Local Bus o 1 x x BD[7] AT-Bus 1 0 x x EEPCSn 386486 Local Bus

The contents of this register are loaded from MD[ZO] during hardware reset

Page 36

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

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1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

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3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

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Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

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u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

~ccedil ~C

t-C-28-~C-Z-7-~-C-2-lC2 teI2r-1I~lt1ar-Tltln4Ihe15o-JJe2bteJ2I-JC8--1SC32--kC5-2--~C53 ~ li 22Ufiuml 2U~22uroZ2UF ~lUF1ii IlIr1ii lUr1iilUrlOluF19middot1UF1O lUlf lUF1l lUCID lU

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(

OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

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bullbull

1

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Page 44: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 (

OTI-087 Reglster Definitions

agraveI 3DF Configuration Reglster 2 Index =8 R Bit DescriptiQn

1

1-0 Local bus interface select bits - These bits define IQcal bus type These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00

Bits 10 Bus Type 00 Oak local bus

l

01 80386 local bus interface 10 80486 local bus interface Il Reserved

1 1 19) CQlOl Palette interface select bits

Bits 32 CoIQr Palette Type 00 Type 0 BT476 SC114871MSGI74 or equivalent

1middot 01 Type 1 MU9C1715 Qr equivalentreg Type 2 BT484 or equivalent 11 Reserved

1 For Type 0 PCLK is passed through For Types 1 and 2 PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode AIso for Types 1 and 2 MUXCLK is generated te Iatch pixel data For Type 2 BLANKn is delayed by 1 divided PCLK

5-4 lleserved 6 Enable Feature Connector for select local bus configurations Bits 0 l and 6 of this

register determine the function of pins 19 and 20 Bit 6 can only be enabled when GAlO and SllDYi are not needed i

1 Bits 6 1 0 Pin 19 fin1Q Pin 99 o 0 0 GAlO NC DCn o 0 1 GAlO SRDYi DCn

1 o 1 0 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA

1 1 1 0 EPCLK SllDYi EPDATA

1 111

7 DllAM support bit This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types The contents of this register are Ioaded from MD[158] during hardware reset

Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 1171 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn

1 3DF Suatcb Reglsters Index =9 A B RW Bit Description

1 7-0 8 scratch bits These scratch pads are defined and reserved for internal use Application software and device drivers should not use them

1

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

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3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

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Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

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tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

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J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

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Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

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WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

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---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

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Page 62

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Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

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856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

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VI 824 AH

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vec Q lU 1 lin An Pl 1131 AU 13

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 45: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

3DF CRr Control Reglster Bit DescriptiQn 7() NQt used

Index =C

3DF Oak Mlscellaneous Register Index = D llit DescriptiQn 2() FIFO depth CQntrol A minimum memQry FIFO depth is filled with display data

befQre CPU readwrite request is allQwed tQ process These bits are the image Qf index register 20 bits 2()

4-3 Extended graphies mode selectiQn These twQ bits are the image Qf extended register 21 bits 3-2

Bits 43 MQde SelectiQn 00 VGA mQdes Qr Oak planar mQdes 01 Oak packed pixel mQdes Used for 256 32K 64K and 16M

cQIQr mQdes 10 Reserved 11 Reserved

5 CIQck select bit 2 (CSEU) Used witll bits 2 and 3 ofMiscellaneQus register in the general registers area to select different dock frequencies Up to eight different dock inputs can be se1ected This bit is the image Qf extended register 6 bit 2 Refer tQ extended register 6 fQr dock table

7-6 Reserved This register is for compatibility purposes only New software devdopment should use extended registers 6 20 amp 21 Software rcset must he executed earo time this register is updated Default 0

3Df Backward CompatlblUcircty Reglster Index =E 1fu DescriptiQn 7() NQt used

3Df NMI Data Cache Reglster Index =F Bit DescriptiQn 7() Not used

3Df Dlp Swltch Resister Index =10 R Bit DescriptiQn 7() Dip switch status register The contents Qf this register are loaded from 5D[70]

during hardware reset

3DF Segment Reglster Index == 11 RW Bit DescriptiQn M Read segment fQr CFU memQry read 7-4 Write segment fQr CPU memQry write

Page 38

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

~ccedil ~C

t-C-28-~C-Z-7-~-C-2-lC2 teI2r-1I~lt1ar-Tltln4Ihe15o-JJe2bteJ2I-JC8--1SC32--kC5-2--~C53 ~ li 22Ufiuml 2U~22uroZ2UF ~lUF1ii IlIr1ii lUr1iilUrlOluF19middot1UF1O lUlf lUF1l lUCID lU

~c lc tClr1te17lJc1eacute~P-cln9r-lC3flb-LCuib-~eJ2~r-te2alc22

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1

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CD

I ~

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 46: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

~~It

1

011087 lieacuteglster Definitions

1 ~ These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater

than 256 Kbytes Bits 3-0 are used to address the video memory read operation Bits 7-4 are used to address the video memory for write mode operations Bits 3-0 are the image of index register 23 bits 3shy

1 O Bits 7-4 are the image of index register 24 bits 3-0

CPUADDR[1916] NRll[30] for read CPUADDR[1916] NRll[74] for write

This register is provided for compatibility purposes only New software devdopment should use

1 registers 23_ 24 Be 25 Default 0

1 3DF Configuration Reglster Index = 12

Bit Description 7-0 Not used

1 3DF Bus Control Reglster Index =13 RfW llit Description

1 2-0 Reserved 3 AT-bus Zero-Wait-State enable

Bit 3 Description

J o Disable zero wait state AT-bus operation 1 Enable zero wait state AT-bus operation

4 BIOS ROM bus width selection JTh1 Description

1 o Enable 8-bit video BIOS ROM interface 1 Enable 16-bit video BIOS ROM interface

S BIOS ROM address selection

1 Ifuiuml Description o Enable video BIOS ROM access at COOOO 1 Disable video BIOS ROM access at COOOO

1 6 10 access bus width selection BiL6 Description

o 8-bit IIO access

1 1 16-bit 10 access 7 Video memory bus width selection

llli1 Description

1 o 8-bit memory access ~ l 0 a 0 c3

1 1 16-bit memory access

Dcfault 0

-

1 3DF Oak Overflow Reglster Index =14

1lli Description o Vertical Total Bit 10

1 Vertical Blank Start Bit 10 rrshy 2 Vertical Retrace Start Bit 10L 3 High Order Stan Address Bit 8

64 Reservcd

1 Pue 39

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

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3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

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Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

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tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

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Vaid V i1

MRDn

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SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

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l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

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Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

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CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

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(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

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( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

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137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

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011-087 VESA Local Bus Schematlcs

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

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(

Page 47: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

7 Enable interlaced display ~lliLZ DescriptiQn ( 1

o nQn-interlaced display 1 interlaced display

DefauIt 0 NQte The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register index = 17 bit O

3DF HSYNC Dlvlded byTwo Start Reglster Index = 15 RW Bit DescriptiQn 7-0 This 7 bit value indicates when the vertical retrace will start in every Qdd frame during

interlaced mode The unit of this value is in the character PQsition

3DF Oak Overflow Reglster 2 Index = 16 Bit DescriptiQn 7-0 NQt used

3DF Extended CRrC Reglster Index = 17 RW Bit Description 2-0 High Order Start Address Bit 10-8 7-3 Reserved

Note The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14 bit 3

3DF EEPROM Control Reglster Index = 18 RW Bit DescriptiQn o EEPROM Data This bit is the data Hne between the seriaI EEPROM and the VGA

controUer When reading this bit data cornes from CSEL(O] When writing te this bit data is sent to CSEL[1] At the board level CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively

1 EEPROM CS This bit is used as the chip select cQntrol fQr the EEPROM It should be set to 1 for the VGA controUer to access the EEPROM

2 EEPROM Function Enable This bit selects the funetion of the CSEL bus When this bit is l CSEL[20] are used to interface with the EEPROM When this bit is 0 the CSEL[20) function as dock select signaIs

3 EEPROM Clock(SK) The value of this bit which acts as the shift dock for the seriaI EEPROM is ref1eeted on CSEL[2] To program the EEPROM this bit is

programmed to toggIe between 1 and 0 every 4us 7-4 Reserved

DegravefauIt 0

Page40

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

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JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

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u_ln

L

u

L

ua o La 0

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I

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LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

~I i Pmiddot1UF 86===idicircx~T~A~L~l--eumlD~VEOD~

~~~~2

NOTEI

AND

xT~gh~ 1-tt-+-------VvgtalIl1----lBlIKgt ~j~~t=tj 50 OVSSf 51 AVSS

ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

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10 1110 r~ e A 1

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 48: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 OTI-oS7 Register Definitions

1

1

3DF Cotor Palette Range Reglster Index =19 RW Jfu pescription 3-0 Color Palette range This register in addition to the IBM VGA Color Palette address 1 range 3C6-3C9 defines the VO address range for the Color Palette The Color

Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed Here x is defined by bits 3-0 of this

1 register The valid value for this register is 0 to E A programmed value of F disables the Color Palette range function

74 Reserved Default 4

1 3DF FIFO Depth Reglster Index = 20 RfW

1 Jfu Description 3-0 FIFO depth control This register defines what minimum level the display FIFO must

be filled to for a CPU readwrite request to be processed Bits 2-0 of this register are a

1 mirror image of bits 2-0 of extended register D

7-4 Reserved Default 1

1 3DF Mode Select Reglster Index =21

llli Description

1 o Enable Hi-eolor This bit is used to select the On-087 for Hi-eolor operation When this bit is enabled aIl horizontal CRT parameters are multiplied by two

1 1 Enable True Color This bit is used to select the On-087 for True Color operation

When this bit is enabled aIl horizontal CRT parameters are multiplied by three 3-2 Extended graphies mode selection

Bits 32 Mode Selection 00 VGA modes or Oak planar modes

1 01 Oak packed pixel modes Used for 256 321lt 64K and 16M color modes

10 Reserved

1 11 Reserved Bits 3-2 of his register are a mirror image of bits 4-3 of extended register D

4-6 Reserved

1 7 Select one refresh Bit 7 Description

o Normal operation

1 1 When this bit is 1 only one memory refresh cycle will be exshyecuted per scan line This bit overrides bit 6 of CRT register index - Il

Note Software raet must be accuted each time this registcr is updated Default 0

Page 41

1

~---_bull_ltbullbullbullbull

3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

(

- co co

u_ln

L

u

L

ua o La 0

0 o Ocirc U

I

a o J o U 1

w J 0 l-

l shyH al 1 ~ N

LLL lJ

Page 62

-------------- -- _-

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

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Page 49: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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3DF Feature Select Reglster Index =22 ( lBit Description o Enable content addressable for 64-bit graphie latch When bit 4 is low and this bit is

high content of the 64-bit graphie latch can be selected from system address to be written out to video memory

1 Reserved 2 EnabIe read cache This bit enables the read cache in the On-087 controller It

should be set to 1 for high performance operation 3 Enable write cache This bit enables the write cache in the controller It should be set

to 1 for high performance local bus operations This bit must not be enabled for ATshybus implementations

4 EnabIe 64-bit graphies latch 5 CPU latch swap This bit reverses the order of the high and low CPU latch during

CPU write operations This feature is useful when the CPU write address and CPU read address are unaligned

7-6 Reserved Default 0

3Df Extended Read Segment Reglster Index =23 RfW Bit Description 4-0 These 5 bits correspond to the CPUADR[2016] for CPU read operations They are

used to extend the 64K video mernory space (AOOOO-AFFFF) The least significant 4 bits of this register are shared with NRll[30] A write to one of these registers effects the contents of the other register

7-5 Reserved

3DF Extended Wrlte Segment Reglster Index = 24 RW Description These 5 bits correspond to the CPUADR[2016) for CPU write operations They are used to extend the 64K video mernory space (AOOOO-AFFFF) The most significant 4 bits of this register are shared with NRll[74] A write to one of these registers effeets the contents of the other register

7-5 Reserved o 3Df fxtended Common Read Wrlte Reglster Index =25 RW

Bit Description 4-0 These 5 bits are a write port for both register 23 and 24 A write to this register is

equivalent to writing into both index registers 23 and 24 A rcad to this register is equivalent to rcading the extended write segment register

7-5 Reserved

o

Page 42

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

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Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

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J

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1

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tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

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Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

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J

1 Vaid1

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XVaId )

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M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

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J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

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7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

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X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

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Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

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CASXn twCR 1

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-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

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Page 62

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820 A20 821 AH 822 A22 Pl

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vec Q lU 1 lin An Pl 1131 AU 13

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 50: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

OTI-087 Register Definitions

3DF Color Expansion Control Reglster Index = 30

1lli Description o Enable color expansion mode 1 llitD Description

o Disable color expansion mode

1 1 Enable color expansion mode Memory data written ta the video

1 memory depends on the contents of the foreground color register the contents of the background color register and the contents of the color pattern register

1 Planarpacked pixel color expansion mode select Bit 1 Description

1 o Packed pixel color expansion mode

1 1 Planar color expansion mode

2 Select pattern register for color expansion Bit 2 Description

o The CPU data bus is used ta select the foreground and backshy

1 ground register

1 The color pattern register is used ta select the foreground and

1 background register

3 Pixel mask enable

Jlli3 Description o Disable pixel mask function In this mode the masking function

1 is compatible with the mM VGA 1

1 Enable pixel mask function In this mode bath the map mask 1 1

register and the address masking in packed pixel mode is disshyabled

4 Pixel mask ordering ~ Description

o Bit 7 correlates to pixel 7 of a character

1 1 Bit 7 conelates to pixel 0 of a character

7-5 Reserved Default 0

1 3DF foreground Color Reglster Index = 3 t RW

1 fu Description 7-0 Foregroundcolor register These 8 bits define the foreground color in color

expansion mode

1 1

3Df Background Color Reglster Index = 32 RW ait Description 7-0 Background color register These 8 bits define the background ~lor in COIOl

expansion mode

bull

Page 43

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

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tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

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cs )

CA)

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U14 R29 ~Ol( A

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CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

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ltt0 YL-tlUI SOS1214 SOli S07

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HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

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POePS 16 17

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Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

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CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

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H4 50J V xe 2Sx4 50

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~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

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E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

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87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

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1- ~

l~ ~~ ~iltIuml i~

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J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

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Page 66

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RAS

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---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 51: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

3DF Color Pattern Reglster Index == 33 RW if ltIfu Description

7-0 Color pattern register These bits select the foreground and background color patterns in color expansion mode When a bit value is 1 the foreground color is selected Background color is seleeted when a bit value is o Bit 7 corresponds to the ftrst pixel

3DF Pixel Mask Reglster Index == 34 R[W llli Description 7-0 Pixel mask bits

lllilQ Description o Mask pixel data 1 Pass through pixel data

These bits are effective when NR30[3 =1 For Oak packed pixd modes this register can be used to mask individual pixels of a character with bit 0 being the first pixel in a characterFor planar modes this register can he used as the map mask register In planar mode the least significant 4 bits are used as the map mask bits when the video memory address is odd and the most significant 4 bits are used when the address is even

3DF CPU Latch Index Reglster Index == 35 RfW llli Description 2-0 CPU latch index register These 3 bits select the CPU latch that will be accessed

through the CPU latch data register (index=3DF) This register is automatically incremented when a read from or write to NR36 oceurs

7-3 Reserved

3Df cru Latch Data Reglster Index = 36 RW Ifu Description 7-0 CPU latch data register These 8 bits reflect the data stored in the graphies latch

selected by the CPU latch index register

3DF HC Horizontal Stan Reglster Hlgb Index == 40 RfW llli Description 7-0 These are the high order bits of the horizontal starting position of the He relative to

the start of the display area in pixel units The top left corner is at (OO)

3DF He Horizontal Stan Reglster low Index == 41 RW Bit Description 7-0 These are the low order bits of the horizontal starting position of the HC relative to

the start of the display area in pixel units The top left corner is at (00)

l

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

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---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

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U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

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CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

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HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

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Page 62

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AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

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v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

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~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

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8-BIT VIDEO BIaS C32KB)

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~~~bull AliAAl0 A11 A12 A13 A14

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87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

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j ~~

1- ~

l~ ~~ ~iltIuml i~

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---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

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856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

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Page 66

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AD DO HA AD DO ~AO DO Al Dl Al Dl Al Dl A2 D2 A2 D2 A2 D2 AJ D3 A3 D3 A3 D3 A4 A4 AS AS A6 A6 Al Al AB AB

RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

RAS CAS WE

~ SOJ 4n6-70

A 1

AD DO Al Dl A2 D2 A3 D3 A4 AS A6 Al AB

RAS CAS WE OE

SOJ 42i6-70

MAP0 Cr0 )

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Qll

$ 1 MB

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CONFIGURATION SETTING

MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

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087C021093-oo1

~~---shy

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Page 52: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 -

~ -

jI

OTlo087 Reglster Definitions

3DF HC Vertical Start Reglster Hlgb Index = 42 RW

1 Ifu 7-0

Description These are the high order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Vertical StartRegister Low Index = 43 RW

1 lfu 7-0

Description These are the 10w order bits of the vertical starting position of the He relative to the start of the display area in pixel units The top left corner is at (00)

1 3DF HC Horizontal Preset Reglster Index = 44 RW

1 lfu 7-0

Description This register defines the starting horizontal position of the He within the 64x64 pixel area The He a1ways ends at position 63 (iebull no wrapping)

1 3Df He Vertical Preset Reglster Index =45 RW

1 fut 7-0

Description This register defines the starting vertical position of the He within the 64x64 pixel area The He always ends at position 63 (iebull no wrapping)

1 3DF HC Stan Address Hlgb Low Reglster Index =47 RW

1 Bit 7-0

Description This register is the 10w order byte of the high order word of the linear starting address of the 64x64 pixel buffer within the video memory

1 3Df HC Stan Address Low Hlgb Reglster Index =48 RW

1 llli 7-0

Description This is the high order byte of the low order word of the tinear starting address of the 64x64 pixel buffer within the video mernory

1 3Df HC Stan Address Low Low Reglster Index 49 RW

1 Bit 7-0

Description This is the low order byte of the low order word of the 1inear start address of the 64x64 pixel buffer within the video memory

1

1 Page 45

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

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Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

e1 MAP2 (r1 ) MAP2 (r3 ) MAP3

1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

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NOTEI

AND

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ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

- ~

j ~~

1- ~

l~ ~~ ~iltIuml i~

-2

---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

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t-C-28-~C-Z-7-~-C-2-lC2 teI2r-1I~lt1ar-Tltln4Ihe15o-JJe2bteJ2I-JC8--1SC32--kC5-2--~C53 ~ li 22Ufiuml 2U~22uroZ2UF ~lUF1ii IlIr1ii lUr1iilUrlOluF19middot1UF1O lUlf lUF1l lUCID lU

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

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MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

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Page 53: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

---3-D-F-H-C-C-o-lo-r-O-R-egl-ste-r--------r-n-d-e-x-4-A--RW------ ( m

llit Description 7-0 This register defines the sprite color O

3DF HC Color t Reglster Index =48

Bit Description 7-0 This register defines the sprite color 1

3DF HC Control Reglster Index4C RW llit Description o HC color control Power-on default is O

BiLQ Description o Disable HC color 1 Enable HC color

1 HC display selection lfu1 Description

o He is in overscan mode 1 HC is displayed over the overscan

2 HC data format lllil Rescription

o Bit 0 is the first pixel 1 Bit 7 is the first pixel

3 HC blink rate enable IDt1 Description

o Disable HC blinking 1 Enable He blinking

HC blink rate control Bits 54 Blinking rate

o0 4 frames on and off o1 8 frames on and off 10 16 frames on and off 1 1 32 frames on and off

7-6 Reserved Default 10

l

Page 46

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

pRO~ - CTO aUFFER al

101 BlJptI 102 B2YltC nnnul

15

101 B3 Ea-Il 160X 104 81-21 l16DX AS es SI 106 B6 Cr107 171Abullbullbull crlS

JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

SADpS SA~ 5102 5103 SA4 SAS SA6 5107 SA8 5109 SAlO SA~l SA12PZ4bullbull 51013 5AJ4ltliIl SAIS no 1610 BUli) SA16 SA1 SAlll SAi9 5A20ri 51021 51022 SA23(0 VL-eulgt ~

lS SRDYI

1 Y~C lt1020

ltTo BUFFER Al _ - 10K 1l00~ rsIl SD1~- rs TO 8UFFERS ) _ - 1l0Z

0 (PS c D E F _ - 803 lS 1l04cPUAO

g~~~ - - 1l07CPURfiSET

bull --- -- SOO

-7 SO~ SOZ 503 504

ltt0 YL-tlUI SOS1214 SOli S07

11 508 501 SOlO sou 5012 5013 5014 SOlS

HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

~m[FB8i[~

Mm1 Pl 12 13 14

POePS 16 17

iiYSYNC 11~~~~~~~~~I~~~III~SIISESE

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L

u

L

ua o La 0

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I

a o J o U 1

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LLL lJ

Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

l ft

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1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

gt PliA 47K

P70 471lt PA 471lt

04 7K

CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

DO Dl 02 03

H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

A$ CAS EDE ~4 SN

(r5 ) MAP3 Cr7 )

E a CI en go CIl a Il)

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8-BIT VIDEO BIaS C32KB)

Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

~~~bull AliAAl0 A11 A12 A13 A14

1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

l vcc

R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

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~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

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j ~~

1- ~

l~ ~~ ~iltIuml i~

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---------- - - - - - r-~~

J2 CON 36 PIN AT IIU5 Pl

Vcc

- T01 clPl 02 c2 03 C3 Pl O c oIL-- 05 cS Bl Al 06 C6 B2 A207 C7 B3 A308 C8 94 A4 D c

Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

l11lH lQ1(

VESA LOCAL-BUS

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Page 66

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apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 54: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1

OTI-G87 AC Timing and DC Parameters

~ Signal Timing 1

Video Memory Cycle Timing

1 1 1 1 l 1 ~

1 1 1

~

Valld

J J

~SMC tMCP tAllMC

- toVMR 1

SA[t90

J

~MRDt

J

~toSMW tDHMW ~

X Valld X ~ DY ~

Valld )(J(Ilead)

(WrIte)

___)l-__V_alld__-X _

______flt- _

tows

Mt6n

AU

MWRn Mmn

5D1150]

SD[tSO]

1A[13171

IOœRDY

ZEROWSn

1 1 1 1 ~

1

5ymbCl1 Pamew MIn (Ils) Max(ns)

tAU AU AdNe ID lnadIve 40

dAS ~17) $eq) ID FEdse clAU 15

l1AH ~17) HoId ltom ralkls Edp clA1L 5

lM16 M 1611 Adve fiom laid lAI23171 40

ONS ZEIlIOYtSn Delay IanCcnmnI ZS

tASMC SA(16O Secup ID Memory Corrwrw1d kJNe ZS

wa lVIemclly Ccmnwld NMWIdlh 165

tAHlVC SA(16O HoId tcm Memory CcmNnd nIclIYe 20

lDVMIl R-I DcaVlIId ampam MllDnAcllw (0 W State) 65

MNJ( ROY lniIcIIw hm MemcIy Ccmrnand ADNe 3J

tDSMN WIftIIt Daca $eq) ID MIlWft Adtve middot45 tDl-NW WJtœ Dara HoId Iian MWIln NcMt 15

rsNPJ]( RNd Data VIId ftom ROY Aatve 5

tDHMR R-I DMa HoId fian MllDn lMclIoie 0

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

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WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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1098 (2790)

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( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

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CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

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HAOIC2J HA01C3J MAOl(4) HAOICSJ MAOIC6J HAOlcn MAO leS)

HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

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Page 62

-------------- -- _-

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MAP0 (r0 ) MAP0 (r2 ) MAPi

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CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

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CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

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IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

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Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Pl Pl Pl~1I10

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936 A36 1116 A16 837 A37817 A17

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820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 55: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

Video ROM Cycle Timing (

AU n -----------------shyLAr2311] ___fi1 VaUd

l-------------shy

5AI190] V i~

Vaid V i1

MRDn

BDI150]

SDI1501 (Read)

ROMENn ~

1

~ASM~~ tMCP t~M~ 1

J

1 Vaid1

tBDSD DHM~ ~

XVaId )

~M~ tMRRE ~

M16n remains high when the Bus Control Register bit 4 or Configuration Register 1 bit 0 is set to O

Symbol Parameter Min (os) Max (os)

tM16 M 16n Aettve from VaId LA23 t 71 40

tASMC SA[160 Setup ID Memory Command ActIve 25

tMCP Memory Command Pulse Wldth 165

tAHMC SA[1601 Hold from Memory Command Inactive 20

tDHMW Wrlte Data Hold from MWRn Inactive 15

tOHMR Read Data Hold lrom MRDn Inactive middot0

tBDSD 8D[70 VaUd to SOU 501 VaUd 3S

tMRRE ROMENLn Delay from MRDn 15

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

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tSRDY tSRDY

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~ W J

J

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WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

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Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

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middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

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011-087 VESA Local Bus Schematlcs

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HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

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Page 62

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CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

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IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

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820 A20 821 AH 822 A22 Pl

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VI 824 AH

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vec Q lU 1 lin An Pl 1131 AU 13

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apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 56: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

l

l Video Pixel Timing arame ersOTI-oS7 AC Timing and DC P t

i

P[70)

VCLI(

PCLI(

BLANKn

Type 0 DAC 1 1 1 1 1 1 1

Type 1 DAC -1516 Bit Color

PCLK

VCLK

BLANJCn

1 1 1 1 1 1 1 [

Page 49

1

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

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PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

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ATOEHn ATOELn

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LBSELn

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WrlteSD

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Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

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1 1 1 1 1 1 1 1 ~

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OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

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l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

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(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

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137 (347)

125 (317)

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TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

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Page 57: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

Type 1 amp Type 2 DAC True Color r--------------------------- (

VCLK

t MXPXS t MXPXH t MXPXS t MXPXH tlVOI tCHPX

ffi ffi

PCLK

MXCLK

BLANKn

Video Pixel Timing

Type 0 Type t and Type 2 DAC Timing

Symbol Parameter Min (os) Max (os)

tVCKP Video Input Cock Perlod 12

tVCKH VCLK Wldth High 6

tVCKL VCLK Wldth Low 6

tCHCH Pixel aock Perlod 12

tCHCL PCLK Wldth High tVCKH-1

tCLCH PCLK Wldth Low tVCKL-1

tPVCH Pixel Word Setup nme 3

tCHPX Pixel Word Hold lime 3

tBVCH Blankn Setup lime 3

tCHBX Slankn Hold nme 3

tMXPXS Mux Code Setup nme 3

tMXPXH Mux Cock Hold lime 3

tPKMXK Pixel CJock to Mux Cock Delay 2

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

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~ W J

J

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X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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1 40

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PagcS8

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---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

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Page 62

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Pl B19 A1B B19 A19

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YCc A3Œi Al

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AD DO HA AD DO ~AO DO Al Dl Al Dl Al Dl A2 D2 A2 D2 A2 D2 AJ D3 A3 D3 A3 D3 A4 A4 AS AS A6 A6 Al Al AB AB

RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

RAS CAS WE

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$ 1 MB

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MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

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1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 58: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 ( OT-o87 AC TlmlnB and De Parameters

Video DAC 10 Timing

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SAIt90) ValldJ J~

ASIO tloCP t-H1ct IfIOWn ~ J

tlcDC towP j ~

DACWRn toVJw toHIW ~ ~

50[150] II XVaUd(WrJte) JI

tsOBD J

8D[70 V VaUd (Write) 1

IORn

Valld

1

J1

~CDCtlCDC

J

DACRDn

8D[10) 1 (Read) tsoso SD150 V ~ VaUd

(Read) Symbol Parameter Min (ns) Max (ns)

tAS10 SA[160] Setup to 10 Command Active 25

tAHIO SA[160] Setup from 10 Command Inactive 30

tlOCP 10 Command Pulse Width 115

tOVIW Wrlte Data VaUd from 10Wn Active -55

tOHIW Wrlte Data Hold from 10Wn lnaetlve 15

tOHIR Read Data Hold from 10Rn Inactive 0

tICOC DAC Command Delay from 10 Command 25

tDWP DACWRn Pulse Wldth 70

tSDBD SO[70] VaUd to 80[10] Valld 50

tBOSD BD[70] Valld to SD[150 Valld 35

Page 51

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

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15

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CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

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ltt0 YL-tlUI SOS1214 SOli S07

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HA23CO)rtA23C 1) t1A23C23 HA23C3J HA23[4J HA23C5J A21(6) t1A23CJ A23CIl)

HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

H010 11011 HD12 H013 11014 HD11S H016 D17

H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

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POePS 16 17

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Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

MAP0 (r0 ) MAP0 (r2 ) MAPi

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v~ PUA 47Kv~ ~ 1

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CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

PlOA 47K

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H4 50J V xe 2Sx4 50

(r4 ) MAPi (r6 )

~ AO DO Al 01 A2 02 A 03 A4 AS A6 A7 A8

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E a CI en go CIl a Il)

n CIJ

8-BIT VIDEO BIaS C32KB)

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~~~bull AliAAl0 A11 A12 A13 A14

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CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

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JPS

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j ~~

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l~ ~~ ~iltIuml i~

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J2 CON 36 PIN AT IIU5 Pl

Vcc

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Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

-12V 1 til 187 A7 828 A2e88 A8 829 A29B A~ 830 A30Pl BU A31

Pl Pl Pl~1I10

Al0 1111 All 932 A32 B12 A12 B33 A33Pl 813 AU11 VCC NloR9 Il 6sect 1~ ~ Bl5 A15 814 A14

936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

A18 R13~~Rl06 ~~gA~11 -- - 81 AlS iK 1( Il ff 1i~ i 1- shy

856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

826 A26 827 A27 Pl 828 A28 Pl 830 A30

vec Q lU 1 lin An Pl 1131 AU 13

P3 Pl

ISA BUS Pl

Pl

CcedilC

~ Pl B42 A42 841 A41 -- - Pl 843 A43 shy ~~- Pl844 A44 - - Pl84S A45 846 A46 -=-shy847 A47 nv_ Pl848 A49 - -- Pl84~ A4~ 8S0 ASO 851 ASl 8S2 AS2

Rl041 VCC Bi3 AS3 lK 854 A54 855 A55 Tn 13

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

- - - - - - - - - - - -

bullbull

1

fIBAZ2lJC-oclAlJ4mrnn]lC122 230 IBA23tO B] gt T~l R65tT

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rmiddotmiddotmiddotr~ r-iuml IC ~6 c

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14

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10 1110 r~ e A 1

yoUT1 AP A6 AI V~C U A4 U middotAS i-C-7-lttIC-ll-I-C-----L C10a AZ 81 Al L luF 1 luF =r luF t 1

V~CVCC

i-c-14-I--Cl-S-X-C-l-Z-1cu 14 u zzuF eacute 2Zul eacuteZZul f-ZZUl

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AD DO HA AD DO ~AO DO Al Dl Al Dl Al Dl A2 D2 A2 D2 A2 D2 AJ D3 A3 D3 A3 D3 A4 A4 AS AS A6 A6 Al Al AB AB

RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

RAS CAS WE

~ SOJ 4n6-70

A 1

AD DO Al Dl A2 D2 A3 D3 A4 AS A6 Al AB

RAS CAS WE OE

SOJ 42i6-70

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Qll

$ 1 MB

Il c 10K

1

D lDK ~ Rn

shy i--lDK

2

Il ~

11 lOIlt 10il lOK -rOM

Ii7

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MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

CI i en g ~

1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 59: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

middot bull)_-___- _-__

Video 10 Access Timing

Valkl5AI190J

1016n

~OCP

10Wn 10Rn

toVIW

5D[150] (Wrlte)

toVIR

5D1150 Valkl (Read)l

VaUd

Symbol Parametel Min (ns) Max (ns)

tI016 1016n Active (rom Valld 5A[150) 60

tASIO SA[160) Setup to 10 Command Active 25

tAHIO SA[160) Hold from 10 Command Inactive 30

tIOCP 10 Command Pulse Wldth 115

tDVlW Wrlte Data Valld from IOWn Actfve ~55

tDHIW Wrlte Data Hoid from IOWn Inactive 15

tDVIR Read Data VaUd from JORn Active 70

tDHIR Read Data Hoid from 10Rn InactIve 0

l

PJse52

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

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[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

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X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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PagcS8

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---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

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Page 66

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 60: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 OTI-087 AC Timing and DC Parameters

~

1 1 1 1 1middot 1 1 1 1 1 1 1 1 1

Local Bus Interface Timing1

Tt n

386 CLK2

486CLK

ADS

ADDR

DIR

SDHOEn SDLOEn

SRDYO

CPUAO CPUAl

CPUBHIn

1010 10Wn

ATOEHn ATOELn

DIR

LBSELn

DCa WIla

SRDI

JleadSD

WrlteSD

JVv~~rv-v-V 1

J 1 J

tss

V Valld ~

J Jrr

~toIR tolR ~

7 - tSD~

~ tsoOEI

tSRDY tSRDY

~ kJ tADEL

~ W J

J

tAT ~E ~~

1 tusSEL _tu EL

[ ~ ~ I

J A

I~DIlYl J fHsRDYI

( v bull lRDs _ ~tI

icirc Vald X~

WDs ~ ~

X WoH1

VlIIId D_ C2

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

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Page 62

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 61: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

Local Bus Interface Timing (

Symbof 1 Parameter Min (ns) Max (ns)

tDIR DIR Active from CPUCLK 6 25

tSDOE SDHOEn SDLOEn Active from VaUd Address 6 15

tSRDY SRDYn ActiveInactive from CPUCLK 6 15

tADEL CPU AO At BHEn VaUd from BE()3n see Note 1

tATOt ArOt Active from rOWRnIORDn 20

tLBSEL LBSELn VaUd (rom SA 15

tSSRDYI SRDYI Setup nme 5

tHSRDYI SRDYI Hold Tlme 3

tSS Status Setup nme 4

tHS Status Hold TIme 4

tRDS Read Data Setup TIme 12

tRDH Read Data Hold lime 7

tWDS Wrlte Data Setup Tlme 7

tWDH Wrlte Data Hold TIme 5

Note 1 This delay depends on the necessary external PAL Please refer to the tables below for PAL speed requirements

PAL Interface for 80386DX CPU

Loccedilal Bus FreQuency 20 MHz 25 MHz 33MHz 40 MHz

PAL Interface for 80486 cru

LgqI Bu freacnc 20 MHz 25 MHz 33 MHz

pAL 1618 t5 ns t5 ns tOns 7ns

PAL 16LB 15 ns 15 ns tOns

Page 54

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

1098 (2790)

-- --0

~ t 00

~ -

(~ - ~ C C ~ - - shy

41

1 40

El 004 (102) 1

PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

~t1AOICO) MAOlC IJnn

018 1 f l

UKfK 1

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101 BlJptI 102 B2YltC nnnul

15

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JI6 fi)~glR CC) (0) gshy l~I 1

CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

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HOO Hol HOZ 03 H04 HOS HOlt H07 HOB HO1

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H011 11020 H021 11022 11023 HD24 H025 11026 11027 028

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Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

AS CAS EDE Mol SOJ

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1 MB VIDEO ME MORY w 256Kx4

v~ PUA 47Kv~ ~ 1

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CONFIGURATION SETTING

v 6 10 _v v ltIv V ~ ~vv V

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H4 50J V xe 2Sx4 50

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Plbullbull Ul spe 5410 00 1U ~Rq 1 (soto o1SJ gt P125 Al 01 A2 02 A3 03 A4 04 AS OS

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1 BD MBN 1iHU~ampI~ 27CIJC -120

1024-BIT EEPROM

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R26 o OHHDUAL VIDEOMEMORY CLOCK GENERATORt

C41 22~F ~C4 ~50

L

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~~~~2

NOTEI

AND

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ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

(

JPS

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Pl 95 ASPl010 clO 96 A6DU cU B7 A7012 cn B8 A8 013 C13 9~ A~ OH C14 910 Al0OlS C15 B11 All016 CU 912 A12Pl 017 C17 BU A13

_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

1 CON 62 PIN AT US 920 A20Pl B21 A21 B22 A22RESETPl ltBESEIJ A2 B23 A23

YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Pl Pl Pl~1I10

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936 A36 1116 A16 837 A37817 A17

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856 AS6 B57 A57 858 A5B

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VI 824 AH

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vec Q lU 1 lin An Pl 1131 AU 13

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Page 66

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LA1BCA1B D1G B A 81 A18

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

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Page 62: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

V-

11 Ir

~ AS~ ~ tpc ~ C tAAtcPA

J tRAC lOl I_i--+~ _ V VaUd V IId

L_

tRAH RSH

Ir-~==t1r ~ ~ Col Address Col Ad ~ress J_

ASC teAH ~

tRAS J

1 1 1 1 1 1 1 1 ~

1 1 1 1 1 1

OTIo87AC Timing and DC Parameters

DRAM Interface Timing

tMCKR tMCKR

MCLK

tRC ~

tRP ~ If

RASXn --J

~ tASR

-------~==~S====~__--MAO1[801 __________X Row ~ddress MA23[801

CASXn

)shyMDI3101 ____(Read)

CASXn twCR 1

~s ~ _ ~tcWL

-------------+------1 f --WEXn toHR 1 J (Wrlte only)

~ tos ~ toH ~ MD[3tO] )- v VaUd W VaUd

l -- 11-- 1 (Wrlte)

Memory Refresh Timing

CAS

RAS

MCLK

tcHR

bull Page SS

1

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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00

r--80

1098 (2790)

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1 40

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( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

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Page 62

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Page 66

- - - - - - - - - - - -

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5TR081 AUDO 5D1Ccedil H5YNC

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 63: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

c DRAM Interface Timing amp Memory Refresh Timing

SYMBOL PUlAMETIR Min (ns) Max (ns) tMP Memory Clock Perlod 22 25

tMCKR Memory CJock RiseFall 25

tRC Random RdWr Cycle TIme 7tMP

tRP RASn Precharge TIme 3tMP

tRAS RASn Pulse Wldth 4tMP

tCSH CASn Hold Referenced to RASn 4tMP

tAR Column Address Hold Ref to RASn 4tMP

tRAL Column Address ta RASn Lead TIme 2tMP

tASR Row Address Setup Time 1tMP

tRAH Row Address Hold Time 1tMP

tRSH RASn Hold Referenced to CASn 1tMP

tASC Column Address Setup Time 1tMP

tCAH Column Address Hold Time 1tMP

tcP CASn Precharge Time 1tMP

tCAS CASn Pulse Width 1tMP

tPC Fast Page Mode Cycle Time 2tMP

tRAC Access Time from RASn 4tMP

tCAC Access Time from CASn 1tMP

tAA Access Time from Col Addr (MA) 2tMP

tCPA Access Time from CASn Precharge 2tMP

tRWL WExxn to RASn Lead Time 1tMP

tWCR WExxn Hold Ref to RASn 4tMP

tWCS WExxn Setup to CASn OtMP

tWCH WExxn Hold Ref to CASn 1tMP

tCWL WExxn to CASn Lead Time 1tMP

tWP WExxn Pulse Wldth 1tMP

tDHR MD Hold Ref to RASn 4tMP

tDS MD Setup to WExxn 1tMP

tDH MD Hold to WExxn ltMP

tCSR CASn Setup to RASn (Ref Cycle) (2) 1tMP

tCHR CASn Hold to RASn (Ref Cycle) (2) 2tMP

Notes 1 Refresh Cycles are implemented as CASn before RASn REFRESH cycles 2 Write cycles are implemented as EARLY WRITE cycles

Page 56

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

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( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

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016 (40) 025 (65)

008 (20)

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125 (317)

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137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

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Page 66

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1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 64: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

1 bullbullCmiddotmiddot

OTI-GS7 AC Timing and DC Parameters

DC Specification ABSOLUTEMAXIMUM RATINGS

1 AmblentOperatlngTemperature OOCto +70oC Storage Temperature -650C to +150oC Supply Voltageto Ground Potentlal -Q5V to +70V1 Applled InputVoltage Q5V to +70V

1 Stresses above those listed may cause permanent damage to the On-087 These specifications are stress ratings on1y and do not apply to operational use Functional operation of this device at these or any other conditions above those indicated in this datasheet is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability

1 l 1 1 1 1 1 1

Symbol Parameter Min Max Unit Conditions

Voh Output Voltage Hlgh 24 V loh-400 uA

Vol Output Voltage Low 4 V 10124 mA Note 12

Vol Output Voltage Low 4 V 101-12 mA Note 1

Vol Output Voltage Low 4 V 101=10 mA Note 1

Vol Output Voltage Low 4 V 101-8 mA Note 1

Vol Output Voltage Low 4 V 101-4 mA Note t

Vol Output Voltage Low 4 V 101-2 mA Note 1

Vlh Input Voltage Hlgh 2 VCC+05 V TIL Note 3

VII Input Voltage Low ()S 08 V TIL Note 3

III Input Leakage Current -to 10 uA

011 Output Leakage Current -10 10 uA

ICC Operatlng Supply Current 125 mA

CI Input Capacltance 8 pF

Co Output Capacltance 8 pF

Cio VO Capacltance 8 pF

1 Notes

1 1) Output Current (Iol) Capabilities

24mA SD[150 with slew control SmA SRDY RASLn RASHn CASAn WEAn WEBn MAO1[O MA23[O] HSYNC VSYNC

1 LBSELn BLANKn P[70 PCLK

4mA BD[70] MAOl[81 MA23[81] MD[310] 2mA CSEL[30] DACRn RACWn ROMENLn

2) Open Drain (open collector) Outputs [ 24mA IOOlRDY CINfn 1016n M16n ZEROWSn

1 3) Input Structures TIL AlI

Page 57

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

ii) 0bull ~ 0) shy- - ci a t t t

00

r--80

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-- --0

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1 40

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PagcS8

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

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016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

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026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

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Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

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87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

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_018 C18 914 A141124YCC~ US A15R30 816 A16300 OHI1 B17 A17

Pl B19 A1B B19 A19

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Pl Pl Pl~1I10

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vec Q lU 1 lin An Pl 1131 AU 13

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

- - - - - - - - - - - -

bullbull

1

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5TR081 AUDO 5D1Ccedil H5YNC

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1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 65: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

--

middot ~

(Package OntUnes AIl dimensiQns in mils (mm)

1238 (3145)

1218 (3095)

1106 (2810)

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r--80

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1 40

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( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

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-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

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Page 62

-------------- -- _-

AO AO DO AO Al MAl Dl Al 2 A2 02 A2 A~ A3 03 A3 A4 A4 A4 AS AS AS A6 A6 A6 A7 A7 A7 Alli Alli A

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v 6 10 _v v ltIv V ~ ~vv V

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ST ROllE AIIOO

53 e7KDIIaJCgt-_~-Il IL ~~~~~~FS2 OlODDVS5

~eg ~~~ 1-tt----------gtvvgtalIl1--J=---ElIKgt

87 SHOULD liE DELETED

CONNECT OIECTLY WHEN )USINe 66 I1IIZ CLIC

4 CLII

IN IN 440 HZ IN OUT 500 HZ 25 24 OUT IN 660 HZ 4711 711 UT OUT 400 HHZ Li ~

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Pl B19 A1B B19 A19

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YCc A3Œi Al

B24 A2484 A4 825 A2585 AS 926 A26 86 A6 827 A27

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Pl Pl Pl~1I10

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936 A36 1116 A16 837 A37817 A17

9~0- Pl~818

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856 AS6 B57 A57 858 A5B

820 A20 821 AH 822 A22 Pl

Imiddot 8231 A2JI Pl 825 A25

VI 824 AH

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vec Q lU 1 lin An Pl 1131 AU 13

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OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

- - - - - - - - - - - -

bullbull

1

fIBAZ2lJC-oclAlJ4mrnn]lC122 230 IBA23tO B] gt T~l R65tT

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5TR081 AUDO 5D1Ccedil H5YNC

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$ 1 MB

Il c 10K

1

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2

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11 lOIlt 10il lOK -rOM

Ii7

CONFIGURATION SETTING

MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

CI i en g ~

1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 66: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

~ _ i bullbull

---OTI-087 Package Outline

( Package Outlines AIl dimensions in mils (mm)

1 1 1 1 1 1 1 1

1 1 1 1 1

Notes

1

063 (160)

008 (20)

JJ 0middot10 _ 037 (95)

016 (40) 025 (65)

008 (20)

~ 013 (0005) TYP ~

-J[tt

137 (347)

125 (317)

-shy020 (50) 002 (05)

026 (65)------~

TYP

137 (347)

125 (317)

1 Controlling dimension is mm

( 2 Oak Technology Ine reserves the right to change the package dimensions at any time andwithoutshy

notice

PageS9 1

(

011-087 VESA Local Bus Schematlcs

- - - - - - - - - - - - -lBI

- _-shy -- -

cs )

CA)

_- shyr r

Y~C YCC

U14 R29 ~Ol( A

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101 BlJptI 102 B2YltC nnnul

15

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CD 51 IIIOTI-087 LOCAL-BUS YGA CONTROLLER ~ () III

PS FRSROY15 PS PS PS PS PS PS PS LPS PS PS PS fir~

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lS SRDYI

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 67: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 68: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

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Page 69: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 70: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

-------------- -- _-

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

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Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

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Page 71: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 72: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

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Qll

$ 1 MB

Il c 10K

1

D lDK ~ Rn

shy i--lDK

2

Il ~

11 lOIlt 10il lOK -rOM

Ii7

CONFIGURATION SETTING

MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

CI i en g ~

1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 73: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

~

(

OTI-087 Trile Color ISA-Bus Schematlcs

Page 66

- - - - - - - - - - - -

bullbull

1

fIBAZ2lJC-oclAlJ4mrnn]lC122 230 IBA23tO B] gt T~l R65tT

~mm ~~ ~j~EmmE lMllPllCJQlJJiJ1J_ltEImllJOHDO ~_~ ~~~ _1 CHoto 3D gt

~g~mw

t 1

11~IIIII~I~~~il~

r - -__- shy r

0shy~

Cl~g~ CZ 03 C3 Ul 04 C4 Ji05 CS 06 C6 ~ADICDJ 07 C7 08 C8

MAOle1Jnn 4

AOIC2J78 I~SROY t1AOIC3J

010 CIO 09 C

IOCHRDY MAOlCJ 011 CU HADICiJ OU C1Z f1AOIC6J OU CU AOIC7J

C14IICC -mm MAOleeJ 1 016 Cl6 017 CH

CUi L-OA ~~i~~~ALE018 C18 A23C2J bUs-J

MA23C3JIr~

SAOCAOC681 Al SA1CAlSAZCAZ

IICC4 ~ n A3 sa AZ ZZOpf l

SA3CA3 HDI B4 A4 SA4CA4 H02 BS AS SASCAS HD3 86 AI SA6CAI HD4 B7 A7 SAl7CA7 HOS-1ZV 1U1 $80Y A8 SASCAS8 A SA9CA9810 A10 SAlOCAlO HOS B A SAllCALi 09 Bl2 AU SA12CAJ2 010 BU A13 SA13CA13 11011 814 Al4 5A14CA14 H012 BIS A15 SAISCAlS H013 B16 A16 SA15CA16 H014 B17 AH LA 17CA17 HDiS

LA1BCA1B D1G B A 81 A18

LAL9CA1 f1017 BZO AZO LA20lCA20 11019 21 AU LA211CA21 H019 u AZZ LA22CA22 11020 BU AU LA23CA23 11021sa4 AZ4 H022 ZS AZS XPCLIlt~ 023 826 A26 H024 8Z7 A27 ~5 71 ii1~m~~~~gYl 025

PU 1 1 1Z AZ8 D261Iee Q 829 A29 ~ R~9 +9 BOOlITrn H027 30 AJa HD2BBOl31 AU BOZ HD29

B03 HD30 B04CPUAO HOUliCe

=g~~~ ii 1CPURESET HA1

lS00

SOZ 503 S04 ~S ~

liCe yec 506 Pl501507 12

R44) R4S SOS 13 SD 14

UALZ VCLK SDll 16TAll DVDO PSi~~I~SD10 ~~laH$f==I~~~S )(~5~~~ Rl FRl ~gt~ P7 fil AYS5 5014 YSYNC

5TR081 AUDO 5D1Ccedil H5YNC

- e~s ~~~ ~i~OeRO ~ bullHtt~~~~t~~~ g~~~ ~ft~----_-JI---sectI~~~~~~~~i~~~~~IVCLI( ~ CSELIEEPWO SWSENSE

~~~t~EEP5K IIT6rRtE~ bull bull g~ ~

liPi 9S ENVQAAm PROCLK~lice unlice

R301129 7K7M Innun 1IC on-oB7

15 IN 1Re~14 1kamp~ijk~glZ P1S 1 lM IN lM OUT sa OUT IN U OUT OUT 40

Xl 1431Z 1

~

a=shyC i fi) g ~

~ n QI

TRUE COLOR RAMDAC

CZ7

Rtt9iI~ ~

m~I~~ 1s~ ~NSEI ~

amp8

07 06 O~ D4

R51

03 02

Di R5Z

R50 17 P6PIP ~3 12 ~1

PO

R18

47 OHM __ css ~47PF

Rl

7 OH -- c34

~47

1 F83 ~I ~

1 0815

R2Z 715 OH --J lV

l R21

75 OHtl 0 ~~ vcc

IN Tgo 20C1IIT481 lICCoura A SC Illr V4CArr bull ArrZOC141KI1ll4 liT bull IIT481100 1-C--O------- shy

IN TluFOU Ubullbulln

JS rft bullbull

8U AllI 81Z A1Z

bullbull~ A11 ~

rmiddotmiddotmiddotr~ r-iuml IC ~6 c

~ 8U

14

tAIURE CONNECTOIll

10 1110 r~ e A 1

yoUT1 AP A6 AI V~C U A4 U middotAS i-C-7-lttIC-ll-I-C-----L C10a AZ 81 Al L luF 1 luF =r luF t 1

V~CVCC

i-c-14-I--Cl-S-X-C-l-Z-1cu 14 u zzuF eacute 2Zul eacuteZZul f-ZZUl

~47K

r egrave~

shy

----- r-- ~-- - - - - - - -

AD DO HA AD DO ~AO DO Al Dl Al Dl Al Dl A2 D2 A2 D2 A2 D2 AJ D3 A3 D3 A3 D3 A4 A4 AS AS A6 A6 Al Al AB AB

RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

RAS CAS WE

~ SOJ 4n6-70

A 1

AD DO Al Dl A2 D2 A3 D3 A4 AS A6 Al AB

RAS CAS WE OE

SOJ 42i6-70

MAP0 Cr0 )

- HLshy

JI MAP2 (ri)

Qll

$ 1 MB

Il c 10K

1

D lDK ~ Rn

shy i--lDK

2

Il ~

11 lOIlt 10il lOK -rOM

Ii7

CONFIGURATION SETTING

MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

CI i en g ~

1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 74: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

- - - - - - - - - - - -

bullbull

1

fIBAZ2lJC-oclAlJ4mrnn]lC122 230 IBA23tO B] gt T~l R65tT

~mm ~~ ~j~EmmE lMllPllCJQlJJiJ1J_ltEImllJOHDO ~_~ ~~~ _1 CHoto 3D gt

~g~mw

t 1

11~IIIII~I~~~il~

r - -__- shy r

0shy~

Cl~g~ CZ 03 C3 Ul 04 C4 Ji05 CS 06 C6 ~ADICDJ 07 C7 08 C8

MAOle1Jnn 4

AOIC2J78 I~SROY t1AOIC3J

010 CIO 09 C

IOCHRDY MAOlCJ 011 CU HADICiJ OU C1Z f1AOIC6J OU CU AOIC7J

C14IICC -mm MAOleeJ 1 016 Cl6 017 CH

CUi L-OA ~~i~~~ALE018 C18 A23C2J bUs-J

MA23C3JIr~

SAOCAOC681 Al SA1CAlSAZCAZ

IICC4 ~ n A3 sa AZ ZZOpf l

SA3CA3 HDI B4 A4 SA4CA4 H02 BS AS SASCAS HD3 86 AI SA6CAI HD4 B7 A7 SAl7CA7 HOS-1ZV 1U1 $80Y A8 SASCAS8 A SA9CA9810 A10 SAlOCAlO HOS B A SAllCALi 09 Bl2 AU SA12CAJ2 010 BU A13 SA13CA13 11011 814 Al4 5A14CA14 H012 BIS A15 SAISCAlS H013 B16 A16 SA15CA16 H014 B17 AH LA 17CA17 HDiS

LA1BCA1B D1G B A 81 A18

LAL9CA1 f1017 BZO AZO LA20lCA20 11019 21 AU LA211CA21 H019 u AZZ LA22CA22 11020 BU AU LA23CA23 11021sa4 AZ4 H022 ZS AZS XPCLIlt~ 023 826 A26 H024 8Z7 A27 ~5 71 ii1~m~~~~gYl 025

PU 1 1 1Z AZ8 D261Iee Q 829 A29 ~ R~9 +9 BOOlITrn H027 30 AJa HD2BBOl31 AU BOZ HD29

B03 HD30 B04CPUAO HOUliCe

=g~~~ ii 1CPURESET HA1

lS00

SOZ 503 S04 ~S ~

liCe yec 506 Pl501507 12

R44) R4S SOS 13 SD 14

UALZ VCLK SDll 16TAll DVDO PSi~~I~SD10 ~~laH$f==I~~~S )(~5~~~ Rl FRl ~gt~ P7 fil AYS5 5014 YSYNC

5TR081 AUDO 5D1Ccedil H5YNC

- e~s ~~~ ~i~OeRO ~ bullHtt~~~~t~~~ g~~~ ~ft~----_-JI---sectI~~~~~~~~i~~~~~IVCLI( ~ CSELIEEPWO SWSENSE

~~~t~EEP5K IIT6rRtE~ bull bull g~ ~

liPi 9S ENVQAAm PROCLK~lice unlice

R301129 7K7M Innun 1IC on-oB7

15 IN 1Re~14 1kamp~ijk~glZ P1S 1 lM IN lM OUT sa OUT IN U OUT OUT 40

Xl 1431Z 1

~

a=shyC i fi) g ~

~ n QI

TRUE COLOR RAMDAC

CZ7

Rtt9iI~ ~

m~I~~ 1s~ ~NSEI ~

amp8

07 06 O~ D4

R51

03 02

Di R5Z

R50 17 P6PIP ~3 12 ~1

PO

R18

47 OHM __ css ~47PF

Rl

7 OH -- c34

~47

1 F83 ~I ~

1 0815

R2Z 715 OH --J lV

l R21

75 OHtl 0 ~~ vcc

IN Tgo 20C1IIT481 lICCoura A SC Illr V4CArr bull ArrZOC141KI1ll4 liT bull IIT481100 1-C--O------- shy

IN TluFOU Ubullbulln

JS rft bullbull

8U AllI 81Z A1Z

bullbull~ A11 ~

rmiddotmiddotmiddotr~ r-iuml IC ~6 c

~ 8U

14

tAIURE CONNECTOIll

10 1110 r~ e A 1

yoUT1 AP A6 AI V~C U A4 U middotAS i-C-7-lttIC-ll-I-C-----L C10a AZ 81 Al L luF 1 luF =r luF t 1

V~CVCC

i-c-14-I--Cl-S-X-C-l-Z-1cu 14 u zzuF eacute 2Zul eacuteZZul f-ZZUl

~47K

r egrave~

shy

----- r-- ~-- - - - - - - -

AD DO HA AD DO ~AO DO Al Dl Al Dl Al Dl A2 D2 A2 D2 A2 D2 AJ D3 A3 D3 A3 D3 A4 A4 AS AS A6 A6 Al Al AB AB

RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

RAS CAS WE

~ SOJ 4n6-70

A 1

AD DO Al Dl A2 D2 A3 D3 A4 AS A6 Al AB

RAS CAS WE OE

SOJ 42i6-70

MAP0 Cr0 )

- HLshy

JI MAP2 (ri)

Qll

$ 1 MB

Il c 10K

1

D lDK ~ Rn

shy i--lDK

2

Il ~

11 lOIlt 10il lOK -rOM

Ii7

CONFIGURATION SETTING

MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

CI i en g ~

1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 75: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

TRUE COLOR RAMDAC

CZ7

Rtt9iI~ ~

m~I~~ 1s~ ~NSEI ~

amp8

07 06 O~ D4

R51

03 02

Di R5Z

R50 17 P6PIP ~3 12 ~1

PO

R18

47 OHM __ css ~47PF

Rl

7 OH -- c34

~47

1 F83 ~I ~

1 0815

R2Z 715 OH --J lV

l R21

75 OHtl 0 ~~ vcc

IN Tgo 20C1IIT481 lICCoura A SC Illr V4CArr bull ArrZOC141KI1ll4 liT bull IIT481100 1-C--O------- shy

IN TluFOU Ubullbulln

JS rft bullbull

8U AllI 81Z A1Z

bullbull~ A11 ~

rmiddotmiddotmiddotr~ r-iuml IC ~6 c

~ 8U

14

tAIURE CONNECTOIll

10 1110 r~ e A 1

yoUT1 AP A6 AI V~C U A4 U middotAS i-C-7-lttIC-ll-I-C-----L C10a AZ 81 Al L luF 1 luF =r luF t 1

V~CVCC

i-c-14-I--Cl-S-X-C-l-Z-1cu 14 u zzuF eacute 2Zul eacuteZZul f-ZZUl

~47K

r egrave~

shy

----- r-- ~-- - - - - - - -

AD DO HA AD DO ~AO DO Al Dl Al Dl Al Dl A2 D2 A2 D2 A2 D2 AJ D3 A3 D3 A3 D3 A4 A4 AS AS A6 A6 Al Al AB AB

RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

RAS CAS WE

~ SOJ 4n6-70

A 1

AD DO Al Dl A2 D2 A3 D3 A4 AS A6 Al AB

RAS CAS WE OE

SOJ 42i6-70

MAP0 Cr0 )

- HLshy

JI MAP2 (ri)

Qll

$ 1 MB

Il c 10K

1

D lDK ~ Rn

shy i--lDK

2

Il ~

11 lOIlt 10il lOK -rOM

Ii7

CONFIGURATION SETTING

MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

CI i en g ~

1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 76: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

----- r-- ~-- - - - - - - -

AD DO HA AD DO ~AO DO Al Dl Al Dl Al Dl A2 D2 A2 D2 A2 D2 AJ D3 A3 D3 A3 D3 A4 A4 AS AS A6 A6 Al Al AB AB

RAS

- CAS WE OE

MAP0 Cr2) MAP1 Cr4) MAP1 (r6 )

---- ~ shy ~--- Ut2 _-shy _--shy Ut AD 00 Al Dl A2 D2 A3 03 A4 AS A6 Al A8

RAS CAS WE

~ SOJ 4n6-70

A 1

AD DO Al Dl A2 D2 A3 D3 A4 AS A6 Al AB

RAS CAS WE OE

SOJ 42i6-70

MAP0 Cr0 )

- HLshy

JI MAP2 (ri)

Qll

$ 1 MB

Il c 10K

1

D lDK ~ Rn

shy i--lDK

2

Il ~

11 lOIlt 10il lOK -rOM

Ii7

CONFIGURATION SETTING

MAP2 Cr3 ) MAP3 CrS) MAP3 Cr7 )

VIDEO MEMORY wl 256Kx4

J

5f YP

RO 00 Al 01 A2 02 A3 03

II =~ g~ A6 06 Al 07 AS A9 A1D All A12 A13 A14

~ 1

CI i en g ~

1 1raquon li)

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 77: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

--------------------(

Corporate Headquarters Oak Technology Ine 139 Kifer Court Sunnyvale CA 94086 UsA (408) 737~888 FAX (408) 737-3838

apan Oak Technology KK Kouraku Building 2F 2-5-3 Nakamachi Musashino City Tokyo 180 ]apan 0422middot56-3761 FAX 0422-56-3778

Taiwan Oak Technology Ine Taiwan Room B 7F No 370 Section l Fu HsingSouth Road l Taipci Taiwan ROC (02) 784-9123 FAX (02) 706-7641

087C021093-oo1

~~---shy

(

Page 78: Second Sight VGA Graphic Controller - boutillon.free.frboutillon.free.fr/tmp/JeanPierre/Second_Sight/Second Sight Graphic Controller.pdf · Prefa~e. The information eontained in this

~~---shy

(