sdes code

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library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;

entity P10 is port (key: in std_logic_vector(0 to 9); p10: out std_logic_vector(0 to 9));end;

architecture P10 of P10 isbegin p10(0)

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ip(5)

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end if;when SXOR=>

out_en

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entity SW is port (input: in std_logic_vector(0 to 7); switched : out std_logic_vector(0 to 7));end;

architecture SW of SW isbegin switched(0)

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entity EP is port(input: in std_logic_vector(0 to 3); eped: out std_logic_vector(0 to 7));end;

architecture EP of EP isbegin eped(0)

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library IEEE;use IEEE.std_logic_1164.all;

entity reg8 isport (

en,clk: in std_logic;inp: in std_logic_vector(0 to 7);outp: out std_logic_vector(0 to 7));

end reg8;

architecture rtl of reg8 isbegin

seq: process (en,clk,inp)begin

if en='1' thenif rising_edge(clk) then

outp

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beginif en='1' then

if rising_edge(clk) thenoutp

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end process;end;


entity F is port (clk, rst, en_f:in std_logic;

input: in std_logic_vector(0 to 3); key: in std_logic_vector(0 to 7); fed : out std_logic_vector(0 to 3);

outen_f: out std_logic);end;

architecture F of F iscomponent S0

port(input: in std_logic_vector(0 to 3);output: out std_logic_vector(0 to 1));

end component;component S1

port(input: in std_logic_vector(0 to 3);output: out std_logic_vector(0 to 1));

end component;

component EPport(input: in std_logic_vector(0 to 3);eped: out std_logic_vector(0 to 7));

end component;component P4

port(input: in std_logic_vector(0 to 3);p4ed: out std_logic_vector(0 to 3));

end component;component reg2

port (en,clk: in std_logic;inp: in std_logic_vector(0 to 1);outp: out std_logic_vector(0 to 1));





end component;

component XOR8port (inp1: in std_logic_vector(0 to 7);inp2: in std_logic_vector(0 to 7);outp: out std_logic_vector(0 to 7));

end component;component FFSMport (clk, rst, en_f: in std_logic;

sig_ep, sig_xor, sig_s0s1: out std_logic;out_en: out std_logic);

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end component;signal eped, r_eped, xored, r_xored: std_logic_vector(0 to 7);signal p4ed: std_logic_vector(0 to 3);signal esed0, r_esed0, esed1, r_esed1: std_logic_vector(0 to 1);signal sig_ep, sig_xor, sig_s0s1, out_en: std_logic;begin

EX: EP port map(input, eped);R_81: reg8 port map(sig_ep,clk,eped,r_eped);S_XOR: XOR8 port map(r_eped, key, xored);R_82: reg8 port map(sig_xor,clk,xored,r_xored);S_0: S0 port map(r_xored(0 to 3), esed0);R_21: reg2 port map(sig_s0s1,clk,esed0, r_esed0);S_1: S1 port map(r_xored(4 to 7), esed1);R_22: reg2 port map(sig_s0s1,clk,esed1, r_esed1);P_4: P4 port map(input(0 to 1)=>r_esed0, input(2 to 3)=>r_esed1, p4ed=>p

4ed);R_41: reg4 port map(out_en,clk,p4ed,fed);FCTRL: FFSM port map(clk, rst, en_f, sig_ep, sig_xor, sig_s0s1, out_en);outen_f

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end;

architecture LS1 of LS1 isbegin

ls1

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state

sig_p8

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signal p8ed1, p8ed2: std_logic_vector(0 to 7);signal sig_p10, sig_p8 ,sig_ls1, sig_ls2, out_en: std_logic;begin

P_10: P10 port map(key10, p10ed);R_101: reg10 port map(sig_p10,clk,p10ed,r_p10ed);LS_1: LS1 port map(r_p10ed, lsed1);R_102: reg10 port map(sig_ls1,clk,lsed1,r_lsed1);P_81: P8 port map(r_lsed1, p8ed1);R_81: reg8 port map(sig_p8,clk,p8ed1,key2_8(0 to 7));LS_2: LS2 port map(r_lsed1, lsed2);R_103: reg10 port map(sig_ls2,clk,lsed2,r_lsed2);P_82: P8 port map(r_lsed2,p8ed2);R_82: reg8 port map(out_en,clk,p8ed2,key2_8(8 to 15));KEYFSM: KFSM port map(clk, rst, sig_p10, sig_p8, sig_ls1, sig_ls2, out_e

n);keys_ready

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state out_en

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sig_ip, sig_sw: out std_logic;out_en: out std_logic);

end component;signal switch, r_switch, fked1, fked2: std_logic_vector(0 to 7);signal r_fked1,r_fked2, riped, iped, r_iped: std_logic_vector(0 to 7);signal sig_ip, sig_sw, out_en, en_fk1, en_fk2, keys_ready: std_logic;signal keys: std_logic_vector(0 to 15);

beginKK: KEYGEN port map(clk,rst,key,keys, keys_ready);IP_0: IP port map(input, iped);R_81: reg8 port map(sig_ip,clk,iped,r_iped);FK1: Fk port map(clk, rst, keys_ready, r_iped, keys(0 to 7), fked1, en_f

k1);R_82: reg8 port map(en_fk1,clk,fked1,r_fked1);SW_0: SW port map(r_fked1, switch);R_83: reg8 port map(sig_sw,clk,switch,r_switch);FK2: Fk port map(clk, rst, sig_sw, r_switch, keys(8 to 15), fked2, en_fk

2);R_84: reg8 port map(en_fk2,clk,fked2,r_fked2);RIP_0: RIP port map(r_fked2, riped);R_85: reg8 port map(out_en,clk,riped,output);ACTRL: SFSM port map(clk, rst, en_fk1, en_fk2, sig_ip, sig_sw, out_en);

end;

--------------- decrypt ---------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;use IEEE.numeric_std.all;

entity r_sdes is port(clk, rst: std_logic;

input :in std_logic_vector(0 to 7); key: in std_logic_vector(0 to 9);

output: out std_logic_vector(0 to 7));end;

architecture r_sdes of r_sdes iscomponent reg8


end component;component IP port (input: in std_logic_vector(0 to 7);

ip : out std_logic_vector(0 to 7));end component;

component Fkport (clk, rst, en: in std_logic;ip: in std_logic_vector(0 to 7);key : in std_logic_vector(0 to 7);fked : out std_logic_vector(0 to 7);outen_fk: out std_logic);

end component;component SW

port (input: in std_logic_vector(0 to 7);switched : out std_logic_vector(0 to 7));

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end component;component RIP port (input: in std_logic_vector(0 to 7);

rip : out std_logic_vector(0 to 7));end component;component KEYGEN

port (clk, rst: in std_logic;key10: in std_logic_vector(0 to 9);key2_8: out std_logic_vector(0 to 15);keys_ready: out std_logic);

end component;component SFSM

port (clk, rst: in std_logic;sig_fk1, sig_fk2: in std_logic;sig_ip, sig_sw: out std_logic;out_en: out std_logic);

end component;signal switch, r_switch, fked1, fked2: std_logic_vector(0 to 7);signal r_fked1,r_fked2, riped, iped, r_iped: std_logic_vector(0 to 7);signal sig_ip, sig_sw, out_en, en_fk1, en_fk2, keys_ready: std_logic;signal keys: std_logic_vector(0 to 15);

beginKKR: KEYGEN port map(clk,rst,key,keys, keys_ready);IP_0R: IP port map(input, iped);

R_81R: reg8 port map(sig_ip,clk,iped,r_iped);FK1R: Fk port map(clk, rst, keys_ready, r_iped, keys(8 to 15), fked1, en_fk1);

R_82R: reg8 port map(en_fk1,clk,fked1,r_fked1);SW_0R: SW port map(r_fked1, switch);R_83R: reg8 port map(sig_sw,clk,switch,r_switch);FK2R: Fk port map(clk, rst, sig_sw, r_switch, keys(0 to 7), fked2, en_fk

2);R_84R: reg8 port map(en_fk2,clk,fked2,r_fked2);RIP_0R: RIP port map(r_fked2, riped);R_85R: reg8 port map(out_en,clk,riped,output);ACTRLR: SFSM port map(clk, rst, en_fk1, en_fk2, sig_ip, sig_sw, out_en);

end;

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