scl8019v081

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SCL8019- 16-Bit Constant Current LED Driver with Current Gain Adjustment

SiliconCore Technology Confidential Jan. 2011 v.081 2

Pin Description (SCL8019S/P/T/QA)

Pins

#

Pin name Type Description

1 GND Ground for control logic, internal analog circuit and currentsink

2 SDI DI Serial data input to the shift register

3 CLK DI Clock input for data shift on rising edge

4 LE DI Latch enable input, serial data is transferred to the output

latch when LE is high. The data is latched when LE goes

low

5-20 0OUT ~

15OUT

AO Constant current sink output

21 OE DI Output enable terminal. The output drivers are enabledwhen low, all output drivers are turned off when high.

22 SDO DO Serial data output to the following SDI of next driver IC

23 REXT AI An external resistor connected to ground for setting up

output current for all output channels.

24 VDD 3.3V or 5V supply voltage

Note: AI-Analog Input, AO-Analog Output, DI-Digital Input.

Maximum Ratings

Characteristic Symbol Rating Unit

Supply Voltage VDD 0~7.0 V

Input Voltage VIN -0.4 ~ VDD +0.4 V

Output Current IOUT 90 mA

Output Voltage VDS -0.5 ~ 17.0 V

Clock Frequency FCLK 35 MHz

GND Terminal Current IGND 1440 mA

Power Dissipation

(On PCB, Ta=25)

SSOP-type

PD

1.52

WTSSOP-type 1.30

QFN - type 2.10

Thermal Resistance

(On PCB, Ta=25)

SSOP - type

Rth(j-a)

82

/WTSSOP -type

96

QFN - type 49

Operating Temperature Topr -40 ~ +85

Storage Temperature Tstg -55 ~+150

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SCL8019- 16 Bit Constant Current LED Driver with Current Gain Adjustment


Recommended Operating Conditions (VDD=5V)

Characteristic Symbol Condition Min. Typ. Max. Uni

Supply Voltage VDD - 4.5 5.0 5.5 V

Output Voltage VDS OUT0~OUT15 - - 17.0 V

Output Current

IOUT 2 - 90 mA

IOH SDO - - -1.0 mA

IOL SDO - - 1.0 mA

Input VoltageVIH CLK, OE , LE and SDI 0.8VDD - VDD+0.3 V

VIL CLK, OE , LE and SDI -0.3 - 0.3VDD V

LE Pulse Width tw(L)

VDD=4.5~5.5V

40 - - ns

CLK Pulse Width tw(CLK) 15 - - ns

OE Pulse Width tw(OE) 20 - - ns

Set-up Time for SDI tsu(D) 5 - - ns

Hold Time for SDI th(D) 10 - - ns

Set-up Time for LE tsu(L) 40 - - ns

Hold Time for LE th(L) 30 - - ns

Maximum CLK RiseTime

- - 500 ns

Maximum CLK Fall

Time

- - 500 ns

Clock Frequency FCLK Cascade Operation - - 35 MH

Power Dissipation PD

Ta=85(SSOP

type

- - 0.79

WTa=85TSSOP

type

- - 0.85

Ta=85QFN

type

- - 0.95

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Recommended Operating Conditions (VDD=3.3V)

Characteristic Symbol Condition Min. Typ. Max. Uni

Supply Voltage VDD - 3.0 3.3 3.6 V

Output Voltage VDS OUT0~OUT15 - - 17.0 V

Output Current

IOUT 2 - 70 mA

IOH SDO - - -1.0 mA

IOL SDO - - 1.0 mA

Input VoltageVIH CLK, OE , LE and SDI 0.8VDD - VDD+0.3 V

VIL CLK, OE , LE and SDI -0.3 - 0.3VDD V

LE Pulse Width tw(L)

VDD=4.5~5.5V

40 - - ns

CLK Pulse Width tw(CLK) 15 - - ns

OE Pulse Width tw(OE) 20 - - ns

Setup Time for SDI tsu(D) 5 - - nsHold Time for SDI th(D) 10 - - ns

Setup Time for LE tsu(L) 40 - - ns

Hold Time for LE th(L) 30 - - ns

Maximum CLK RiseTime

tr - - 500 ns

Maximum CLK Fall

Timetf - - 500 ns

Clock Frequency FCLK Cascade Operation - - 35 MH

Power Dissipation PD

Ta=85 (SSOP ) - - 0.79

WTa=85TSSOP - - 0.85

Ta=85QFN - - 0.95

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Electrical Characteristics (VDD=5V)(VDD=4.5V~5.5V,Ta=40~85. Typical values at VDD=5V,Ta=25 , unless otherwise noted)

Characteristic Symbol Condition Min. Typ. Max. Unit

Input Voltage

Hlevel VIH0.8VD

D- VDD V

Llevel VIL Ta=-40~85 GND - 0.3 VOutput Leakage Current IOH VOH=17.0V - - 0.5 uA

Output Voltage SDO

VOL IOL=+1.0mA - - 0.4 V

VOH IOH=-1.0mA 4.6 - - V

Output Current 1 IOUT1 VDS=1V Rext=2.344k - 20.0 - mA

Current Skew (channel)dIout1,1

IOL=20mA

VDS=1VRext=2.344k - 1 2.5 %

Current Skew (chip)dIout1,2

IOL=20mA

VDS=1VRext=2.344k - 1.5 5 %



IOL=40mAVDS=1V Rext=1.172k

- 1 2.5 %


IOL=40mA

VDS=1V Rext=1.172k- 1.5 5 %

Output Current vs.

Output Voltage Regulation %/dVDS VDS within 0.5v and 3.0v- 0.1 - %/V

Output Current vs.

Supply Voltage Regulation %/dVDS VDD within 4.5v and 5.5v- 1 - %/V

Output open circuit detection VOD,TH 0.15 V

Pull-up Resistor RIN(up) OE 250 500 800 K

Pull-down Resistor RIN(down) LE 250 500 800 K

Supply Current

IDD(Off) Rext=2.344k,Iout=0mA 5.0 mA

IDD(Off) Rext=1.172k, Iout=0mA 7.5 mA

IDD(On)Rext=2.344k, CG=2

(default), Iout=20mA6.0 mA


(default), Iout=90mA12 mA

Thermal detection threshold(1)

T TD 150 C

(1) Not tested, specified by design

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Test Circuit for Electrical Characteristics

OUT0

OUT15

SDO

VDD

GNDREXT

CLK

LE

SDI

OE

Iref

IOUT

IDD

VIH,VIL

IIH,IIL

Electrical Characteristics (VDD=3.3V)(VDD=3.0V~3.6V,Ta=40~85. Typical values at VDD=3.3V,Ta=25 , unless otherwise noted)

Characteristic Symbol Condition Min. Typ. Max. Unit

Input Voltage

Hlevel VIH Ta=-40~85 0.8VDD - VDD V

Llevel VIL Ta=-40~85 GND - 0.3 V

Output Leakage Current IOH VOH=17.0V - - 0.5 uA

Output Voltage SDO

VOL IOL=+1.0mA - - 0.4 V

VOH IOH=-1.0mA 2.9 - - V

Output Current 1 IOUT1 VDS=0.6V Rext=2.344k - 20.0 - mA


IOL=20mA

VDS=0.6VRext=2.344k

- 1 2.5 %


IOL=20mA

VDS=0.6VRext=2.344k

- 1.5 5 %



IOL=40mA

VDS=1V Rext=1.172k- 1 2.5 %


IOL=40mA

VDS=1V Rext=1.172k- 1.5 5 %

Iout vs. VDS Regulation %/dVDS VDS within 0.5v and 2.0v - 0.1 - %/V

Iout vs. VDD Regulation %/dVDS VDD within 3.0v and 3.6v - 1 - %/V

Output open circuit detection VOD,TH 0.15 V

Pull-up Resistor RIN(up) OE 250 500 800 K

Pull-down Resistor RIN(down) LE 250 500 800 K

Supply Current

IDD(Off) Rext=2.344k,Iout=0mA 5.0 mA

IDD(Off) Rext=1.172k, Iout=0mA 7.5 mA

IDD(On)Rext=2.344k, CG=2(default), Iout=20mA

6.0 mA


(default), Iout=90mA12.0 mA

Thermal detection threshold(1)

T TD 150 C

(1) Not tested, specified by design

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Switching Characteristics (VDD=5V)(VDD=4.5V~5.5V,Ta=40~85. Typical values at VDD=5V,Ta=25 , unless otherwise noted)

Characteristic Symbol Condition Min. Typ. Max. U

Propagation Delay Time

(L to H)

CLK- OUTn tpLH1

VDD=5.0VVDS=0.8V

VIH=VDD

VIL=GND

Rext=2.34K

VL=3.0VRL=52

CL=10pF

- 50 - n

LE- OUTn tpLH2 -

50 - n

OE - OUTn tpLH3 - 23 - n

CLK-SDO tpLH - 20 - n


(H to L)

CLK-

OUTn

tpHL1- 50 100 n

LE-OUTn tpHL2 - 50 100 n

OE - OUTn tpHL3 - 50 100 n

CLK-SDO tpHL 15 20 - n

Stagger delayOUTn -

OUTn +1

tstag- 2 - n

Output Rise Time of lout tor - 10 - n

Output Fall Time of lout tof - 10 - n

Test Circuit for Switching Characteristics

Function

Generator

OUT0

OUT15

SDO

VDD

GNDREXT

CLK

LE

SDI

OE

Iref

IOUT

IDD

VIH VIL

CL

CL

RL

VL

Logic input

waveformVIH=5V

VIL=0V

tr=tf=10ns

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Switching Characteristics (VDD=3.3V)(VDD=3.0V~3.6V,Ta=40~85. Typical values at VDD=3.3V,Ta=25 , unless otherwise noted)

Characteristic Symbol Condition Min. Typ. Max. U


(L to H)

CLK- OUTn tpLH1

VDD=3.3VVDS=0.8V

VIH=VDD

VIL=GND

Rext=2.34K

VL=3.0VRL=52

CL=10pF

- 50 - n

LE-OUTn tpLH2 - 50 - n

OE - OUTn tpLH3 - 23 - n

CLK-SDO tpLH - 20 - n


(H to L)

CLK-

OUTn

tpHL1 - 50 100 n

LE-OUTn tpHL2 - 50 100 n

OE - OUTn tpHL3 - 50 100 n

CLK-SDO tpHL 15 20 - n

Stagger delay OUTn -

OUTn +1

tstag - 2 - n

Output Rise Time of Iout tor - 10 - n

Output Fall Time of Iout tof - 10 - n

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Block Diagram

6-bit Current

GainAdjustment

REXT

OE

Control Logic

VDD

GND

LE

Configuration

RegistersOpen/Short

LED Detection

16-bit Shift Register (FIFO)

SDI

DCLK

1616

16-bitErrorStatus

SDO

6

_

16-bit Output Latch

16

16-bit Output Driver

16

OUT0 OUT1 OUT14 OUT15

Equivalent Circuits of Inputs and Outputs

VDD

IN

OE terminal

VDD

IN

terminalLE

VDD

terminalSDO

OUT

VDD

IN

terminalCLK, SDI

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Timing Waveform

50%50%

50% 50%

50%

50%

50% 50%

CLK

SDI

SDO

LE

OE

tW(CLK)

tsu(D) th(D)

tPLH, tPHL

th(L) tsu(L)

tW(L)

LOW=OUTPUTS ENABLED

HIGH = OUTPUT OFF

LOW = OUTPUT ON

50%

tPLH1, tPHL1

tPLH2, tPHL2

OUTn

OE

OUTn

50% 50%

50%

90%

10% 10%

50%

90%

tW(OE)

tpHL3 tpLH3

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Constant Current Sink Control

The data is shifted from the SDI to the 16-bits shift registers. If the LE is asserted and no CLK togglewhile

LE=H, the data in the shift register are latched to the output latch.

When OE is low and the data in the output latch is 1, the corresponding output channel is turned on andsink current from external LED.

N=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFFON

Dont care:

SDO

OUT15

OUT0

OUT1

OUT2

OUT3

OE

LE

SDI

CLK

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Principle of Operation

Control Command

Signals Combination

Description

Description

Command Name LE Number of DCLK

Rising Edge when

LE is asserted

The Action after a Falling Edge of LE

Latch data (In-message error detection) High 0 Latch the serial data to the output latch

Compulsory open-circuit detection High 1 Perform Open-circuit error detection once

Compulsory short-circuit detection High 2 Perform Short-circuit error detection once

Compulsory Thermal detection High 3 Perform IC thermal detection once

Write configuration High 4 Transfer serial data to the configuration register

Read configuration High 5 Output serial data from the configuration register

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In-Message Error Detection

By default, SCL8019 conducts in-message error detection at the falling edge of LE, if no CLK rising edge is detected when

LE remains high.

16 bits input data A

ERR

15

0 1 12 13 14 15 0 1 13 14 15 0

In-message Error Detection

ERR

14

16 bits input data B

1 2 13 14 15

ERR

2

ERR

1

ERR

0

Data

B15

Data

B14

Data

B13

Data

B3

Data

B2

Data

B1

tED

11

tOED

CLK

LE

SDI

SDO

OE__

>tED

Note1: tED is the time interval reserved for error detection, with typical value 600ns. The rising edge of the 1

st clock is required to lagbehind the falling edge of LE more than tED.

Note2: tED is the minimum OE pulse width required for error detection with typical value 500ns to prevent any false error detection.

There are 3 types of error detection:

1. LED Open Detection (LOD)Vout < VOD,TH @Iout set byRext (effective when DATA=1 & OE > 500ns)2. LED Short Detection (LSD)Vout > VSD,TH @Iout set byRext (effective when DATA=1 & OE > 500ns)3. Over Temperature Detection (OTD)Tj>150C

During in-message LOD and LSD, an internal comparator is used to compare Vout vs. VOD, TH (0.15V) orVSD,TH, where Vout is

the voltage potential at the output pin of each channel. The current used to sink current from Vout in in-message detection isthe one go through the output transistor, which is set by an external resistorRext.

OTD is always active in in-message error detection mode. Whether or not to conduct LOD or LSD depends on configuration

register bit B~A. Set bitB high enables LOD; set bitB low disables LOD. Set bitA high enables LSD; set bitA low disables

LSD.

A dedicated error register is used to store error information, which reset to 0 when power up. And bit6 of the configuration

register (BIT6) decides whether the error is low effective or high effective. By default, CONF6=0, error information would

be low effective; reverse versa, as shown in the following table.

The error information is latched in corresponding error register when tED elapsed after the falling edge of LE and goes to the

shift register at the same time. What originally stored in the shift register goes to the data latch and control the output current

right before the contents in shift registers get replaced. After that SDO shifts out the error information from the shift register

by each serial clock.

ConditionError Register Value

BIT6=0 (default) BIT6=1

No Error (VoutVOD,TH & Vout VSD,TH &Tj VSD,TH || Tj>150C) 0 1

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Compulsory Silent Error Detection

Compulsory silent error detection is also named as dark orblind error detection. No matter the datais 1 or 0, the output will be turned on with current 0.1mA in 500ns in the compulsory silent error

detection mode. The turn on time and turn current are so short and so small, so that the human eye will

not perceive it and the quality of the video and image are not influenced. According the issued Controlcommand, the compulsory silent error detection will do Open-Circuit or Short-Circuit detection

separately.

LED Open Detection

Open-Circuit Detection is realized by comparing Vout of each output port with the open-circuitthreshold VOD,TH (0.15V). After the command ofcompulsory open-circuit detection, the output

ports will be turned on with current 0.1mA in 500ns. The error status saved in the built-in

register would be shifted out through SDO pin bit by bit afterwards.

Open Circuit Detection


Open

15

0 1 12 13 14 15 0 1 13 14 15 0

O14


1 2 13 14 15

O2 O1 O0Data

B15

Data

B14

Data

B13

Data

B2

Data

B1

Data

B0

CLK

LE

SDI

SDO

>tED



No Error (VoutVOD,TH) 1 0

Error Detected (Vout < VOD,TH ) 0 1

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LED Short Detection

Similarly, Short-Circuit Detection is implemented by comparing Vout of each output port with a short-circuit

threshold VSD,TH, which is configurable through the F~E bits of the configuration register. After the command of

compulsory open-circuit detection, the output ports will be turned on with current 0.1mA in 500ns. The error

status saved in the built-in register would be shifted out through SDO pin bit by bit afterwards.

Short Circuit Detection


Short

15

0 1 12 13 14 15 0 1 13 14 15 0

S14


1 2 13 14 15 0

S2 S1 S0Data

B15

Data

B14

Data

B13

Data

B2

Data

B1

Data

B0

CLK

LE

SDI

SDO

>tED

Over Temperature Detection

Also, all the error registers will store error information if over-temperature is detected after the command of

compulsory thermal detection.

Thermal Detection


Thermal

15

0 12 13 14 15 0 1 13 14 15 0

T14


1 2 13 14 15 0

T2 T1 T0Data

B15

Data

B14

Data

B13

Data

B2

Data

B1

Data

B0

CLK

LE

SDI

SDO



No Error ( Vout VSD,TH ) 1 0

Error Detected ( Vout > VSD,TH ) 0 1



No Error ( Tj150C ) 0 1

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Configuration Registers

This register is address and bit-wise compatible to the configuration register as defined by existing 16-bit LED driver in the market. The following text further defines the bits in the register:

Bit Attribute Definition Value Function

F~E R/W

Voltage thresholds

for short circuit

detection

00 0.4VDD01 0.5VDD

10 0.6VDD

11(Default) 0.7VDD

D~C R/WIn-message error

detection trigger

00 Reserved bits

01 Enable LE to trigger error detection

10 Enable OE to trigger error detection

11 (Default) Enable LE or OE to trigger error detection

B~A R/WIn-message error

detection enable

00 Disable in-message LSD or LOD

01 Enable in-message LSD

10 Enable in-message LOD

11 (Default) Enable in-message LSD and LOD

9 ~ 7 R/W Check bits 010 Confirm a intentional write6 R/W Error polarity

0 Error is low effective

1 Error is high effective

5~0 R/WCurrent Gain

Adjustments

000000~111111

111111(Default)

CG=b5*2 + b4*2- + b3*2

- + b2*2- + b1*2

- +

b0*2-5+2-5

Initialization Programming

The SCL8019 device is initialized after power up into default mode of operation. The defaultregister settings are marked in the configuration register map above.

Write Configuration Mode

If 4 rising edges of CLK are detected during LE high, SCL8019 enters write configuration mode.If bits 9~7 are confirmed to be 010, the serial data in the Shift Register, which inputs from SDI

will then transferred to a 16-bit Configuration Register rather than the 16-bit Output Latch.

Write Configuration

Input 16 bits configuration data

CLK

LE

SDI

0 1 14 15 0 1 12 13 14 1512 13

>tED

Read Configuration

Output 16 bits configuration d

CLK

LE

SDO

0 1 14 15 0 1 12 13 112 1311

>tED

Read Configuration ModeIf 5 rising edges of CLK are detected during LE high, SCL8019 enters read configuration mode.

The data stored in a 16-bit Configuration Register will be shift out through SDO by the serial

CLK.

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Current Gain Configuration

After entering the Current Adjust mode, the system controller sends a 6-bit Current Adjust code

to 16-bit Shift Register through SCL8019 SDI pin. Current Gain of SCL8019 could be easily

programmed by the following simple formula:CG=b5*2

0+ b4*2

-1+ b3*2

-2+ b2*2

-3+ b1*2

-4+ b0*2

-5+2

-5

This indicates a programmable Current Gain range of (3.125%, 200%) with 3.125% step. Please

be aware of that the output current range should be also within [2mA, 90mA]; if exceed the

recommended range, accuracy will not be guaranteed. The following figure shows some keypoints of the programming:

Delay Time of Staggered Output

A 2ns delay time among OUTn and OUTn +1 is implemented to prevent current surge and improve EMI performance.

000000

011111

111111

0

20

40

60

80

100

120

140

160

180

200

0 10 20 30 40 50 60

CG(%)

Steps

SCL8019 Current Gain

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Package Type: 24L QFN4x4

Part Name: SCL8019N

D

E

Pin #1 Mark

A

A1

A3

E2

Pin #1 Mark

L

e

b

1

2

24 23

PACKAGE OUTLINE

D2

SYMBOL MIN NOM MAX

A 0.80 0.90 1.00

A1 0.00 0.02 0.05

A3 --- 0.20 ---

D

D2 2.00 2.15 2.25

E

E2 2.00 2.15 2.25

L 0.30 0.40 0.50b 0.18 0.25 0.30

e

DIMENSIONS (UNIT: mm)

4.00

4.00

0.50

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Package Type: SSOP-236-1.0

Part Name: SCL8019P

H E

B B

DETAIL

e

D

A2 A

A1

C0.10MM

SEATING PLANE

b

c1

b1

c

SECTOIN B-B

0.25MM

DETAIL AL O

SYMBOL

UNIT

mm

Min.

Nom.

Max.

A A1 A2 b b1 c c1 D e E H L

-

-

1.90

0.05

0.10

0.15

1.30

1.50

1.70

0.30

0.40

0.52

0.30

0.40

0.52

0.10

0.15

0.27

0.10

0.15

0.25

12.80

13.00

13.20

1.00

BSC

5.80

6.00

6.20

7.70

8.00

8.30

0.25

0.45

0.65

0

-

10

Note: Plating thickness spec: 0.3mil ~ 0.8mil

o

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Package Type: QSOP-150-0.635

Part Name: SCL8019Q/SCL8019QA

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Package Type: TSSOP24-173-0.65

Part Name: SCL8019T

24 13

1 12

0.65 0.2450.245

4.40.1

6.4

3.61

1.95

THERMALLY ENHANCED VARIATIONS ONLY

0.1

27

TYP,

7.80.1

1.00.2 1.2MAX.

0.15MAX.

9.80.1

0.2MIN

0.60.15

1.0

GAUAE PLANE

SEATING PLANE

0 00 ~ 8

0.2

5

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Package Type: SOP24-300-1.27

Part Name: SCL8019S

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Device Marking

(Top View)

Marking:Line 1: SCL8019VVXX( VV is version number, XX stands for the package type)

Line 2: XYYWW(YYWW is Date Code)

SCL8019VVXX

XYYWW

scl8019v081

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