school of engineering vhdl 4: getaktete logik (d-ff, zähler, automaten)
TRANSCRIPT
![Page 1: School of Engineering VHDL 4: Getaktete Logik (D-FF, Zähler, Automaten)](https://reader035.vdocuments.us/reader035/viewer/2022070310/55204d7649795902118cbb02/html5/thumbnails/1.jpg)
School ofEngineering
VHDL 4: Getaktete Logik (D-FF, Zähler, Automaten)
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School ofEngineeringInhalt
● Getaktete Logik ○ D-FF○ 8-bit Register○ D-FF mit asynchronem Reset○ D-FF mit synchronem Reset
● Synthese● Beispiel Flankendetektor
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School ofEngineering
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY vhdl IS
PORT(clk : IN std_logic;d : IN std_logic;q : OUT std_logic);
END vhdl;
ARCHITECTURE rtl OF vhdl ISBEGIN
logik : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENq <= d;
ELSEq <= q;
END IF;END PROCESS logik;
END rtl;
Was könnte dieses VHDL beschreiben?
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School ofEngineering
clk
QD
D
Q
D Qn+1
1 1
0 0
CLK
D-FF
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School ofEngineering
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY dff_logic IS
PORT(clk : IN std_logic;d : IN std_logic;q : OUT std_logic);
END dff_logic;
ARCHITECTURE rtl OF dff_logic ISBEGIN
dff : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENq <= d;
ELSEq <= q;
END IF;END PROCESS dff;
END rtl;
Prozess nur aktiviert wenn clk ändert
wahr wenn sich clk ändert
Else nicht notwendig,wenn if nicht zutrifft bleibt q wie vorher
VHDL Beschreibung eines D-FF
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LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY dff_logic IS
PORT(clk : IN std_logic;d : IN std_logic_vector(7 downto 0);q : OUT std_logic_vector (7 downto 0);
END dff_logic;
ARCHITECTURE rtl OF dff_logic ISBEGIN
dff : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENq <= d;
END IF;END PROCESS dff;
END rtl;
Was ist hier anders als vorher ?
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School ofEngineering
QD
CLK
QD
Q(7)
D(0)
D(7)
Q(0)
8-bit breites Register
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LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY dff_arst IS PORT( clk, din, reset : IN std_logic;
qout : OUT std_logic );END dff_arst;
ARCHITECTURE rtl OF dff_arst ISBEGIN dff : PROCESS(clk, reset) BEGIN IF reset = '1' THEN
qout <= '0'; ELSIF clk'EVENT AND clk = '1' THEN qout <= din; END IF; END PROCESS dff;END rtl;
Welches Signal ist bei diesem Prozess neu?
Reset zu oberst im if statementhat deshalb höchste Priorität
- Asynchroner Reset !
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School ofEngineering
Was passiert hier ?
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY dff_arst IS
PORT(clk,d,reset : IN std_logic;q : OUT std_logic);
END dff_arst;
ARCHITECTURE rtl OF dff_arst IS
BEGINdff : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENIF reset = '1' THEN
q <= '0';ELSE
q <= d;END IF;
END IF;END PROCESS dff;
END rtl;
Synchroner Reset
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D-Flip Flop mit synchronem Reset
CLK
D
Q
RESET
dff : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENIF reset = '1' THEN
q <= '0';ELSE
q <= d;END IF;
END IF;END PROCESS dff;
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School ofEngineeringD-Flip Flop mit synchronem Reset
Q
S
D
CLKRESET &
D
dff : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENIF reset = '1' THEN
q <= '0';ELSE
q <= d;END IF;
END IF;END PROCESS dff;
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School ofEngineeringGeschachteltes IF statement
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY dff_srst IS
PORT(clk,d,reset : IN std_logic;q : OUT std_logic);
END dff_srst;
ARCHITECTURE rtl OF dff_srst IS
BEGINdff : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENIF reset = '1' THEN
q <= '0';ELSE
q <= d;END IF;
END IF;END PROCESS dff;
END rtl;
Geschachteltes IF statement
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School ofEngineeringErzeugung eines Taktes für Simulation
SIGNAL clk_halfp : time := 20ns;
clkgen : PROCESS
BEGIN WAIT FOR 1*clk_halfp; clk <= '1'; WAIT FOR 1*clk_halfp; clk <= '0'; END PROCESS clkgen;
END struct;
Ohne Sensitivity Liste
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School ofEngineeringÜbung:
Zeichnen Sie den Schaltplan dieses VHDL
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY dff_logic IS
PORT( clk,j,k : IN std_logic;h : OUT std_logic);
END dff_logic;
ARCHITECTURE rtl OF dff_logic ISSignal i : std_logic;
BEGINdff : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENh <= i;i <= j OR k;
END IF;END PROCESS dff;
END rtl;
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School ofEngineeringLösung der Übung
clk
QD QD hij >1
k
dff : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENh <= i;i <= j OR k;
END IF;END PROCESS dff;
Als Faustregel gilt:Jedes Signal das nach clk‘event zugewiesen wird, wird alsFlip-Flop synthetisiert
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School ofEngineeringÜbung:
Eindeutiger VHDL Kode
ARCHITECTURE rtl OF dff_logic ISSignal i, next_i : std_logic;
Signal next_h : std_logic;
BEGINdff : PROCESS(clk)BEGIN
IF clk'EVENT AND clk = '1' THENi <= next_i;h <= next_h;
END IF;END PROCESS dff;
comb : PROCESS(i,j,k)BEGIN
next_i <= j OR k;next_h <= i;
END PROCESS dff;END rtl;
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School ofEngineeringZeitliches Verhalten der Übung
clk
k
i
h
clk
QD QD hij >1
k
j
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School ofEngineeringZeitliches Verhalten der Übung
clk
k
i
h
clk
QD QD hij >1
k
j
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Aufbau und Architektur von PLD
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Übersicht Programmierbare Logik
Programmierbare Bausteine
FPGAField Programmable Gate Array
CPLD
Look Up Tablebasierend
Multiplexerbasierend
LogicArray
basierend
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School ofEngineeringDarstellung von kombinatorischer
Logik
N ALogischeVerknüpfung
(Disjunktive Form)A = Z & K & !S # Z & N & !S
&
&
>1
S
Z
K
N A
Gute Minterme
K
S
Z
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School ofEngineering
Darstellung von sequentieller Logik
GegenwärtigerZustand
n = Anzahl der FFsQ
!Q
Takt
nn+
int. 1
Reset
Folge-Zustand
Beispiel synchroner Zähler
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D Q D Q
L4
D QIN_A OUT_A
L3L2L1 L5
FF1 FF2 FF3
Allgemeine RTL Beschreibung einer Synchronen Digitalen Schaltung
(RTL = Register Transfer Level)
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24
School ofEngineering
&
I1 I0
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
>1
AND Feld(programmierbar)
OR Feld(fest verdrahtet)
Eingangsignal invertiert
Eingangspuffer
>1
>1
>1
DQ
DQ
DQ
DQ
Out1
Out0
Out2
Out3
CLK
PLD
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School ofEngineeringComplex Programmable Logic Device
Ein Logik Block = 16 FF
Programmable Interconnect Matrix
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2. Aufbau mit Multiplexern
B
0
A
X = A UND B1
0 &B
AX
A B X
0 0 0
1 0 0
0 1 0
1 1 1
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School ofEngineeringRS-Flip-Flop aufgebaut aus
Multiplexern
Q0
1
Q
SR
0
10
0
1
1
0
!R !S Qn+1 !Qn+1
0 0 0 0
1 0 1 0
0 1 0 1
1 1 Qn !Qn
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School ofEngineeringLogikgrundzelle von Actel basierend
auf Multiplexern
Transfergate
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a
b
a b y
0 0 0
0 1 1
1 0 1
1 1 0XOR Funktion im LUT
Y
4 x 1 RAM
LUT
Logik mit Look Up Tabellen
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Ein Logic Element (LE) im MAXII
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MAXII Block Diagram
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LE Kluster (Logic Array Blocks)
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Direkte Links zu benachbarten LAB
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MAXII Floorplan
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Verteilung spezieller Signale
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MAX II I/O
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Spezielle Pins
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Synthese
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Synthese
FF0
QD
&&
&
&
&
G3
G2
G1
Q1
Q2
Q0
E3
E0E1E2
= Umwandlung einer VHDLSchaltungsbeschreibung inphysikalische Gatter und Flip Flops
Gatter/Flip-Flop Bibliothek
Hardware Beschreibung
Netzliste
ARCHITECTURE comb OF beisp IS
BEGIN
q0 <= not (e0 and e1);
sig3 <=(e2 and e3) or (e0 and e1);......(Beschreibung nicht vollständig)
END comb;
sig3
!! Jedes synthetisierbare VHDL wird Hardware !!
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VHDL Synthesizer
Entity: A
Architecture: A
Entity: B
Architecture: B Package: A
VHDL Synthesizer (umwandlung von VHDL code in Gatter und Flip Flops)
WorkingLibrary
ieeeLibrary
.pin .vhd
BauteileLibraries
.jed .rpt
Dateien fürProgrammiergerät
Bericht Pin Belegung
Ergebnis inVHDL Form
primitiveLibrary
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41
School ofEngineeringSynthese Beispiel I
D
ENA
QPRE
CLR
BUF (DIRECT)
D
ENA
QPRE
CLR
comb~0
clk
kh
h~reg0\dff:ii~0j
Synthese Ergebnis der Übung (Folie 14)
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LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY dff_arst IS PORT( clk, din, reset : IN std_logic;
qout : OUT std_logic );END dff_arst;
ARCHITECTURE rtl OF dff_arst ISBEGIN dff : PROCESS(clk, reset) BEGIN IF reset = '1' THEN
qout <= '0'; ELSIF clk'EVENT AND clk = '1' THEN qout <= din; END IF; END PROCESS dff;END rtl;
Synthese Beispiel II D-FF mit async. Reset
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Synthese Ergebnis
qout~reg0
D
ENA
QPRE
CLR
dclk
reset
qout
Synthese Beispiel II D-FF mit async. Reset
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LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY dff_srst IS PORT( clk, d, reset : IN std_logic;
qout : OUT std_logic );END dff_srst;
ARCHITECTURE rtl OF dff_srst ISBEGIN dff : PROCESS(clk, reset) BEGIN IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN qout <= '0';ELSE qout <= d;END IF;
END IF; END PROCESS dff;END rtl;
Synthese Beispiel III D-FF mit Sync. Reset
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Synthese Ergebnis
qout~reg0
S
D
ENA
QPRE
CLR
dreset
qout
clk
Synthese Beispiel III D-FF mit Sync. Reset
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Erklärungen zum LabFlankendetektor
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clk
flin
q1
q2
steig
&flinQD QD
q1 q2
steig
reset
clk
Wie können wir die Schaltung ändern, so dass wir fallende und steigende Flanken anzeigen
Flankendetektor
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Simulation von getakteter Logik (am Beispiel Flankendetektor)
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School ofEngineeringWas muss man testen?
Was weiss man vom Logikverhalten?
• Nach der zweiten Taktflanke nachdem flin =‚1‘ wird steig = ‚1‘
• „steig“ bleibt genau für eine Taktperiode ‚1‘
• Nach der fallenden Taktflanke von flin =‚1‘ bleibt „steig“ auf ‚0‘.
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Simulatoren und Debugger
DUTProcess:Stimulus
Process:clk
Testbench
Process:Stimulus
Check mit Assert
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Signal Stimulus
stimuli: processbeginwait for 1*clk_halfp ;flin <= '0';
reset <= '1'; RESET RAUSwait for 5*clkp;reset <= '0';assert (steig = '0') report " after reset should be zero" severity failure;wait for 1*clkp ;flin <= '1'; assert (steig = '0') report " should still be zero" severity failure;wait for 1*clkp;-- 1. Takt nach flin = '1'flin <= '1';assert (steig = '0') report " should still be zero" severity failure;
wait;