sampling chip in 130nm cmos
DESCRIPTION
Sampling chip in 130nm CMOS. Prototype: 2-channel 256 cells (6.4ns) 40 GHz with 2x interleaved DLL Phase detector Self-trigger. Full chip: 32-channel 256 x 256 cells (6.4ns window at each BCO @ LHC). - PowerPoint PPT PresentationTRANSCRIPT
Sampling chip in 130nm CMOS
Prototype:
2-channel 256 cells (6.4ns) 40 GHz with 2x interleaved DLLPhase detectorSelf-trigger
Full chip:
32-channel 256 x 256 cells (6.4ns window at each BCO @ LHC)