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SAMA5D2-PTC-EK SAMA5D2-PTC-EK User's Guide
Scope
This user's guide describes how to use the SAMA5D2 PTC Evaluation Kit (SAMA5D2-PTC-EK).
The SAMA5D2-PTC-EK is used to evaluate the capabilities of the Peripheral Touch Controller (PTC)designed for the SAMA5D2 series of embedded MPUs. Refer to the Configuration Summary table in theSAMA5D2 Series Datasheet for the list of MPUs featuring PTC.
© 2017 Microchip Technology Inc. DS50002709A-page 1
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Table of Contents
Scope.............................................................................................................................. 1
1. Introduction................................................................................................................31.1. Document Layout......................................................................................................................... 31.2. Recommended Reading...............................................................................................................3
2. Product Overview...................................................................................................... 42.1. SAMA5D2-PTC-EK Features.......................................................................................................42.2. SAMA5D2-PTC-EK Content.........................................................................................................52.3. Evaluation Kit Specifications........................................................................................................ 52.4. Power Sources.............................................................................................................................5
3. Board Components....................................................................................................63.1. Board Overview............................................................................................................................63.2. Function Blocks............................................................................................................................93.3. External Interfaces..................................................................................................................... 313.4. Debugging Capabilities.............................................................................................................. 353.5. PIO Usage on Expansion Connectors........................................................................................40
4. Installation and Operation........................................................................................484.1. System and Configuration Requirements...................................................................................484.2. Board Setup............................................................................................................................... 48
5. Appendix A. Schematics and Layouts..................................................................... 49
6. Revision History.......................................................................................................626.1. Rev. A - 12/2017.........................................................................................................................62
The Microchip Web Site................................................................................................ 63
Customer Change Notification Service..........................................................................63
Customer Support......................................................................................................... 63
Microchip Devices Code Protection Feature................................................................. 63
Legal Notice...................................................................................................................64
Trademarks................................................................................................................... 64
Quality Management System Certified by DNV.............................................................65
Worldwide Sales and Service........................................................................................66
SAMA5D2-PTC-EK
© 2017 Microchip Technology Inc. DS50002709A-page 2
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1. Introduction
1.1 Document LayoutThe document is organized as follows:
• Chapter 1. "Introduction"• Chapter 2. "Product Overview" – Important information about the SAMA5D2-PTC-EK board• Chapter 3. "Board Components" – Specifications of the SAMA5D2-PTC-EK and high-level
description of the major components and interfaces• Chapter 4. "Installation and Operation" – Instructions on how to get started with the SAMA5D2-
PTC-EK• Appendix A. "Schematics and Layouts" – SAMA5D2-PTC-EK schematics and layout diagrams
1.2 Recommended ReadingThe following Microchip document is available and recommended as a supplemental reference resource:
• SAMA5D2 Series Datasheet. Lit. Number DS60001476
SAMA5D2-PTC-EKIntroduction
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2. Product Overview
2.1 SAMA5D2-PTC-EK FeaturesThe SAMA5D2-PTC-EK follows the Microchip MPU strategy for low cost evaluation kits with maximumreuse capability, and is built on the SAMA5D2 Xplained Ultra (XULT) hardware and software ecosystem.This board is mainly dedicated to evaluating the Peripheral Touch Controller capabilities.
Table 2-1. SAMA5D2-PTC-EK Features
Characteristics Specifications Components
Processor SAMA5D27-CU (289-ball BGA) 14x14mmbody, 0.8mm pitch
–
Clock speed MPU: 24 MHz, 32.768 KHzPHY: Crystal 25 MHz
–
Memory Two 16-bit, 2-Gbit DDR2One 4-Gbit Nand Flash
One QSPI Flash
One Serial Data Flash (optional)
One EEPROM
Winbond W972GG6KB-25Micron MT29F4G08
Microchip SST26VF064B
Microchip SST26VF032B
Microchip 24AA02E48
Display One LCD interface connector RGB, 18 bits
SD/MMC One standard SD card interfaceOne microSD card interface
With 3.3V/1.8V power switch–
USB One USB host type AOne USB device type MicroAB
One USB HSIC
With 5V power switch–
Connector not mounted
Ethernet One ETH PHY Micrel KSZ8081RN
Debug Port One JLINK-OB/ JLINK-CDCOne JTAG interface
Embedded JLINK-OB and JLINK-CDC (ATSAM3U4C TFBGA100)
Board Monitor One RGB (Red, Green, Blue) LEDFour push button switches
–DisableBoot, Reset, WakeUp, UserFree
Expansion One set of XPRO WINGS connectorsOne ITO FLEX connector
One Port B connector
One PIOBU connector
One mikroBUS connector
Dedicated PTC QTouchOptional
Optional
Optional
–
SAMA5D2-PTC-EKProduct Overview
© 2017 Microchip Technology Inc. DS50002709A-page 4
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Characteristics Specifications Components
Board Supply From USB A and USB JLINK-OB 5VDC
Backup Power Supply SuperCap ELNA DSK-3R3H204T614-H2L
2.2 SAMA5D2-PTC-EK ContentThe SAMA5D2-PTC-EK evaluation kit includes the following:
• The SAMA5D2-PTC-EK board• A USB cable
2.3 Evaluation Kit SpecificationsTable 2-2. Evaluation Kit Specifications
Characteristic Specification
Board SAMA5D2-PTC-EK
Board supply voltage USB-powered
Temperature Operating: 0°C to +70°CStorage: –40°C to +85°C
Relative humidity 0 to 90% (non-condensing)
Main board dimensions 135 × 90 × 20 mm
RoHS status Compliant
Board identification SAMA5D2 Peripheral Touch Controller Evaluation Kit
2.4 Power SourcesSeveral options are available to power up the SAMA5D2-PTC-EK board:
• USB powering through the USB Micro-AB connector (J4 - default configuration)• Powering through the USB Micro-AB connector on the JLlink-OB Embedded Debugger interface
(J9)
Table 2-3. Electrical Characteristics
Electrical Parameter Value
Input voltage 5VCC
Maximum input voltage 6VCC
Maximum 3.3VDC current available 1.2A
I/O voltage 3.3V only
SAMA5D2-PTC-EKProduct Overview
© 2017 Microchip Technology Inc. DS50002709A-page 5
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3. Board ComponentsThis section covers the specifications of the SAMA5D2-PTC-EK and provides a high-level description ofthe board's major components and interfaces. This document is not intended to provide a detaileddocumentation about the processor or about any other component used on the board. It is expected thatthe user will refer to the appropriate documents of these devices to access detailed information.
3.1 Board OverviewThe fully-featured SAMA5D2-PTC-EK board integrates multiple peripherals and interface connectors, asshown in the figure below.
3.1.1 Default Jumper SettingsThe figure below shows the default jumper settings. Jumpers in red are configuration items and currentmeasurement points. Jumpers in blue are not populated.
SAMA5D2-PTC-EKBoard Components
© 2017 Microchip Technology Inc. DS50002709A-page 6
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Figure 3-1. Default Jumper Settings
The following table describes the functionality of the jumpers.
Table 3-1. SAMA5D2-PTC-EK Jumper Settings
Jumper Default Function
JP1 Closed VDD_MAIN_5V current measurement
JP2 Closed VDDOSC, VDDUTMII, VDDANA, VDDAUDIOPLL current measurement
JP3 Closed VDDISC + VDDIOP0/1/2 current measurement
JP4 Closed VDDIODDR_MPU current measurement
JP5 Closed VDDCORE current measurement
JP6 Closed VDDBU current measurement
JP7 Open PIOBU1, PIOBU7
JP8 Closed Disables NAND_CS (open=disable)
JP9 Open Enables JTAG-CDC (closed=disable)
JP10 Open Enables JTAG-OB (closed=disable)
JP11 Open Erases SAM3U Flash Code (closed = erase)
SAMA5D2-PTC-EKBoard Components
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Jumper Default Function
WARNING Warning: This jumper is reserved for factory configuration and shouldnever be used by the end user.
JP12 Closed Powers mikroBUS extension (3.3V)
JP13 Open Disables QSPI
JP14 1-2 Enables 3.3V JLINK-OB, connected to shutdown circuitry
2-3 Enables 3.3V JLINK-OB, always ON
3.1.2 Connectors on BoardThe following table describes the interface connectors on the SAMA5D2-PTC-EK.
Table 3-2. SAMA5D2-PTC-EK Board Interface Connectors
Connector Interfaces to
J1 PIOBU, tamper and analog comparator connector (not populated)
J2 JTAG, 10-pin IDC connector
J3 USB Host B. Supports USB host using a type A connector
J4 USB A Device. Supports USB device using a type Micro-AB connector
J5 USB-C HSIC header (not populated)
J6 Standard SDMMC connector
J7 microSD connector
J8 Ethernet 10/100 RJ45
J9 USB-A MicroAB, JLink-OB port
J10 PCB connector for factory-programming the JLINK-OB/SAM3U
J11, J12 Xplained Pro expansion connectors (PTC-dedicated add-on boards)
J13 PIOs PortB connector
J14 ITO connector
J15 A&B mikroBUS connector
J16 Expansion TFT LCD connector for display module
SAMA5D2-PTC-EKBoard Components
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3.2 Function BlocksFigure 3-2. SAMA5D2-PTC-EK Block Diagram
POWERMONITOR
JLINK-OB JTAG Interface
JLINK Power5v/3v3
USBConnector
Function Select
System SuppliesPOWER
REGULATORS
SHDN
UART
MPU JTAGInterface
JTAG Switch
JTAG LCD (18bits)
TWI/SPI
RJ45
USB A&B
SDHC0 SDHC1
SAMA5D2-PTC-EK
Push Button
FPC Connector
DEBUGInterface
Reset, Wkup
DisBoot, UserSD Card
ConnectoruSD
Connector
3v3, 2v5,1v8, 1v2
VDDBU
GPIO
USBDetection
ETHPHY
PTC
QSPIFlash
DDR2SDRAM
DDR2SDRAM
Power Cap
SerialEEprom
NandFlash
PIOBU Connector
MikroBUSInterface
ITO Connector
XPRO (1&2)PTC Interface
GPIO
PortB[0-7]
PowerSwitch
VBUS
5v
5v
5v
USB-BConnector
USB-AConnector
SPIFlash
Leds
JLINK-OBJLINK-CDC
SAMA5D27
RGBLeds
TriState
3.2.1 ProcessorThe SAMA5D2 Series is a high-performance, power-efficient embedded MPU based on the ARM®
Cortex®-A5 processor.
Please refer to the SAMA5D2 Series datasheet for more information.
3.2.2 Power Supply Topology and Power Distribution
3.2.2.1 Input Power OptionsTwo options are available to power the SAMA5D2-PTC-EK board. The USB-powered operation is thedefault configuration and comes from the USB device ports (J4-J9) connected to a PC or a 5VDC supply.Such USB power source is sufficient to supply the board in most applications. It is important to note thatwhen the USB-powered operation is used, the USB port down the way has a limited powering capability.If the USB-B Host port (J3) is required to provide full powering capabilities to the target application, it isrecommended to use an external DC supply instead of a USB power source.
The following figure is a schematic of the power options.
SAMA5D2-PTC-EKBoard Components
© 2017 Microchip Technology Inc. DS50002709A-page 9
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Figure 3-3. Input Powering
VDD_MAIN_5V
GND_POWER
GND_POWER
GND_POWER
GND_POWERGND_POWER
VBUS_USBA
VBUS_JLINKU1A
DMP2160UFD
1
2
67
C1100nFC0402
U4ADMP2160UFD
1
2
67
R5 100KR0402
R6 DNPR0402
U1BDMP2160UFD
4
5
38
JP1Header 1X2
1 2
C12100nFC0402
R110KR0402
U4BDMP2160UFD
4
5
38
R2100KR0402
JPR1Jumper
C2100nFC0402
Note: USB-powered operation eliminates additional wires and batteries. It is the preferred mode ofoperation for any project that requires only a 5V source at up to 500 mA.
Jumper JP1 is used to perform MAIN_5V current measurements on the SAMA5D2-PTC-EK board.
3.2.2.2 Power Supply Requirements and RestrictionsDetailed information on the device power supplies is provided in tables “SAMA5D2 Power Supplies” and“Power Supply Connections” in the SAMA5D2 Series datasheet.
3.2.2.3 Power-up and Power-down ConsiderationsPower-up and power-down considerations are described in section “Power Considerations” of theSAMA5D2 Series datasheet.
CAUTION Caution: The power-up and power-down sequences provided in the SAMA5D2 Seriesdatasheet must be respected for reliable operation of the device.
3.2.2.4 Power ManagementThe board power management uses three types of regulators:
• One dual synchronous step-down DC-DC regulator (U2 MIC2230) generates the 3.3V/800mA and1.8V/800mA power lines and utilizes a high-efficiency, fixed-frequency (2.5 MHz), current-modePWM control architecture that requires a minimum number of external components.
• One ultra low-dropout linear regulator (U3 MIC47053) generates the 1.25V/500mA from the 1.8Vsource.
• One high-performance single 2.5V/150mA is used as a VDDFUSE generator (U5 MIC5366).
The main regulators are enabled through a Field Effect Transistor (FET) scheme. The processor canassert SHDN (a VDDBU-powered I/O) to shut down the regulators to enter Backup mode. All regulatorson the board are also shut down by the action of the SHDN signal.
A 3.3V battery (supercap) is implemented to permanently maintain VDDBU voltage (note: jumper JP6must be in place). The board can be woken up by action on the PB4 button, which drives the WKUPsignal (also a VDDBU-powered I/O).
The figure below shows the power management scheme.
SAMA5D2-PTC-EKBoard Components
© 2017 Microchip Technology Inc. DS50002709A-page 10
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Figure 3-4. Board Power Management
EN_1
EN_VDD_1V25
STARTB
STARTB
FPWM#
FPWM#
EN_1
EN_VDD_1V25
VDD_MAIN_5V
GND_POWER
GND_POWER
VDD_3V3VDD_1V8
VDD_MAIN_5V
VDD_1V8VDD_1V25
VDD_MAIN_5V
GND_POWER GND_POWERGND_POWER
VDD_MAIN_5V
VDD_3V3
VDD_MAIN_5V
GND_POWER
VDD_3V3
GND_POWER
GND_POWER
VDD_3V3
GND_POWER GND_POWERGND_POWER
GND_POWER
SHDN
C410uFC0603
U2
MIC2230-GSYMLMLF3x3mm
AVIN3
EN111
FPWM#7
SW18
OUT112
AGND5
PGND6
OUT21
SW24
PGOOD10
EN22
VIN9
EPAD
13
R249 4.7KR0402
R1339KR0402
C610uFC0603
R3100KR0402
R25110KR0402
R12220KR0402
C10 390pFC0402
C7100nFC0402
L2 LQH43CN2R2M03LL1812
C310uFC0603
R24820KR0402
R10DNPR0402
R11100KR0402
C134.7nFC0402
R2503.3KR0402
L1 LQH43CN2R2M03LL1812
C51uFC0603
Q1BSS138SOT23_1231
3
2
R410KR0402
C91uFC0603
D1PMEG6010CEGWXsod123
Q2BSS138SOT23_1231
3
2
C8100nFC0402
R9100KR0402
C1110uFC0603
Q3BSS138SOT23_1231
3
2
U3
MIC47053YMT
BIAS1
GND2
IN13
IN24
ADJ6
OUT5
EPAD
9
PGOOD7
EN8
Q4
BC847CSOT-23 1
32
R8 100KR0402
C142.2uFC0603
NRST
3.2.2.5 Supply Group ConfigurationThe main regulators provide all power supplies required by the SAMA5D2 device:
• 1.25V VDDCORE, VDDPLLA, VDDUTMIC, VDDHSIC• 1.8V VDDIODDR, VDDSDHC1V8• 2.5V VDDFUSE• 3.3V VDDIOP0, VDDIOP1, VDDIOP2, VDDISC• 3.3V VDDOSC, VDDUTMI, VDDANA, VDDAUDIOPLL• 3.3V VDDBU
SAMA5D2-PTC-EKBoard Components
© 2017 Microchip Technology Inc. DS50002709A-page 11
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Figure 3-5. Power Lines Distribution
For DDR2 For MPU
VDDHSIC
VDD_3V3
VDD_1V25 VDDCORE
VDDIOP0
VDDIOP2
VDDIOP1
VDDPLLA
VDDUTMIC
VDDIODDR
VDDAUDIOPLL
VDDANA
VDDOSC
VDDUTMII
VDDISC
VDD_1V8 VDDSDHC1V8
L3
BLM18PG181SN1DR0603
1 2
R162R2R0603
R15
2R2R0603
R170RR0603
L7MLZ1608N100LL0603
L11
BLM18PG181SN1DR0603
1 2
L10
BLM18PG181SN1DR0603
1 2
JP5Header 1X2
1 2
R180RR0603
L4
BLM18PG181SN1DR0603
1 2
L14
BLM18PG181SN1D
1 2
L9MLZ1608N100LL0603
JP4Header 1X2
1 2
L13
BLM18PG181SN1DR0603
1 2
L6
BLM18PG181SN1DR0603
1 2
L8MLZ1608N100L
L0603
R192R2R0603
L5
BLM18PG181SN1DR0603
1 2
L12
BLM18PG181SN1DR0603
1 2
JP3Header 1X2
1 2
JP2Header 1X2
1 2
Figure 3-6. Processor Power Lines Supplies
(3V3)
(1V2)
(1V8)
(3V3)
)3V3()3V3()3V3(
)5V2()2V1(
(3V3)
(3V3)
(3V3)
(3V3)
(3V3)
(3V3)
(3V3)
(3V3)
(3V3)
(1V8)
(1V2)
(1V2)
(1V2)
(1V2)
(2V5)
(3V3)
(1V2)
)3V3()2V1(
(3V3)
(3V3)
(3V3 or 1V8)
(3V3 or 1V8)
VDDBU
VDDCORE
VDDPLLA
VDDIOP0
VDDIOP1
VDDIOP2
VDDHSIC
VDDUTMIC
VDDUTMII
VDDSDHC
VDDPLLA
VDDOSC
VDDISC
VDDFUSE
VDDAUDIOPLL
VDDBU
VDDIODDR
VDDANA
VDDANA
VDDIOP0 VDDIOP1 VDDIOP2
VDDHSIC VDDFUSE
VDDUTMII VDDSDHC
VDDOSC VDDISC
VDDUTMIC
VDDCORE
VDDIODDR
VDDAUDIOPLL
GND_POWER
VDDBU
GND_POWER
GND_POWER
VDDCORE
GND_POWER
VDDIODDR
VDDANA
GND_POWER
VDDIOP0
GND_POWER
VDDIOP1
GND_POWER
VDDIOP2
GND_POWER
VDDHSIC
GND_POWER
VDDFUSE
GND_POWER
VDDUTMII
GND_POWER
VDDSDHC
GND_POWER
VDDPLLA
GND_POWER
VDDOSC VDDISC
GND_POWER
GND_POWER
VDDUTMIC
GND_POWER
GNDUTMII
GND_POWER
VDDAUDIOPLL
C35100nFC0402
C511nFC0402
C544.7uFC0805
C31100nFC0402
C254.7uFC0805 C611nF
C0402
C56100nFC0402
C37100nFC0402
C591nFC0402
C2010uFC0603
C1910uFC0603
C21100nFC0402
C42100nFC0402
C40100nFC0402
C521nFC0402
C50100nFC0402
C48100nFC0402
C26100nFC0402
C53100nFC0402
C2810uFC0603
C30100nFC0402
C34100nFC0402
C601nFC0402
C46100nFC0402
C414.7uFC0805
C49100nFC0402
C2710uFC0603
C44100nFC0402
R201R-1%R0603
C29100nFC0402
C36100nFC0402
R211R-1%R0603
C244.7uFC0805
C47100nFC0402
C32100nFC0402
ATSAMA5D27C-CN
U6G
bga289p8
GNDADCK5
GNDANAL3
GNDBUN6
GNDCORE_1E7
GNDCORE_2E9
GNDCORE_3H4
GNDCORE_4K12
GNDCORE_5M5
GNDCORE_6M9
GNDDDR_1D14
GNDDDR_2E11
GNDDDR_3E12
GNDDDR_4E14
GNDDDR_5H14
GNDDDR_6J14
GNDDDR_7L14
GNDDPLLT5
GNDAUDIOPLLT4
GNDIOP0_1F6
GNDIOP0_2G7
GNDIOP1_1M13
GNDIOP1_2P14
GNDIOP2F9
GNDISCG4
GNDOSCT6
GNDPLLAU5
GNDSDMMCR11
GNDUTMIIP9
GNDUTMICR7
VDDADCL5
VDDANAK3
VDDBUN7
VDDCORE_1D7
VDDCORE_2D9
VDDCORE_3H3
VDDCORE_4K13
VDDCORE_5N5
VDDCORE_6N9
VDDDDR_1D11
VDDDDR_2D12
VDDDDR_3D15
VDDDDR_4E15
VDDDDR_5H15
VDDDDR_6J15
VDDDDR_7L15
VDDAUDIOPLLT3
VDDFUSEM12
VDDHSICR9
VDDIOP0_1E6
VDDIOP0_2F7
VDDIOP1_1N13
VDDIOP1_2R14
VDDIOP2F10
VDDISCF4
VDDOSCT7
VDDPLLAU4
VDDSDMMCP11
VDDUTMIIP8
VDDUTMICP7
C55100nFC0402
C23100nFC0402
C43100nFC0402
C38100nFC0402
C581nFC0402
C57100nFC0402
C33100nFC0402
C39100nFC0402
C45100nFC0402
C22100nFC0402
3.2.2.6 VDDFUSEThe SAMA5D2-PTC-EK board embeds a 2.5V regulator for fuse box programming.
SAMA5D2-PTC-EKBoard Components
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Figure 3-7. VDDFUSE RegulatorVDD_3V3
GND_POWER
VDDFUSE
EN_1 12 C161uFC0603
U5
MIC5366-2.5YMTMLF1x1mm
VIN4
GND2
VOUT1
EN3
EPAD
5
C151uFC0603
3.2.2.7 Backup Power SupplyThe SAMA5D2-PTC-EK board requires a power source in order to permanently power the backup part ofthe SAMA5D2 device (refer to SAMA5D2 Series datasheet). The super capacitor C17 sustains suchpermanent power to VDDBU when all system power sources are off.
Figure 3-8. VDDBU Powering Options
(Super)-Capacitorenergy storage
VDDBU
GND_POWERGND_POWER
VDD_3V3
C18100nFC0402
JP6Header 1X2
1 2
+ C170.2F/3.3Vc117x68
D2
PMEG6010CEGWXsod123
R14 100R-1%R0402
D3BAT54C
SOT23_1233
1
2
3.2.3 Reset CircuitryThe reset sources for the SAMA5D2-PTC-EK board are:
• Power-on reset from the power management unit,• Push button reset BP3,• JTAG or JLINK-OB reset from an in-circuit emulator.
Figure 3-9. Main Reset Control
STARTB
GND_POWER
VDD_MAIN_5V
VDD_3V3
NRST
R1339KR0402
R12220KR0402
R11100KR0402
D1PMEG6010CEGWXsod123
Q3BSS138SOT23_1231
3
2
Q4
BC847CSOT-23 1
32
C142.2uFC0603
PowerGood VDD_1V25
3.2.4 Shutdown CircuitryThe SHDN signal, output of Shutdown Controller (SHDN), drives the shutdown request to the powersupply. This output signal is supplied by VDDBU, which is present in Backup mode.
The Shutdown Controller manages the main power supply and is connected to the ENABLE input pin ofthe DC/DC converter providing the main power supplies of the system.
SAMA5D2-PTC-EKBoard Components
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Figure 3-10. Shutdown Controller
STARTB
EN_1
VDD_MAIN_5V
GND_POWER GND_POWER
VDD_3V3
GND_POWER
SHDN
R3100KR0402
Q1BSS138SOT23_1231
3
2
R410KR0402
Q2BSS138SOT23_1231
3
2
C8100nFC0402
3.2.5 Push Button SwitchesThe SAMA5D2-PTC-EK features four push buttons:
• One board reset push button (BP3). When pressed and released, it causes a power-on reset of theboard.
• One wakeup push button (BP4) connected to the SAMA5D2 WKUP pin, used to exit the processorfrom low-power mode.
• One disable boot push button (BP2) used to devalidate the boot memories (refer to CS Disable).Figure 3-11. System Push Buttons
WAKE UP
RESET
DIS BOOT
GND_POWERVDDBU
DISABLE_BOOT
NRST
WKUP
R146 100R-1%
r0402
BP3 Tact Switch
FSM2JSML
R147 100R-1%
r0402
R238 10K
R0402
BP2 Tact Switch
FSM2JSML
R145 100R-1%
r0402
BP4 Tact Switch
FSM2JSML
• One user push button (BP1) connected to PIO PB10.Figure 3-12. User Push Button
USER BUTTON
PA10_USER_BT R144 0R
R0402
BP1 Tact Switch
FSM2JSML
GND_POWER
3.2.6 Clock CircuitryThe embedded microcontroller generates its necessary clocks based on two crystal oscillators: one slowclock (SLCK) oscillator running at 32.768 KHz and one main clock oscillator running at 24 MHz.
The SAMA5D2-PTC-EK board includes four clock sources:
• The two clocks mentioned above are alternatives for the SAMA5D2 processor (24 MHz, 32.768kHz)
• One crystal oscillator for the Ethernet RMII chip (25 MHz)• One crystal oscillator for the JLink-OB microcontroller (12 MHz)
SAMA5D2-PTC-EKBoard Components
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Figure 3-13. MPU Clock CircuitryXIN
XOUTXOUT32
XIN32
GND_POWERGND_POWERGND_POWER GND_POWER
R122 DNPR0402
C9820pFC0402
C9720pFC0402
R123 DNPR0402
C9620pFC0402
Y1
24MHz CL=10pFx4s32x25
1 4
32
C9920pFC0402Y2
32.768KHz CL=12.5pF
X4S70X15
1
23
4
3.2.7 Memory
3.2.7.1 Memory OrganizationThe SAMA5D2 features a DDR/SDR memory interface and an External Bus Interface (EBI) to enableinterfacing to a wide range of external memories and to almost any kind of parallel peripheral.
This section describes the memory devices mounted on the SAMA5D2-PTC-EK board:
• Two DDR2 SDRAMs• One NAND Flash• One QSPI Flash• One SPI Flash (optional)• One serial EEPROM
Additional memory can be added to the board by:
• Installing an SD or MMC card in the SD/MMC0 or SD/MMC1 slot,• Using the USB-B port.
Support is dependent upon driver support in the OS.
3.2.7.2 DDR2/SDRAMsTwo DDR2/SDRAMs (W972GG6KB-25-2 Gbits = 16 Mbits x 16 x 8 banks) are used as main systemmemory, totalling 4 Gbits of SDRAM on the board. The memory bus is 32 bits wide and operates with afrequency of up to 166 MHz.
The figure below illustrates the implementation for the DDR2 memories.
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Figure 3-14. DDR2 SDRAMs
DDR_VREFDDR_VREF
DDR_DQM0DDR_DQM1
DDR_DQM2DDR_DQM3
DDR_DQS0-DDR_DQS0+
DDR_DQS1+DDR_DQS1-
DDR_DQS2+DDR_DQS2-DDR_DQS3+DDR_DQS3-
DDR_BA1DDR_BA0
DDR_BA1DDR_BA0
DDR_WE DDR_WEDDR_CSDDR_CS
DDR_CLK-DDR_CLK+
DDR_CLK-DDR_CLK+
DDR_CKE DDR_CKE
DDR_CASDDR_RAS
DDR_CASDDR_RAS
DDR_D16DDR_D17DDR_D18DDR_D19DDR_D20DDR_D21DDR_D22DDR_D23DDR_D24DDR_D25DDR_D26DDR_D27DDR_D28DDR_D29DDR_D30DDR_D31
DDR_D0DDR_D1DDR_D2DDR_D3DDR_D4DDR_D5DDR_D6DDR_D7DDR_D8DDR_D9DDR_D10DDR_D11DDR_D12DDR_D13DDR_D14DDR_D15
DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11DDR_A12
DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11DDR_A12
DDR_BA2 DDR_BA2
DDR_A13DDR_A13
GND_POWER
VDD_1V8 GND_POWER
VDD_1V8
GND_POWER
GND_POWER
VDD_1V8 GND_POWER
VDD_1V8
GND_POWER
C94100nFC0402
R29 DNP R0402
C951nFC0402
U8
W972GG6KB-25bga84-32-1509e
A0M8
A1M3
A2M7
A3N2
A4N8
A5N3
A6N7
A7P2
A8P8
A9P3
A10M2
A11P7
A12R2
A13R8
BA0L2
BA1L3
BA2L1
CKEK2
CK_PJ8
CK_NK8
RASK7
CASL7
WEK3
CSL8
DQ0G8
DQ1G2
DQ2H7
DQ3H3
DQ4H1
DQ5H9
DQ6F1
DQ7F9
DQ8C8
DQ9C2
DQ10D7
DQ11D3
DQ12D1
DQ13D9
DQ14B1
DQ15B9
LDQS_PF7
NU/LDQS_NE8
UDQS_PB7
NU/UDQS_NA8
LDMF3
UDMB3
ODTK9
NC1A2 NC2E2 NC3R3 NC4R7
VDD1A1
VDD2E1
VDD3J9
VDD4M9
VDD5R1
VDDQ1A9
VDDQ2C1
VDDQ3C3
VDDQ4C7
VDDQ5C9
VDDQ6E9
VDDQ7G1
VDDQ8G3
VDDQ9G7
VDDQ10G9
VDDLJ1
VREFJ2
VSS1A3
VSS2E3
VSS3J3
VSS4N1
VSS5P9
VSSQ1A7
VSSQ2B2
VSSQ3B8
VSSQ4D2
VSSQ5D8
VSSQ6E7
VSSQ7F2
VSSQ8F8
VSSQ9H2
VSSQ10H8
VSSDLJ7
U7
W972GG6KB-25bga84-32-1509e
A0M8
A1M3
A2M7
A3N2
A4N8
A5N3
A6N7
A7P2
A8P8
A9P3
A10M2
A11P7
A12R2
A13R8
BA0L2
BA1L3
BA2L1
CKEK2
CK_PJ8
CK_NK8
RASK7
CASL7
WEK3
CSL8
DQ0G8
DQ1G2
DQ2H7
DQ3H3
DQ4H1
DQ5H9
DQ6F1
DQ7F9
DQ8C8
DQ9C2
DQ10D7
DQ11D3
DQ12D1
DQ13D9
DQ14B1
DQ15B9
LDQS_PF7
NU/LDQS_NE8
UDQS_PB7
NU/UDQS_NA8
LDMF3
UDMB3
ODTK9
NC1A2 NC2E2 NC3R3 NC4R7
VDD1A1
VDD2E1
VDD3J9
VDD4M9
VDD5R1
VDDQ1A9
VDDQ2C1
VDDQ3C3
VDDQ4C7
VDDQ5C9
VDDQ6E9
VDDQ7G1
VDDQ8G3
VDDQ9G7
VDDQ10G9
VDDLJ1
VREFJ2
VSS1A3
VSS2E3
VSS3J3
VSS4N1
VSS5P9
VSSQ1A7
VSSQ2B2
VSSQ3B8
VSSQ4D2
VSSQ5D8
VSSQ6E7
VSSQ7F2
VSSQ8F8
VSSQ9H2
VSSQ10H8
VSSDLJ7
C72100nFC0402
R32 0R R0402
C751nFC0402
R31 DNP R0402
R30 0R R0402
3.2.7.3 DDR_CAL Analog InputOne specific analog input, DDR_CAL, is used to calibrate all DDR I/Os.
Table 3-3. Calibration Cell DDR_CAL Value
Memory Resistor value
LPDDR2/LPDDR3 24K
DDR3L 23K
DDR3 22K
DDR2/LPDDR1 21K
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Figure 3-15. DDR Signals and CAL Analog Input
DDR_D0DDR_D1DDR_D2DDR_D3DDR_D4DDR_D5DDR_D6DDR_D7DDR_D8DDR_D9DDR_D10DDR_D11DDR_D12DDR_D13DDR_D14DDR_D15DDR_D16DDR_D17DDR_D18DDR_D19DDR_D20DDR_D21DDR_D22DDR_D23DDR_D24DDR_D25DDR_D26DDR_D27DDR_D28DDR_D29DDR_D30DDR_D31
DDR_DQM0DDR_DQM1DDR_DQM2DDR_DQM3
DDR_DQS0+DDR_DQS0-
DDR_DQS1+DDR_DQS1-
DDR_DQS2+DDR_DQS2-
DDR_DQS3+DDR_DQS3-
DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11DDR_A12DDR_A13
DDR_BA0DDR_BA1
DDR_RASDDR_CAS
DDR_BA2
DDR_CSDDR_WE
DDR_VREF
DDR_RESETN
DDR_CLK+DDR_CLK-DDR_CKE
GND_POWER
GND_POWER
GND_POWER
VDDIODDR
R23100KR0402
R2421K-1%
R0402
R25100KR0402
C6422pF
C0402
ATSAMA5D27C-CN
U6E
bga289p8
DDR_A0F12
DDR_A1C17
DDR_A10C15
DDR_A11A16
DDR_A12A17
DDR_A13G11
DDR_A2B17
DDR_A3B16
DDR_A4C16
DDR_A5G14
DDR_A6F14
DDR_A7F11
DDR_A8C14
DDR_A9D13
DDR_BA0H12
DDR_BA1H13
DDR_BA2F17
DDR_CALE13
DDR_CASG12
DDR_CKEF16
DDR_CLKE17
DDR_CLKND17
DDR_CSG13
DDR_D0B12
DDR_D1A12
DDR_D10H17
DDR_D11K17
DDR_D12K16
DDR_D13J13
DDR_D14K14
DDR_D15K15
DDR_D16B8
DDR_D17B9
DDR_D18C9
DDR_D19A9
DDR_D2C12
DDR_D20A10
DDR_D21D10
DDR_D22B11
DDR_D23A11
DDR_D24J12
DDR_D25H10
DDR_D26J11
DDR_D27K11
DDR_D28L13
DDR_D29L11
DDR_D3A13
DDR_D30L12
DDR_D31M17
DDR_D4A14
DDR_D5C13
DDR_D6A15
DDR_D7B15
DDR_D8G17
DDR_D9G16
DDR_DQM0C11
DDR_DQM1G15
DDR_DQM2C8
DDR_DQM3H11
DDR_DQS0B13
DDR_DQS1J17
DDR_DQS2C10
DDR_DQS3L17
DDR_DQSN0B14
DDR_DQSN1J16
DDR_DQSN2B10
DDR_DQSN3L16
DDR_RASF13
DDR_RESETNE16
DDR_VREFCMD16 DDR_VREFB0H16
DDR_WEF15
C62100nFC0402
C63100nFC0402
3.2.7.4 NAND FLASHThe SAMA5D2-PTC-EK has native support for NAND Flash memory through its NAND Flash Controller.The board implements one MT29F4G08ABA 4Gb x 16 NAND Flash connected to chip select three(NCS3) of the microcontroller.
CAUTION Caution: The NAND Flash interface is shared with the SDMMC1 and QSPI interfaces.
The figure below illustrates the NAND Flash memory implementation.
Figure 3-16. NAND Flash
NAND_WPn
3V3_NAND
VDD_3V3 3V3_NAND
3V3_NAND
NAND_CLE_PB1NAND_ALE_PB0NAND_REn_PB2
NAND_WEn_PA30
NAND_RDY_PC8
NAND_IO5_PA27NAND_IO6_PA28NAND_IO7_PA29
NAND_IO0_PA22NAND_IO1_PA23NAND_IO2_PA24NAND_IO3_PA25NAND_IO4_PA26
NAND_CS_PA31
R175100K
MT29F4G08ABADAWP
U13
NC11
NC22
NC33
NC44
NC55
NC66
R/B#7
CE#9
NC710
VCC_112
VSS_113
NC914
NC1015
CLE16
ALE17
NC2147
VSS_448
RE#8
NC811
WE#18
WP#19
DNU220
DNU121
NC1122
NC1223
NC1324
VSS_225
NC1426
NC1527
NC1628
DQ029
DQ130
DQ231
DQ332
NC1733
VCC_234
DNU335
VSS_336
VCC_337
DNU438
VCC_439
NC1840
DQ441
DQ542
DQ643
DQ744
NC1945
NC2046R177
DNP
R174 0R
C113100nF
R180100K
C112100nF
JP8Header 1X2
12
C114100nF
R179 0R
C115100nF
R17610K
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Table 3-4. NAND Flash Signal Descriptions
PIO Mnemonic Shared PIO Signal Description
PA22 NAND_D0 SDMMC1-QSPI Data 0
PA23 NAND_D1 QSPI Data 1
PA24 NAND_D2 QSPI Data 2
PA25 NAND_D3 QSPI Data 3
PA26 NAND_D4 QSPI Data 4
PA27 NAND_D5 QSPI Data 5
PA28 NAND_D6 SDMMC1 Data 6
PA29 NAND_D7 – Data 7
PA30 NANDWE SDMMC1 –
PA31 NCS3 – Chip Select
PB00 NANDALE – –
PB01 NANDCLE – –
PB02 NANDOE – –
PC08 NANRDY – –
3.2.7.5 NAND Flash CS DisableOn-board jumper JP8 controls the selection (CS#) of the NAND Flash memory.
3.2.8 Additional Memories
3.2.8.1 Serial FlashThe SAMA5D2 includes two high-speed Serial Peripheral Interface (SPI) controllers. The SPI is a fullduplex synchronous bus supporting a single master and multiple slave devices. The SPI bus consists ofthe following items:
• a serial clock line (generated by the master)• a data output line from the master• a data input line to the master• one or more active low chip select signals (output from the master)
One SPI port is used to interface with the on-board serial Flash.
The following figure illustrates the implementation of an SPI Flash memory.
Figure 3-17. Serial Flash
SPI0_CS0_PA17
GND_POWER
VDD_3V3
SPI0_MOSI_PA15SPI0_MISO_PA16SPI0_SPCK_PA14 C119100nF
C0402
U16
SST26VF032B-104I/SMsoic8jg
HOLD7
GND4
VCC8
CS1
SCK6
SI5
SO2
WP3
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Note: The serial Flash is optional and not mounted on board.
3.2.8.2 QSPI Serial FlashThe SAMA5D2 provides two Quad Serial Peripheral Interfaces (QSPI).
A QSPI is a synchronous serial data link that provides communication with external devices in Mastermode.
The QSPI can be used in SPI mode to interface with serial peripherals (such as ADCs, DACs, LCDcontrollers, CAN controllers and sensors), or in Serial Memory mode to interface with serial Flashmemories.
The QSPI allows the system to execute code directly from a serial Flash memory (XIP, or Execute Inplace, technology) without code shadowing to RAM. The serial Flash memory mapping is seen in thesystem as other memories (ROM, SRAM, DRAM, etc.).
With the support of the Quad SPI protocol, the QSPI allows the system to use high-performance serialFlash memories which are small and inexpensive, instead of larger and more expensive parallel Flashmemories.
The figure below illustrates the implementation of a QSPI Flash memory.
Figure 3-18. QSPI Serial Flash
QSPI0_CS_PA23
VDD_3V3
GND_POWER
VDD_3V3
VDD_3V3
QSPI0_IO0_PA24QSPI0_IO1_PA25QSPI0_IO2_PA26QSPI0_IO3_PA27 QSPI0_SCK_PA22
U14
SST26VF064B-104I/SMsoic8jg
SI/SIO05
SO/SIO12
SIO23
SIO37
SCLK6CS#1GND4VCC8
C120100nFC0402
R18610KR0402
R18710KR0402
JP13Header 1X2
1 2
R24210K
A jumper (JP13) is used to disable the QSPI Flash.
Table 3-5. SPI and QSPI Signal Descriptions
PIO Mnemonic PIO Shared Signal Description
PA14 SPI0_SPCK _ SPI clock
PA15 SPI0_MOSI _ Master out - Slave in
PA16 SPI0_MISO _ Master in - Slave out
PA17 SPI0_NPCS0 _ Chip select
_ _ _ _
PA22 QSPI0_SCK SDMMC1-Nand Flash QSPI clock
PA23 QSPI0_CS Nand Flash Chip select
PA24 QSPI0_IO0 Nand Flash Data0
PA25 QSPI0_IO1 Nand Flash Data1
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PIO Mnemonic PIO Shared Signal Description
PA26 QSPI0_IO2 Nand Flash Data2
PA27 QSPI0_IO3 Nand Flash Data3
3.2.8.3 CS DisableOn-board push button PB2 controls the selection (CS#) of the bootable memory components (QSPI andserial Flash) using a non-inverting 3-state buffer.
Figure 3-19. CS Disable
BOOT_DIS
QSPI Flash CS
SPI Flash CS
QSPI0_CS_PA23
SPI0_CS0_PA17
GND_POWER
GND_POWER
VDD_3V3
SPI0_NPCS0_PA17
QSPI0_NPCS_PA23
DISABLE_BOOT
C116100nF
VCC
GND
U11
NL17SZ126DFT2G
1
2
3
4
5
VCC
GND
U12
NL17SZ126DFT2G
1
2
3
4
5
R18410K
C117100nF
R18510K
R17810K
The rule of operation is:
• PB2 (DISABLE_BOOT) and PB3 (RESET) pressed = booting from QSPI or optional serial Flash isdisabled.
Refer to the SAMA5D2 Series datasheet for more information on standard boot strategies andsequencing.
3.2.8.4 Serial EEPROM with Unique MAC AddressThe SAMA5D2-PTC-EK board embeds one Microchip 24AA02E48 I²C serial EEPROM connected on theTWI1 interface.
The TWI interface is I2C-compatible and similarly uses only two lines, namely serial data (SDA) and serialclock (SCL). According to the standard, the TWI clock rate is limited to 400 kHz in Fast mode and 100kHz in Normal mode, but configurable baud rate generator permits the output data rate to be adapted to awide range of core clock frequencies. The TWI is used in Master mode.
The 24AA02E48 features 2048 bits of Serial Electrically-Erasable Programmable Read-Only Memory(EEPROM) organized as 256 words of eight bits each and is accessed via an I2C-compatible (2-wire)serial interface. In addition, the 24AA02E48 incorporates an easy and inexpensive method to obtain aglobally unique MAC or EUI address (EUI-48).
The EUI-48 addresses can be assigned as the actual physical address of a system hardware device ornode, or it can be assigned to a software instance. These addresses are factory-programmed byMicrochip and guaranteed unique. They are permanently write-protected in an extended memory blocklocated outside the standard 2-Kbit memory array.
CAUTION Caution: The EEPROM device is used as a “software label” to store board information such aschip type, manufacturer name and production date, using the last two 16-byte blocks inmemory. The information contained in these blocks should not be modified.
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Table 3-6. EEPROM PIOs Signal Descriptions
PIO Mnemonic Shared Signal Description
PC6 TWD1 XPRO TWI Data
PC7 TWCL1 XPRO TWI Clock
The figure below illustrates the implementation for the EEPROM.
Figure 3-20. EEPROM 24AA02E48
TWD1TWCK1
GND_POWER
VDD_3V3
GND_POWER
TWD1_PC6TWCK1_PC7
C118100nFC0402
R18810KR0402
U15
24AA02E488MA2
A01
A12
A23
GND4
SDA5
SCL6
WP7
VCC8
3.2.9 Secure Digital Multimedia Card (SDMMC) InterfaceThe SD (Secure Digital) Card is a non-volatile memory card format used as a mass storage memory inmobile devices.
3.2.9.1 Secure Digital Multimedia Card (SDMMC) ControllerThe SAMA5D2-PTC-EK board has two Secure Digital Multimedia Card (SDMMC) interfaces that supportthe MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and theSDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 Specification.
• The SDMMC0 interface is connected to a standard SD card interface.• The SDMMC1 interface is connected to a microSD card interface.
3.2.9.2 SDMMC0 Card ConnectorA standard MMC/SD card connector, connected to SDMMC0, is mounted on the top side of the board.The SDMMC0 communication is based on a 12-pin interface (clock, command, data (8) and power lines(2)). A card detection switch is included.
The figure below illustrates the implementation for the SDMMC0 interface.
Figure 3-21. SDMMC0 Standard SD Socket
(MCI0_CD)(MCI0_WP)
(MCI0_DA1)(MCI0_DA0)
(MCI0_CK)
(MCI0_CDA)(MCI0_DA3)(MCI0_DA2)
(MCI0_DA4)(MCI0_DA5)
(MCI0_DA7)(MCI0_DA6)
GND_POWER
GND_POWER
VDDSDHCVDD_3V3
SDMMC0_CK_PA0
SDMMC0_CMD_PA1
SDMMC0_DAT1_PA3
SDMMC0_DAT2_PA4SDMMC0_DAT3_PA5
SDMMC0_DAT4_PA6SDMMC0_DAT5_PA7SDMMC0_DAT6_PA8SDMMC0_DAT7_PA9
SDMMC0_WP_PA12SDMMC0_CD_PA13
SDMMC0_DAT0_PA2
R1540RR0402
R16910kR0402
R16768kR0603
R17310kR0402
C110 10uFC0603
R16168kR0603
R15568kR0603
R16368kR0603
J6
7SDMM-B0-2211con_kingconn_7sdmm_2211
8
5
76
43219
141516
13121110
R16568kR0603
R1710RR0402
R15768kR0603
R17210kR0402
C111 100nFC0402
R15868kR0603
R15968kR0603
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Figure 3-22. Standard SD Socket J6 Location
The table below describes the pin assignment of SD/MMC connector J6.
Table 3-7. Standard SD Socket J6 Pin Assignment
Pin No Mnemonic Signal Description
1 MCI0_DA3 SDMMC0_DAT3_PA5
2 MCI0_CDA SDMMC0_CMD_PA1
3 GND GND
4 VCC VDDSDHC (3.3V or 1.8V)
5 MCI0_CK SDMMC0_CK_PA0
6 MCI0_CD SDMMC0_CD_PA13 (card detect)
7 MCI0_DA0 SDMMC0_DAT0_PA2
8 MCI0_DA1 SDMMC0_DAT1_PA3
9 MCI0_DA2 SDMMC0_DAT2_PA4
10 MCI0_DA4 SDMMC0_DAT4_PA6
11 MCI0_DA5 SDMMC0_DAT5_PA7
12 MCI0_DA6 SDMMC0_DAT6_PA8
13 MCI0_DA7 SDMMC0_DAT7_PA9
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Pin No Mnemonic Signal Description
14 MCI0_WP SDMMC0_WP_PA12
15 GND GND
16 GND GND
3.2.9.3 SDMMC0 VDDHC Voltage SwitchingThe board uses an ADG849 to switch the power line VDDSDHC_3V3 or VDDSDHC_1V8 through thecommand line SDMMC0_VDDSEL_PA11.
Figure 3-23. SDMMC0 VDDSDHC Voltage Switching
GND_POWER
GND_POWER
VDD_3V3
VDD_3V3
VDDSDHC1V8
VDDSDHC
SDMMC0_VDDSEL_PA11
U9
ADG849YKSZ-REELSC70
S26
S14
IN1
GN
D3
D5
VDD
2
R151 DNPR0402
R15010kR0402
R152 DNPR0402
C107100nFC0402
Table 3-8. SDMMC1 Power Command
PIO Mnemonic Signal Description
PA11 SDMMC0_VDDSEL Selects 3.3V or 1.8V
3.2.9.4 SDMMC1 Card ConnectorA microSD card connector, connected to SDMMC1, is mounted on the top side of the board. TheSDMMC1 communication is based on a 9-pin interface (clock, command, card detect, four data andpower lines). A card detection switch is included. The microSD connector can be used to connect anymicroSD card for mass storage.
Figure 3-24. SDMMC1 microSD Socket
(MCI1_DA1)(MCI1_DA0)
(MCI1_CK)
(MCI1_CDA)(MCI1_DA3)(MCI1_DA2)
(MCI1_CD)
GND_POWER
GND_POWER
VDD_3V3
SDMMC1_CK_PA22
SDMMC1_CD_PA30
SDMMC1_CMD_PA28
SDMMC1_DAT1_PA19SDMMC1_DAT0_PA18
SDMMC1_DAT2_PA20SDMMC1_DAT3_PA21
R16010kR0402
R16268kR0603
R17010kR0402
R16468kR0603
R16668kR0603
R16868kR0603
C109100nFC0402
C10810uFC0603
SW1
SW2J7
PJS008-2120-0Micro_SD_PJS008
8
5
76
4321
9
131211
10
14
SAMA5D2-PTC-EKBoard Components
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Figure 3-25. microSD Socket J7 Location
The table below describes the pin assignment of microSD connector J7.
Table 3-9. microSD Socket J7 Pin Assignment
Pin No Mnemonic PIO Shared Signal Description
1 SDMMC1_DAT2 PA20 – Data bit 2
2 SDMMC1_DAT3 PA21 – Data bit 3
3 SDMMC1_CDA PA28 – Command
4 VCC – – 3.3V supply voltage
5 SDMMC1_CK PA22 – Clock
6 GND – – Common ground
7 SDMMC1_DAT0 PA18 – Data bit 0
8 SDMMC1_DAT1 PA19 – Data bit 1
9 SW1 GND – Not used
10 SDMMC1_CD PA30 – Card detection switch
11 GND – – Common ground
SAMA5D2-PTC-EKBoard Components
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Pin No Mnemonic PIO Shared Signal Description
12 GND – – Common ground
13 GND – – Common ground
14 GND – – Common ground
3.2.10 Communication InterfacesThe SAMA5D2-PTC-EK board is equipped with Ethernet and USB host/device communication interfaces.This section describes the signals and connectors related to the ETH and USB communication interfaces.
3.2.10.1 Ethernet 10/100 (GMAC) PortThe SAMA5D2-PTC-EK board features a Micrel PHY device (KSZ8081) operating at 10/100 Mb/s. Theboard supports RMII interface modes. The Ethernet interface consists of two pairs of low-voltagedifferential pair signals designated from GRX± and GTX± plus control signals for link activity indicators.These signals can be used to connect to a 10/100 Base-T RJ45 connector integrated on the SAMA5D2-PTC-EK board.
An individual 48-bit MAC address (Ethernet hardware address) is allocated to each product. This numberis stored in the Microchip 24AA02E48 I2C serial EEPROM (refer to Serial EEPROM with Unique MACAddress).
Additionally, for monitoring and control purposes, a LED functionality is carried on the RJ45 connectors toindicate activity, link, and speed status.
For more information about the Ethernet controller device, refer to the Micrel KSZ8081RN controllermanufacturer's datasheet.
Figure 3-26. Ethernet Interface
top/bot
top/bot
top/bot
top/bot
ETH_LED0
TX+
ETH_XI
ETH_XO
ETH_LED1
TX-
RX+
RX-
GND_POWER
GND_POWER
GND_POWER
GND_POWER
VDDA_3V3
VDD_3V3
VDD_3V3
VDD_3V3
ETH_INT_PB24
ETH_GTXCK_PB14
ETH_GTXEN_PB15
ETH_GRXDV_PB16ETH_GRXER_PB17
ETH_GRX0_PB18ETH_GRX1_PB19
ETH_GTX0_PB20ETH_GTX1_PB21
ETH_GMDC_PB22ETH_GMDIO_PB23
NRST
R20010KR0402
R1981KR0402
R20
210
KR
0402
U17
KSZ8081RNBqfn32_1p5h
RXC/B-CAST_OFF19
CRS/CONFIG129
COL/CONFIG028
TXD125
TXD024
TXEN23
RXD3/PHYAD013
RXD2/PHYAD114
RXD1/PHYAD215
RXD0/DUPLEX16
RXDV/CONFIG218
RXER/ISO20
MDC12
MDIO11
INTRP/NAND21
VDDA_3V33
VDDIO17
RESET32
TXP7
TXM6
RXP5
RXM4
VDD_1V22
GND1
PADDLE33
TXC22
TXD226
TXD327
REXT10
XO8
XI9
LED0/NWAYEN30
LED1/SPEED31
R19310KR0402
R1971KR0402
C130100nFC0402
R19210KR0402 C128
10uFC0603
R19910KR0402
C129100nFC0402
R20310KR0402
R20
410
KR
0402
C123 2.2uFC0603
C12710uFC0603
C124 100nFC0402
R20
510
KR
0402
L19BLM18PG181SN1D
R06031 2 R
206
10K
R04
02
R194 6.49K 1%R0402
R196 0RR0402
R20
110
KR
0402
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Table 3-10. Ethernet PHY 10/100 Signal Descriptions
PIO Mnemonic Shared Signal Description
PB14 ETH_GTXCK _ Transmit clock
PB15 ETH_GTXEN _ Transmit enable
PB16 ETH_GRXDV _ Receive data valid
PB17 ETH_GRXER _ Receive error
PB18 ETH_GRX0 _ Receive data 0
PB19 ETH_GRX1 _ Receive data 1
PB20 ETH_GTX0 _ Transmit data 0
PB21 ETH_GTX1 _ Transmit data 1
PB22 ETH_GMDC _ Management data clock
PB23 ETH_GMDIO _ Management data in/out
PB24 ETH_GTX_INT _ Interrupt (open drain)
Figure 3-27. Ethernet PHY Connector J8
LINKACT
ETH_LED0
TX+
ETH_LED1
RX-
RX+
TX-
EARTH_ETH EARTH_ETH
GND_ETH
VDD_3V3
R190 510RR0402
C122100nFC0402
C121100nFC0402
1
2
3
6
4
5
7
8
75
75
75 75
1nF
TD+
TD-
CT
NC
RD-
CT
TX+
TX-
RX+
RX-
RD+
Left Green LED Right yellow LED
J8 13F-64GYD2PL2NL
rj45_13f-64gy_P12_4
1
2
7
8
3
6
5
4
9101112
1314
1516
R189 510RR0402
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Figure 3-28. Ethernet RJ45 Connector J8 Location
The table below describes the pin assignment of Ethernet connector J8.
Table 3-11. Ethernet RJ45 Connector J8 Pin Assignment
Pin No Mnemonic Signal Description
1 TX+ Transmit
2 TX- Transmit
3 RX+ Receive
4 Decoupling capacitor –
5 Decoupling capacitor –
6 RX- Receive
7 NC –
8 EARTH / GND Common ground
9 ACT LED LED activity
10 ACT LED LED activity
11 LINK LED LED link connection
12 LINK LED LED link connection
13 EARTH / GND Common ground
SAMA5D2-PTC-EKBoard Components
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Pin No Mnemonic Signal Description
14 EARTH / GND Common ground
15 NC –
16 NC –
3.2.10.2 USB Host/Device A, BThe USB (Universal Serial Bus) is a hot-pluggable general-purpose high-speed I/O standard for computerperipherals. The standard defines connector types, cabling, and communication protocols forinterconnecting a wide variety of electronic devices. The USB 2.0 Specification defines data transfer ratesas high as 480 Mbps (also known as High Speed USB). A USB host bus connector uses 4 pins: a powersupply pin (5V), a differential pair (D+ and D- pins) and a ground pin.
The SAMA5D2-PTC-EK board features three USB communication ports named USB-A to USB-C:
• USB-A device interface– One USB device standard micro-AB connector.– This port has a VBUS detection function made through the R148-R149 resistor bridge.– The USB-A port is used as a primary power source and as a communication link for the
board, and derives power from the PC over the USB cable. In most cases, this port is limitedto 500 mA.
• USB-B (host port B high- and full-speed interface)– One USB host type A connector.– The USB-B host port is equipped with a 500 mA high-side power switch to enable powering
devices connected to it.• UBC-C (High-Speed Inter-Chip/HSIC port)
– One USB high-speed host port with an HSIC interface.– The port is connected to a single 2-pin jumper.
3.2.10.3 USB-A Interface
SAMA5D2-PTC-EKBoard Components
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Figure 3-29. USB-A Type microAB Connector J4 Location
3.2.10.4 USB-A VBUS DetectionThe USB-A port (J4) features a VBUS detection function provided by the R148-R149 resistor bridge.
The figure below shows the USB implementation on the USBA port.
Figure 3-30. USB-A Power and VBUS Detection
GND_POWER
EARTH_USB_A
GND_POWERGND_POWER
VBUS_USBA
USBA_VBUS_5V_PB11
USBA_DPUSBA_DM
C10320pFC0402
VBUS
SHD
DMDPID
GND
J4
MicroUSB AB ConnectorUSBMICRO5_6A
12345
8 6
11 7
9
10
R149200KR0402
R148 100KR0402
Table 3-12. USB-A PIO Signal Descriptions
PIO Mnemonic Shared Signal Description
PB11 USBA_VBUS_5V - VBUS insertion detection
3.2.10.5 USB-B InterfaceThe figure below shows the USB implementation on the USB-B port.
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Figure 3-31. USB-B Interface
USBB_VBUS_5V
GND_POWER
EARTH_USB_B
USBB_DPUSBB_DM
A
J3Single USB Type AUSB4_2AL
VBUS1
DM2
DP3
GND4
SH1
5
SH2
6
Figure 3-32. USB-B Type A Connector J3 Location
Table 3-13. USB-B PIO Signal Descriptions
PIO Mnemonic Shared Signal Description
PB12 USBB_EN_5V – Power switch enable (active high)
PB13 USBB_OVCUR – Indicates overcurrent (open drain)
USB-B Power SwitchThe USB-B Host port is equipped with a 500 mA high-side power switch for self-powered and bus-powered applications. If the client device is bus-powered, the carrier can supply a 5V, 500mA power tothe client device. The USBB_EN_5V_PB12 signal controls the power switch and current limiter, the MicrelMIC2025, which in turn supplies power to a bus-powered client device. Per the USB specification, bus-powered USB 2.0 devices are limited to a maximum of 500 mA. The MIC2025 limits the current andindicates an overcurrent with the USBB_OVCUR_PB13 signal.
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The table below describes the pin assignment of the USB-A and USB-B connectors.
Table 3-14. USB-A and USB-B Connector Signal Descriptions
Pin No Mnemonic Signal Description
1 VBUS 5V power
2 DM Data minus
3 DP Data plus
4 ID On-the-go identification
5 GND Common ground
3.2.10.6 HSICHigh-Speed Inter-Chip (HSIC) is a standard for USB chip-to-chip interconnect with a 2-signal (strobe,data) source synchronous serial interface using 240 MHz DDR signaling to provide only high-speed 480Mbps data rate.
The interface operates at high speed, 480 Mbps, and is fully compatible with existing USB softwarestacks. It meets all data transfer needs through a single unified USB software stack.
The HSIC interface is not used on the board and is connected to two-point jumper J5 (not mounted).
Figure 3-33. HSIC InterfaceHSIC_DATAHSIC_STRBJ5
DNP12
3.3 External Interfaces
3.3.1 LCD TFT InterfaceThis section describes the signals and connectors related to the LCD interface.
3.3.1.1 LCD InterfaceThe SAMA5D2-PTC-EK board provides a connector with 18 bits of data and control signals to the LCDinterface. Other signals are used to control the LCD and are available on connector J16: TWI, SPI, twoGPIOs for interrupt, 1-wire and power supply lines.
This connector is used to connect LCD display series 43xx or 70xx from PDA.
3.3.1.2 LCD Expansion HeaderJ16 is a 1.27-mm pitch, 50-pin header. It gives access to the LCD signals.
SAMA5D2-PTC-EKBoard Components
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Figure 3-34. LCD Expansion Header Interface
GND_POWER
VDD_3V3VDD_MAIN_5V
LCD_D2_PC10LCD_D3_PC11
LCD_D4_PC12LCD_D5_PC13LCD_D6_PC14LCD_D7_PC15
LCD_D10_PC16LCD_D11_PC17
LCD_D12_PC18LCD_D13_PC19LCD_D14_PC20LCD_D15_PC21
LCD_D18_PC22LCD_D19_PC23
LCD_D20_PC24LCD_D21_PC25LCD_D22_PC26LCD_D23_PC27
LCD_PCLK_PD0LCD_VSYNC_PC30LCD_HSYNC_PC31
LCD_DE_PD1
LCD_EN_PC29
LCD_IRQ1_PC9LCD_IRQ2_PD2
LCD_PWM_PC28
SPI_CS_PB31
SPI_SCK_PB30
SPI_MISO_PB29SPI_MOSI_PB28
TWI_SCL_PB29TWI_SDA_PB28
NRST
SPI_CS_PB31
R230
DNPR0603
R2310RR0603
R234 100R-1%R0402
J16
XF2M-5015-1AFPC50-0p5mm
ID1
GND12
D03
D14
D25
D36
GND27
D48
D59
D610
D711
GND312
D813
D914
D1015
D1116
GND417
D1218
D1319
D1420
D1521
GND522
D1623
D1724
D1825
D1926
GND627
D2028
D2129
D2230
D2331
GND732
PCLK/CMD33
VSYNC/CS34
HSYNC/WE35
DE/RE36
SPI_SCK37
SPI_MOSI38
SPI_MISO39
SPI_CS40
ENABLE41
TWI_SDA42
TWI_SCL43
IRQ144
IRQ245
PWM46
RESET47
VCC148
VCC249
GND850
3.3.1.3 LCD PowerIn order to operate correctly with various LCD modules, two voltage lines are available: 3.3V and 5VCC(default). The selection is made with 0R resistors R230 and R231.
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3.3.1.4 LCD Connector JXFigure 3-35. LCD Connector J16 Location
The table below describes the pin assignment of LCD FPC connector J16.
Table 3-15. LCD Connector J16 Signal Descriptions
Pin No Signal PIO Signal RGB Interface Function
1 ID PB31 _ ID LCD module
2 GND _ GND GND
3 LCDDAT0 – D0 –
4 LCDDAT1 – D1 –
5 LCDDAT2 PC10 D2 Data line
6 LCDDAT3 PC11 D3 Data line
7 GND _ GND GND
8 LCDDAT4 PC12 D4 Data line
9 LCDDAT5 PC13 D5 Data line
10 LCDDAT6 PC14 D6 Data line
SAMA5D2-PTC-EKBoard Components
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Pin No Signal PIO Signal RGB Interface Function
11 LCDDAT7 PC15 D7 Data line
12 GND _ GND GND
13 LCDDAT8 – D8 –
14 LCDDAT9 – D9 –
15 LCDDAT10 PC16 D10 Data line
16 LCDDAT11 PC17 D11 Data line
17 GND GND GND GND
18 LCDDAT12 PC18 D12 Data line
19 LCDDAT13 PC19 D13 Data line
20 LCDDAT14 PC20 D14 Data line
21 LCDDAT15 PC21 D15 Data line
22 GND _ GND GND
23 LCDDAT16 – D16 –
24 LCDDAT17 – D17 –
25 LCDDAT18 PC22 D18 Data line
26 LCDDAT19 PC23 D19 Data line
27 GND _ GND GND
28 LCDDAT20 PC24 D20 Data line
29 LCDDAT21 PC25 D21 Data line
30 LCDDAT22 PC26 D22 Data line
31 LCDDAT23 PC27 D23 Data line
32 GND _ GND GND
33 LCDPCK PD0 PCLK Pixel clock
34 LCDVSYNC PC30 VSYNC/CS Vertical sync
35 LCDHSYNC PC31 HSYNC/WE Horizontal sync
36 LCDDEN PD1 DATA_ENABLE Data enable
37 SPI_SPCK PB30 SPI_SCK –
38 SPI_MOSI PB28 SPI_MOSI (Shared with TWI)
39 SPI_MISO PB29 SPI_MISO (Shared with TWI)
40 SPI_NPCS0 PB31 SPI_CS –
41 LCDDISP PC29 ENABLE Display enable signal
42 TWD PB28 TWI_SDA I2C data line (maXTouch)
SAMA5D2-PTC-EKBoard Components
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Pin No Signal PIO Signal RGB Interface Function
43 TWCK PB29 TWI_SCL I2C clock line (maXTouch)
44 GPIO PC9 IRQ1 maXTouch interrupt line
45 GPIO PD2 IRQ2 Interrupt line for other I2C devices
46 LCDPWM PC28 PWM Backlight control
47 RESET – RESET Reset for both display and maXTouch
48 Main_5V/3V3 VCC VCC 3.3V or 5V supply (0R)
49 Main_5V/3V3 VCC VCC 3.3V or 5V supply (0R)
50 GND _ GND GND
3.3.2 RGB LEDThe SAMA5D2-PTC-EK board features one RGB LED which can be controlled by the user. The threeLED cathodes are controlled via GPIO PWM or timer/counter pins.
Figure 3-36. RGB LED Indicators
LED
VDD_3V3GND_POWER
GND_POWER
GND_POWER
GND_POWER
GND_POWER
LED_RED_PB10
LED_GREEN_PB8
LED_BLUE_PB6
R240 1KR0402
R182 100R-1%R0402
R183 100R-1%R0402
R24410K
Q7BSS138SOT23_1231
3
2
R181 100R-1%R0402
D4
CLV1A-FKB-CJ1M1F1BB7R4S3
Red1
Green4
Blue3
Anode2
R241 1KR0402
R239 2.2K-1%R0402
Q5BSS138SOT23_1231
3
2
R24310K
Q6BSS138SOT23_1231
3
2
Table 3-16. RGB LED PIOS
Signal PIO Function
LED_RED PB10 TIOB3
LED_GREEN PB8 PWML3
LED_BLUE PB6 PWML2
3.4 Debugging CapabilitiesThe SAMA5D2-PTC-EK includes two main debugging interfaces to provide debug-level access to theSAMA5D2:
• One UART through USB JLINK-CDC• Two JTAG interfaces, one connected directly to the MPU using connector J2 and one through the
JLINK-OB interface USB port J9
SAMA5D2-PTC-EKBoard Components
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3.4.1 Debug JTAGThis section describes the signals and connectors related to the JTAG interface.
A 10-pin JTAG header is provided on the SAMA5D2-PTC-EK board to facilitate software developmentand debugging using various JTAG emulators. The interface signals have a voltage level of 3.3V.
Figure 3-37. JTAG Interface
GND_POWER
VDD_3V3
VDD_3V3
GND_POWER
NRST
CON_JTAG_Pin2CON_JTAG_Pin4CON_JTAG_Pin6CON_JTAG_Pin8RTCKIN
R140100KR0402
R23610KR0402
R142100KR0402
R143 100R-1% R0402
R141100KR0402
R138 DNPR0402
J2
Header 2X5FTSH-105-01-F-DV-P-TR
1 23 45 67 89 10
Figure 3-38. JTAG Connector J2 Location
The table below describes the pin assignment of JTAG connector J2.
SAMA5D2-PTC-EKBoard Components
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Table 3-17. JTAG/ICE Connector J2 Pin Assignment
Pin No Mnemonic Signal Description
1 VTref. 3.3V power This is the target reference voltage (main 3.3V).
2 TMS TEST MODE SELECT JTAG mode set input into target CPU
3 GND Common ground
4TCK TEST CLOCK - Output timing signal,for synchronizing test logic and controlregister access
JTAG clock signal into target CPU
5 GND Common ground
6 TDO JTAG TEST DATA OUTPUT - Serialdata input from the target JTAG data output from target CPU
7 RTCK - Input return test clock signal fromthe target
Some targets with a slow system clock mustsynchronize the JTAG inputs to internal clocks. Inthe present case, such synchronization isunneeded and TCK is merely looped back intoRTCK.
8TDI TEST DATA INPUT - Serial data outputline, sampled on the rising edge of the TCKsignal
JTAG data input into target CPU
9 GND Common ground
10 nRST RESET Active-low reset signal. Target CPU reset signal.
3.4.2 Embedded Debugger (JLINK-OB) InterfaceThe SAMA5D2-PTC-EK includes a built-in SEGGER J-Link-On-Board device. The functionality isimplemented with an ATSAM3U4C microcontroller in an LFBGA100 package. The ATSAM3U4C providesthe functions of JTAG and a bridge USB/Serial debug port (CDC). One two-colored LED (D6) mountednear the SAM3 chip (U20) shows the status of the J-Link-On-Board device.
J-Link-OB-ATSAM3U4C was designed in order to provide an efficient, low-cost, on-board alternative tothe standard J-Link.
The USB JLINK-OB port is used as a secondary power source and as a communication link for theboard, and derives power from the PC over the USB cable. This port is limited in most cases to 500 mA.A single PC USB port is sufficient to power the board.
SAMA5D2-PTC-EKBoard Components
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Figure 3-39. JLINK-OB Interface
EDBG_USB_DPEDBG_USB_DM
ENSPI
ERASE_3U
TDI_3UTDO_3UTCK_3UTMS_3U
NRST_3U
TRSTINTRSTOUT
TRESINTRESOUT
TDIIN
TMSIN
TCKOUTTMSOUT
TDIOUTTDOINTCKINENSPITCKOUTPA25_3UPA26_3U
LED2_3U
LED1_3U
EDBG_XIN
RX_3UTX_3U
EARTH_USB_EDBG
VDD_3V3_3UVDD_OUT_3UVDD_3V3_3U
GND_POWER
VDD_3V3_3U
VDD_3V3_3U
GND_POWER
GND_POWER
VDD_3V3_3U
GND_POWER
VDD_3V3_3U
VBUS_JLINK
VDD_3V3_3U
GND_POWER
RTCKIN
R210100R-1%R0402
R211 39R R0402
R209 100R-1%R0402
R215 100KR0402
VBUS
SHD
DMDPID
GND
J9MicroUSB AB Connector
USBMICRO5_6A
12345
8 6
11 7
9
10
R212 39R R0402
C156100nFC0402
R208 10KR0402
R2450R
R214 6.8K-1%R0402
C136 10nFC0402D5 PMEG6010CEGWX
sod123
Y4
ASE-12.000MHz-LC-TNC
1VCC
4Out
3
GND2
U20
ATSAM3U4CA-CUTFBGA100
VBGA1
XINA2
XOUTA3
PB17
A4
PB21
A5
PB23
A6
TCK/SWCLKA7
VDD
INA8
VDD
OU
TA9
XIN32A10
VDD
CO
RE_
1B1
GN
DU
TMI
B2
VDD
UTM
IB3
PB10
B4
PB18
B5
PB24
B6
NRSTB7
TDO/TRACESWOB8 TDIB9
XOUT32B10
DFSDPC1
DHSDPC2
GN
DPL
LC
3
PB14
C4
PB19
C5
PB22
C6
TMS/SWDIOC7
NRSTBC8
JTAGSELC9
VDD
BUC
10
DFSDMD1 DHSDMD2
VDD
PLL
D3
VDD
CO
RE_
2D
4
PB20
D5
ERASED6
TSTD7
FWUPD8
PA11/PGMD3D9
PA12/PGMD4D10
PA29E1
GN
D_1
E2
PA28E3
PB9
E4
GN
DBU
E5
VDD
IO_3
E6
VDD
CO
RE_
3E7
PA10/PGMD2E8PA9/PGMD1E9PA8/PGMD0E10
PB1
F1
PB12
F2
VDD
IO_1
F3
PA31F4
VDD
IO_2
F5
GN
D_2
F6
PB16
F7
PA6/PGMM2F8
VDD
CO
RE_
6F9
PA7/PGMM3F10
PB11
G1
PB2
G2
PB0
G3
PB13
G4
VDD
CO
RE_
5G
5
GN
D_3
G6
PB15
G7
PA3/PGMNVALIDG8
PA5/PGMM1G9PA4/PGMM0G10
VDD
CO
RE_
4H
1
PB5
H2
PA27H3
PA22/PGMD14H4
PA13/PGMD5H5
PA15/PGMD7H6
PA18/PGMD10H7
PA24H8
PA1/PGMRDYH9
PA2/PGMNOEH10
PB6
J1
PB8
J2
ADVREFJ3
PA30J4
PB3
J5
PA16/PGMD8J6
PA19/PGMD11J7
PA21/PGMD13J8
PA26J9
PA0/PGMNCMDJ10P
B7K1
VDD
ANA
K2
GN
DAN
AK3
AD12BVREFK4
PB4
K5
PA14/PGMD6K6
PA17/PGMD9K7
PA20/PGMD12K8
PA23/PGMD15K9
PA25K10
C137 10pFC0402
C132 10nFC0402
R213 DNPR0402
VDD_3V3_3U
R216 150R-1%R0402
R217 150R-1%R0402
D6
KPTB-1615
Green4
11
RED2
33
LED1_3U
LED2_3UERASE_3U
VDD_3V3_3U
JP11Header 1X2
1 2
3.4.2.1 Disabling JLINK-OB (ATSAM3U4C)Jumper JP10 disables the J-Link-OB-ATSAM3U4C JTAG functionality. When the jumper is installed, itgrounds pin 26 of the ATSAM3U4C that is normally pulled high. A quad analog switch is used to selectthe JTAG interface.
• Jumper JP10 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional.• Jumper JP10 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG controller can be
used through the 10-pin JTAG port J2.
Jumper JP10 disables only the J-Link functionality. The debug serial com port that is emulated through aCommunication Device Class (CDC) of the same USB connector remains operational (if JP9 is open).
Figure 3-40. Enabling/Disabling JLINK-OB and JLINK-CDC
JTAG-OB disable
JTAG-CDC disable PA25_3U
PA26_3U
VDD_3V3_3U
GND_POWER
GND_POWER
VDD_3V3_3U
JP9Header 1X2
1 2
R22410KR0402
R22510KR0402
JP10Header 1X2
1 2
SAMA5D2-PTC-EKBoard Components
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Figure 3-41. JTAG Switch
TDIOUT
TDIIN
PA26_3U PA26_3U
TDOIN
TMSIN
TMSOUT
TCKIN
TCKOUT
VDD_3V3_3U
GND_POWER
JTAG_TCK_PD27
JTAG_TMS_PD30
JTAG_TDI_PD28
CON_JTAG_Pin2
CON_JTAG_Pin4
CON_JTAG_Pin8
JTAG_TDO_PD29
CON_JTAG_Pin6
R223 150R-1%R0402
U22
NLAS3899BMNTWGWQFN-16
NCA1
COMA16
NOA15
NOB3
COMB4
NCB5
ABIN2
NOC7
COMC8
NCC9
CDIN10
NOD11
COMD12
NCD13V
CC
14G
ND
6
R222 150R-1%R0402
R218 150R-1%R0402
3.4.3 Hardware UART via CDCIn addition to the J-Link-OB functionality, the ATSAM3U4C microcontroller provides a bridge to a debugserial port (UART DBGU) of the SOM's processor. The port is made accessible over the same USBconnection used by JTAG by implementing Communication Device Class (CDC), which allows terminalcommunication with the target device.
This feature is enabled only if the SAM3U/PA25 (pin K10) is not grounded. The pin is normally pulled highand controlled by jumper JP9.
• Jumper JP9 not installed: the J-Link-CDC is enabled and fully functional.• Jumper JP9 installed: the J-Link-CDC device is disabled.
The USB Communications Device Class (CDC) enables to convert the USB device into a serialcommunication device. The target device running USB-Device CDC is recognized by the host as a serialinterface (USB2COM, virtual COM port) without the need to install a special host driver (since the CDC isstandard). All PC software using a COM port work without modifications with this virtual COM port. UnderWindows, the device shows up as a COM port; under Linux, as a /dev/ACMx device. This enables theuser to use host software which was not designed to be used with USB, such as a terminal program.
Table 3-18. Debug COM Port PIOs Signal Descriptions
PIO Mnemonic Shared Signal Description
PB26 URXD0 - Receive data
PB27 UTXD0 - Transmit data
SAMA5D2-PTC-EKBoard Components
© 2017 Microchip Technology Inc. DS50002709A-page 39
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Figure 3-42. JLINK-OB and CDC USB Connector J9 Location
The table below describes the pin assignment of USB connector J9.
Table 3-19. USB Connector J9 Pin Assignment
Pin No Mnemonic Signal Description
1 VBUS 5V power
2 DM Data minus
3 DP Data plus
4 ID Not used
5 GND Common ground
3.4.3.1 Board Edge ConnectorThis connector is used to upgrade or download code to the ATSAM3U4C microcontroller JLINK-OB.
3.5 PIO Usage on Expansion Connectors
3.5.1 PIOBU InterfaceThe SAMA5D2-PTC-EK board features eight tamper pins for static or dynamic intrusion detection, UARTreception, and two analog pins for comparison.
SAMA5D2-PTC-EKBoard Components
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For a description of intrusion detection, refer to the SAMA5D2 datasheet, chapter "Security Module".
Figure 3-43. PIOBU Connector
RXD
PIOBU0
ACN
PIOBU2PIOBU4PIOBU6
PIOBU3PIOBU5
ACP
GND_POWER
R132 0R R0402R127 330R R0402
R130 330R R0402R124 330R R0402 R129 330R R0402
R131 0R R0402R125 330R R0402
J1DNP
FTSH-105-01-F-DV-P-TR
1 23 45 67 89 10
R126 330R R0402
R128 0R R0402
Figure 3-44. PIOBU Connector J1 Location
The table below describes the pin assignment of PIOBU connector J1.
Table 3-20. PIOBU Connector J1 Pin Assignment
Signal Pin No. Signal
PIOBU0 1 2 PIOBU3
PIOBU2 3 4 PIOBU5
PIOBU4 5 6 RXD
PIOBU6 7 8 ACN
ACP 9 10 GND
3.5.2 mikroBUS InterfaceThe SAMA5D2-PTC-EK hosts a pair of 8-pin female headers as mikroBus interface. The mikroBUSinterface defines the main board sockets and add-on boards used for interfacing microprocessors with
SAMA5D2-PTC-EKBoard Components
© 2017 Microchip Technology Inc. DS50002709A-page 41
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integrated modules with proprietary pin configuration and silkscreen markings. The pinout consists ofthree groups of communication pins (SPI, UART and TWI), four additional pins (PWM, interrupt, analoginput and reset) and two power groups (+3.3V and GND on the left, and 5V and GND on the right 1x8header).
Figure 3-45. mikroBUS InterfacePD25RSTNPCS0SPCKMISOMOSI3V3
PWMINTRXTXSCLSDA
+5vVDD_3V3 VDD_MAIN_5V
GND_POWER
AN-AD6
NPCS0_PC04SPCK_PC01MISO_PC03MOSI_PC02
PWM_PD20INT_PD19RX_PD23TX_PD24TWCK0_PD22
TWD0_PD21
MBUS_RST_PC05
JP12Header 1X2
12
J15A
SSQ-108-01-G-S
12345678
J15B
SSQ-108-01-G-S
12345678
R229 DNPR0402
Figure 3-46. mikroBUS Connector J15 Location
The table below describes the pin assignment of mikroBUS1 connector J15.
Table 3-21. mikroBUS Connector J15 Pin Assignment
SAMA5D27
MBUS Signal Pin No. MBUS Signal
SAMA5D27
Function PIO PIO Function
Analog input PD25 AN 1 1 PWM PD20 PWM
Reset PC05 RST 2 2 INT PD19 Interrupt
SPI chip select PC04 SPI_NPCS 3 3 UART_RX PD23 UART receive
SAMA5D2-PTC-EKBoard Components
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SAMA5D27
MBUS Signal Pin No. MBUS Signal
SAMA5D27
Function PIO PIO Function
SPI clock PC01 SPI_SPCK 4 4 UART_TX PD24 UART transmit
SPI MISO PC03 SPI_MISO 5 5 TWI_SCL PD22 TWI clock
SPI MOSI PC02 SPI_MOSI 6 6 TWI_SDA PD21 TWI data
3.3VCC – 3V3 Supply 7 7 5V Supply _ 5VDD
GROUND – GND 8 8 GND _ GROUND
3.5.3 XPRO InterfaceThe SAMA5D2-PTC-EK board hosts two connectors to interface XPRO QT boards. The QTouch XplainedPro are extension boards that enable evaluation of Self-capacitance and Mutual capacitance modesusing the Peripheral Touch Controller (PTC). The boards show how easy it is to design a capacitive touchboard solution using the PTC without the need for any external components.
Nevertheless, the PTC IO pins available on XPRO connectors can be used as GPIO pins. Each of thesecan be configured as an input or output pin according to the PIO peripheral functions.
The GPIO voltage levels depend on the VDDIOP level supported by the SAMA5D2, 3.3V in this case.
Figure 3-47. XPRO EXT1 Connector
PD16
PD26PD17
PD11PD13PB9PD15
7CP6CP
PD18PD17
PC0PD14PD12
VDD_3V3
GND_POWER
PTC_YLINE0PTC_YLINE2
XPRO1_GPIO_PB9PTC_YLINE4
PTC_YLINE6
PTC_YLINE1PTC_YLINE3
PTC_YLINE5
PTC_YLINE7PTC_YLINE6XPRO1_GPIO_PD26
XPRO1_GPIO_PC0
XPRO_PC6 XPRO_PC7
R227 DNPR226 0R
J11
Header 2X10
1 23 45 67 89 10
11 1213151719
14161820
XPRO2_GPIO_PD31R235 0R
SAMA5D2-PTC-EKBoard Components
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Figure 3-48. XPRO EXT1 Connector J11 Location
The table below describes the pin assignment of XPRO EXT1 connector J11.
Table 3-22. XPRO EXT1 Connector J11 Pin Assignment
SAMA5D27
XPRO Signal Pin No. XPRO Signal
SAMA5D27
Function Pin Pin Function
_ Not used ID 1 2 GND – GROUND
PTC_YLINE0 PD11 ADC(+) 3 4 ADC(-) PD12 PTC_YLINE1
PTC_YLINE2 PD13 GPIO 5 6 GPIO PD14 PTC_YLINE3
GPIO PA10 PWM(+) 7 8 PWM(-) PC0 GPIO
PTC_YLINE4 PD15 IRQ/GPIO 9 10 SPI_SS_B/GPIO PD16 PTC_YLINE5
XPRO_TWD PC6 TWI_SDA 11 12 TWI_SCL PC7 XPRO_TWCK
_ _ UART_RX 13 14 UART_TX _ –
PTC_YLINE6 PD17 SPI_SS_A 15 16 SPI_MOSI PD18 PTC_YLINE7
GPIO PD26 SPI_MISO 17 18 SPI_SCK PD31 or PD17 PTC_YLINE6
GROUND – GND 19 20 VCC 3V3 – 3.3V Supply
SAMA5D2-PTC-EKBoard Components
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Figure 3-49. XPRO EXT2 Connector
PD10
PB25
PD4
PD8
PD3PD6PD5
PD7PD9
PD31
VDD_3V3
GND_POWER
PTC_XLINE0PTC_XLINE2PTC_XLINE4PTC_XLINE6
XPRO2_GPIO_PB25
PTC_XLINE1PTC_XLINE3PTC_XLINE5PTC_XLINE7XPRO2_GPIO_PD31
J12
Header 2X10
1 23 45 67 89 10
11 1213151719
14161820
R228 0R
R235 0RXPRO1
Figure 3-50. XPRO EXT2 Connector J12 Location
The table below describes the pin assignment of XPRO EXT2 connector J12.
Table 3-23. XPRO EXT2 Connector J12 Pin Assignment
SAMA5D27 XPROSignal Pin No.
XPROSignal
SAMA5D27
Function Pio Pio Function
_ Not used ID 1 2 GND – GROUND
PTC_XLINE0 PD3 ADC(+) 3 4 ADC(-) PD4
PTC_XLINE1
PTC_XLINE2 PD5 GPIO 5 6 GPIO PD6
PTC_XLINE3
SAMA5D2-PTC-EKBoard Components
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SAMA5D27 XPROSignal Pin No.
XPROSignal
SAMA5D27
Function Pio Pio Function
PTC_XLINE4 PD7 PWM(+) 7 8 PWM(-) PD8
PTC_XLINE5
PTC_XLINE6 PD9 IRQ/GPIO 9 10
SPI_SS_B/GPIO PD10
PTC_XLINE7
– – TWI_SDA 11 12 TWI_SCL PD31 GPIO
– – UART_RX 13 14 UART_TX – –
GPIO PB25 SPI_SS_A 15 16 SPI_MOSI – –
– – SPI_MISO 17 18 SPI_SCK – –
GROUND – GND 19 20 VCC 3V3 – 3.3VSupply
3.5.4 Miscellaneous PIOB[0-7]PIOs PB00 to PB07 are available on connector J13 and can be used as GPIO pins. Each of these can beconfigured as an input or output pin according to the PIO peripheral functions.
Figure 3-51. PIOs PB[0-7] ConnectorVDD_3V3
GND_POWER
PB_PORT_0PB_PORT_1PB_PORT_2PB_PORT_3PB_PORT_4PB_PORT_5PB_PORT_6PB_PORT_7
J13
PIOB[0-7] connector
123456789
10
SAMA5D2-PTC-EKBoard Components
© 2017 Microchip Technology Inc. DS50002709A-page 46
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Figure 3-52. PIOB[0-7] Connector J13 Location
The table below describes the pin assignment of PIOs PB[0-7] connector J13.
Table 3-24. PIOs PB[0-7] Connector J13 Pin Assignment
Pin No PIO Mnemonic Shared Signal Description
1 _ VDD_3V3 _ Main 3.3V
2 PB0 GPIO NAND Flash PIO port B
3 PB1 GPIO NAND Flash PIO port B
4 PB2 GPIO NAND Flash PIO port B
5 PB3 GPIO _ PIO port B
6 PB4 GPIO _ PIO port B
7 PB5 GPIO _ PIO port B
8 PB6 GPIO LED_BLUE PIO port B
9 PB7 GPIO _ PIO port B
10 _ GND _ Common ground
SAMA5D2-PTC-EKBoard Components
© 2017 Microchip Technology Inc. DS50002709A-page 47
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4. Installation and Operation
4.1 System and Configuration RequirementsThe SAMA5D2-PTC-EK requires the following:
• Personal Computer• USB cable
4.2 Board SetupFollow these steps before using the SAMA5D2-PTC-EK:
1. Unpack the board, taking care to avoid electrostatic discharge.2. Check the default jumper settings.3. Connect the USB Micro-AB cable to connector J9.4. Connect the other end of the cable to a free port of your PC.5. Open a terminal (console 115200, N, 8, 1) on your Personal Computer.6. Reset the board. A startup message appears on the console.
SAMA5D2-PTC-EKInstallation and Operation
© 2017 Microchip Technology Inc. DS50002709A-page 48
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5. Appendix A. Schematics and LayoutsThis appendix contains the following schematics and layouts for the SAMA5D2-PTC-EK board:
• Title and Revision History• Block Diagram• Power Domains• MPU Power• DDR2-SDRAM• PIOA & PIOB• PIOC & PIOD• System• USB & TF• Memories & RGB LED• Ethernet 10/100M• JLINK-OB• EXT Connectors
Figure 5-1. Title and Revision History5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
030201
SHEET NAMESHEETSchematic: A5D2-PTC-EK
0807060504
1312111009
Power domainsBlock DiagramTitle & Revision History
SYSTEM
PIOA&PIOBDDR2-SDRAM
JLINK-OB
MEMORIES&RGBLED
MPU_POWER
Ethernet_10/100M
PIOC&PIOD
USB&TF
EXT_CONNECTORS
DATERevA-2016010706 Jan 2017
NOITPIRCSEDNOISIVERRevision History
Init edit
RevA release07-MAR-17 RevA
RevB
RevB release03-OCT-17 RevB
REV DATEMODIF. DES. DATE VER.SCALE 1/1 REV. SHEET
INIT EDITAA RevA
113B
XX-XXX-XXZhouB XXX
01) Title & Revision History
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XXZhouB 07-MAR-1703-OCT-17THR XX-XXX-XXXXXB
REV DATEMODIF. DES. DATE VER.SCALE 1/1 REV. SHEET
INIT EDITAA RevA
113B
XX-XXX-XXZhouB XXX
01) Title & Revision History
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XXZhouB 07-MAR-1703-OCT-17THR XX-XXX-XXXXXB
REV DATEMODIF. DES. DATE VER.SCALE 1/1 REV. SHEET
INIT EDITAA RevA
113B
XX-XXX-XXZhouB XXX
01) Title & Revision History
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XXZhouB 07-MAR-1703-OCT-17THR XX-XXX-XXXXXB
SAMA5D2-PTC-EKAppendix A. Schematics and Layouts
© 2017 Microchip Technology Inc. DS50002709A-page 49
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Figure 5-2. Block Diagram5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB AOTG
POWER5V INPUT
USB A,B,C
ResetForce PwrOn
PushButtons
JTAG JLINK-OBUser LEDsQSPI FlashNAND Flash
PIO
SPIDataFlash
PIO A,B,C,D
Atmel SAMA5D27Cortex(R)-A5 Processor
XPRO Connectors
5V & 3V3
EBI2GbDDR2SDRAM
Power rails
ANALOG Reference
USBDEVICE
JTAGConnectorSheet 8
Sheet 13
Sheet 95V INPUT
Sheet 12
01 teehS01 teehS
Sheet 5
Sheet 10
Sheet 3Sheet 8
Sheet 4: MPU_POWERSheet 5: DDR2-SDRAMSheet 6: PIOA & PIOBSheet 7: PIOC & PIODSheet 8: SYSTEM
11 teehS01 teehS
Ethernet10/100M bps
USB BHost
USB CHSIC
QSPI Flash PTC PORT
Sheet 13
24AA02E48
Sheet 13
LCD CON
USB TO UART
Sheet 09
SDCARD CON
RevB
REV DATEMODIF. DES. DATE VER.SCALE 1/1 REV. SHEET
INIT EDITAA RevA
213B
XX-XXX-XXZhouB XXX
02) Block Diagram
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XXZhouB 07-MAR-1703-OCT-17THR XX-XXX-XXXXXB
REV DATEMODIF. DES. DATE VER.SCALE 1/1 REV. SHEET
INIT EDITAA RevA
213B
XX-XXX-XXZhouB XXX
02) Block Diagram
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XXZhouB 07-MAR-1703-OCT-17THR XX-XXX-XXXXXB
REV DATEMODIF. DES. DATE VER.SCALE 1/1 REV. SHEET
INIT EDITAA RevA
213B
XX-XXX-XXZhouB XXX
02) Block Diagram
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XXZhouB 07-MAR-1703-OCT-17THR XX-XXX-XXXXXB
SAMA5D2-PTC-EKAppendix A. Schematics and Layouts
© 2017 Microchip Technology Inc. DS50002709A-page 50
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Figure 5-3. Power Domains5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
For DDR2 For MPU
Switching Power lines
(Super)-Capacitorenergy storage
POWER SUPPLY VDDBU Power Supply
Fixed output 1V8, 3v3,
Fixed output 1V2
RevB
EN_1
EN_VDD_1V25
STARTB
STARTB
FPWM#
FPWM#
EN_1
EN_VDD_1V25
VDDHSIC
VDD_3V3
VDD_1V25 VDDCORE
VDDIOP0
VDDIOP2
VDDIOP1
VDDPLLA
VDDUTMIC
VDDIODDR
VDDAUDIOPLL
VDDANA
VDDOSC
VDDUTMII
VDDISC
VDD_1V8
VDD_MAIN_5V
VDDBU
GND_POWERGND_POWER
VDD_3V3
VDD_MAIN_5V
GND_POWER
GND_POWER
VDD_3V3VDD_1V8
VDD_MAIN_5V
VDD_1V8VDD_1V25
VDD_MAIN_5V
GND_POWER GND_POWERGND_POWER
VDD_MAIN_5V
VDD_3V3
VDDSDHC1V8
VDD_3V3
GND_POWER
VDDFUSE
GND_POWER
GND_POWER
GND_POWER
GND_POWERGND_POWER
VDD_MAIN_5V
GND_POWER
VDD_3V3
GND_POWER
GND_POWER
VDD_3V3
VBUS_USBA
VBUS_JLINK
GND_POWER GND_POWERGND_POWER
GND_POWER
NRST 8,11,12,13
SHDN8
EN_1 12
REV DATEMODIF. DES. DATE VER.SCALE 1/1 REV. SHEET
INIT EDITAA RevA
313B
XX-XXX-XXZhouB XXX
03) Power domains
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XXZhouB 07-MAR-1703/10/17THR XX-XXX-XXXXXB
REV DATEMODIF. DES. DATE VER.SCALE 1/1 REV. SHEET
INIT EDITAA RevA
313B
XX-XXX-XXZhouB XXX
03) Power domains
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XXZhouB 07-MAR-1703/10/17THR XX-XXX-XXXXXB
REV DATEMODIF. DES. DATE VER.SCALE 1/1 REV. SHEET
INIT EDITAA RevA
313B
XX-XXX-XXZhouB XXX
03) Power domains
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XXZhouB 07-MAR-1703/10/17THR XX-XXX-XXXXXB
L3
BLM18PG181SN1DR0603
1 2
R162R2R0603
C18100nFC0402
R15
2R2R0603
R170RR0603
L7MLZ1608N100LL0603
L11
BLM18PG181SN1DR0603
1 2
L10
BLM18PG181SN1DR0603
1 2
C410uFC0603
U2
MIC2230-GSYMLMLF3x3mm
AVIN3
EN111
FPWM#7
SW18
OUT112
AGND5
PGND6
OUT21
SW24
PGOOD10
EN22
VIN9
EPAD
13
R249 4.7KR0402
JP5Header 1X2
1 2
R1339KR0402
C610uFC0603
R180RR0603
U1ADMP2160UFD
1
2
67
L4
BLM18PG181SN1DR0603
1 2
R3100KR0402
R25110KR0402
R12220KR0402
JP6Header 1X2
1 2
C1100nFC0402
C10 390pFC0402
U4ADMP2160UFD
1
2
67
C7100nFC0402
L2 LQH43CN2R2M03LL1812
R5 100KR0402
R6 DNPR0402
C310uFC0603
R24820KR0402
+ C170.2F/3.3Vc117x68
R10DNPR0402
R11100KR0402
L14
BLM18PG181SN1DR0603
1 2
C134.7nFC0402
U1BDMP2160UFD
4
5
38
R2503.3KR0402
L1 LQH43CN2R2M03LL1812
L9MLZ1608N100LL0603
C51uFC0603
D2
PMEG6010CEGWXsod123
JP1Header 1X2
1 2
JP4Header 1X2
1 2
C12100nFC0402
L13
BLM18PG181SN1DR0603
1 2
Q1BSS138SOT23_1231
3
2
R14 100R-1%R0402
L6
BLM18PG181SN1DR0603
1 2
R110KR0402
U4BDMP2160UFD
4
5
38
R410KR0402
C91uFC0603
R2100KR0402
D1PMEG6010CEGWXsod123
Q2BSS138SOT23_1231
3
2
C161uFC0603
L8MLZ1608N100L
L0603
R192R2R0603
JPR1Jumper
U5
MIC5366-2.5YMTMLF1x1mm
VIN4
GND2
VOUT1
EN3
EPAD
5
C8100nFC0402
L5
BLM18PG