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TRANSCRIPT
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C C
B B
A A
100-0321312-C1110-0321312-C1120-0321312-C1130-0321312-C1140-0321312-C1150-0321312-C1160-0321312-C1170-0321312-C1180-0321312-C1210-0321312-C1220-0321312-C1320-0321312-C1
Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework
1.NOTES:
Stratix 10 GX SI Development Kit
DESCRIPTIONREV DATE PAGESINITIAL REVISION A RELEASEA 28 Oct 2015 All
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PAGE DESCRIPTION
56
28
PAGE DESCRIPTION
2Title, Notes, Block Diagram, Rev. History1
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78910111213141516171819202122232425
3031
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Copyright (c) 2016, Intel Corporation. All Rights Reserved.
323334353637383940414243444546474849505152535455565758
Power TreeClock Tree, Bank UsageClocksClocksClocksClocks
MAX10 PWR Manager 2MAX10 PWR Manager 1On Board USB BLASTER II, JTAG ChainOn Board USB BLASTER II
LT PWR Manager
System MAX VCFI Flash Memory10/100/1000 Ethernet PHYButtons/Switches/LEDs/LCD
Current Sense ADC/DAC/FAN
I2C Chain/Buffer
SFP+ Interface 0QSFP28 Interface 1QSFP28 Interface 0CFP4 Voltage Translators
SFP+ Interface 1
CFP4 Interface
S10 Banks - 3 I/J/L/KS10 XCVR Banks - 1C/D/E/FS10 XCVR Banks - 1K/L/M/N
S10 Banks - 2 F/L/M/N
S10 XCVR Banks - 4C/D/E/F
S10 Banks - 3 A/B/C
PWR - 12V to 3.3VPWR - POWER INPUTS10 GNDS10 PWR
PWR 12V to VCCT/1.8V/2.4V
S10 XCVR Banks - 4K/L/M/N
PWR VCC 4PWR - VCCERAM VCCH
PWR VCC 1
PWR - VCCR_GXB
PWR VCC 2PWR VCC 3
Decoupling 2Decoupling 1PWR - FMC B/2.5VPWR - FMC A
Fast Discharge and V-Sense
MXP / 2.4mm ConnectorsFMC Port AFMC Port BS10 Banks - CFGS10 Banks 2 A/B/C
Revision History
B 05 Nov 2016C 4 Jan 2017 Refer to Page 53 for change lists
Add two GND layers and exchange two power layers, fix one trace width issueChange part number for J14
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B1 53Monday, April 17, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B1 53Monday, April 17, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B1 53Monday, April 17, 2017
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B2 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B2 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B2 53Thursday, March 09, 2017
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Clock Tree, Bank Usage
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B3 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B3 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B3 53Thursday, March 09, 2017
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Clocks
Place termination at S10
Route as matched pair0.5" Max
0.2" Max 1.8"-14.4"
0.2" Max 0.2" Max
CAD Notes:
Default 100M No Spread
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
CLK_50M_MAX10
CLK_S10TOP_ADJ_NCLK_Trigger_P
S0S1SS0SS1CLK_Trigger_N
CLK_2Jp
CLK_S10TOP_ADJ_P
CLK_2Jn
CLK_50M_MAX5CLK_50M_S10
1.8V
3.3V_STBY
3.3V_STBY
3.3V
3.3V
3.3V
CLK_50M_MAX1011CLK_S10TOP_ADJ_P30 CLK_S10TOP_ADJ_N30
CLK_50M_S1031 CLK_50M_MAX514
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B4 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B4 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B4 53Thursday, March 09, 2017
R13150
R40
R9 33
C1016pF
C70.01uF
C60.01uF
U2
ICS557-03
S01S12SS03
X1/ICLK4X25
OE6
GNDX
D7
SS18
IREF9 CLK1N 10CLK1P 11VDDO
DA12
GNDO
DA13
CLK0N 14CLK0P 15
VDDX
D16
U1
SL18860DC
CLKIN3 CLKOUT1 8CLKOUT2 9
GND 1
CLKOUT3 10VDD2
OE16OE_OSC 4OE27
OE35
C80.1uF
R1249.9
C916pF
R1149.9
R210.0K
C210uF
X3ABM10-25MHz
1
2
3
4
C30.1uF
R51K R7100
C10.1uF
FB1120ohm, 800mA
12
R8100
R10 475
C50.1uF
OPEN
SW1
TDA04H0SB1
12345678
X2
50MHz
VCC 4
GND2 OUT 3EN1
R110.0K
R30
C42.2uF
RP110K
1 2 3 45678
X1
50MHz
VCC 4
GND2 OUT 3EN1
R14150
R6 33
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Clocks
Silicon Labs Oscillatorfactory program@ 706.25MHzADDR - 77h
Silicon Labs Oscillatorfactory program@ 644.53125MHzADDR - 66h
External Clock InputSlew rates > 0.6 V/ns
Default OFF for Si570 sourceOFF: Si570 is sourceON: SMA is source
External Clock InputSlew rates > 0.6 V/ns
Diff clock freq from 10M-945M
Diff clock freq from 10M-945M
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
CLKSEL_706M
OEA_706M
OEB_706M
I2C_2V5_SDAI2C_2V5_SCL
OEA_706MOEB_706M
SMA2_CLKpSMA2_CLKn
CLKSEL_706M
CLKSEL_644M
I2C_2V5_SCLI2C_2V5_SDA
OEB_644M
OEA_644M
OEB_644MOEA_644M
SMA1_CLKpSMA1_CLKn
CLKSEL_644M
CLKSEL_644MCLKSEL_706M
CLK_CFP4_644M_NCLK_CFP4_644M_PCLK_QSFP0_644MB_NCLK_QSFP0_644MB_PCLK_QSFP0_644MT_NCLK_QSFP0_644MT_P
CLK_FMCB_644M_NCLK_FMCB_644M_PCLK_SFP_644M_NCLK_SFP_644M_P
CLK_SMA_706M_NCLK_SMA_706M_PCLK_MXP2_706M_NCLK_MXP2_706M_PCLK_MXP1_706M_NCLK_MXP1_706M_P
CLK_MXP3_706M_NCLK_MXP3_706M_PCLK_FMCA_706M_NCLK_FMCA_706M_P
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
CLK_FMCB_644M_N34 CLK_FMCB_644M_P34CLK_SFP_644M_N34 CLK_SFP_644M_P34CLK_QSFP0_644MT_P33 CLK_QSFP0_644MT_N33CLK_QSFP0_644MB_P33 CLK_QSFP0_644MB_N33CLK_CFP4_644M_N33 CLK_CFP4_644M_P33
I2C_2V5_SDA18 I2C_2V5_SCL18
CLK_FMCA_706M_N36 CLK_FMCA_706M_P36CLK_MXP3_706M_N35 CLK_MXP3_706M_P35CLK_MXP2_706M_N35 CLK_MXP2_706M_P35CLK_MXP1_706M_N35 CLK_MXP1_706M_P35CLK_SMA_706M_N35 CLK_SMA_706M_P35
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B5 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B5 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B5 53Thursday, March 09, 2017
FB3120ohm, 800mA
12
C140.1uF C18
1uF
R221K
C1425 0.1uF
C1417 0.1uF
R171K
C1423 0.1uF
R26DNI
C1429 0.1uF
U4
Si53311
CLKIN1_P14CLKIN1_N15
CLKIN0_P10
OEA12
OEB13
CLK_SEL8
VDD 7
GND 6VREF 17
VDDOB 19VDDOA 18DIVA1
CLK3n 27CLK3p 28
NC19
CLK2n 29CLK2p 30
CLK1n 31CLK1p 32
NC016
CLK0n 4CLK0p 5
EPAD 33
CLK4n 25CLK4p 26CLK5p 21CLK5n 20
CLKIN0_N11
DIVB24
SFOUTA12 SFOUTA03
SFOUTB022SFOUTB123 C1435 0.1uF
R19DNIFB2
120ohm, 800mA12
C1426 0.1uF
U3
Si53311
CLKIN1_P14CLKIN1_N15
CLKIN0_P10
OEA12
OEB13
CLK_SEL8
VDD 7
GND 6VREF 17
VDDOB 19VDDOA 18DIVA1
CLK3n 27CLK3p 28
NC19
CLK2n 29CLK2p 30
CLK1n 31CLK1p 32
NC016
CLK0n 4CLK0p 5
EPAD 33
CLK4n 25CLK4p 26CLK5p 21CLK5n 20
CLKIN0_N11
DIVB24
SFOUTA12 SFOUTA03
SFOUTB022SFOUTB123
C1418 0.1uF
C1424 0.1uF
FB7120ohm, 800mA
12
C190.1uF C1430 0.1uF
C1436 0.1uF
J61
2345
C110.1uF
C171uF
J21
2345
R23
100
C200.1uFJ71
2345
C1419 0.1uF
C231uF
J81
2 3 4 5
R251K
C1431 0.1uF
C251uF
C261uF
C210.1uF
C120.1uF
R241K
R18
100
C1420 0.1uF
R20100
R15100
J31
2345
J41
2 3 4 5
J91
2 3 4 5
C1432 0.1uF
OPEN
S15
mini_dip_2pos
12 34
C130.1uF
C240.1uFY2
Si570
NC1OE2GND3 OUT 4nOUT 5VCC 6
SDA7 SCL 8
C1421 0.1uF
C1427 0.1uF
Y1
Si570
NC1OE2GND3 OUT 4nOUT 5VCC 6
SDA7 SCL 8
J51
2 3 4 5
C1433 0.1uF
C160.1uFC15
1uF
C220.1uF
C1422 0.1uF
R211K
C1428 0.1uF
FB8120ohm, 800mA
12
R161K
C1434 0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ClocksSi5341 Signals
Default LVDS 625 MHz
Default LVDS 625 MHz
Default LVDS 614.4 MHz
Default LVDS 614.4 MHzDefault LVDS 614.4 MHz
Default LVDS 614.4 MHz
Set VDDIO = VDD7-bit I2C Address 74h
Default LVDS 100 MHz
Isolate Si5341 from system I2C bus:Plug Silab CBPro dongle cable into J102Program U5/U6 with Silab ClockBuilder toolsDefault ON position for full chain.OFF = Si5341 ISOLATEDON = FULL CHAIN
Default LVDS 614.4 MHz
Diff clock freq from 10M-750M
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
SI5341_1_XB
SI5341_1_XA
SI5341_1_X
SI5341_1_INTnSI5341_1_LOLn
SI5341_1_OUT9nSI5341_1_OUT9p
SI5341_1_OUT0nSI5341_1_OUT0p
SI5341_1_OUT1nSI5341_1_OUT1p
SI5341_1_OUT4nSI5341_1_OUT4p
SI5341_1_OUT5nSI5341_1_OUT5p
SI5341_1_IN_SEL1SI5341_1_IN_SEL0SI5341_1_ENnSI5341_1_A0SI5341_1_A1I2C_1V8_SCL_Si5341I2C_1V8_SDA_Si5341
SI5341_1_I2C_SEL
SI5341_1_IN_SEL0SI5341_1_IN_SEL1
SI5341_1_A0SI5341_1_A1
SI5341_1_RSTn
SI5341_1_X
SI5341_1_OUT8nSI5341_1_OUT8p
I2C_1V8_SCLI2C_1V8_SDA I2C_1V8_SCL_Si5341I2C_1V8_SDA_Si5341
I2C_1V8_SCL_Si5341I2C_1V8_SDA_Si5341
SI5341_1_OUT6nSI5341_1_OUT6p
1.8V
1.8VSI5341_1_VDDO
1.8V
SI5341_1_VDDA
3.3V
SI5341_1_VDD
1.8V
1.8V
1.8V
SI5341_1_ENn14 SI5341_1_RSTn14
I2C_1V8_SCL14,18,31 I2C_1V8_SDA14,18,31
SI5341_1_INTn14 SI5341_1_LOLn14
CLK_S10BOT_100M_P29 CLK_S10BOT_100M_N29
I2C_1V8_SDA_Si53417 I2C_1V8_SCL_Si53417
CLK_GXBL1E_614MT_P33 CLK_GXBL1E_614MT_N33
CLK_GXBL1E_614MB_P33 CLK_GXBL1E_614MB_N33
CLK_GXBL1L_625M_P34 CLK_GXBL1L_625M_N34
CLK_GXBL1F_625M_P33 CLK_GXBL1F_625M_N33
CLK_GXBL1K_614M_P34 CLK_GXBL1K_614M_N34
REFCLK_CFP4_614M_N19 REFCLK_CFP4_614M_P19
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B6 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B6 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B6 53Thursday, March 09, 2017
R40DNI
C411uF
C321uF
R36DNI
C431uF
R320
C421uF
R31 4.70K
C51 0.1uF
C401uF
Y3 50.00MHz
13
24
C52 0.1uF
R6220
R35DNI
C59 DNI
J101
2 3 4 5
R29 4.70K
C331uF
L1742792780
C391uF
C54 DNI
R30 1.00K C45 0.1uF
C281uF
J111
2 3 4 5
J102
HEADER, 1x3-PIN123
C48 0.1uFR3310.0K
U5
Si5341A-B05805-GM
VDD032VDD146VDD260
VDDA13
SDA_SDIO18SCLK16A1_SDO17A0_CSB19I2C_SEL39OEB11IN_SEL03IN_SEL14RSTB6
IN063IN0_N64IN11IN1_N2IN214IN2_N15FBIN61FBIN_N62
X17XA8XB9X210
ePAD65
VDDO0 22VDDO1 26VDDO2 29VDDO3 33
OUT0 24OUT0B 23
OUT1B 27OUT1 28
OUT2B 30OUT2 31
OUT3 35OUT3B 34
INTRB12 LOLB47 SYNCB5
RSVD
120
OUT4 38OUT4B 37
OUT5 42OUT5B 41
OUT6 45OUT6B 44
OUT7 51OUT7B 50
OUT8 54OUT8B 53
OUT9 59OUT9B 58
FDEC25 FINC48
RSVD
221
RSVD
355
RSVD
456
VDDO4 36VDDO5 40VDDO6 43VDDO7 49VDDO8 52VDDO9 57
C44 0.1uF
C381uF
OPEN
S1
mini_dip_2pos
12 34
C291uF
R27 1.00K
C311uF
R6230R394.70K
L3742792780
C47 0.1uF
R28 1.00K
C49 0.1uF
C351uF
C630.1uF
C55 0.1uF
R3410.0K
R80710.0K
V1
C46 0.1uF
C50 0.1uF
C660.1uF
C53 0.1uF
C361uF
C301uF
R384.70K
R80810.0K
C341uF
C371uF
C57 0.1uF
C271uF
C56 0.1uF
L2742792780
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ClocksSi5341 Signals
Default LVDS 625 MHz
Default LVDS 644.53125 MHzDefault LVDS 644.53125 MHzDefault LVDS 644.53125 MHz
Default LVDS 125 MHz
Default LVDS 625 MHz
Set VDDIO = VDD7-bit I2C Address 76h
Default 1.8V 125 MHz
Default LVDS 644.53125 MHz
Diff clock freq from 10M-750MSE clock freq from 10M-250M
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
SI5341_2_XB
SI5341_2_XA
SI5341_2_X
SI5341_2_INTnSI5341_2_LOLn
SI5341_2_OUT9nSI5341_2_OUT9p
SI5341_2_OUT0nSI5341_2_OUT0p
SI5341_2_OUT4nSI5341_2_OUT4p
SI5341_2_OUT5nSI5341_2_OUT5p
SI5341_2_IN_SEL1SI5341_2_IN_SEL0SI5341_2_ENnSI5341_2_A0SI5341_2_A1SI5341_2_I2C_SEL
SI5341_2_IN_SEL0SI5341_2_IN_SEL1
SI5341_2_A0SI5341_2_A1
SI5341_2_RSTn
SI5341_2_X
SI5341_2_OUT7nSI5341_2_OUT7p
SI5341_2_OUT2nSI5341_2_OUT2p
SI5341_2_OUT3nSI5341_2_OUT3p
SI5341_2_OUT8pSI5341_2_OUT8n
I2C_1V8_SCL_Si5341I2C_1V8_SDA_Si5341
1.8V
1.8VSI5341_2_VDDO
1.8V
SI5341_2_VDDA
3.3V
SI5341_2_VDD
1.8V
1.8V1.8V
CLK_GXBR4M_625M_P36 CLK_GXBR4M_625M_N36
CLK_GXBR4E_644M_N35 CLK_GXBR4E_644M_P35
SI5341_2_ENn14 SI5341_2_RSTn14
I2C_1V8_SDA_Si53416 I2C_1V8_SCL_Si53416
SI5341_2_INTn14 SI5341_2_LOLn14
MAX_OSC_CLK_114 FPGA_OSC_CLK_128
CLK_GXBR4L_644M_N36 CLK_GXBR4L_644M_P36
CLK_S10TOP_125M_P32 CLK_S10TOP_125M_N32
CLK_GXBR4F_644M_N35 CLK_GXBR4F_644M_P35
CLK_GXBR4D_644M_P35 CLK_GXBR4D_644M_N35
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B7 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B7 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B7 53Thursday, March 09, 2017
R534.70K
R4610.0K
U6
Si5341A-B05914-GM
VDD032VDD146VDD260
VDDA13
SDA_SDIO18SCLK16A1_SDO17A0_CSB19I2C_SEL39OEB11IN_SEL03IN_SEL14RSTB6
IN063IN0_N64IN11IN1_N2IN214IN2_N15FBIN61FBIN_N62
X17XA8XB9X210
ePAD65
VDDO0 22VDDO1 26VDDO2 29VDDO3 33
OUT0 24OUT0B 23
OUT1B 27OUT1 28
OUT2B 30OUT2 31
OUT3 35OUT3B 34
INTRB12 LOLB47 SYNCB5
RSVD
120
OUT4 38OUT4B 37
OUT5 42OUT5B 41
OUT6 45OUT6B 44
OUT7 51OUT7B 50
OUT8 54OUT8B 53
OUT9 59OUT9B 58
FDEC25 FINC48
RSVD
221
RSVD
355
RSVD
456
VDDO4 36VDDO5 40VDDO6 43VDDO7 49VDDO8 52VDDO9 57
C681uF
R62420
C811uF
C821uF
R43 4.70K
R4710.0K
C1040.1uF
C831uF
C88 0.1uF
L6742792780
C741uF
V2 C87 0.1uF
R54DNI
C751uF
C85 0.1uF
C701uF
C89 0.1uF
R62520R524.70K R6260
R480
R41 1.00KC84 0.1uF
C761uF
C90 0.1uF
R6270
R42 1.00K
C671uF
C93 0.1uFR50DNI
L5742792780
C822 0.1uF
Y4 50.00MHz
13
24
C91 0.1uFC823 0.1uF
C791uF
C711uF
R44 1.00K
J121
2 3 4 5
C781uF
C95 0.1uF
R45 4.70K
C731uF
J131
2 3 4 5
C96 DNI
C801uF
C94 0.1uFR49DNI
C771uF
L4742792780
C1010.1uF
C92 DNI
C721uF
C691uF
C86 0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
On Board USB BLASTER II 1
USB CLK
JTAG INTERFACE
Put on Bottom Layer
FMC Present
PLACE CLOSE CY7C68013
Route as matched pair on Top layer FPGA PWR
UB2/PWR MGMT INTERFACE
UB2 doesn't drive S10 if FPGA_PWRGD is low
UB2 power recycle FPGA rails
CAD Notes:
CAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
FX2_D_NFX2_D_PVBUS_5V
24M_XTALIN24M_XTALOUT
FX2_RESETn
FX2_SDA MAX_SDA
FX2_FLAGB
FX2_PA2
FX2_SLWRnFX2_SLRDn
FX2_WAKEUPVBUS_5V
USB_T_CLK
FX2_PD2FX2_PD0FX2_PD3
FX2_PD1
USB_MAX_TCKUSB_MAX_TMSUSB_MAX_TDO
EXT_JTAG_TDIEXT_JTAG_TCKEXT_JTAG_TMS
USB_MAX_TDI
FX2_PA0FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7FX2_PD0FX2_PD1FX2_PD2FX2_PD3FX2_PD4FX2_PD5FX2_PD6FX2_PD7
FX2_SLWRnFX2_SLRDnFX2_FLAGCFX2_FLAGBFX2_FLAGAFX2_WAKEUP
FX2_SDAFX2_SCLFX2_RESETn
FX2_SCL
FX2_PB2FX2_PB3FX2_PD5FX2_PD7FX2_PD6FX2_PD4
FX2_FLAGAFX2_FLAGC
MAX_SDA
FX2_PB0
FX2_PB7
USB_MAX_TCKUSB_MAX_TMSUSB_MAX_TDIUSB_MAX_TDO
FAPRSNT_NFBPRSNT_N
BLASTER_DISn
EXT_JTAG_TDI
EXT_JTAG_TDOEXT_JTAG_TCKEXT_JTAG_TMS
FPGA_RECYCLEFPGA_PWRGD
MAX_IO9FATMS
BLASTER_DISn
FATDIFATCKFATDO
EXT_JTAG_TDO
EXT_JTAG_TDIEXT_JTAG_TMSEXT_JTAG_TCK
FATMSFATDIFATCK
FX2_PB1
FX2_PB5
FX2_PB4
FX2_PB6
FX2_PA6FX2_PA7
FX2_PA4
FX2_PA5
FX2_PA3
FX2_PA0
FX2_PA1
MAX_IO2
MAX_IO4MAX_IO0MAX_IO1
MAX_IO7
MAX_IO3
MAX_IO5MAX_IO6
FBTMS
FBTMS
USB_MAX5_CLKUSB_FPGA_CLK USB_T_CLK
1.8V 3.3V_PRE
3.3V_PRE 3.3V_PRE
3.3V_PRE
3.3V_PRE
3.3V_PRE3.3V_PRE
3.3V_PRE
3.3V_PRE
1.8V_PRE
3.3V_PRE
3.3V_PRE
1.8V
FBTMS27
FATDO26FATDI26 FATMS26 FATCK26
FPGA_RECYCLE11 FPGA_PWRGD11,12
USB_MAX5_CLK9,14USB_T_CLK9USB_FPGA_CLK9,30FX2_RESETn9
FAPRSNT_N11,26,32 FBPRSNT_N11,27,30
MAX_IO[9:0]9,10,11
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B8 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B8 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B8 53Tuesday, April 11, 2017
C1090.1uF
C106DNI
C1110.1uF
R7521K
R6610.0K
R75010.0K
J15
TSM-105-01-T-DV-TR
11335577
2 24 46 68 8
99 10 10
C121DNI
R681 10.0K
U8
MAX811
GND1
RESET2VCC 4
MR 3
J14
HDR2X5
246810
13579
C1140.1uF
R72 10.0K
C10712pF
MAX10 10M04SCU169
U97IIO_1B_E5/JTAGEN/DIFFIO_RX_L9PE5IO_1B_G1/TMS/DIFFIO_RX_L11NG1IO_1B_G2/TCK/DIFFIO_RX_L11PG2IO_1B_F5/TDI/DIFFIO_RX_L12NF5IO_1B_F6/TDO/DIFFIO_RX_L12PF6IO_8_B9/DEV_CLRN/DIFFIO_RX_T16NB9IO_8_D8/DEV_OE/DIFFIO_RX_T18PD8IO_8_D7/BOOT_SELD7IO_8_D6/CRC_ERROR/DIFFIO_RX_T22ND6IO_8_C4/NSTATUS/DIFFIO_RX_T24PC4IO_8_C5/CONF_DONE/DIFFIO_RX_T24NC5INPUT_ONLY_8_E7/NCONFIGE7
R590
R6710.0K
C118 DNI
R55 0
R6520.0K
R56100K
R58 2.00K
C119DNI
R678 10.0K
R75310.0KR630
R836DNI
R70 DNI
R838DNI
U9
CY7C68013A_QFN
RDY0 1RDY1 2
XTALIN5
AVCC03
DMINUS9
AGND06
VCC011
GND012
PD7 52
CLKOUT 54
XTALOUT4
AVCC17
DPLUS8
AGND110
IFCLK13
RESERVED14
PD5 50PD4 49
PD6 51
SCL 15SDA 16
PB0 18
GND126GND228GND341
PB1 19
PB3 21PB2 20
VCC117VCC227
PB6 24PB5 23PB4 22
PD3 48PD2 47
PA740PA437PA134
PB7 25
PD1 46
WAKEUP 44
PA639
GND453
VCC443
PA336
CTL1 30CTL0 29
PD0 45
RESET 42
PA538
GND556
VCC555
PA235PA033
CTL2 31VCC332
EXPOSED_PAD 57
R64 10.0K
R620
R691K
R71 1.00K
R75110.0K
R679 10.0K
R73 10.0K
Y5
24.00MHz1 3
24
R6810.0K
C1150.1uF
U11
DNI
VLB2
IO_VL4C1 IO_VL3C2 IO_VL2C3 IO_VL1C4
GND B4
VCC B1
IO_VCC1 A4IO_VCC2 A3IO_VCC3 A2IO_VCC4 A1
ENB3
R680 10.0K
C1120.1uF
CN1CN-USB 1234
5 6
C1170.1uF
C10812pF
R57 2.00KU10
TPD2EUSB30D- 2D+ 1
GND3
C1130.1uF
C1160.1uF
C120DNI
R600
R837DNI
MAX10 10M04SCU169
U97DIO_3_L5/DIFFIO_TX_RX_B1NL5IO_3_M4/DIFFIO_RX_B2NM4IO_3_L4/DIFFIO_TX_RX_B1PL4IO_3_M5/DIFFIO_RX_B2PM5IO_3_K5/DIFFIO_TX_RX_B3NK5IO_3_N4/DIFFIO_RX_B4NN4IO_3_J5/DIFFIO_TX_RX_B3PJ5IO_3_N5/DIFFIO_RX_B4PN5IO_3_N6/DIFFIO_TX_RX_B5NN6IO_3_N7/DIFFIO_RX_B6NN7IO_3_M7/DIFFIO_TX_RX_B5PM7IO_3_N8/DIFFIO_RX_B6PN8IO_3_J6/DIFFIO_TX_RX_B7NJ6IO_3_M8/DIFFIO_RX_B8NM8IO_3_K6/DIFFIO_TX_RX_B7PK6IO_3_M9/DIFFIO_RX_B8PM9IO_3_J7/DIFFIO_TX_RX_B9NJ7IO_3_K7/DIFFIO_TX_RX_B9PK7IO_3_N12N12IO_3_M13/DIFFIO_TX_RX_B10NM13IO_3_N10/DIFFIO_RX_B11NN10IO_3_M12/DIFFIO_TX_RX_B10PM12IO_3_N9/DIFFIO_RX_B11PN9IO_3_M11/DIFFIO_TX_RX_B12NM11IO_3_L11/DIFFIO_TX_RX_B12PL11IO_3_J8/DIFFIO_TX_RX_B14NJ8IO_3_K8/DIFFIO_TX_RX_B14PK8IO_3_M10/DIFFIO_TX_RX_B16NM10IO_3_L10/DIFFIO_TX_RX_B16PL10
R610
C105 0.1uF
MAX10 10M04SCU169
U97CIO_2_M3/PLL_L_CLKOUTN/DIFFIO_RX_L27NM3IO_2_L3/PLL_L_CLKOUTP/DIFFIO_RX_L27PL3
IO_2_J1/DIFFIO_RX_L19NJ1IO_2_J2/DIFFIO_RX_L19PJ2IO_2_M1/DIFFIO_RX_L21NM1IO_2_M2/DIFFIO_RX_L21PM2IO_2_L2L2IO_2_K1/DIFFIO_RX_L28NK1IO_2_K2/DIFFIO_RX_L28PK2
R682 10.0K
C1100.1uF
MAX10 10M04SCU169
U97BIO_1A_D1/DIFFIO_RX_L1ND1IO_1A_C2/DIFFIO_RX_L1PC2IO_1A_E3/DIFFIO_RX_L3NE3IO_1A_E4/DIFFIO_RX_L3PE4IO_1A_C1/DIFFIO_RX_L5NC1IO_1A_B1/DIFFIO_RX_L5PB1IO_1A_F1/DIFFIO_RX_L7NF1IO_1A_E1/DIFFIO_RX_L7PE1
IO_1B_F4/DIFFIO_RX_L14NF4IO_1B_G4/DIFFIO_RX_L14PG4IO_1B_H2/DIFFIO_RX_L16NH2IO_1B_H3/DIFFIO_RX_L16PH3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
On Board USB BLASTER II 2, JTAG ChainUSB Direct To S10
UB2/MAX V INTERFACE
JTAG INTERFACE
PLACE CLOSE MAX 10 PWR PIN
Default bypass two FMC nodesON = Device JTAG BypassOFF = Device JTAG Enable
UB2/PWR MGMT INTERFACE
MAX 10 instant mode has power ramp up requirement
CAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
USB_DATA3
FBJTAG_BYPASSnFAJTAG_BYPASSnM5JTAG_BYPASSnS10JTAG_BYPASSn
FMCA_JTAG_MASTERnFMCB_JTAG_MASTERn
USB_SCLUSB_SDAUSB_FULLUSB_EMPTY
RESn_JTAG_TXJTAG_TX
RESn_SC_RXSC_RX
RESn_SC_TXSC_TX
RESn_JTAG_RXJTAG_RX
USB_T_CLK
M5_JTAG_TDIM5_JTAG_TMSM5_JTAG_TCK
M5_JTAG_TDO
SC_TXSC_RXJTAG_RXJTAG_TX
USB_CFG6USB_CFG5
USB_CFG9USB_CFG10USB_CFG11USB_CFG12USB_CFG13USB_CFG14
USB_CFG7USB_CFG8
USB_CFG4
USB_CFG0USB_CFG1USB_CFG2USB_CFG3
M5JTAG_BYPASSn
FMCB_JTAG_MASTERnFMCA_JTAG_MASTERn
FAJTAG_BYPASSnS10JTAG_BYPASSnFBJTAG_BYPASSn
FBTCKMAX_IO8
FBTDOFBTDI
FBTDIFBTCK
S10_JTAG_TCKUSB_DATA6
S10_JTAG_TDIUSB_SDA
USB_SCL
S10_JTAG_TMS
USB_FULL
S10_JTAG_TDO
USB_EMPTYUSB_OEn
USB_RDn
USB_RESETn
USB_DATA2USB_WRn
USB_DATA0USB_DATA1
USB_DATA5
USB_ADDR1USB_ADDR0
USB_DATA7USB_DATA4
FX2_RESETn
USB_MAX5_CLKUSB_FPGA_CLK
1.8V_PRE
3.3V_PRE
1.8V_PRE
3.3V_PRE
MAX10VCCA
1.8V
2.5V
3.3V_PRE MAX10VCCA
MAX10VCCA
1.8V_PRE
3.3V_PRE
3.3V_PRE
1.8V
1.8V
USB_DATA[7:0]30USB_ADDR[1:0]30USB_FULL30 USB_EMPTY30 USB_SCL30 USB_SDA30USB_RESETn30 USB_OEn30 USB_RDn30 USB_WRn30
USB_CFG[14:0]14
S10_JTAG_TCK28 S10_JTAG_TMS28S10_JTAG_TDI28M5_JTAG_TCK14 M5_JTAG_TMS14M5_JTAG_TDI14FBTDI27FBTCK27
S10_JTAG_TDO28
M5_JTAG_TDO14
FBTDO27
USB_T_CLK8FX2_RESETn8
MAX_IO[9:0]8,10,11
USB_FPGA_CLK8,30
USB_MAX5_CLK8,14
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B9 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B9 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B9 53Tuesday, April 11, 2017
R74 10.0K
R88 DNI
C7730.1uF
MAX10 10M04SCU169
U97GIO_8_C10/DIFFIO_RX_T14PC10IO_8_A8/DIFFIO_RX_T15PA8IO_8_C9/DIFFIO_RX_T14NC9IO_8_A9/DIFFIO_RX_T15NA9IO_8_B10/DIFFIO_RX_T16PB10IO_8_A10/DIFFIO_RX_T17PA10IO_8_A11/DIFFIO_RX_T17NA11IO_8_E8/DIFFIO_RX_T18NE8IO_8_A7/DIFFIO_RX_T19PA7IO_8_A6/DIFFIO_RX_T19NA6IO_8_B6/DIFFIO_RX_T20PB6IO_8_A4/DIFFIO_RX_T21PA4IO_8_B5/DIFFIO_RX_T20NB5IO_8_A3/DIFFIO_RX_T21NA3IO_8_E6/DIFFIO_RX_T22PE6IO_8_B3/DIFFIO_RX_T23PB3IO_8_B4/DIFFIO_RX_T23NB4IO_8_A5/DIFFIO_RX_T25PA5IO_8_A2/DIFFIO_RX_T26PA2IO_8_B2/DIFFIO_RX_T26NB2
C1240.1uF
C7810.1uF
R76 10.0K
R81 10.0K
C1280.1uF
R7541K
R83 10.0K
MAX10 10M04SCU169
U97AVCCIO1A__F2F2VCCIO1B__G3G3VCCIO2__K3K3VCCIO2__J3J3VCCIO3__L8L8VCCIO3__L7L7VCCIO3__L6L6VCCIO5__J11J11VCCIO5__H11H11VCCIO6__G11G11VCCIO6__F11F11VCCIO8__C8C8VCCIO8__C7C7VCCIO8__C6C6
VCCA3__D3D3VCCA1__K4K4VCCA2__D10D10VCCA3__D4D4VCCA4__K9K9
VCC_ONE__H7H7VCC_ONE__G8G8VCC_ONE__G6G6VCC_ONE__F7F7
D1
LED_WE1206
R89 DNI
R93 160
C7790.1uF
C1260.1uF
R75510.0K
C7760.1uF
OPEN
SW3
TDA04H0SB1
12345678
MAX10 10M04SCU169
U97FIO_6_F12/DIFFIO_RX_R18PF12IO_6_E12/DIFFIO_RX_R18NE12IO_6_C13C13IO_6_F8/DIFFIO_RX_R27PF8IO_6_B12/DIFFIO_RX_R28PB12IO_6_E9/DIFFIO_RX_R27NE9IO_6_B11/DIFFIO_RX_R28NB11IO_6_C12/DIFFIO_RX_R29PC12IO_6_B13/DIFFIO_RX_R30PB13IO_6_C11/DIFFIO_RX_R29NC11IO_6_A12/DIFFIO_RX_R30NA12IO_6_E10/DIFFIO_RX_R31PE10IO_6_D9/DIFFIO_RX_R31ND9IO_6_D12/DIFFIO_RX_R33PD12IO_6_D11/DIFFIO_RX_R33ND11
R75 10.0K
C7740.1uFR90 160
R82 1.00k
C1250.1uF
C78610uFC770
10uF
C7820.1uF
C7750.1uF
C1230.1uF
R77 10.0K
R91 160
C1290.1uF
D2
LED_WE1206
C7770.1uF
R8410
C1300.1uF
D3
LED_WE1206
C7800.1uF
R86 1.00k
R8420
MAX10 10M04SCU169
U97EIO_5_K10/DIFFIO_RX_R1PK10IO_5_K11/DIFFIO_RX_R2PK11IO_5_J10/DIFFIO_RX_R1NJ10IO_5_L12/DIFFIO_RX_R2NL12IO_5_K12/DIFFIO_RX_R7PK12IO_5_L13L13IO_5_J12/DIFFIO_RX_R7NJ12IO_5_J9/DIFFIO_RX_R8PJ9IO_5_J13/DIFFIO_RX_R9PJ13IO_5_H10/DIFFIO_RX_R8NH10IO_5_H13/DIFFIO_RX_R9NH13IO_5_H9/DIFFIO_RX_R10PH9IO_5_G13/DIFFIO_RX_R11PG13IO_5_H8/DIFFIO_RX_R10NH8IO_5_G12/DIFFIO_RX_R11NG12
C1270.1uF
R84 1.00kD4
LED_WE1206
R79 1.00k
C1220.1uF
R85 1.00k
C78710uF
MAX10 10M04SCU169
U97HIO_2_G5/CLK0N/DIFFIO_RX_L18NG5IO_2_H6/CLK0P/DIFFIO_RX_L18PH6IO_2_H5/CLK1N/DIFFIO_RX_L20NH5IO_2_H4/CLK1P/DIFFIO_RX_L20PH4IO_2_N2/DPCLK0/DIFFIO_RX_L22NN2IO_2_N3/DPCLK1/DIFFIO_RX_L22PN3IO_6_G9/CLK2P/DIFFIO_RX_R14PG9IO_6_G10/CLK2N/DIFFIO_RX_R14NG10IO_6_F13/CLK3P/DIFFIO_RX_R16PF13IO_6_E13/CLK3N/DIFFIO_RX_R16NE13IO_6_F9/DPCLK3/DIFFIO_RX_R26PF9IO_6_F10/DPCLK2/DIFFIO_RX_R26NF10
IO_1B_H1/VREFB1N0H1IO_2_L1/VREFB2N0L1IO_3_N11/VREFB3N0N11IO_5_K13/VREFB5N0K13IO_6_D13/VREFB6N0D13IO_8_B7/VREFB8N0B7
R92 160
C7780.1uF
MAX10 10M04SCU169
U97JGND__A1A1GND__A13A13GND__B8B8GND__C3C3GND__D2D2GND__D5D5GND__E11E11GND__E2E2GND__F3F3GND__G7G7GND__H12H12GND__J4J4GND__L9L9GND__M6M6GND__N1N1GND__N13N13
C7690.1uF
R87 1.00k
C7710.1uF
R78 10.0K
R80 10.0K
L22
BLM15AG221SN1300mA
C7720.1uF
C1310.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Voltage Sense Input
I2C chain
MAX 10 PWR Manager 1
DAC CONTROL
PWR GOOD
UB2/PWR MGMT INTERFACE
SPI/I2C to ADC/DACSlave Address 5E
PWR1: VCCPWR2: VCCERAMPWR3: VCCRLPWR4: VCCRRPWR5: VCCTPWR6: VCCHPWR7: 1.8VPWR8: 12VPWR9: 12V_IN
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
PWR1_VSENSE_GND
PWR3_VSENSE_GNDPWR4_VSENSE_GND
PWR8_VSENSE_GND
PWR5_VSENSE_GND
PWR2_VSENSE_GND
PWR6_VSENSE_GNDPWR7_VSENSE_GND
PWR7_VSENSE
PWR2_VSENSEPWR3_VSENSEPWR4_VSENSEPWR5_VSENSEPWR6_VSENSE
PWR8_VSENSE
PWR1_VSENSE
MAX_IO0
FAPG_M2CFBPG_M2C
I2C_3V3_SCLI2C_3V3_SDA
SENSE_SDISENSE_SDOSENSE_SCK
SENSE_CS0n
DAC_SCLDAC_SDA
DAC_LDACnDAC_TWOC
FMCB_VADJ_PWRGDFMCA_VADJ_PWRGDFAPG_C2MFBPG_C2M
3V3_PWRGD
MAX_IO8
PWR2_PWRGD
PWR5_PWRGDPWR4_PWRGDPWR3_PWRGD
PWR6_PWRGDPWR7_PWRGDPWR8_PWRGD
PWR9_VSENSE
PWR9_VSENSE_GND
MAX_IO1MAX_IO2MAX_IO3MAX_IO4MAX_IO5MAX_IO6MAX_IO7
EXT_VREF
EXT_VREF
2V5_PWRGD
3.3V_STBY
3.3V_STBY
MAX10_VCCA
MAX10_VCCIO1A
3.3V_STBY MAX10_VCCA
3.3V_STBY MAX10_VCCIO1A
A_GND
A_GND
3.3V_STBY
A_GND
A_GND
3.3V_STBY
A_GNDA_GND
3.3V_STBY
SENSE_SDO13 SENSE_CS0n13 SENSE_SDI13 SENSE_SCK13 DAC_SCL13 DAC_SDA13
MAX_IO[9:0]8,9,11
PWR2_PWRGD46 PWR3_PWRGD47 PWR4_PWRGD47 PWR5_PWRGD41 PWR6_PWRGD46 PWR7_PWRGD41 PWR8_PWRGD39 3V3_PWRGD40 2V5_PWRGD49FAPG_M2C26 FBPG_M2C27
FMCA_VADJ_PWRGD48 FMCB_VADJ_PWRGD49
FAPG_C2M26 FBPG_C2M27
PWR1_VSENSE12,42,52 PWR2_VSENSE12,46,52 PWR3_VSENSE12,47,52 PWR4_VSENSE12,47,52 PWR5_VSENSE12,41,52 PWR6_VSENSE12,46,52 PWR7_VSENSE12,52 PWR8_VSENSE12,39 PWR9_VSENSE39
PWR2_VSENSE_GND12,46,52 PWR1_VSENSE_GND12,42,52
PWR4_VSENSE_GND12,47,52 PWR3_VSENSE_GND12,47,52PWR5_VSENSE_GND12,41,52PWR7_VSENSE_GND12,52 PWR6_VSENSE_GND12,46,52PWR8_VSENSE_GND12,39 PWR9_VSENSE_GND39
DAC_LDACn13 DAC_TWOC13
I2C_3V3_SCL12,13,18 I2C_3V3_SDA12,13,18
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B10 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B10 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B10 53Tuesday, April 11, 2017
FB9220ohm, 2.0A
1 2
C137 1pF
V10RSNS 1SNS2
C133 1pF
R5414.70K
C1420.1uF
R94 10
V9RSNS 1SNS2
L7
BLM15AG221SN1300mA
V7RSNS 1SNS2
MAX10 10M16SA U169
U98DIO_3_L5/DIFFIO_TX_RX_B1NL5IO_3_M4/DIFFIO_RX_B2NM4IO_3_L4/DIFFIO_TX_RX_B1PL4IO_3_M5/DIFFIO_RX_B2PM5IO_3_K5/DIFFIO_TX_RX_B3NK5IO_3_N4/DIFFIO_RX_B4NN4IO_3_J5/DIFFIO_TX_RX_B3PJ5IO_3_N5/DIFFIO_RX_B4PN5IO_3_N6/DIFFIO_TX_RX_B5NN6IO_3_N7/DIFFIO_RX_B6NN7IO_3_M7/DIFFIO_TX_RX_B5PM7IO_3_N8/DIFFIO_RX_B6PN8IO_3_J6/DIFFIO_TX_RX_B13NJ6IO_3_M8/DIFFIO_RX_B14NM8IO_3_K6/DIFFIO_TX_RX_B13PK6IO_3_M9/DIFFIO_RX_B14PM9IO_3_J7/DIFFIO_TX_RX_B15NJ7IO_3_K7/DIFFIO_TX_RX_B15PK7IO_3_N12N12IO_3_M13/DIFFIO_TX_RX_B16NM13IO_3_N10/DIFFIO_RX_B17NN10IO_3_M12/DIFFIO_TX_RX_B16PM12IO_3_N9/DIFFIO_RX_B17PN9IO_3_M10/DIFFIO_TX_RX_B22NM10IO_3_L10/DIFFIO_TX_RX_B22PL10
C7410.1uF
C7350.1uF
C7340.1uF
C135 1pF
V5RSNS 1SNS2
R97 10
R95 DNI
C140 1pF
C132 1pF
MAX10 10M16SA U169
U98AVCCIO1A__F2F2VCCIO1B__G3G3VCCIO2__K3K3VCCIO2__J3J3VCCIO3__L8L8VCCIO3__L7L7VCCIO3__L6L6VCCIO5__J11J11VCCIO5__H11H11VCCIO6__G11G11VCCIO6__F11F11VCCIO8__C8C8VCCIO8__C7C7VCCIO8__C6C6VCCA1__K4K4VCCA2__D10D10VCCA3__D4D4VCCA4__K9K9
VCC_ONE__H7H7VCC_ONE__G8G8VCC_ONE__G6G6VCC_ONE__F7F7
C7380.1uF
V3RSNS 1SNS2
C7360.1uF
C7330.1uF
R98 10
MAX10 10M16SA U169
U98EIO_5_K10/RUP/DIFFIO_RX_R1PK10IO_5_J10/RDN/DIFFIO_RX_R1NJ10
IO_5_K11/DIFFIO_RX_R2PK11IO_5_L12/DIFFIO_RX_R2NL12IO_5_K12/DIFFIO_RX_R11PK12IO_5_L13L13IO_5_J12/DIFFIO_RX_R11NJ12IO_5_J9/DIFFIO_RX_R12PJ9IO_5_J13/DIFFIO_RX_R13PJ13IO_5_H10/DIFFIO_RX_R12NH10IO_5_H13/DIFFIO_RX_R13NH13IO_5_H9/DIFFIO_RX_R14PH9IO_5_G13/DIFFIO_RX_R15PG13IO_5_H8/DIFFIO_RX_R14NH8IO_5_G12/DIFFIO_RX_R15NG12
U105
DNI
VIN1 VOUT 2
GND3 C1459DNI
C136 1pF
C7370.1uF
R59310.0K
R6754.70K
R590100K
MAX10 10M16SA U169
U98FIO_6_F12/DIFFIO_RX_R22PF12IO_6_E12/DIFFIO_RX_R22NE12IO_6_C13C13IO_6_F8/DIFFIO_RX_R31PF8IO_6_B12/DIFFIO_RX_R32PB12IO_6_E9/DIFFIO_RX_R31NE9IO_6_B11/DIFFIO_RX_R32NB11IO_6_C12/DIFFIO_RX_R33PC12IO_6_B13/DIFFIO_RX_R34PB13IO_6_C11/DIFFIO_RX_R33NC11IO_6_A12/DIFFIO_RX_R34NA12IO_6_E10/DIFFIO_RX_R35PE10IO_6_D9/DIFFIO_RX_R35ND9IO_6_D12/DIFFIO_RX_R37PD12IO_6_D11/DIFFIO_RX_R37ND11
R99 10
C1470.1uF
C7390.1uF
R4584.70K
C1440.1uF
C14110uF
MAX10 10M16SA U169
U98BIO_1A_D1/ADC1IN1/DIFFIO_RX_L1ND1IO_1A_C2/ADC1IN2/DIFFIO_RX_L1PC2IO_1A_E3/ADC1IN3/DIFFIO_RX_L3NE3IO_1A_E4/ADC1IN4/DIFFIO_RX_L3PE4IO_1A_C1/ADC1IN5/DIFFIO_RX_L5NC1IO_1A_B1/ADC1IN6/DIFFIO_RX_L5PB1IO_1A_F1/ADC1IN7/DIFFIO_RX_L7NF1IO_1A_E1/ADC1IN8/DIFFIO_RX_L7PE1
IO_1B_F4/DIFFIO_RX_L14NF4IO_1B_G4/DIFFIO_RX_L14PG4IO_1B_H2/DIFFIO_RX_L16NH2IO_1B_H3/DIFFIO_RX_L16PH3
FB10220ohm, 2.0A
1 2
V11RSNS 1SNS2
R96 10
R100 10
C7320.1uF
R5294.70K
C14310uF
C134 1pF
R103 10
R566100K
R5234.70K
V8RSNS 1SNS2
C7310.1uF
V6RSNS 1SNS2
R5364.70K
R101 10
MAX10 10M16SA U169
U98KGND__A1A1GND__A13A13GND__B8B8GND__C3C3GND__D5D5GND__E11E11GND__F3F3GND__G7G7GND__H12H12GND__J4J4GND__L9L9GND__M6M6GND__N1N1GND__N13N13
MAX10 10M16SA U169
U98JREFGND__E2E2ADC_VREF__D3D3ANAIN1__D2D2
C1460.1uF
R102 10
C7420.1uF
C138 1pF
C7400.1uF
R40810.0K
C1450.1uF
V108RSNS 1SNS2
C74310uF
MAX10 10M16SA U169
U98CIO_2_M3/PLL_L_CLKOUTN/DIFFIO_RX_L31NM3IO_2_L3/PLL_L_CLKOUTP/DIFFIO_RX_L31PL3
IO_2_J1/DIFFIO_RX_L21NJ1IO_2_J2/DIFFIO_RX_L21PJ2IO_2_M1/DIFFIO_RX_L23NM1IO_2_M2/DIFFIO_RX_L23PM2IO_2_L2L2IO_2_K1/DIFFIO_RX_L32NK1IO_2_K2/DIFFIO_RX_L32PK2
C139 1pF
C1460DNI
R4574.70K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAX10 PWR Manager 2
PWR ENABLE
Put on Bottom LayerNot open for customer
FMC Present
ADC clock
Reset FPGA by nCONFIGas power down start
CAD Notes:
Default on-board powerON: External PowerOFF: On-board Power
Default on-board powerON: External PowerOFF: On-board Power
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
ENPWR7
ENPWR1ENPWR2ENPWR3ENPWR4ENPWR5ENPWR6ENPWR8
PWR_MAX10_TDI
PWR_MAX10_TCKPWR_MAX10_TMSPWR_MAX10_TDO
START
PWR_MAX10_TDIPWR_MAX10_TCKPWR_MAX10_TMS
PWR_MAX10_TDO
PWR_DISABLEn
PWR_MGMT_SEL
PWR_MGMT_SEL
MAX10_BOOTSEL
FBPRSNT_N
FAPRSNT_N
CLK_50M_MAX10
ENVCC_LTENPWR1
ENVCCERAM_LT
ENVCCRL_GXB_LT
ENVCCRR_GXB_LT
ENPWR2
ENPWR3
ENPWR4
ENPWR7
ENPWR5
ENPWR6
ENPWR8
ENVCCT_GXB_LT
ENVCCH_GXB_LT
EN12V_LT
ERR_LED_N
ENVCC_LTENPWR1 EN_VCCENPWR2ENVCCERAM_LT EN_VCCERAMENPWR3ENVCCRL_GXB_LT EN_VCCRL_GXBENPWR4ENVCCRR_GXB_LT EN_VCCRR_GXB
ENPWR5ENVCCT_GXB_LT EN_VCCT_GXBENPWR6ENVCCH_GXB_LT EN_VCCH_GXBENPWR7
EN12V_LTENPWR8 EN_12V
FPGA_RECYCLEFPGA_PWRGD
PWR_MGMT_SEL
FAPRSNT_NFBPRSNT_N
ERR_LED_NMAX10_DIPSWITCH
MAX_IO9
FPGA_nCONFIG
EN_12V
EN_VCC
EN_VCCRR_GXBEN_VCCERAMEN_VCCRL_GXB
EN_VCCT_GXBEN_VCCH_GXB
ENPWR7
ENPWR1ENPWR2ENPWR3ENPWR4ENPWR5ENPWR6ENPWR8
MAX10_USERMD
EN_1V8_LT EN_1V8
EN_3V3_LT
MAX10_USERMD
EN_VCCIO
EN_3V3
EN2V5
EN3V3
ENVCCIO_LT
EN3V3
PWR_DISABLEn
EN2V5
ENVCCIO_LT
EN_1V8_LT EN_1V8
EN_VCCIOEN2V5EN3V3EN_3V3_LT EN_3V3
EN2V5EN3V3PWR_MGMT_SEL
LTM4677_GPIO1
3.3V_STBY3.3V_STBY
3.3V_STBY
3.3V_STBY
3.3V_STBY
3.3V_STBY
3.3V_STBY
3.3V_STBY
3.3V_STBY
3.3V_STBY
3.3V_STBY
3.3V_STBY
CLK_50M_MAX104
FAPRSNT_N8,26,32 FBPRSNT_N8,27,30
FPGA_RECYCLE8 START12,39
ENVCC_LT12 ENVCCERAM_LT12 ENVCCRL_GXB_LT12 ENVCCRR_GXB_LT12 ENVCCT_GXB_LT12 ENVCCH_GXB_LT12 ENVCCIO_LT12 EN12V_LT12 EN_1V8_LT12 EN_3V3_LT12
EN_VCC42,52 EN_VCCERAM46,52 EN_VCCRL_GXB47,52 EN_VCCRR_GXB47,52 EN_VCCT_GXB41,52 EN_VCCH_GXB46,48,52 EN_VCCIO48,49,52 EN_12V39 EN_1V841 EN_3V340
MAX10_DIPSWITCH18 MAX10_BOOTSEL18PWR_MGMT_SEL12,18
LTM4677_GPIO142
MAX_IO[9:0]8,9,10FPGA_PWRGD8,12FPGA_nCONFIG14,28
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B11 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B11 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B11 53Tuesday, April 11, 2017
R784 49.9
D5
LED_WE1206
U13
IDTQS3VH257PART_NUMBER = QS3VH257PAGManufacturer = IDT
I0A2
I0B5I1A3
I0C11I1B6
I1C10
I0D14
I1D13
YA 4
YB 7
YC 9
YD 12
S 1
E 15GND8
VCC16
C14570.1uF
R7610
R785 49.9
R658DNI
J16
TSM-105-01-T-DV-TR
11335577
2 24 46 68 8
99 10 10
U103
IDTQS3861
NC1
A02A13A24A35A46A57A68A79A810A911
GND 12BE23
VCC 24
B0 22B1 21B2 20B3 19B4 18B5 17B6 16B7 15B8 14B9 13
MAX10 10M16SA U169
U98IIO_1B_E5/JTAGENE5IO_1B_G1/TMS/DIFFIO_RX_L11NG1IO_1B_G2/TCK/DIFFIO_RX_L11PG2IO_1B_F5/TDI/DIFFIO_RX_L12NF5IO_1B_F6/TDO/DIFFIO_RX_L12PF6IO_8_B9/DEV_CLRN/DIFFIO_RX_T28NB9IO_8_D8/DEV_OE/DIFFIO_RX_T30PD8IO_8_D7/CONFIG_SELD7INPUT_ONLY_8_E7/NCONFIGE7IO_8_D6/CRC_ERROR/DIFFIO_RX_T34ND6IO_8_C4/NSTATUS/DIFFIO_RX_T36PC4IO_8_C5/CONF_DONE/DIFFIO_RX_T36NC5
R796DNI
R786 49.9
R63349.9
R650DNI
OPEN
S14
mini_dip_2pos
12 34
U14
IDTQS3VH257PART_NUMBER = QS3VH257PAGManufacturer = IDT
I0A2
I0B5I1A3
I0C11I1B6
I1C10
I0D14
I1D13
YA 4
YB 7
YC 9
YD 12
S 1
E 15GND8
VCC16
R797DNI
R646DNIR787 49.9
R659DNI
R652DNI
C1502.2uF
C14582.2uF
R106 10.0K
MAX10 10M16SA U169
U98GIO_8_A8/DIFFIO_RX_T27PA8IO_8_A9/DIFFIO_RX_T27NA9IO_8_B10/DIFFIO_RX_T28PB10IO_8_A10/DIFFIO_RX_T29PA10IO_8_A11/DIFFIO_RX_T29NA11IO_8_E8/DIFFIO_RX_T30NE8IO_8_A7/DIFFIO_RX_T31PA7IO_8_A6/DIFFIO_RX_T31NA6IO_8_B6/DIFFIO_RX_T32PB6IO_8_A4/DIFFIO_RX_T33PA4IO_8_B5/DIFFIO_RX_T32NB5IO_8_A3/DIFFIO_RX_T33NA3IO_8_E6/DIFFIO_RX_T34PE6IO_8_B3/DIFFIO_RX_T35PB3IO_8_B4/DIFFIO_RX_T35NB4IO_8_A5A5IO_8_A2/DIFFIO_RX_T38PA2IO_8_B2/DIFFIO_RX_T38NB2
R798DNI
R647DNI
R651DNI
R11310.0K
R788 49.9
R653DNI
C1522.2uF
D6
LED_WE1206
R63049.9
C1510.1uF
R799DNI
R110 160R112 1.00K
R789 49.9
RP31K
1 2 3 45678
R63449.9
R114 160
R790 49.9
R63149.9
R105 10.0K
R654DNI
U104
IDTQS3VH257PART_NUMBER = QS3VH257PAGManufacturer = IDT
I0A2
I0B5I1A3
I0C11I1B6
I1C10
I0D14
I1D13
YA 4
YB 7
YC 9
YD 12
S 1
E 15GND8
VCC16
R63549.9
R111 1.00K
R11510.0K
R476DNI
C1530.1uF
R644DNI
R107 10.0K
R63249.9
R655DNI
R648DNI
D36Amber_LED
R800 49.9
R7911.00K
R8021.00K
R643 160
R801 49.9
R645DNI
R649DNI
R8031.00K
OPEN
SW9
TDA04H0SB11234 5678
RP21K
1 2 3 45678
R656DNI
MAX10 10M16SA U169
U98HIO_2_G5/CLK0N/DIFFIO_RX_L20NG5IO_2_H6/CLK0P/DIFFIO_RX_L20PH6IO_2_H5/CLK1N/DIFFIO_RX_L22NH5IO_2_H4/CLK1P/DIFFIO_RX_L22PH4IO_2_N2/DPCLK0/DIFFIO_RX_L24NN2IO_2_N3/DPCLK1/DIFFIO_RX_L24PN3IO_3_M11/CLK6N/DIFFIO_TX_RX_B18NM11IO_3_L11/CLK6P/DIFFIO_TX_RX_B18PL11IO_3_J8/CLK7N/DIFFIO_TX_RX_B20NJ8IO_3_K8/CLK7P/DIFFIO_TX_RX_B20PK8IO_6_G9/CLK2P/DIFFIO_RX_R18PG9IO_6_G10/CLK2N/DIFFIO_RX_R18NG10IO_6_F13/CLK3P/DIFFIO_RX_R20PF13IO_6_E13/CLK3N/DIFFIO_RX_R20NE13IO_6_F9/DPCLK3/DIFFIO_RX_R30PF9IO_6_F10/DPCLK2/DIFFIO_RX_R30NF10IO_8_C10/CLK5P/DIFFIO_RX_T26PC10IO_8_C9/CLK5N/DIFFIO_RX_T26NC9
IO_1B_H1/VREFB1N0H1IO_2_L1/VREFB2N0L1IO_3_N11/VREFB3N0N11IO_5_K13/VREFB5N0K13IO_6_D13/VREFB6N0D13IO_8_B7/VREFB8N0B7
C14550.1uF
R783 49.9
R657DNIR108 10.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LT PWR Manager
LT I2C Connector
I2C chain
Isolate LTM2987 from I2C bus:Plug LT DC1613A dongle plugged into J17Use LTpowerplay toolsDefault OFF position for LT dongle supportOFF = LTM2987 ISOLATEDON = FULL CHAIN
Address SelectPM1 = 7'h5C Address SelectPM2 = 7'h5D
PWR MGMT INTERFACE
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
PM_PWRGD is not tri-state as reset
PWR8_VSENSEPWR8_VSENSE_GND
PM_CNTL1
PM_SHARE_CLK
EN12V_LT
PM_PWRGD
PM_CNTL1
PM_SHARE_CLK
PM_ALERTB
PWR1_VSENSEPWR1_VSENSE_GND
ENVCC_LT
VCCRL_GXB_SENSE_NVCCRL_GXB_SENSE_P
VCCRR_GXB_SENSE_NVCCRR_GXB_SENSE_P
VCCT_GXB_SENSE_NVCCT_GXB_SENSE_P
VCCH_GXB_SENSE_NVCCH_GXB_SENSE_P
VCCERAM_SENSE_NVCCERAM_SENSE_P
ENVCCRL_GXB_LT
PWR3_VSENSEPWR3_VSENSE_GND
PM_CNTL1
PM_SHARE_CLK
PM_ALERTBSTARTLT_SCLLT_SDA
VCCRL_DACOUT
PM_ALERTB
ENVCCRR_GXB_LT
PWR4_VSENSEPWR4_VSENSE_GNDVCCRR_DACOUT
ENVCCT_GXB_LT
PWR5_VSENSEPWR5_VSENSE_GNDVCCT_DACOUT
LT_SCLLT_SDA
START
PM_FAULTBPM_RESETBPM_PWRGD
ENVCCERAM_LT
EN_1V8_LT
I2C_3V3_SCLI2C_3V3_SDA
PM_RESETBPM_FAULTB
PWR6_VSENSEPWR6_VSENSE_GND
ENVCCH_GXB_LTVCCH_DACOUT
PWR2_VSENSEPWR2_VSENSE_GNDVCCERAM_DACOUT
LT_SCLLT_SDA
PWR7_VSENSE_GNDPWR7_VSENSE1V8_DACOUT
LT_SCLLT_SDA
ENVCCRL_GXB_LT
EN12V_LT
ENVCCT_GXB_LTENVCCRR_GXB_LTENVCC_LTENVCCH_GXB_LTENVCCERAM_LTEN_1V8_LT
PWR_MGMT_SEL PM_RESETB
PM_PWRGDFPGA_PWRGD
ENVCCIO_LT
2V5_VSENSE2V5_VSENSE_GND
ENVCCIO_LTEN_3V3_LT
S10_1V8_SENSE_NS10_1V8_SENSE_P
EN_3V3_LT
3V3_VSENSE3V3_VSENSE_GND
PM0_VDD33
12V_IN12V_IN
PM1_VDD33
PM0_VDD33
PM0_VDD33 PM1_VDD33
GND_VCCRL
GND_VCCRR
GND_4620
GND_VCCH
GND_VCCERAM
GND_4620
PM0_VDD33
VCCERAM_DACOUT13,46
I2C_3V3_SDA10,13,18
PWR1_VSENSE10,42,52 PWR1_VSENSE_GND10,42,52
PWR2_VSENSE10,46,52 PWR2_VSENSE_GND10,46,52 VCCERAM_SENSE_N13,46 VCCERAM_SENSE_P13,46PWR3_VSENSE10,47,52 PWR3_VSENSE_GND10,47,52 VCCRL_GXB_SENSE_N13,47 VCCRL_GXB_SENSE_P13,47PWR4_VSENSE10,47,52 PWR4_VSENSE_GND10,47,52 VCCRR_GXB_SENSE_N13,47 VCCRR_GXB_SENSE_P13,47PWR5_VSENSE10,41,52 PWR5_VSENSE_GND10,41,52 VCCT_GXB_SENSE_N13,41 VCCT_GXB_SENSE_P13,41
PWR6_VSENSE10,46,52 PWR6_VSENSE_GND10,46,52 VCCH_GXB_SENSE_N13,46 VCCH_GXB_SENSE_P13,46PWR7_VSENSE10,52 PWR7_VSENSE_GND10,52
PWR8_VSENSE_GND10,39 2V5_VSENSE49 2V5_VSENSE_GND49 3V3_VSENSE40,52 3V3_VSENSE_GND40,52
START11,39
PWR_MGMT_SEL11,18 I2C_3V3_SCL10,13,18LT_SCL18,42PM_ALERTB42
VCCRL_DACOUT13,47 VCCRR_DACOUT13,47 VCCT_DACOUT13,41 VCCH_DACOUT13,46 1V8_DACOUT13,41
EN_1V8_LT11 EN_3V3_LT11ENVCC_LT11 ENVCCERAM_LT11 ENVCCRL_GXB_LT11 ENVCCRR_GXB_LT11 ENVCCT_GXB_LT11 ENVCCH_GXB_LT11 ENVCCIO_LT11 EN12V_LT11
FPGA_PWRGD8,11
LT_SDA18,42
PWR8_VSENSE10,39
S10_1V8_SENSE_N13,48 S10_1V8_SENSE_P13,48
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B12 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B12 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B12 53Thursday, March 09, 2017
C1560.1uF
C1580.1uF
RP510K
1 2 3 45678
R793 DNI
R1205.49K
J17
2x6HDR
11 2 233 4 455 6 677 8 899 10 10
12 121111
PM0 PM1
U15
LTM2987CY
U0_VSENSEP0F7U0_VSENSEM0F6U0_VDACP0E7U0_VDACM0E6U0_VOUT_EN0D7
U0_VSENSEP1F12U0_VSENSEM1F11U0_VDACP1F10U0_VDACM1F9U0_VOUT_EN1F8
U0_VSENSEP2E12U0_VSENSEM2E11U0_VDACP2E10U0_VDACM2E9U0_VOUT_EN2E8
U0_VSENSEP3D12U0_VSENSEM3D11U0_VDACP3D10U0_VDACM3D9U0_VOUT_EN3D8
U0_VSENSEP4C12U0_VSENSEM4C11U0_VDACP4C10U0_VDACM4C9U0_VOUT_EN4C8
U0_VSENSEP5B12U0_VSENSEM5B11U0_VDACP5B10U0_VDACM5B9U0_VOUT_EN5B8
U0_VSENSEP6A12U0_VSENSEM6A11U0_VDACP6A10U0_VDACM6A9U0_VOUT_EN6A8
U0_VSENSEP7A7U0_VSENSEM7A6U0_VDACP7B7U0_VDACM7B6U0_VOUT_EN7C7
U0_VPWRB5U0_VIN_SNSA5U0_VIN_ENE5U0_DNCC5
U0_AVDD33A4U0_DVDD33A3U0_VDD25A2U0_WPA1U0_PWRGDB1U0_SHARE_CLKB2U0_WDI/RESETBB4U0_FAULTB00C3U0_FAULTB01D3U0_FAULTB10C4U0_FAULTB11D4U0_SDAC1U0_SCLD1U0_ALERTBE2U0_CNTRL0E1U0_CNTRL1F1U0_ASEL0F3U0_ASEL1F2U0_REFPF5U0_REFMF4
U0_VPUB3U0_PU1E3U0_PU2D2U0_PU3C2U0_PU4E4
U0_GND1C6U0_GND2D6U0_GND3D5
U1_VSENSEP0 M7U1_VSENSEM0 M6
U1_VDACP0 L7U1_VDACM0 L6
U1_VOUT_EN0 K7
U1_VSENSEP1 M12U1_VSENSEM1 M11
U1_VDACP1 M10U1_VDACM1 M9
U1_VOUT_EN1 M8
U1_VSENSEP2 L12U1_VSENSEM2 L11
U1_VDACP2 L10U1_VDACM2 L9
U1_VOUT_EN2 L8
U1_VSENSEP3 K12U1_VSENSEM3 K11
U1_VDACP3 K10U1_VDACM3 K9
U1_VOUT_EN3 K8
U1_VSENSEP4 J12U1_VSENSEM4 J11
U1_VDACP4 J10U1_VDACM4 J9
U1_VOUT_EN4 J8
U1_VSENSEP5 H12U1_VSENSEM5 H11
U1_VDACP5 H10U1_VDACM5 H9
U1_VOUT_EN5 H8
U1_VSENSEP6 G12U1_VSENSEM6 G11
U1_VDACP6 G10U1_VDACM6 G9
U1_VOUT_EN6 G8
U1_VSENSEP7 G7U1_VSENSEM7 G6
U1_VDACP7 H7U1_VDACM7 H6
U1_VOUT_EN7 J7
U1_VPWR H5U1_VIN_SNS G5
U1_VIN_EN L5U1_DNC J5
U1_AVDD33 G4U1_DVDD33 G3
U1_VDD25 G2U1_WP G1
U1_PWRGD H1U1_SHARE_CLK H2U1_WDI/RESETB H4
U1_FAULTB00 J3U1_FAULTB01 K3U1_FAULTB10 J4U1_FAULTB11 K4
U1_SDA J1U1_SCL K1
U1_ALERTB L2U1_CNTRL0 L1U1_CNTRL1 M1
U1_ASEL0 M3U1_ASEL1 M2U1_REFP M5U1_REFM M4
U1_VPU H3U1_PU1 L3U1_PU2 K2U1_PU3 J2U1_PU4 L4
U1_GND1 J6U1_GND2 K6U1_GND3 K5
OPEN
SW2
mini_dip_2pos
12 34
RP610K
1 2 3 45678
R80410.0K
R639 0
C1570.1uF
R84510.0K
C1590.1uF
R84610.0K
C1540.1uF C155
0.1uF
R80510.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Current Sense ADC/DAC/FAN
FAN
1. Put 0.1uF Cap close to VREFIN pin.2. Everything related to this DAC should be connected to analog ground.3. Thermal pad should be connected to GND
DAC Interface
Current Sense
FAN Speed set, default ONSW8 2-7 OFF: FAN AUTOSW8 2-7 ON: FAN ALWAYS ON
I2C Address: 24
CAD Notes:
Note: TEMPDIODE instructions - route as diff pair - use GND guard traces - trace width = 10mils - trace gap = 10mils - trace length < 8inches
SLAVE ADDR = 0011000b = 18h
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
SENSE5_SCK
SENSE5_SCK
SENSE5_CS0nSENSE5_SDO
SENSE5_SDO
SENSE5_CS0n
SENSE5_SDI
SENSE5_SDI
FAN_ON
OVERTEMPDAC_CLRn
DAC_RSTSEL
VCCERAM_SENSE_NVCCERAM_SENSE_P
VCCRL_GXB_SENSE_N
VCCRR_GXB_SENSE_N
VCCRL_GXB_SENSE_P
VCCRR_GXB_SENSE_P
VCCT_GXB_SENSE_N
VCCH_GXB_SENSE_N
VCCT_GXB_SENSE_P
VCCH_GXB_SENSE_P
S10_1V8_SENSE_NS10_1V8_SENSE_P
VCCRL_DACOUT1V8_DACOUTVCCT_DACOUT DAC_TWOCDAC_LDACn
DAC_SCLDAC_SDA
VCCERAM_DACOUTVCCRR_DACOUTVCCH_DACOUT
TEMPDIODE_N
OVERTEMPnTEMP_ALERTn
I2C_3V3_SDAI2C_3V3_SCL
TEMPDIODE_P
FAN_RPM
5V5V
5V 3.3V_STBY
3.3V_STBY
3.3V_DAC
12V
3.3V
3.3V_DAC
3.3V_STBY 3.3V_DAC
A_GND
A_GND
A_GND A_GND
A_GND
A_GND
3.3V_STBY
3.3V_STBY
3.3V
3.3V
SENSE_CS0n10SENSE_SDI10 SENSE_SCK10SENSE_SDO10
DAC_LDACn10 DAC_TWOC10
VCCERAM_SENSE_N12,46 VCCERAM_SENSE_P12,46 VCCRL_GXB_SENSE_N12,47 VCCRL_GXB_SENSE_P12,47 VCCRR_GXB_SENSE_N12,47 VCCRR_GXB_SENSE_P12,47 VCCT_GXB_SENSE_N12,41 VCCT_GXB_SENSE_P12,41 VCCH_GXB_SENSE_N12,46 VCCH_GXB_SENSE_P12,46 S10_1V8_SENSE_N12,48
VCCERAM_DACOUT12,46 VCCRL_DACOUT12,47 VCCRR_DACOUT12,47 VCCT_DACOUT12,41 VCCH_DACOUT12,46 1V8_DACOUT12,41
S10_1V8_SENSE_P12,48DAC_SDA10 DAC_SCL10
OVERTEMP14 FAN_ON18 FAN_RPM14
OVERTEMPn14,31 TEMP_ALERTn14,31
TEMPDIODE_P28 TEMPDIODE_N28
I2C_3V3_SCL10,12,18 I2C_3V3_SDA10,12,18
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B13 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B13 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B13 53Thursday, March 09, 2017
U106
MAX1619
ADD16ADD010
SMBCLK 14SMBDATA 12DXP3
DXN4
VCC1
OVERT 9ALERT 11
STBY15 GND1 2GND2 7GND3 8
NC15NC213NC316
L10
BLM15AG221SN1300mA
Thermal system
HW4
Liquid Cooling system
R133DNI
C16110uF
R1312.00K
J18HDR1X3
1 2 3
R134DNI
Q15FDV305N
R122
10.0K
R135DNI
R1322.00K
U17
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
R127DNI
R14010.0K
R1280
C1640.1uF
U19
REF3112
VIN1 VOUT 2
GND3
U18
DAC7578SRGET
NC11AVdd2VoutA3VoutC4VoutE5VoutG6NC27VREFIN8RSTSEL9
ADDR011 ADDR110
CLRn12 VoutH 13VoutF 14VoutD 15VoutB 16GND 17NC3 18SDA 19SCL 20TWOC 21LDACn 22NC4 23NC5 24
EGND
25
R13910.0K
R811DNI
R1210
C1621uF
C16810uF
C1670.1uF
R84410.0K
R123
10.0K
C14900.1uF
R834 DNI
R138DNI
C1630.1uF
R12610.0KR136DNIC1650.47uF
R835 200
R137DNI Q1FDV305N
R124
10.0K
R821 DNI
U16
LTC2418
CH021CH122
CH223CH324
CH425CH526
CH627CH728
CH81CH92
CH103CH114
CH125CH136
CH147CH158
COM10 GND 15
VCC 9
REF+ 11
REF- 12
F0 19
CSn 16SCK 18SDI 20SDO 17
NC1 13NC2 14
R125
10.0K
C1660.1uF
C14912.2nF
C1600.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAX V I2C Master
FLASH InterfaceSYSTEM MAX V
FPGA Configuration Interface
MAX5 LED
MAX5 Push Button
UB2/MAX V INTERFACE
MAX5 Dipswitch
MAX5 JTAG
S10/MAX V INTERFACE
Temperature Interface
CLOCK IC Signals
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203CLK_CONFIG
SI5341_1_ENn
FPGA_SDM10
FPGA_ASCLKFPGA_AVST_READY
FPGA_CONFIG_D3
USB_MAX5_CLK
FPGA_PR_ERROR
M5_JTAG_TDOM5_JTAG_TDIM5_JTAG_TMS
M5_JTAG_TCKMAX_OSC_CLK_1
FPGA_CONFIG_D30FPGA_CONFIG_D11
FPGA_CONFIG_D4
FPGA_CONFIG_D7
FPGA_CONFIG_D20FPGA_CONFIG_D21
FPGA_CONFIG_D18
FPGA_CONFIG_D5FPGA_CONFIG_D17FPGA_CONFIG_D15
FPGA_CONFIG_D14
FPGA_CONFIG_D16
FPGA_CONFIG_D13
FPGA_CONFIG_D12
FPGA_AVST_VALID
FPGA_CONFIG_D0FPGA_SEU_ERR
FPGA_INIT_DONEFPGA_CONFIG_D23
FPGA_CONFIG_D24
FPGA_AVST_CLK
FPGA_CONF_DONEFPGA_nSTATUS
FPGA_CONFIG_D25
FPGA_CONFIG_D29 FPGA_nCONFIG
FPGA_CONFIG_D28
FPGA_CONFIG_D9
FPGA_CONFIG_D31
FPGA_CONFIG_D6
FPGA_CONFIG_D8
FPGA_CONFIG_D10FPGA_CONFIG_D2FPGA_CONFIG_D1
FPGA_PR_DONEFPGA_CONFIG_D27FPGA_CONFIG_D26FPGA_CONFIG_D22FPGA_PR_REQUEST
TEMP_ALERTn
FPGA_CONFIG_D19
FPGA_MSEL0FPGA_MSEL2
MAX_ERRORMAX_LOADFACTORY_LOAD
PGM_SEL
MAX_CONF_DONE
PGM_CONFIG
MAX5_SWITCH2
CPU_RESETnFPGA_MSEL1
OVERTEMPOVERTEMPn
MAX5_SWITCH1
FLASH_RDYBSYn0FLASH_CEn0
FAPRSNT1V8_NFBPRSNT1V8_N
SI5341_1_RSTn
SI5341_1_INTnSI5341_1_LOLn
SI5341_2_ENn
MAX5_BEn0MAX5_CLK
USB_CFG0USB_CFG5USB_CFG1
USB_CFG12USB_CFG14
USB_CFG11
SPARE3SPARE4
SPARE2
SPARE12SPARE13
SPARE11SPARE17
SPARE15SPARE16
SPARE9 SPARE18
SPARE19SPARE14SPARE10
SPARE1
SPARE8
SPARE7
FPGA_CvP_DONE
SPARE20
FM_A1
FM_A23
FM_A10FM_A9FM_A6
FM_A8FM_A22
FM_A25
FM_A15
FM_A24FLASH_WEnFLASH_OEn
FM_A21
FM_A26
FM_A2
FM_A7
FM_A3
FM_A5
FM_A4
FLASH_RESETn
FM_A11
FM_A12
FM_A13
FM_A14
FM_A16
CLK_50M_MAX5
FM_D1FM_D2
FLASH_ADVn
CLK_CONFIG
FM_D8
FM_D0
FM_D10FM_D11
FM_D9
FM_D3
FM_D24FM_D17
FM_D19FM_D28FM_D21
FM_D22
FM_D12
FM_D5
FM_D13
FM_D4FM_D7
FM_D14
FM_D6
FM_D15
FM_D25
FM_D18
FLASH_CLKFM_A17
FM_A20 FM_A19
SPARE6
SPARE5
MAX_RESETn
FLASH_RDYBSYn1USB_CFG2
USB_CFG6 FAN_RPM
MAX5_SWITCH0PGM_LED2PGM_LED1PGM_LED0
SI5341_2_RSTn
SI5341_2_INTnSI5341_2_LOLn
I2C_1V8_SCL
I2C_1V8_SDAMAX5_OEn
USB_CFG4USB_CFG3
USB_CFG7USB_CFG9USB_CFG10
USB_CFG8USB_CFG13
FM_D20
FM_D31
FM_D16
FM_D26FM_D27
FM_D29
FM_D23FM_D30
FM_A18
FLASH_CEn1
FPGA_ASDATA0
FPGA_ASDATA1FPGA_ASDATA2FPGA_ASDATA3 MAX5_BEn1
MAX5_BEn2
MAX5_BEn3MAX5_CSnMAX5_WEn
EN_MASTER0
EN_MASTER1
1.8V1.8V 1.8V
1.8V
SPARE[20:1] 30
FPGA_CONFIG_D[31:0] 31
FPGA_nCONFIG 11,28
FPGA_PR_DONE 31FPGA_PR_REQUEST 31FPGA_PR_ERROR 31
USB_MAX5_CLK 8,9
M5_JTAG_TDO 9M5_JTAG_TCK 9M5_JTAG_TMS 9M5_JTAG_TDI 9
FM_D[31:0] 15,29
CPU_RESETn 17,31
I2C_1V8_SCL 6,18,31
FLASH_WEn 15,29
FLASH_OEn 15,29FLASH_RDYBSYn0 15,29FLASH_RDYBSYn1 15,29FLASH_RESETn 15,29
FACTORY_LOAD 17
FLASH_CLK 15,29
MAX5_SWITCH[2:0] 17
FLASH_ADVn 15,29
MAX5_BEn[3:0] 31MAX5_OEn 31MAX5_CSn 31MAX5_WEn 31MAX5_CLK 31
USB_CFG[14:0] 9
PGM_SEL 17PGM_CONFIG 17MAX_RESETn 17
PGM_LED[2:0] 17MAX_ERROR 17MAX_LOAD 17MAX_CONF_DONE 17
FM_A[26:1] 15,29FLASH_CEn0 15,29FLASH_CEn1 15,29
FPGA_AVST_CLK 31FPGA_AVST_VALID 31FPGA_AVST_READY 28
FPGA_ASCLK 28
TEMP_ALERTn 13,31OVERTEMPn 13,31OVERTEMP 13FAN_RPM 13
FBPRSNT1V8_N 30FAPRSNT1V8_N 32I2C_1V8_SDA 6,18,31
CLK_50M_MAX5 4
FPGA_SDM10 28FPGA_SEU_ERR 28FPGA_CvP_DONE 28
FPGA_nSTATUS 28
FPGA_MSEL0 28FPGA_MSEL1 28FPGA_MSEL2 28
FPGA_CONF_DONE 28FPGA_INIT_DONE 28
FPGA_ASDATA1 28FPGA_ASDATA2 28FPGA_ASDATA3 28
FPGA_ASDATA0 28
MAX_OSC_CLK_1 7
SI5341_1_ENn 6SI5341_1_RSTn 6SI5341_2_ENn 7SI5341_2_RSTn 7SI5341_1_INTn 6SI5341_1_LOLn 6SI5341_2_INTn 7SI5341_2_LOLn 7
EN_MASTER0 18EN_MASTER1 18
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B14 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B14 53Thursday, March 09, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B14 53Thursday, March 09, 2017
MAX VBANK3U20C
5M2210ZF256
IOB3/CLK2J12IOB3/CLK3H12
DIFFIO_R9PG12DIFFIO_R9NG16
DIFFIO_R8PG13DIFFIO_R8NG15DIFFIO_R7PG14DIFFIO_R7NF16DIFFIO_R6PE16DIFFIO_R6NF15DIFFIO_R5PF13DIFFIO_R5NE15
DIFFIO_R4PF14DIFFIO_R4ND16DIFFIO_R3PE12DIFFIO_R3ND15DIFFIO_R2PC15DIFFIO_R2NE13
DIFFIO_R22P P15DIFFIO_R22N P14DIFFIO_R21P N15DIFFIO_R21N N14
DIFFIO_R20P N16DIFFIO_R20N M13
DIFFIO_R1PE14DIFFIO_R1NC14
DIFFIO_R19P M15DIFFIO_R19N L14DIFFIO_R18P M16DIFFIO_R18N L13DIFFIO_R17P L15DIFFIO_R17N L12
DIFFIO_R16P L16DIFFIO_R16N L11DIFFIO_R15P K15DIFFIO_R15N K14DIFFIO_R14P K16DIFFIO_R14N K13DIFFIO_R13P J14DIFFIO_R13N J15
DIFFIO_R12PJ13DIFFIO_R12NJ16DIFFIO_R11PH13DIFFIO_R11NH16DIFFIO_R10PH14DIFFIO_R10NH15
IOB3_21 D13IOB3_22 D14IOB3_23 F11
IOB3_24 F12IOB3_25 K12IOB3_26 M14IOB3_27 N13
C7950.1uF
C8150.1uF
C1720.1uF
C7970.1uF
C8170.1uF
MAX VPowerU20E
5M2210ZF256
GNDINTF7GNDINTG6GNDINTH7GNDINTH9
GNDIOA1GNDIOA16GNDIOB15GNDIOB2GNDIOG10GNDIOG7GNDIOG8GNDIOG9GNDIOK10GNDIOK7GNDIOK8GNDIOK9GNDIOR15GNDIOR2GNDIOT1GNDIOT16
VCCINT H8VCCINT H10VCCINT G11VCCINT F10
VCCIO1 C1VCCIO1 H6VCCIO1 J6VCCIO1 P1
VCCIO2 A14VCCIO2 A3VCCIO2 F8VCCIO2 F9
VCCIO3 C16VCCIO3 H11VCCIO3 J11VCCIO3 P16
VCCIO4 L8VCCIO4 L9VCCIO4 T14VCCIO4 T3
GNDINTJ10 VCCINT J7
VCCINT L7GNDINTJ8GNDINTK11 VCCINT K6VCCINT J9
GNDINTL10
GNDIOT6
C7940.1uF
C7960.1uF
C7980.1uF
C7990.1uF
C8080.1uF
C8000.1uF
MAX VBANK4U20D
5M2210ZF256
DIFFIO_B13N/DEV_CLRnM9DIFFIO_B13P/DEV_OEM8
DIFFIO_B9PP8DIFFIO_B9NT7
DIFFIO_B8PM7DIFFIO_B8NR7DIFFIO_B7PR6DIFFIO_B7NN7DIFFIO_B6PT5DIFFIO_B6NP7DIFFIO_B5PR5DIFFIO_B5NM6
DIFFIO_B4PP6DIFFIO_B4NN6DIFFIO_B3PR3DIFFIO_B3NN5DIFFIO_B2PT2DIFFIO_B2NP5
DIFFIO_B22P R16DIFFIO_B22N P13
DIFFIO_B21P P12DIFFIO_B21N T15DIFFIO_B20P N12DIFFIO_B20N R14
DIFFIO_B1PR1DIFFIO_B1NP4
DIFFIO_B19P T13DIFFIO_B19N R13DIFFIO_B18P R12DIFFIO_B18N P11
DIFFIO_B17P T12DIFFIO_B17N N11DIFFIO_B16P P10DIFFIO_B16N R11DIFFIO_B15P N10DIFFIO_B15N T11DIFFIO_B14P M10DIFFIO_B14N R10
DIFFIO_B12PR9DIFFIO_B12NP9DIFFIO_B11PT8DIFFIO_B11NT9DIFFIO_B10PN8DIFFIO_B10NR8 IOB4_28 M11
IOB4_29 M12IOB4_30 N9IOB4_31 R4IOB4_32 T10IOB4_33 T4
C8020.1uF
C8090.1uF
C8010.1uF
MAX VBANK2U20B
5M2210ZF256
DIFFIO_T9PB8DIFFIO_T9NA8
DIFFIO_T8PD8DIFFIO_T8NA7DIFFIO_T7PC8DIFFIO_T7NB7DIFFIO_T6PB6DIFFIO_T6NE7DIFFIO_T5PA5DIFFIO_T5ND7
DIFFIO_T4PE6DIFFIO_T4NB5DIFFIO_T3PB4DIFFIO_T3ND6DIFFIO_T2PC5DIFFIO_T2NC4DIFFIO_T1PD4DIFFIO_T1NB1
DIFFIO_T18P C13DIFFIO_T18N B16DIFFIO_T17P D12DIFFIO_T17N B14
DIFFIO_T16P C11DIFFIO_T16N B13DIFFIO_T15P E11DIFFIO_T15N B12DIFFIO_T14P B11DIFFIO_T14N A12DIFFIO_T13P E10DIFFIO_T13N A11
DIFFIO_T12PA10DIFFIO_T12NC9DIFFIO_T11PB9DIFFIO_T11ND9DIFFIO_T10PA9DIFFIO_T10NE9
IOB2_6 A13IOB2_7 A15
IOB2_8 A2IOB2_9 A4
IOB2_10 A6IOB2_11 B10IOB2_12 B3IOB2_13 C10IOB2_14 C12IOB2_15 C6
IOB2_16 C7IOB2_17 D10IOB2_18 D11IOB2_19 D5IOB2_20 E8
C8040.1uF
C8100.1uFR141 33 C803
0.1uFC8110.1uF
MAX VBANK1U20A
5M2210ZF256
DIFFIO_L19P N1
IOB1/CLK0H5IOB1/CLK1J5
DIFFIO_L9PG1DIFFIO_L9NG4
DIFFIO_L8PG2DIFFIO_L8NG3DIFFIO_L7PF1DIFFIO_L7NF6DIFFIO_L6PF4DIFFIO_L6NF2DIFFIO_L5PF3DIFFIO_L5NE1
DIFFIO_L4PD1DIFFIO_L4NE5DIFFIO_L3PD2DIFFIO_L3NE4DIFFIO_L2PC3DIFFIO_L2NE3
DIFFIO_L21P N3DIFFIO_L21N P2
DIFFIO_L20P N2DIFFIO_L20N M3
DIFFIO_L1PD3DIFFIO_L1NC2
DIFFIO_L19N M4DIFFIO_L18P L4DIFFIO_L18N L3DIFFIO_L17P M1DIFFIO_L17N M2
DIFFIO_L16P L2DIFFIO_L16N K3DIFFIO_L15P K5DIFFIO_L15N L1DIFFIO_L14P J3DIFFIO_L14N K2DIFFIO_L13P J4DIFFIO_L13N K1
DIFFIO_L12PH4DIFFIO_L12NJ2DIFFIO_L11PH3DIFFIO_L11NJ1DIFFIO_L10PH2DIFFIO_L10NG5 IOB1_1 E2
IOB1_2 F5IOB1_3 H1IOB1_4 K4IOB1_5 L5
TMS N4TDO M5TDI L6TCK P3
C8060.1uF
C8120.1uF
C8050.1uF
C8130.1uF
C1712.2uF
C8070.1uF
C8140.1uF
X4
100MHz
VCC 4
GND2 OUT 3EN1
C8160.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFI Flash Memory
- When using a single x16 flash device a word consists of 16data bits so addressing starts with FM_A1 mapped to addressbit 1 in software.- When using dual x16 flash devices for an equivalent x32(x16||x16) flash device a word consists of 32 data bits soaddressing starts with FM_A1 mapped to address bit 2 insoftware.
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
FM_D0FM_D1FM_D2FM_D3FM_D4FM_D5FM_D6FM_D7
FM_D[15:0]
FM_D8FM_D9FM_D10FM_D11FM_D12FM_D13FM_D14FM_D15FLASH_RDYBSYn0FM_A26
FM_A26
FM_A1FM_A2
FLASH_CEn1
FM_A3FM_A4FM_A5FM_A6FM_A7FM_A8FM_A9FM_A10FM_A11FM_A12FM_A13FM_A14FM_A15FM_A16FM_A17FM_A18FM_A19FM_A20FM_A21FM_A22FM_A23FM_A24FM_A25
FM_D16FM_D17FM_D18FM_D19FM_D20FM_D21FM_D22FM_D23
FM_D[31:16]
FM_D24FM_D25FM_D26FM_D27FM_D28FM_D29FM_D30FM_D31FLASH_RDYBSYn1
FLASH_OEnFLASH_ADVn
FLASH_RESETnFLASH_CEn0FLASH_WEn
FLASH_CLK
F_WPn
FM_A1FM_A2FM_A3FM_A4FM_A5FM_A6FM_A7FM_A8FM_A9FM_A10FM_A11FM_A12FM_A13FM_A14FM_A15FM_A16FM_A17FM_A18FM_A19FM_A20FM_A21FM_A22FM_A23FM_A24
FM_A[26:1]
FM_A25
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
FM_D[31:0]14,29FM_A[26:1]14,29FLASH_WEn14,29 FLASH_CEn014,29 FLASH_CEn114,29 FLASH_OEn14,29
FLASH_RESETn14,29 FLASH_CLK14,29 FLASH_ADVn14,29
FLASH_RDYBSYn014,29 FLASH_RDYBSYn114,29
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B15 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B15 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B15 53Monday, March 13, 2017
R14810.0K
C1750.1uF
C1790.1uF
C1810.1uF
C1820.1uF
C1830.1uF
C1840.1uF
R146
10.0K
C1850.1uF
C1800.1uF
R142
DNI
PC28FxxxP30B85FLASHU21
PC28F00AP30BF
A1A1A2B1A3C1A4D1A5D2A6A2A7C2A8A3A9B3A10C3A11D3A12C4A13A5A14B5A15C5A16D7A17D8A18A7A19B7A20C7A21C8A22A8A23G1
CE#B4OE#F8WE#G8
WP#C6
VCC1 A6
RESET#D4
VCC2 H3
D0 F2D1 E2D2 G3D3 E4D4 E5D5 G5D6 G6D7 H7
D8 E1D9 E3
D10 F3D11 F4D12 F5D13 H5D14 G7D15 E7
WAIT F7
GND1 B2
GND3 H4GND2 H2CLKE6
ADV#F6
A26(1GIG)/NCB8
RFU3 E8RFU2 F1RFU1 G2RFU0 H1
A24H8A25(512M/1GIG)/NCB6
VPP A4
VCCQ2 D6VCCQ1 D5
VCCQ3 G4
GND4 H6
C1860.1uF
R143
DNI
R15010.0K
R15110.0K
C1730.1uF
R144
DNI
C1870.1uF
C1740.1uF
R145
10.0K
R147
DNI
C1760.1uF
R14910.0K
C1770.1uF
PC28FxxxP30B85FLASHU22
PC28F00AP30BF
A1A1A2B1A3C1A4D1A5D2A6A2A7C2A8A3A9B3A10C3A11D3A12C4A13A5A14B5A15C5A16D7A17D8A18A7A19B7A20C7A21C8A22A8A23G1
CE#B4OE#F8WE#G8
WP#C6
VCC1 A6
RESET#D4
VCC2 H3
D0 F2D1 E2D2 G3D3 E4D4 E5D5 G5D6 G6D7 H7
D8 E1D9 E3
D10 F3D11 F4D12 F5D13 H5D14 G7D15 E7
WAIT F7
GND1 B2
GND3 H4GND2 H2CLKE6
ADV#F6
A26(1GIG)/NCB8
RFU3 E8RFU2 F1RFU1 G2RFU0 H1
A24H8A25(512M/1GIG)/NCB6
VPP A4
VCCQ2 D6VCCQ1 D5
VCCQ3 G4
GND4 H6
C1880.1uF
C1780.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
10/100/1000 Ethernet PHY
Ethernet_1.2V
connect GNDsthrough a single via
Place near 88E1111 PHY
Place near 88E1111 PHY
CAD Notes:
CAD Notes:
Cage GND on all layers
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
MDI_N0
ENET_LED_RXENET_LED_LINK1000ENET_LED_LINK10
ENET_T_INTnENET_T_RSTn
ENET_MDIOENET_MDCMDIO_TMDC_T ENET_INTnENET_RSTn
ENET_SGMII_RX_N
ENET_SGMII_TX_PENET_SGMII_TX_NENET_SGMII_RX_P
ENET_T_RSTn
ENET_LED_RX
ENET_LED_TX
ENET_LED_LINK10
ENET_LED_LINK100
ENET_LED_LINK1000
MDC_T
ENET_LED_TX
ENET_T_INTn
MDI_P1
ENET_T_INTn
MDI_N1MDI_P2MDI_N2
ENET_T_RSTn
MDI_P3
ENET_LED_RXENET_LED_LINK1000ENET_LED_LINK100ENET_LED_LINK10
MDI_N3
ENET_XTAL_25MHZ
ENET_RSET
MDIO_T
MDI_P0
MDI_P1MDI_N1MDI_P2MDI_N2MDI_P3MDI_N3
MDI_N0MDI_P0
Ethernet_1.2V
2.5V
Ethernet_1.2V
1.8V 1.8V2.5V
2.5V
2.5V2.5V
2.5V
2.5V
2.5V
2.5V
GND_E1V2
GND_E1V2
GND_E1V2
Ethernet_1.2V
2.5V
GND_ETHE
GND_ETHE
ENET_SGMII_TX_P29 ENET_SGMII_TX_N29
ENET_RSTn29
ENET_MDIO29 ENET_MDC29
ENET_SGMII_RX_P29 ENET_SGMII_RX_N29
ENET_INTn29
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B16 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B16 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B16 53Monday, March 13, 2017
R153 DNI
C1910.1uF
R1634.99K
C199 0.01uF
C2130.1uF
C1901uF
R1644.7K
R165237K
R1544.7K
D9
LED_WE1206
R175 160
C200 0.01uF
U25
EP53F8QI
NC(SW)1PGND02PGND13AVIN14VFB5NC66
VOUT
07
VOUT
18
AGND 9AVIN0 10POK 11ENABLE 12PVIN1 13PVIN0 14
NC(SW
)1515
NC(SW
)1616
R171 49.9
C2030.1uF
R173 49.9
R1554.7K
R176 160
C204 0.01uF
R170237K
R174 49.9
C2080.1uF
R169 49.9
R177 160
C192 10uF
R166 49.9
D10
LED_WE1206
GMII/MII/TBI I
NTERFACE
TEST
SGMII
INTERFACE
JTAGMDI INTERFACE
MGMT
U23A
88E1111
COMA27RESET_N28
CONFIG658 CONFIG559 CONFIG460 CONFIG361 CONFIG263 CONFIG164 CONFIG065
125CLK22XTAL155XTAL254VSSC53
RSET30SEL_FREQ56
MDI3_P42MDI3_N43MDI2_P39MDI2_N41MDI1_P33MDI1_N34MDI0_P29MDI0_N31
MDIO24MDC25INT_N23
HSDAC_P37HSDAC_N38
GTX_CLK 8TX_CLK 4
TX_EN 9
RXCLK 2RX_DV 94
CRS 84COL 83
S_CLK_P 79S_CLK_N 80
S_IN_P 82S_IN_N 81
S_OUT_P 77S_OUT_N 75
LED_TX 68LED_RX 69
LED_DUPLEX 70LED_LINK1000 73
LED_LINK100 74LED_LINK10 76
RXD0 95RXD1 92RXD2 93RXD3 91RXD4 90RXD5 89RXD6 87RXD7 86
RX_ER 3
TXD0 11TXD1 12TXD2 14TXD3 16TXD4 17TXD5 18TXD6 19TXD7 20
TX_ER 7
TMS46 TDO50 TDI44 TCK49 TRST_N47
C2050.1uF
R1590
R84310.0K
R168 49.9
R178 160
C196 22uF
C2110.1uF
C2100.1uF
R1580
R179 160
C1951uF
C1975pF
C2120.1uF
J19
HFJ11-1G02E
TD0_P 1TD0_N 2
TD1_P 3TD1_N 6
TD2_P 4TD2_N 5
TD3_P 7TD3_N 8
VCC 9
GND 10
GND_
TAB
11GN
D_TA
B12
C14924.7nF
C193 680pF
D11
LED_WE1206
C1940.01uF
C2060.1uF
D7
LED_WE1206
C2010.1uF
X5
25.00MHz
VCC 4
GND2 OUT 3EN1
R167 49.9
U23B
88E1111
NC113
VSS97
DVDD0 1DVDD1 6DVDD2 10DVDD3 15DVDD4 57DVDD5 62DVDD6 67DVDD7 71DVDD8 85
AVDD032AVDD136AVDD235AVDD340AVDD445AVDD578
VDDO
X026
VDDO
X148
VDDO
05
VDDO
121
VDDO
288
VDDO
396
VDDO
H072
VDDO
H166
VDDO
H252
NC251
V12RSNS1 SNS 2
R1564.7K
C2140.1uF
R16210.0K
R152 DNI
R172 49.9
R1574.7K
R16110
C2090.1uF
C2070.1uF
C1890.1uF
U24
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
D8
LED_WE1206
C2020.1uF
C198 0.01uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Buttons/Switches/LEDs/LCD
FPGA USERPUSHBUTTONS
MAX5PUSHBUTTONS
USER GPIO
MAX5 LEDs
USER LEDs
MAX5 DIPSWITCHES
USER DIP SWITCHESLCD DISPLAY HEADER
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
MAX_ERROR
MAX_CONF_DONE
MAX_LOAD
USER_IO0USER_IO1USER_IO2USER_IO3
I2C_5V_SDAI2C_5V_SCL
USER_PB7USER_PB6
MAX_RESETnPGM_CONFIGPGM_SEL
CPU_RESETn
USER_PB1
USER_PB5
USER_PB0
USER_PB4USER_PB3USER_PB2
S10_UnlockUSER_DIP6USER_DIP4USER_DIP3USER_DIP2
USER_DIP5
USER_DIP1USER_DIP0
PGM_LED0
USER_IO4USER_IO5 PGM_LED1USER_IO6 PGM_LED2
USER_IO7USER_IO8USER_IO9
MAX5_SWITCH1MAX5_SWITCH2FACTORY_LOADMAX5_SWITCH0
USER_LED1
USER_LED0
USER_LED5
USER_LED2
USER_LED3
USER_LED7
USER_LED6
USER_LED4
1.8V
5V
1.8V
2.5V
1.8V
USER_LED[7:0] 31
MAX_ERROR 14MAX_LOAD 14MAX_CONF_DONE 14
PGM_LED[2:0] 14
USER_IO[9:0] 31
S10_Unlock 31
FACTORY_LOAD 14MAX5_SWITCH[2:0] 14
I2C_5V_SCL 18I2C_5V_SDA 18
USER_DIP[6:0] 31
PGM_SEL 14PGM_CONFIG 14MAX_RESETn 14
CPU_RESETn 14,31
USER_PB[7:0] 31
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B17 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B17 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B17 53Monday, March 13, 2017
D14
LED_WE1206
S81 2C222 1uF
D21
LED_WE1206
RP810K
1 2 3 45678
R1881K
R2031K
OPENSW6TDA04H0SB1
1 2 3 45678
C215 1uF
R1961K
C220 1uF
R19756K
R18756K
R208 160D18
LED_WE1206
R1981K
R214 160
C226 1uF
R18356K
R20456K
C218 1uF
D15
LED_WE1206
R215 160
S41 2
R1901K
R18156K
R207 160
R1861K
R19956K
C1234
0.1uF
RP1010K
1 2 3 45678
C216 1uF R1821K
OPENSW4TDA04H0SB1
1 2 3 45678
R1921K
S51 2
D22
LED_WE1206
R19156K
J20
LCD_HEADER
12345678910
C223 1uF
R210 160
D19
LED_WE1206
R18556K
R19356K
S61 2
R1801K
R216 160
R211 160
C221 1uF
S131 2
D16
LED_WE1206
R1841K
J21
HDR2X7
113355779911111313
2 24 46 68 8
10 1012 1214 14
RP910K
1 2 3 45678
R202 160
D23
LED_WE1206
S71 2
S91 2
R212 160
R217 160
D13
LED_WE1206
D20
LED_WE1206
C224 1uF
R2001K
C219 1uF
R1941K
S101 2
S31 2
D24
LED_WE1206
R20156K
R209 160
R19556K
S21 2
S111 2
C217 1uF
B1
2x16 LCD BOM I2C
OPEN SW5TDA04H0SB1
1 2 3 45678
D17
LED_WE1206
D25
LED_WE1206
R18956K
S121 2
R213 160
R205 160
R206 160
C225 1uF D12
LED_WE1206
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C Chain/BufferI2C Buffer / Translators
I2C BUS
Power Manager select, default OFF for LT managerSW8 3-6 OFF: LTM2987 is selectedSW8 3-6 ON: MAX10 is selectedDO NOT change PWR_MAG_SEL setting during board running!Power recycle mannually if PWR_MAG_SEL setting is changed during board running!
1.8V to 2.5V
1.8V to 3.3V
1.8V to 5V
1.8V to 3.3V
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
I2C_5V_SDAI2C_5V_SCL
I2C_2V5_SDAI2C_2V5_SCLI2C_1V8_SCLI2C_1V8_SDA
I2C_3V3_SCLI2C_3V3_SDA
FAN_ONMAX10_BOOTSEL
VCC_SCLVCC_SDA LT_SCLLT_SDA
PWR_MGMT_SELMAX10_DIPSWITCH
I2C_1V8_SCLI2C_1V8_SDA
I2C_1V8_SCLI2C_1V8_SDA
EN_MASTER1
EN_MASTER0
1.8V 5V
2.5V1.8V
3.3V1.8V
3.3V_STBY
LTM4677_VDD331.8V
I2C_2V5_SCL 5
I2C_5V_SDA 17
I2C_3V3_SCL 10,12,13
I2C_5V_SCL 17
I2C_2V5_SDA 5
I2C_1V8_SDA 6,14,31
I2C_3V3_SDA 10,12,13
FAN_ON 13
MAX10_BOOTSEL 11PWR_MGMT_SEL 11,12MAX10_DIPSWITCH 11
I2C_1V8_SCL 6,14,31
LT_SCL 12,42LT_SDA 12,42
VCC_SDA 28VCC_SCL 28
EN_MASTER0 14EN_MASTER1 14
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B18 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B18 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B18 53Monday, March 13, 2017
C2380.01uF
U28
FXMA2102UMX
A02A13 B0 7
B1 6
VCCA1GND4OE5
VCCB 8
R22410.0K
R23310.0K
R22510.0K
R25010.0K
R22210.0K
R227DNI
R240DNI
C2280.1uF
R64010.0K R63710.0K
R241DNI
C2310.01uF
R226 DNI
R234 DNI
C2330.1uF
C2361uFR24210.0K
OPEN
SW8
TDA04H0SB1
1234 5678
C2370.01uF
C2400.01uF
R243 DNI
C2320.01uF
R2324.7K
R24910.0K
C2270.01uF
R2384.7K
C2301uF
R251 DNI
U27
FXMA2102UMX
A02A13 B0 7
B1 6
VCCA1GND4OE5
VCCB 8
C2390.1uF
C2340.01uF
U29
FXMA2102UMX
A02A13 B0 7
B1 6
VCCA1GND4OE5
VCCB 8
R2394.7K
R24810.0K
R2314.7K
R245DNI
C2350.1uF
R2202.49K
C2290.01uF
U26
FXMA2102UMX
A02A13 B0 7
B1 6
VCCA1GND4OE5
VCCB 8
R2212.49K
R244DNI
R228DNI
R22310.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFP4 Interface
1.2V LVCMOS
1.2V LVCMOS
Place CAPs near CFP4 connector
Rout signals as 100OHM differential
Cage GND on top layerCAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
REFCLKCFP4nREFCLKCFP4p
REFCLK_CFP4_614M_N
REFCLK_CFP4_614M_P
MCLKpMCLKn
CFP4_A_TX_DISCFP4_A_MOD_LOPWRCFP4_A_MOD_RSTn
CFP4_A_MDCCFP4_A_MDIO
CFP4_A_PRTADR1CFP4_A_PRTADR2CFP4_A_PRTADR0
CFP4_A_RX_LOSCFP4_A_GLB_ALRMn
CFP4_A_MOD_ABSMCLKpMCLKn
GXBL_1C_TXP1GXBL_1C_TXN1
GXBL_1C_TXP3GXBL_1C_TXN3
GXBL_1C_TXN0GXBL_1C_TXP0
GXBL_1C_RXN3GXBL_1C_RXP3GXBL_1C_RXN4GXBL_1C_RXP4GXBL_1C_TXN4GXBL_1C_TXP4
GXBL_1C_RXN0GXBL_1C_RXP0GXBL_1C_RXN1GXBL_1C_RXP1
CFP4_3.3V
CFP4_3.3V3.3V
GND_CFP4_CAGE
GND_CFP4_CAGE
GND_CFP4_CAGE GND_CFP4_CAGE
REFCLK_CFP4_614M_P 6REFCLK_CFP4_614M_N 6
GXBL_1C_TXP0 33GXBL_1C_TXN0 33
GXBL_1C_RXP0 33GXBL_1C_RXN0 33
CFP4_A_MDIO 20CFP4_A_MDC 20
CFP4_A_GLB_ALRMn 20CFP4_A_RX_LOS 20CFP4_A_MOD_ABS 20CFP4_A_TX_DIS 20CFP4_A_MOD_LOPWR 20CFP4_A_MOD_RSTn 20
CFP4_A_PRTADR0 20CFP4_A_PRTADR1 20CFP4_A_PRTADR2 20
GXBL_1C_TXP1 33
GXBL_1C_RXN1 33GXBL_1C_RXP1 33
GXBL_1C_TXN1 33
GXBL_1C_RXP3 33
GXBL_1C_TXN3 33GXBL_1C_TXP3 33
GXBL_1C_RXN3 33
GXBL_1C_TXN4 33
GXBL_1C_RXP4 33GXBL_1C_RXN4 33
GXBL_1C_TXP4 33
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B19 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B19 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B19 53Monday, March 13, 2017
C2430.1uF
R8130
R79210.0K
C2520.1uF
CFP4 QUAD PORTCONN COVER
HW2
CFP4_COVER
C2530.1uF
CFP4 SNGL PORTHEAT SINK
HW3
CFP4 HEAT SINKC2540.1uF
J251
2 3 4 5
C14564.7nF
R253DNI
J261
2 3 4 5R806100
CFP4 CAGE
HW1
CN121C-056-0002
R8120
C24622uF C250100u
J24
CFP4-CN121S-056-0001
Rx0p 30Tx0p45Rx0n 31Tx0n46
Rx1n 34Rx1p 33
Rx2p 36Rx2n 37
Rx3n 40Rx3p 39
Tx1n49 Tx1p48
Tx2p51Tx2n52
Tx3p54Tx3n55
REFCLKp42REFCLKn43
MDC17MDIO18
MCLKn26MCLKp27
GLB_ALRMn 13
PRTADR019
PRTADR221 PRTADR120
TX_DIS11MOD_LOPWR14
RX_LOS 12
MOD_RSTn16
MOD_ABS 15
VND_IO_A 9
VND_IO_C 22VND_IO_B 10
VND_IO_E 24VND_IO_D 23
3.3V033.3V143.3V253.3V36
3.3VGND38 3.3VGND27 3.3VGND12 3.3VGND01
GND0 25GND1 28GND2 29GND3 32GND4 35GND5 38GND6 41GND7 44GND8 47
GND11 56GND10 53GND9 50
CGND0G1CGND1G2CGND2G3CGND3G4CGND4G5CGND5G6
CGND7G8 CGND6G7
CGND10 G11
CGND9G10 CGND8G9
CGND11 G12
CGND14 G15CGND15 G16
CGND20 G21CGND18 G19
CGND13 G14
CGND17 G18
CGND12 G13
CGND16 G17
CGND19 G20
CGND21 G22CGND22 G23
C249100u
FB4 12
R254 33
C248100uC247100uC24510uF C2510.1uFC244100u
R252 33
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFP4 Voltage Translators
CFP4 1.2V
connect GNDsthrough a single via
Addr = 000
CAD Notes:Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
CFP4_PRTADR0CFP4_PRTADR1CFP4_MDCCFP4_MDIO
CFP4_A_PRTADR0CFP4_A_MDCCFP4_A_MDIO
CFP4_PRTADR2
CFP4_A_PRTADR2CFP4_A_PRTADR1CFP4_A_PRTADR0 CFP4_A_MOD_ABSCFP4_A_RX_LOSCFP4_A_GLB_ALRMn
CFP4_A_PRTADR1
CFP4_A_PRTADR2
CFP4_MOD_ABSCFP4_RX_LOSCFP4_GLB_ALRMnCFP4_A_RX_LOSCFP4_A_MOD_ABSCFP4_A_GLB_ALRMn
CFP4_A_TX_DISCFP4_A_MOD_RSTnCFP4_A_MOD_LOPWR CFP4_MOD_RSTn
CFP4_TX_DISCFP4_MOD_LOPWR
CFP4_MOD_ABSCFP4_RX_LOSCFP4_GLB_ALRMn
CFP4_3.3VCFP4_1.2V
CFP4_1.2V
CFP4_1.2V
1.8V
1.8V
CFP4_1.2V1.8V
CFP4_3.3VCFP4_1.2V 1.8V
1.8V1.8V
CFP4_3.3V
GND_C1V2
GND_C1V2
GND_C1V2
CFP4_1.2V
CFP4_1.2V
CFP4_3.3V
1.8V
CFP4_A_MDIO 19
CFP4_A_TX_DIS 19CFP4_A_MOD_LOPWR 19CFP4_A_MOD_RSTn 19
CFP4_A_GLB_ALRMn 19CFP4_A_RX_LOS 19CFP4_A_MOD_ABS 19
CFP4_MDC 29CFP4_MDIO 29
CFP4_GLB_ALRMn 29
CFP4_TX_DIS 29CFP4_MOD_ABS 29CFP4_RX_LOS 29
CFP4_MOD_RSTn 29CFP4_MOD_LOPWR 29
CFP4_PRTADR1 29
CFP4_A_MDC 19
CFP4_PRTADR2 29CFP4_PRTADR0 29
CFP4_A_PRTADR0 19CFP4_A_PRTADR1 19CFP4_A_PRTADR2 19
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B20 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B20 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B20 53Monday, March 13, 2017
U31
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
C2800.1uF
R268DNI
C286 680pF
C2780.1uF
U33
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
C2810.1uF
C2830.1uF
R26310
R27410.0K
C2871uF
C2590.1uFU30
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
C2570.1uF
R269DNI
C2581uF
R276237K
C2760.1uF
R255DNI
U34 EP53F8QI
NC(SW)1PGND02PGND13AVIN14VFB5NC66
VOUT
07
VOUT
18
AGND 9AVIN0 10POK 11ENABLE 12PVIN1 13PVIN0 14
NC(SW
)1515
NC(SW
)1616
R256DNI
R26610.0K
R277237K
C1233 22uF
R2574.7K
C285 10uF
C2560.1uF
R2701.00K
C2791uF
R267DNI
C288 22uF
R2584.7K
C2770.1uF
C2840.1uF
R26410.0K
C2600.1uF
U32
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
R27510.0K
R2711.00K
C2895pF
C2551uF
R26510.0K
V13RSNS1 SNS 2
R2721.00K
C2821uF
R27310.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
QSFP28 Interface 0
QSFP28 Interface
Cage GND on top layer
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
eQSFP_resetL0eQSFP_modselL0eQSFP_T_resetL0eQSFP_T_modselL0
eQSFP_T_intl0
eQSFP_T_sda0eQSFP_T_scl0
eQSFP_intl0eQSFP_modprsL0eQSFP_T_modprsL0
eQSFP_T_modselL0eQSFP_T_resetL0eQSFP_T_modprsL0eQSFP_T_LPmode0eQSFP_T_intl0
eQSFP_T_sda0eQSFP_T_scl0
eQSFP_LPmode0eQSFP_T_LPmode0
eQSFP_scl0eQSFP_sda0
GXBL_1D_RXP0GXBL_1D_RXN0
GXBL_1D_RXN1GXBL_1D_RXP1GXBL_1D_RXN3GXBL_1D_RXP3GXBL_1D_RXN4GXBL_1D_RXP4
GXBL_1D_TXP0GXBL_1D_TXN0
GXBL_1D_TXN1GXBL_1D_TXP1GXBL_1D_TXN3GXBL_1D_TXP3GXBL_1D_TXN4GXBL_1D_TXP4
QSFP0_VCC1QSFP0_VCCTXQSFP0_VCCRX
QSFP0_VCC1
QSFP0_VCCTX
3.3V
QSFP0_VCCRX
1.8V3.3V
1.8V3.3V
1.8V
1.8V
GND_QSFP_CAGE
GND_QSFP_CAGE
eQSFP_sda0 29
eQSFP_modselL0 29eQSFP_resetL0 29eQSFP_LPmode0 29eQSFP_modprsL0 29eQSFP_intl0 29
eQSFP_scl0 29
GXBL_1D_TXP0 33GXBL_1D_TXN0 33
GXBL_1D_RXN0 33GXBL_1D_RXP0 33
GXBL_1D_TXN1 33GXBL_1D_TXP1 33
GXBL_1D_RXN1 33GXBL_1D_RXP1 33GXBL_1D_RXN3 33
GXBL_1D_TXN3 33
GXBL_1D_RXP3 33
GXBL_1D_TXP3 33GXBL_1D_TXP4 33
GXBL_1D_RXP4 33
GXBL_1D_TXN4 33
GXBL_1D_RXN4 33
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B21 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B21 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B21 53Monday, March 13, 2017
C29122uF
L12 1.0uH
C3021uF
R283DNI R2854.7KC2980.1uF R2844.7K
C3030.1uF
J27
zQSFP+
GND0 1
TX2n 2TX2p 3
GND1 4
TX4n 5TX4p 6
GND2 7
ModselL8ResetL9
VCCRX 10
SCL11SDA12
GND3 13
RX3p14RX3n15
GND4 16
RX1p17RX1n18
GND5 19GND6 20
RX2n21 RX2p22
GND7 23
RX4n24 RX4p25
GND8 26
ModPrsL27
Intl28VCCTX 29VCC1 30
LPMode31
GND9 32
TX3p 33TX3n 34
GND10 35
TX1p 36TX1n 37
GND11 38
R282DNI
C3010.1uF
R2814.7K
B4
zQSFP+_CAGE
CAGE_GND01CAGE_GND12CAGE_GND23CAGE_GND34CAGE_GND45CAGE_GND56 CAGE_GND6 7CAGE_GND7 8CAGE_GND8 9CAGE_GND9 10CAGE_GND10 11CAGE_GND11 12
C2960.1uF
C2900.1uF
R2784.7K
R75610.0K
R2794.7K R2804.7K
C29322uf
U35
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
L13 1.0uH
C2920.1uF
C12354.7nF
C29522uf
L14 1.0uH
C2940.1uF C2971uF
C30022uf
U36
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
C2990.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
QSFP28 Interface 1
QSFP28 Interface
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
eQSFP_resetL1eQSFP_modselL1eQSFP_T_resetL1eQSFP_T_modselL1
eQSFP_T_intl1 eQSFP_intl1eQSFP_modprsL1eQSFP_T_modprsL1
eQSFP_T_modprsL1eQSFP_T_LPmode1eQSFP_T_intl1
eQSFP_T_modselL1eQSFP_T_resetL1
eQSFP_T_sda1eQSFP_T_scl1 eQSFP_scl1eQSFP_sda1
eQSFP_T_scl1eQSFP_T_sda1
eQSFP_T_LPmode1 eQSFP_LPmode1
GXBL_1E_RXP0GXBL_1E_RXN0 GXBL_1E_TXP0GXBL_1E_TXN0
GXBL_1E_TXN1GXBL_1E_TXP1
GXBL_1E_RXP3GXBL_1E_RXN3 GXBL_1E_TXP3GXBL_1E_TXN3
GXBL_1E_RXN4GXBL_1E_RXP4
GXBL_1E_RXN1GXBL_1E_RXP1
GXBL_1E_TXN4GXBL_1E_TXP4
QSFP1_VCC1QSFP1_VCCTXQSFP1_VCCRX
QSFP1_VCC1
QSFP1_VCCTX
3.3V
QSFP1_VCCRX
1.8V3.3V
1.8V3.3V
1.8V
1.8V
eQSFP_modselL1 29eQSFP_LPmode1 29eQSFP_resetL1 29
eQSFP_modprsL1 29eQSFP_intl1 29
eQSFP_sda1 29eQSFP_scl1 29
GXBL_1E_RXP0 33GXBL_1E_RXN0 33
GXBL_1E_TXP0 33GXBL_1E_TXN0 33
GXBL_1E_RXP1 33
GXBL_1E_TXN1 33GXBL_1E_TXP1 33
GXBL_1E_RXN1 33GXBL_1E_RXN3 33GXBL_1E_RXP3 33
GXBL_1E_TXN3 33GXBL_1E_TXP3 33
GXBL_1E_RXP4 33GXBL_1E_RXN4 33
GXBL_1E_TXP4 33GXBL_1E_TXN4 33
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B22 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B22 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B22 53Monday, March 13, 2017
C3040.1uF
R2954.7KL17 1.0uH
C3110.1uFR2884.7K
C31422uf
L15 1.0uH
R2904.7KR2944.7K
C3080.1uF
C3150.1uF
C30922uf
R2934.7KR292DNI
C3130.1uF
C3121uF
C30722uf
R291DNI
J28
zQSFP+
GND0 1
TX2n 2TX2p 3
GND1 4
TX4n 5TX4p 6
GND2 7
ModselL8ResetL9
VCCRX 10
SCL11SDA12
GND3 13
RX3p14RX3n15
GND4 16
RX1p17RX1n18
GND5 19GND6 20
RX2n21 RX2p22
GND7 23
RX4n24 RX4p25
GND8 26
ModPrsL27
Intl28VCCTX 29VCC1 30
LPMode31
GND9 32
TX3p 33TX3n 34
GND10 35
TX1p 36TX1n 37
GND11 38
C30522uF
U37
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
C3060.1uF
C3100.1uF
C3161uF
R2894.7K
L16 1.0uH
U38
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
C3170.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SFP+ Interface 0
SFP+ Interface
SFP modules have RS1 connected to GND.If using SFP+ Rate Select pin are defined as: RS1=0 -> TX datarates <= 4.25GB/sRS1=1 -> TX datarates > 4.25GB/sRS0=0 -> RX datarates <= 4.25GB/sRS0=1 -> RX datarates > 4.25GB/s
VEET / VEER needs tobe isolated from cageGND
Bypass Capacitors should be placed as close to the associated 20-pinconnector as possible.Assuming that the SFP RD 100-ohm termination on the Host Board FPGAdevice will be implemented via the on-chip termination circuit.DC blocking capacitors are in the module for RX and TX.
Optical (SFP+) Transceiver Cage & Connector
Cage GND on top layer
CAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
SFP0_T_RX_LOSSFP0_T_TX_FLT
SFP0_T_TX_DIS
SFP0_RX_LOSSFP0_TX_FLT
SFP0_T_RS0SFP0_T_RS1 SFP0_RS0SFP0_RS1
SFP0_RX_LOSSFP0_TX_FLTSFP0_TX_DISSFP0_MOD_ABS
SFP0_RS1SFP0_RS0SFP0_T_RS0SFP0_T_RS1
SFP0_T_MOD_ABSSFP0_T_RX_LOSSFP0_T_TX_FLT
SFP0_T_TX_DISSFP0_T_TX_DISSFP0_T_RS0SFP0_T_RS1SFP0_T_MOD_ABS
SFP0_T_RX_LOSSFP0_T_TX_FLT
SFP0_TX_DIS
SFP0_T_SDASFP0_T_SCL
SFP0_T_SDASFP0_T_SCL SFP0_SCLSFP0_SDA
SFP0_T_MOD_ABS SFP0_MOD_ABSGXBL_1K_RXN0GXBL_1K_RXP0
GXBL_1K_TXN0GXBL_1K_TXP0
1.8V 1.8V3.3V
1.8V
SFP0_VCCR
SFP0_VCCT3.3V
SFP0_VCCR SFP0_VCCT
3.3V
1.8V3.3V
1.8V
GND_SFP_CAGEGND_SFP_CAGE
SFP0_RS0 29SFP0_RS1 29SFP0_TX_DIS 29
SFP0_MOD_ABS 29SFP0_RX_LOS 29SFP0_TX_FLT 29
SFP0_SDA 29SFP0_SCL 29
GXBL_1K_RXP0 34GXBL_1K_RXN0 34
GXBL_1K_TXP0 34GXBL_1K_TXN0 34
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B23 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B23 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B23 53Monday, March 13, 2017
R306 DNI
C3291uF C3270.1uF
R310 DNI
R3004.7K
R75710.0K
R308 DNI
C3280.1uF
R3014.7K
L18 4.7uH1 2
L19 4.7uH1 2
R302 4.7K
C3260.1uF
C12364.7nF
C3190.1uF
R305 4.7K
C3210.1uFC324
0.1uF
R315 DNI
R307 4.7K
C3180.1uF
R314 DNIR312 4.7K
B6
SFP+_CAGE
CAGE_GND01CAGE_GND12CAGE_GND23CAGE_GND34CAGE_GND45CAGE_GND56CAGE_GND67
R313 4.7K
C3230.1uF
U39
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
R309 DNI
C32522uF
C3221uFR2984.7K
R311 DNI
R2994.7K
C32022uF
R303 DNI
J29
SFP+_CONN
VEET0 1VEET1 17VEET2 20RS19
VEER0 10VEER1 11VEER2 14
TD_P 18TD_N 19
RX_LOS 8TX_FAULT 2
VCCT16VCCR15
RD_P13RD_N12
TX_DISABLE3RS07
MOD_ABS6SCL5SDA4
U40
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SFP+ Interface 1
SFP+ Interface
SFP modules have RS1 connected to GND.If using SFP+ Rate Select pin are defined as: RS1=0 -> TX datarates <= 4.25GB/sRS1=1 -> TX datarates > 4.25GB/sRS0=0 -> RX datarates <= 4.25GB/sRS0=1 -> RX datarates > 4.25GB/s
VEET / VEER needs tobe isolated from cageGND
Bypass Capacitors should be placed as close to the associated 20-pinconnector as possible.Assuming that the SFP RD 100-ohm termination on the Host Board FPGAdevice will be implemented via the on-chip termination circuit.DC blocking capacitors are in the module for RX and TX.
Optical (SFP+) Transceiver Cage & ConnectorCAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
SFP1_T_TX_DIS
SFP1_T_SDASFP1_T_SCL
SFP1_T_SDASFP1_T_SCL SFP1_SCLSFP1_SDA
SFP1_T_MOD_ABS SFP1_MOD_ABS
SFP1_T_TX_DIS
SFP1_T_TX_FLTSFP1_T_RX_LOS SFP1_TX_FLTSFP1_RX_LOS
SFP1_RS0SFP1_RS1SFP1_T_RS0SFP1_T_RS1
SFP1_RX_LOSSFP1_TX_FLTSFP1_TX_DISSFP1_MOD_ABS
SFP1_RS1SFP1_RS0SFP1_T_RS0SFP1_T_RS1
SFP1_T_MOD_ABSSFP1_T_RX_LOSSFP1_T_TX_FLT
SFP1_T_TX_DISSFP1_T_RS0SFP1_T_RS1SFP1_T_MOD_ABS
SFP1_TX_DIS
SFP1_T_RX_LOSSFP1_T_TX_FLT
GXBL_1K_TXN3GXBL_1K_TXP3
GXBL_1K_RXP3GXBL_1K_RXN3
1.8V1.8V3.3V
1.8V
3.3V
SFP1_VCCR SFP1_VCCT
3.3V
1.8V3.3V
SFP1_VCCT
SFP1_VCCR
1.8V
SFP1_RS0 29SFP1_RS1 29SFP1_TX_DIS 29
SFP1_MOD_ABS 29SFP1_RX_LOS 29SFP1_TX_FLT 29
SFP1_SDA 29SFP1_SCL 29
GXBL_1K_RXP3 34GXBL_1K_RXN3 34
GXBL_1K_TXN3 34GXBL_1K_TXP3 34
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B24 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B24 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B24 53Monday, March 13, 2017
C3330.1uF
U42
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
L21 4.7uH1 2
J30
SFP+_CONN
VEET0 1VEET1 17VEET2 20RS19
VEER0 10VEER1 11VEER2 14
TD_P 18TD_N 19
RX_LOS 8TX_FAULT 2
VCCT16VCCR15
RD_P13RD_N12
TX_DISABLE3RS07
MOD_ABS6SCL5SDA4
C3310.1uF
R322 4.7K
C3390.1uF
C3341uF
R326 4.7K
C3360.1uF
R327 4.7K
C3400.1uF
C3411uF
R332 4.7K
C3300.1uF
R333 4.7K
C3350.1uF
R329 DNI
R3204.7KC33722uF
R331 DNI
R3214.7K
R335 DNIR334 DNI
R323 DNIR324 DNI
C33222uF
R3184.7K
R330 DNI
C3380.1uF
U41
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
R328 DNI
R3194.7K
L20 4.7uH1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MXP / 2.4mm Connectors
PLATINUM CHANNEL - 2.4mm SMA PLATINUM CHANNEL - 2.4mm SMA
GOLD CHANNEL - 2.4mm SMAGOLD CHANNEL - 2.4mm SMA
MXP0
MXP1
MXP2
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
GXBR4C_RXP2
GXBR4C_RXN2
GXBR4C_RXN5
GXBR4C_RXP5
GXBR4C_RXN0
GXBR4C_RXP1
GXBR4C_RXN1
GXBR4C_RXP0
GXBR_4F_RXP4GXBR_4F_RXN4
GXBR_4F_RXP1GXBR_4F_RXN1GXBR_4F_TXN1GXBR_4F_TXP1
GXBR_4F_TXN4GXBR_4F_TXP4
GXBR4F_RXN1GXBR4F_RXP1
GXBR4F_RXN4GXBR4F_RXP4
GXBR_4D_RXN3GXBR_4D_RXN4GXBR_4D_RXP4GXBR4D_RXN4GXBR4D_RXP4
GXBR4D_RXN0GXBR4D_RXP0GXBR_4D_RXP1GXBR_4D_RXN1GXBR4D_RXN1GXBR4D_RXP1GXBR_4D_RXP3GXBR4D_RXP3GXBR4D_RXN3
GXBR_4D_TXN1GXBR_4D_TXP1GXBR_4D_TXN3GXBR_4D_TXP3GXBR_4D_TXN4GXBR_4D_TXP4
GXBR_4E_TXP1GXBR_4E_TXN1
GXBR_4E_TXP3GXBR_4E_TXN3GXBR_4E_TXN4GXBR_4E_TXP4
GXBR_4E_RXN0GXBR_4E_RXP0GXBR4E_RXP0GXBR4E_RXN0
GXBR_4E_RXP1GXBR_4E_RXN1GXBR4E_RXN1GXBR4E_RXP1
GXBR_4E_RXP4GXBR_4E_RXN4GXBR4E_RXP3GXBR4E_RXN3GXBR4E_RXN4GXBR4E_RXP4
GXBR_4E_RXN3GXBR_4E_RXP3
GXBR_4F_TXP0GXBR_4F_TXN0
GXBR_4F_TXN3GXBR_4F_TXP3 GXBR_4F_RXP3GXBR_4F_RXN3GXBR4F_RXP3GXBR4F_RXN3
GXBR_4F_RXN0GXBR_4F_RXP0GXBR4F_RXN0GXBR4F_RXP0
GXBR4C_RXP3
GXBR4C_RXN3
GXBR4C_RXP4
GXBR4C_RXN4
GXBR_4D_RXP0GXBR_4D_RXN0
GXBR_4E_TXP0GXBR_4E_TXN0
GXBR_4D_TXN0GXBR_4D_TXP0
GXBR_4D_RXN0 35GXBR_4D_RXP0 35
GXBR_4D_RXN1 35GXBR_4D_RXP1 35GXBR_4D_RXP3 35GXBR_4D_RXN3 35GXBR_4D_RXN4 35GXBR_4D_RXP4 35
GXBR_4D_TXP0 35GXBR_4D_TXN0 35GXBR_4D_TXP1 35GXBR_4D_TXN1 35GXBR_4D_TXN3 35GXBR_4D_TXP3 35
GXBR_4D_TXN4 35GXBR_4D_TXP4 35
GXBR_4E_RXN0 35GXBR_4E_RXP0 35 GXBR_4E_TXP0 35GXBR_4E_TXN0 35
GXBR_4F_RXN0 35GXBR_4F_RXP0 35 GXBR_4F_TXP0 35GXBR_4F_TXN0 35
GXBR_4C_RXP2 35
GXBR_4C_RXN2 35
GXBR_4C_TXP235
GXBR_4C_TXN235
GXBR_4C_RXP5 35
GXBR_4C_TXN535
GXBR_4C_TXP535
GXBR_4C_RXN5 35
GXBR_4C_TXP035
GXBR_4C_TXN035
GXBR_4C_RXP0 35
GXBR_4C_RXN0 35
GXBR_4C_RXP1 35 GXBR_4C_TXP135
GXBR_4C_TXN135GXBR_4C_RXN1 35
GXBR_4E_RXP1 35GXBR_4E_RXN1 35 GXBR_4E_TXN1 35GXBR_4E_TXP1 35GXBR_4E_RXP3 35GXBR_4E_RXN3 35 GXBR_4E_TXN3 35GXBR_4E_TXP3 35
GXBR_4E_RXN4 35GXBR_4E_RXP4 35 GXBR_4E_TXP4 35GXBR_4E_TXN4 35
GXBR_4F_TXP1 35GXBR_4F_TXN1 35GXBR_4F_RXP1 35GXBR_4F_RXN1 35
GXBR_4F_TXP3 35GXBR_4F_TXN3 35GXBR_4F_RXP3 35GXBR_4F_RXN3 35
GXBR_4F_TXN4 35GXBR_4F_TXP4 35GXBR_4F_RXN4 35GXBR_4F_RXP4 35
GXBR_4C_RXP3 35
GXBR_4C_RXN3 35
GXBR_4C_RXP4 35
GXBR_4C_RXN4 35
GXBR_4C_TXN335
GXBR_4C_TXP335
GXBR_4C_TXN435
GXBR_4C_TXP435
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B25 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B25 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B25 53Monday, March 13, 2017
SCRW22
C350 68nF
C372 68nF
VIA - GND
J312.4mm
C37568nF
SCRW11
C356 68nF
VIA - GNDJ562.4mm
SCRW33
C36568nF
C35168nF
C352 68nF
SCRW12
VIA - GND J352.4mm
SCRW23
SCRW34
SCRW45
C357 68nFC35368nF
SCRW24
SCRW35
SCRW46
VIA - GND
J512.4mm
VIA - GND
J362.4mm
VIA - GND
J572.4mm
SCRW13
C35468nF
C369 68nF
VIA - GND J522.4mm
SCRW36
SCRW47VIA - GNDJ34
2.4mm
C36368nF
SCRW14
2X8 M
XP
J44
2x8 MXP
1 12 23 34 45 56 67 78 899 1010 1111 1212 1313 1414 1515 1616
M1M1
M2M2
SCRW25
C35568nF
C370 68nF
SCRW48
C358 68nF
SCRW26
VIA - GND J552.4mm
VIA - GNDJ532.4mm
SCRW15
C359 68nF
C362 68nF
SCRW37
VIA - GND
J402.4mm
C36668nF
SCRW16
VIA - GND
J472.4mm
C348 68nF
SCRW27 VIA - GND
J432.4mm
SCRW38
C364 68nF
SCRW49
2X8 M
XP
J33
2x8 MXP
1 12 23 34 45 56 67 78 899 1010 1111 1212 1313 1414 1515 1616
M1M1
M2M2
SCRW28
SCRW39
C349 68nF
SCRW50
SCRW53
SCRW17
SCRW40
SCRW51
VIA - GND J422.4mm
VIA - GND J452.4mm
C367 68nF
VIA - GNDJ412.4mm
VIA - GNDJ382.4mm
SCRW54
SCRW18
2X8 M
XP
J50
2x8 MXP
1 12 23 34 45 56 67 78 899 1010 1111 1212 1313 1414 1515 1616
M1M1
M2M2
C343 68nF
SCRW52
VIA - GND
J372.4mm
SCRW55
C368 68nF
SCRW29
C37668nF
C344 68nF
VIA - GND
J462.4mm
C34668nF
SCRW56
SCRW19
SCRW30
SCRW41
C37768nF
VIA - GND J392.4mm
SCRW20
C34268nF
SCRW31
SCRW9
SCRW42
C345 68nF
C360 68nF
C373 68nFSCRW32
SCRW43
VIA - GNDJ482.4mm
VIA - GND
J542.4mm
SCRW10
C347 68nF
VIA - GND
J492.4mm
SCRW21
C371 68nF
C361 68nF
VIA - GND
J322.4mm
SCRW44
C374 68nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FMC+ (Port A)
I2C Address: b' 101 0010
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
FATRST
FAPRSNT_N
FAGA1 FAGA0
FAPG_C2M
FATRST
FAGA0FAGA1
FAPG_M2C 3.3V
12VFAM2CVIO
FAREFBFAREFA
FMCA_VADJ
3.3V
3.3V_STBY
3.3V
FALAP030 FALAN030 FALAP130 FALAN130 FALAP230 FALAN230FALAN330 FALAP330
FALAN430 FALAP430FALAP530 FALAN530 FALAP630 FALAN630 FALAP730 FALAN730FALAP830 FALAN830FALAN930 FALAP930FALAP1030 FALAN1030FALAN1130 FALAP1130
FALAP1230 FALAN1230FALAN1330 FALAP1330
FALAN1430 FALAP1430
FALAN1530 FALAP1530
FALAN16 30FALAP16 30FALAP17 32FALAN17 32FALAN18 32FALAP18 32FALAP19 32FALAN19 32
FALAN20 32FALAP20 32FALAP21 32FALAN21 32FALAN22 32FALAP22 32
FALAN23 32FALAP23 32
FALAN24 32FALAP24 32
FALAN25 32FALAP25 32
FALAN26 32FALAP26 32FALAP27 32FALAN27 32
FALAN28 32FALAP28 32FALAP29 32FALAN29 32FALAN30 32FALAP30 32FALAP31 32FALAN31 32FALAP32 32FALAN32 32FALAP33 32FALAN33 32
FAHBP032 FAHBN032 FAHBP132 FAHBN132 FAHBP232 FAHBN232 FAHBP332 FAHBN332
FAHBN432 FAHBP432FAHBP532 FAHBN532FAHBN632 FAHBP632FAHBP732 FAHBN732
FAHBN832 FAHBP832
FAHBN932 FAHBP932
FAHBN1032 FAHBP1032
FAHBN11 32FAHBP11 32FAHBP12 32FAHBN12 32FAHBP13 32FAHBN13 32FAHBN14 32FAHBP14 32
FAHBP15 32FAHBN15 32FAHBN16 32FAHBP16 32FAHBP17 32FAHBN17 32FAHBN18 32FAHBP18 32
FAHBN19 32FAHBP19 32
FAHBN20 32FAHBP20 32
FAHBN21 32FAHBP21 32
FAHAP032 FAHAN032 FAHAP132 FAHAN132FAHAN232 FAHAP232FAHAP332 FAHAN332
FAHAN432 FAHAP432FAHAP532 FAHAN532FAHAN632 FAHAP632
FAHAN732 FAHAP732
FAHAN832 FAHAP832FAHAP932 FAHAN932FAHAN1032 FAHAP1032FAHAP1132 FAHAN1132
FAHAN12 32FAHAP12 32FAHAP13 32FAHAN13 32FAHAN14 32FAHAP14 32FAHAP15 32FAHAN15 32
FAHAN16 32FAHAP16 32FAHAP17 32FAHAN17 32FAHAN18 32FAHAP18 32
FAHAN19 32FAHAP19 32
FAHAN20 32FAHAP20 32FAHAP21 32FAHAN21 32FAHAN22 32FAHAP22 32FAHAP23 32FAHAN23 32
FAPRSNT_N8,11,32EXTA_SDA32
EXTA_SCL32FACLKBIDIRP232 FACLKBIDIRN232 FACLKBIDIRP332 FACLKBIDIRN332
FAM2CP0 36FAM2CN0 36FAM2CP1 36FAM2CN1 36FAM2CN2 36FAM2CP2 36FAM2CP3 36FAM2CN3 36FAM2CN4 36FAM2CP4 36
FAC2MP036 FAC2MN036 FAC2MP136 FAC2MN136FAC2MN236 FAC2MP236FAC2MP336 FAC2MN336FAC2MN436 FAC2MP436
FAC2MN536 FAC2MP536
FAC2MN636 FAC2MP636
FAC2MN736 FAC2MP736FAC2MP836 FAC2MN836FAC2MN936 FAC2MP936FAC2MP1036 FAC2MN1036FAC2MN1136 FAC2MP1136FAC2MP1236 FAC2MN1236FAC2MN1336 FAC2MP1336
FAC2MN1436 FAC2MP1436
FAC2MN1536 FAC2MP1536
FAC2MN1636 FAC2MP1636FAC2MP1736 FAC2MN1736FAC2MN1836 FAC2MP1836FAC2MP1936 FAC2MN1936FAC2MN2036 FAC2MP2036FAC2MP2136 FAC2MN2136 FAC2MP2236 FAC2MN2236 FAC2MP2336 FAC2MN2336
FAM2CP5 36FAM2CN5 36FAM2CN6 36FAM2CP6 36
FAM2CN7 36FAM2CP7 36
FAM2CN8 36FAM2CP8 36
FAM2CN9 36FAM2CP9 36
FAM2CN10 36FAM2CP10 36FAM2CP11 36FAM2CN11 36FAM2CN12 36FAM2CP12 36
FAM2CN13 36FAM2CP13 36
FAM2CN14 36FAM2CP14 36
FAM2CN15 36FAM2CP15 36FAM2CP16 36FAM2CN16 36FAM2CN17 36FAM2CP17 36FAM2CP18 36FAM2CN18 36FAM2CN19 36FAM2CP19 36FAM2CP20 36FAM2CN20 36FAM2CP21 36FAM2CN21 36FAM2CP22 36FAM2CN22 36FAM2CP23 36FAM2CN23 36FAGBTCLKM2CP0 36FAGBTCLKM2CN0 36FAGBTCLKM2CP1 36FAGBTCLKM2CN1 36FAGBTCLKM2CP2 36FAGBTCLKM2CN2 36
FAGBTCLKM2CP336 FAGBTCLKM2CN336
FATMS 8FATDI 8FATCK 8FATDO 8
FACLKM2CP0 30FACLKM2CN0 30FACLKM2CP1 32FACLKM2CN1 32
FAPG_M2C 10FAPG_C2M10
FACLKDIR32
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C26 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C26 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C26 53Monday, March 13, 2017
J58A
ASP-184329-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16 G19
LA_N17_CC D21
LA_N18_CC C23
LA_N19 H23LA_N2H8
LA_N20 G22
LA_N21 H26
LA_N22 G25
LA_N23 D24
LA_N24 H29
LA_N25 G28
LA_N26 D27
LA_N27 C27
LA_N28 H32
LA_N29 G31
LA_N3G10
LA_N30 H35
LA_N31 G34
LA_N32 H38
LA_N33 G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16 G18
LA_P17_CC D20
LA_P18_CC C22
LA_P19 H22LA_P2H7
LA_P20 G21
LA_P21 H25
LA_P22 G24
LA_P23 D23
LA_P24 H28
LA_P25 G27
LA_P26 D26
LA_P27 C26
LA_P28 H31
LA_P29 G30
LA_P3G9
LA_P30 H34
LA_P31 G33
LA_P32 H37
LA_P33 G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
V117
C383 10uF
R340 100K
C386 10uF
C378 1uF
V118
C385 10uF
C379 1uF
V113
V119
C380 10uF
V120
R338 100K C381 10uF
R735DNI
V121
J58C
ASP-184329-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11 J31
HB_N12 F32
HB_N13 E31
HB_N14 K35
HB_N15 J34
HB_N16 F35
HB_N17_CC K38
HB_N18 J37
HB_N19 E34
HB_N2F23
HB_N20 F38
HB_N21 E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11 J30
HB_P12 F31
HB_P13 E30
HB_P14 K34
HB_P15 J33
HB_P16 F34
HB_P17_CC K37
HB_P18 J36
HB_P19 E33
HB_P2F22
HB_P20 F37
HB_P21 E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
R736DNI
C384 1uF
R343 1.00K
V114
J58B
ASP-184329-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12 F14
HA_N13 E13
HA_N14 J16
HA_N15 F17
HA_N16 E16
HA_N17_CC K17
HA_N18 J19
HA_N19 F20
HA_N2K8
HA_N20 E19
HA_N21 K20
HA_N22 J22
HA_N23 K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12 F13
HA_P13 E12
HA_P14 J15
HA_P15 F16
HA_P16 E15
HA_P17_CC K16
HA_P18 J18
HA_P19 F19
HA_P2K7
HA_P20 E18
HA_P21 K19
HA_P22 J21
HA_P23 K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
R7371.00K
J58D
ASP-184329-01
DP0_C2M_NC3 DP0_C2M_PC2DP0_M2C_N C7DP0_M2C_P C6
DP1_C2M_NA23 DP1_C2M_PA22DP1_M2C_N A3DP1_M2C_P A2
DP2_C2M_NA27 DP2_C2M_PA26DP2_M2C_N A7DP2_M2C_P A6
DP3_C2M_NA31 DP3_C2M_PA30DP3_M2C_N A11DP3_M2C_P A10
DP4_C2M_NA35 DP4_C2M_PA34DP4_M2C_N A15DP4_M2C_P A14
DP5_C2M_NA39 DP5_C2M_PA38DP5_M2C_N A19DP5_M2C_P A18
DP6_C2M_NB37 DP6_C2M_PB36DP6_M2C_N B17DP6_M2C_P B16
DP7_C2M_NB33 DP7_C2M_PB32DP7_M2C_N B13DP7_M2C_P B12
DP8_C2M_NB29 DP8_C2M_PB28DP8_M2C_N B9DP8_M2C_P B8
DP9_C2M_NB25 DP9_C2M_PB24DP9_M2C_N B5DP9_M2C_P B4
GBTCLK0_M2C_N D5GBTCLK0_M2C_P D4
GBTCLK1_M2C_N B21GBTCLK1_M2C_P B20
DP10_C2M_PZ24DP10_C2M_NZ25DP11_C2M_PY26DP11_C2M_NY27DP12_C2M_PZ28DP12_C2M_NZ29DP13_C2M_PY30DP13_C2M_NY31DP14_C2M_PM18DP14_C2M_NM19DP15_C2M_PM22DP15_C2M_NM23DP16_C2M_PM26DP16_C2M_NM27DP17_C2M_PM30DP17_C2M_NM31DP18_C2M_PM34DP18_C2M_NM35DP19_C2M_PM38DP19_C2M_NM39DP20_C2M_PZ8DP20_C2M_NZ9DP21_C2M_PY6DP21_C2M_NY7DP22_C2M_PZ4DP22_C2M_NZ5DP23_C2M_PY2DP23_C2M_NY3
DP10_M2C_P Y10DP10_M2C_N Y11DP11_M2C_P Z12DP11_M2C_N Z13DP12_M2C_P Y14DP12_M2C_N Y15DP13_M2C_P Z16DP13_M2C_N Z17DP14_M2C_P Y18DP14_M2C_N Y19DP15_M2C_P Y22DP15_M2C_N Y23DP16_M2C_P Z32DP16_M2C_N Z33DP17_M2C_P Y34DP17_M2C_N Y35DP18_M2C_P Z36DP18_M2C_N Z37DP19_M2C_P Y38DP19_M2C_N Y39DP20_M2C_P M14DP20_M2C_N M15DP21_M2C_P M10DP21_M2C_N M11DP22_M2C_P M6DP22_M2C_N M7DP23_M2C_P M2DP23_M2C_N M3
GBTCLK2_M2C_P L12GBTCLK2_M2C_N L13
GBTCLK3_M2C_PL8GBTCLK3_M2C_NL9GBTCLK4_M2C_PL4GBTCLK4_M2C_NL5GBTCLK5_M2C_PZ20GBTCLK5_M2C_NZ21
R739 DNIV115
R339 100K
V122
V116R7381.00K
V123
J58F
ASP-184329-01
GND8K2GND9K3GND10K6GND11K9GND12K12GND13K15GND14K18GND15K21GND16K24GND17K27GND18K30GND19K33GND20K36GND21K39GND22J1GND23J4GND24J5GND25J8GND26J11GND27J14GND28J17GND29J20GND30J23GND31J26GND32J29GND33J32GND34J35GND35J38GND36J40GND37H3GND38H6GND39H9GND40H12GND41H15GND42H18GND43H21GND44H24GND45H27GND46H30GND47H33GND48H36GND49H39GND50D2GND51D3GND52D6GND53D7GND54D10GND55D13GND56D16GND57D19GND58D22GND59D25GND60D28GND61D37GND62D39GND63C1GND64C4GND65C5GND66C8GND67C9GND68C12GND69C13GND70C16GND71C17GND72C20GND73C21GND74C24GND75C25GND76C28GND77C29GND78C32GND79C33 GND118 C36GND117 C38GND116 C40GND115 B2GND114 B3GND113 B6GND112 B7GND111 B10GND110 B11GND159 B14GND158 B15GND157 B18GND156 B19GND155 B22GND154 B23GND153 B26GND152 B27GND151 B30GND150 B31GND149 B34GND148 B35GND147 B38GND146 B39GND145 A1GND144 A4GND143 A5GND142 A8GND141 A9GND140 A12GND139 A13GND138 A16GND137 A17GND136 A20GND135 A21GND134 A24GND133 A25GND132 A28GND131 A29GND130 A32GND129 A33GND128 A36GND127 A37GND126 A40GND125 G1GND124 G4GND123 G5GND122 G8GND121 G11GND120 G14GND109 G17GND108 G20GND107 G23GND106 G26GND105 G29GND104 G32GND103 G35GND102 G38GND101 G40GND100 F2GND99 F3GND98 F6GND97 F9GND96 F12GND95 F15GND94 F18GND93 F21GND92 F24GND91 F27GND90 F30GND89 F33GND88 F36GND87 F39GND86 E1GND85 E4GND84 E5GND83 E8GND82 E11GND81 E14GND80 E17GND0E20GND1E23GND2E26GND3E29
GND5E32GND6E35GND4E38
GND7E40
V124
J58E
ASP-184329-01
CLK_DIRB1 CLK0_M2C_N H5CLK0_M2C_P H4
CLK1_M2C_N G3CLK1_M2C_P G2CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34GA1D35
PG_C2MD1 PG_M2C F1
PRSNT_M2C_LH2
RES0 B40
SCLC30 SDAC31
TCK D29TDI D30TDO D31TMS D33TRST_L D34
3P3VAUXD32
3P3V0D403P3V1C393P3V2D363P3V3D38
12P0V0C3512P0V1C37
VADJ0 E39VADJ1 F40VADJ2 G39VADJ3 H40
VIO_B_M2C_0 K40VIO_B_M2C_1 J39
VREF_B_M2C K1VREF_A_M2C H1
3P3V4Z40
12P0V4L4012P0V2L3612P0V3L37
RES1 L1
REFCLK_M2C_PL24REFCLK_M2C_NL25
SYNC_C2M_P L16SYNC_C2M_N L17
HSPC_PRSNT_M2C_LZ1RES2 L32RES3 L33
REFCLK_C2M_PL20REFCLK_C2M_NL21
SYNC_M2C_N L29SYNC_M2C_P L28
J58G
ASP-184329-01
GND119M1GND160M4GND161M5GND162M8GND163M9GND164M12GND165M13GND166M16GND167M17GND168M20GND169M21GND170M24GND171M25GND172M28GND173M29GND174M32GND175M33GND176M36GND177M37GND178M40GND179L2GND180L3GND181L6GND182L7GND183L10GND184L11GND185L14GND186L15GND187L18GND188L19GND189L22GND190L23GND191L26GND192L27GND193L30GND194L31GND195L34GND196L35GND197L38GND198L39
GND219 Z2GND220 Z3GND221 Z6GND222 Z7GND223 Z10GND224 Z11GND225 Z14GND226 Z15GND227 Z18GND228 Z19GND229 Z22GND230 Z23GND231 Z26GND232 Z27GND233 Z30GND234 Z31GND235 Z34GND236 Z35GND237 Z38GND238 Z39
GND200 Y4GND201 Y5GND202 Y8GND203 Y9GND204 Y12GND205 Y13GND206 Y16GND207 Y17GND208 Y20GND209 Y21GND210 Y24GND211 Y25GND212 Y28GND213 Y29GND214 Y32GND215 Y33GND216 Y36GND217 Y37GND218 Y40
GND199 Y1
C382 10uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FMC+ (Port B)
I2C Address: b' 101 0011
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
FBGA1 FBGA0
FBPRSNT_N
FBPG_C2M
FBPG_C2M
FBTRST
FBTRST
FBGA0FBGA1
FBPG_M2C
3.3V
12V
FMCB_VADJ3.3V
3.3V_STBY
FBREFA
3.3V
FBLAN130 FBLAP130
FBLAN230 FBLAP230FBLAP330 FBLAN330
FBLAN430 FBLAP430FBLAP530 FBLAN530FBLAN630 FBLAP630FBLAP730 FBLAN730FBLAP830 FBLAN830 FBLAP930 FBLAN930 FBLAP1030 FBLAN1030FBLAN1130 FBLAP1130
FBLAP1230 FBLAN1230FBLAN1330 FBLAP1330FBLAP1430 FBLAN1430FBLAN1530 FBLAP1530
FBLAP030 FBLAN030FBLAN17 30FBLAP17 30FBLAP18 30FBLAN18 30FBLAN19 30FBLAP19 30
FBLAP20 30FBLAN20 30FBLAP21 30FBLAN21 30FBLAP22 30FBLAN22 30FBLAP23 30FBLAN23 30
FBLAN24 30FBLAP24 30FBLAP25 30FBLAN25 30FBLAN26 30FBLAP26 30FBLAP27 30FBLAN27 30
FBLAN28 30FBLAP28 30
FBLAN29 30FBLAP29 30
FBLAN30 30FBLAP30 30
FBLAN31 30FBLAP31 30FBLAP32 30FBLAN32 30FBLAN33 30FBLAP33 30
FBPRSNT_N8,11,30EXTB_SDA30
EXTB_SCL30
FBLAN16 30FBLAP16 30
FBC2MN10 34FBC2MP10 34
FBM2CP1034 FBM2CN1034
FBC2MN1134 FBC2MP1134
FBC2MP1234 FBC2MN1234
FBC2MN1334 FBC2MP1334
FBC2MP14 34FBC2MN14 34
FBC2MN15 34FBC2MP15 34
FBM2CN1134 FBM2CP1134
FBM2CP1234 FBM2CN1234
FBM2CN1334 FBM2CP1334
FBM2CP14 34FBM2CN14 34
FBM2CN15 34FBM2CP15 34
FBGBTCLKM2CP0 34FBGBTCLKM2CN0 34FBGBTCLKM2CP1 34FBGBTCLKM2CN1 34
FBM2CN1 34FBM2CP1 34
FBM2CN2 34FBM2CP2 34
FBM2CN3 34FBM2CP3 34FBM2CP4 34FBM2CN4 34
FBM2CP0 34FBM2CN0 34
FBM2CN5 34FBM2CP5 34FBM2CP6 34FBM2CN6 34FBM2CN7 34FBM2CP7 34FBM2CP8 34FBM2CN8 34FBM2CN9 34FBM2CP9 34
FBC2MN134 FBC2MP134FBC2MP234 FBC2MN234 FBC2MP334 FBC2MN334 FBC2MP434 FBC2MN434
FBC2MP034 FBC2MN034
FBC2MN534 FBC2MP534FBC2MP634 FBC2MN634FBC2MN734 FBC2MP734FBC2MP834 FBC2MN834FBC2MN934 FBC2MP934
FBPG_C2M10 FBPG_M2C 10
FBTMS 8FBTDI 9FBTCK 9FBTDO 9
FBCLKM2CP0 30FBCLKM2CN0 30FBCLKM2CP1 30FBCLKM2CN1 30
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C27 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C27 53Tuesday, April 11, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C27 53Tuesday, April 11, 2017
R351 100K
J59F
ASP-184329-01
GND8K2GND9K3GND10K6GND11K9GND12K12GND13K15GND14K18GND15K21GND16K24GND17K27GND18K30GND19K33GND20K36GND21K39GND22J1GND23J4GND24J5GND25J8GND26J11GND27J14GND28J17GND29J20GND30J23GND31J26GND32J29GND33J32GND34J35GND35J38GND36J40GND37H3GND38H6GND39H9GND40H12GND41H15GND42H18GND43H21GND44H24GND45H27GND46H30GND47H33GND48H36GND49H39GND50D2GND51D3GND52D6GND53D7GND54D10GND55D13GND56D16GND57D19GND58D22GND59D25GND60D28GND61D37GND62D39GND63C1GND64C4GND65C5GND66C8GND67C9GND68C12GND69C13GND70C16GND71C17GND72C20GND73C21GND74C24GND75C25GND76C28GND77C29GND78C32GND79C33 GND118 C36GND117 C38GND116 C40GND115 B2GND114 B3GND113 B6GND112 B7GND111 B10GND110 B11GND159 B14GND158 B15GND157 B18GND156 B19GND155 B22GND154 B23GND153 B26GND152 B27GND151 B30GND150 B31GND149 B34GND148 B35GND147 B38GND146 B39GND145 A1GND144 A4GND143 A5GND142 A8GND141 A9GND140 A12GND139 A13GND138 A16GND137 A17GND136 A20GND135 A21GND134 A24GND133 A25GND132 A28GND131 A29GND130 A32GND129 A33GND128 A36GND127 A37GND126 A40GND125 G1GND124 G4GND123 G5GND122 G8GND121 G11GND120 G14GND109 G17GND108 G20GND107 G23GND106 G26GND105 G29GND104 G32GND103 G35GND102 G38GND101 G40GND100 F2GND99 F3GND98 F6GND97 F9GND96 F12GND95 F15GND94 F18GND93 F21GND92 F24GND91 F27GND90 F30GND89 F33GND88 F36GND87 F39GND86 E1GND85 E4GND84 E5GND83 E8GND82 E11GND81 E14GND80 E17GND0E20GND1E23GND2E26GND3E29
GND5E32GND6E35GND4E38
GND7E40
J59G
ASP-184329-01
GND119M1GND160M4GND161M5GND162M8GND163M9GND164M12GND165M13GND166M16GND167M17GND168M20GND169M21GND170M24GND171M25GND172M28GND173M29GND174M32GND175M33GND176M36GND177M37GND178M40GND179L2GND180L3GND181L6GND182L7GND183L10GND184L11GND185L14GND186L15GND187L18GND188L19GND189L22GND190L23GND191L26GND192L27GND193L30GND194L31GND195L34GND196L35GND197L38GND198L39
GND219 Z2GND220 Z3GND221 Z6GND222 Z7GND223 Z10GND224 Z11GND225 Z14GND226 Z15GND227 Z18GND228 Z19GND229 Z22GND230 Z23GND231 Z26GND232 Z27GND233 Z30GND234 Z31GND235 Z34GND236 Z35GND237 Z38GND238 Z39
GND200 Y4GND201 Y5GND202 Y8GND203 Y9GND204 Y12GND205 Y13GND206 Y16GND207 Y17GND208 Y20GND209 Y21GND210 Y24GND211 Y25GND212 Y28GND213 Y29GND214 Y32GND215 Y33GND216 Y36GND217 Y37GND218 Y40
GND199 Y1
C389 10uF
J59C
ASP-184329-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11 J31
HB_N12 F32
HB_N13 E31
HB_N14 K35
HB_N15 J34
HB_N16 F35
HB_N17_CC K38
HB_N18 J37
HB_N19 E34
HB_N2F23
HB_N20 F38
HB_N21 E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11 J30
HB_P12 F31
HB_P13 E30
HB_P14 K34
HB_P15 J33
HB_P16 F34
HB_P17_CC K37
HB_P18 J36
HB_P19 E33
HB_P2F22
HB_P20 F37
HB_P21 E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
R356DNI
J59E
ASP-184329-01
CLK_DIRB1 CLK0_M2C_N H5CLK0_M2C_P H4
CLK1_M2C_N G3CLK1_M2C_P G2CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34GA1D35
PG_C2MD1 PG_M2C F1
PRSNT_M2C_LH2
RES0 B40
SCLC30 SDAC31
TCK D29TDI D30TDO D31TMS D33TRST_L D34
3P3VAUXD32
3P3V0D403P3V1C393P3V2D363P3V3D38
12P0V0C3512P0V1C37
VADJ0 E39VADJ1 F40VADJ2 G39VADJ3 H40
VIO_B_M2C_0 K40VIO_B_M2C_1 J39
VREF_B_M2C K1VREF_A_M2C H1
3P3V4Z40
12P0V4L4012P0V2L3612P0V3L37
RES1 L1
REFCLK_M2C_PL24REFCLK_M2C_NL25
SYNC_C2M_P L16SYNC_C2M_N L17
HSPC_PRSNT_M2C_LZ1RES2 L32RES3 L33
REFCLK_C2M_PL20REFCLK_C2M_NL21
SYNC_M2C_N L29SYNC_M2C_P L28
R357DNI
R3531.00K
J59B
ASP-184329-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12 F14
HA_N13 E13
HA_N14 J16
HA_N15 F17
HA_N16 E16
HA_N17_CC K17
HA_N18 J19
HA_N19 F20
HA_N2K8
HA_N20 E19
HA_N21 K20
HA_N22 J22
HA_N23 K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12 F13
HA_P13 E12
HA_P14 J15
HA_P15 F16
HA_P16 E15
HA_P17_CC K16
HA_P18 J18
HA_P19 F19
HA_P2K7
HA_P20 E18
HA_P21 K19
HA_P22 J21
HA_P23 K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
R355 100K
R3521.00K
J59A
ASP-184329-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16 G19
LA_N17_CC D21
LA_N18_CC C23
LA_N19 H23LA_N2H8
LA_N20 G22
LA_N21 H26
LA_N22 G25
LA_N23 D24
LA_N24 H29
LA_N25 G28
LA_N26 D27
LA_N27 C27
LA_N28 H32
LA_N29 G31
LA_N3G10
LA_N30 H35
LA_N31 G34
LA_N32 H38
LA_N33 G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16 G18
LA_P17_CC D20
LA_P18_CC C22
LA_P19 H22LA_P2H7
LA_P20 G21
LA_P21 H25
LA_P22 G24
LA_P23 D23
LA_P24 H28
LA_P25 G27
LA_P26 D26
LA_P27 C26
LA_P28 H31
LA_P29 G30
LA_P3G9
LA_P30 H34
LA_P31 G33
LA_P32 H37
LA_P33 G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
C391 10uF
J59D
ASP-184329-01
DP0_C2M_NC3 DP0_C2M_PC2DP0_M2C_N C7DP0_M2C_P C6
DP1_C2M_NA23 DP1_C2M_PA22DP1_M2C_N A3DP1_M2C_P A2
DP2_C2M_NA27 DP2_C2M_PA26DP2_M2C_N A7DP2_M2C_P A6
DP3_C2M_NA31 DP3_C2M_PA30DP3_M2C_N A11DP3_M2C_P A10
DP4_C2M_NA35 DP4_C2M_PA34DP4_M2C_N A15DP4_M2C_P A14
DP5_C2M_NA39 DP5_C2M_PA38DP5_M2C_N A19DP5_M2C_P A18
DP6_C2M_NB37 DP6_C2M_PB36DP6_M2C_N B17DP6_M2C_P B16
DP7_C2M_NB33 DP7_C2M_PB32DP7_M2C_N B13DP7_M2C_P B12
DP8_C2M_NB29 DP8_C2M_PB28DP8_M2C_N B9DP8_M2C_P B8
DP9_C2M_NB25 DP9_C2M_PB24DP9_M2C_N B5DP9_M2C_P B4
GBTCLK0_M2C_N D5GBTCLK0_M2C_P D4
GBTCLK1_M2C_N B21GBTCLK1_M2C_P B20
DP10_C2M_PZ24DP10_C2M_NZ25DP11_C2M_PY26DP11_C2M_NY27DP12_C2M_PZ28DP12_C2M_NZ29DP13_C2M_PY30DP13_C2M_NY31DP14_C2M_PM18DP14_C2M_NM19DP15_C2M_PM22DP15_C2M_NM23DP16_C2M_PM26DP16_C2M_NM27DP17_C2M_PM30DP17_C2M_NM31DP18_C2M_PM34DP18_C2M_NM35DP19_C2M_PM38DP19_C2M_NM39DP20_C2M_PZ8DP20_C2M_NZ9DP21_C2M_PY6DP21_C2M_NY7DP22_C2M_PZ4DP22_C2M_NZ5DP23_C2M_PY2DP23_C2M_NY3
DP10_M2C_P Y10DP10_M2C_N Y11DP11_M2C_P Z12DP11_M2C_N Z13DP12_M2C_P Y14DP12_M2C_N Y15DP13_M2C_P Z16DP13_M2C_N Z17DP14_M2C_P Y18DP14_M2C_N Y19DP15_M2C_P Y22DP15_M2C_N Y23DP16_M2C_P Z32DP16_M2C_N Z33DP17_M2C_P Y34DP17_M2C_N Y35DP18_M2C_P Z36DP18_M2C_N Z37DP19_M2C_P Y38DP19_M2C_N Y39DP20_M2C_P M14DP20_M2C_N M15DP21_M2C_P M10DP21_M2C_N M11DP22_M2C_P M6DP22_M2C_N M7DP23_M2C_P M2DP23_M2C_N M3
GBTCLK2_M2C_P L12GBTCLK2_M2C_N L13
GBTCLK3_M2C_PL8GBTCLK3_M2C_NL9GBTCLK4_M2C_PL4GBTCLK4_M2C_NL5GBTCLK5_M2C_PZ20GBTCLK5_M2C_NZ21
R350 100K
C392 10uF
C390 1uFC387 1uFR354 1.00K
C388 10uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPGA Configuration Interface
S10 Banks - CFG
ATB Header
AS x4 (Optional)
MSEL[2:0]0 0 0 AVSTx321 0 1 AVSTx160 1 1 Normal AS0 0 1 Fast ASDefault AVSTx32
VID INTERFACE
VFEF_ADC sources from 1.25V zener
S10 JTAG INTERFACEClose to EPCQL
Install R365/R366 for interposer card
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
FPGA_INIT_DONEFPGA_CONF_DONEFPGA_nSTATUS
FPGA_OSC_CLK_1FPGA_nCONFIGFPGA_nSTATUSFPGA_INIT_DONE
FPGA_CONF_DONE
FPGA_AS_CLK
FPGAMSEL0
FPGA_MSEL2FPGA_MSEL1FPGA_AVST_READY
S10_JTAG_TCKS10_JTAG_TMSS10_JTAG_TDI
S10_JTAG_TDO
FPGA_SEU_ERRFPGA_CvP_DONE
FPGA_CvP_DONEFPGA_SEU_ERR
FPGA_AS_CLKFPGAMSEL0
FPGA_AS_DATA0FPGA_AS_DATA1FPGA_AS_DATA2FPGA_AS_DATA3
FPGA_AS_DATA0
FPGA_AS_DATA1FPGA_AS_DATA2
FPGA_AS_DATA3
VCC_SCLVCC_ALERTnVCC_SDA
NPERSTR0
NPERSTR2
NPERSTL0
NPERSTL2
NPERSTR0NPERSTR2NPERSTL0NPERSTL2
FPGA_SDM10
FPGA_MSEL1 FPGA_MSEL2 FPGAMSEL0
FPGA_nCONFIG
FPGA_AS_CLK FPGA_ASCLK
FPGA_ASDATA0FPGA_ASDATA1FPGA_ASDATA2FPGA_ASDATA3FPGAMSEL0 FPGA_MSEL0
TEMPDIODE_NTEMPDIODE_P
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V1.8V1.8V
FPGA_OSC_CLK_1 7FPGA_ASCLK 14
VCC_SCL 18VCC_SDA 18VCC_ALERTn 42
S10_JTAG_TDI 9S10_JTAG_TCK 9S10_JTAG_TMS 9S10_JTAG_TDO 9
FPGA_SEU_ERR 14FPGA_CvP_DONE 14FPGA_SDM10 14
FPGA_nSTATUS 14
FPGA_nCONFIG 11,14
FPGA_MSEL0 14FPGA_MSEL1 14FPGA_MSEL2 14
FPGA_CONF_DONE 14
FPGA_INIT_DONE 14
FPGA_AVST_READY 14
FPGA_ASDATA0 14FPGA_ASDATA1 14FPGA_ASDATA2 14FPGA_ASDATA3 14
TEMPDIODE_P 13TEMPDIODE_N 13
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B28 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B28 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B28 53Monday, March 13, 2017
R815DNI
R686 DNIR618 10.0K
R621 10.0K
1SG280LU3F50E3VGS1
U43JNC1E29NC2C33NC3D30NC4A30NC5C32NC6A27NC7A29NC8E33NC9F29NC10E32NC11B30NC12D29NC13F31NC14R29NC15G28NC16F30NC17J28NC18E28NC19B34NC20E31NC21P29NC22B32NC23G29NC24H28NC25G30NC26C28
NC34F32 NC33K29 NC32A34 NC31N30 NC30B33 NC29H31 NC28K28 NC27J29
NC35G32
NC36 A32NC37 P30NC38 J30NC39 A31NC40 H30NC41 D31NC42 H32NC43 B29NC44 J31NC45 D33NC46 D28NC47 K31NC48 B28
DNU1 C31DNU2 C30DNU3 BJ38DNU4 BH38DNU5 AD36DNU6 AE37DNU7 BJ48DNU8 A48DNU9 BJ2
DNU10 B1
DNU20 AF13DNU19 AF37DNU18 AG13DNU17 AG37DNU16 BF25DNU15 AW23DNU14 BH23DNU13 BF24DNU12 BG24DNU11 BJ24
R816DNI
R6884.7K
J60
DNI
11 2 233 4 455 6 677 8 899 10 10
12 121111
SW11
CAS-120TB1
1
2
3
R358 2K
R365 DNI
R6894.7K
R817DNI
R359 2K
R8390
D26
LT1389
Gnd0 4Vout6Gnd1 5
nc1 1nc2 2nc3 3
nc47nc58
R758 10.0K
R367 4.7KR372 4.7K
R360 2K
R8190
R361 2KR362 2K
SW10
CAS-D20TB1
4
6
5
1
2
3
R818DNI
R814DNI
R37010.0K
R366 DNI
R810 DNI
R619 10.0K
1SG280LU3F50E3VGS1
U43IIO3V0_10, NPERSTL0AJ34IO3V1_10AG35IO3V2_10AH33IO3V3_10AF34IO3V4_10AE36IO3V5_10AG34IO3V6_10AH32IO3V7_10AJ33
IO3V0_12, NPERSTL2AD34IO3V1_12AD35IO3V2_12AC35IO3V3_12AB34IO3V4_12AC33IO3V5_12AC36IO3V6_12AB35IO3V7_12AB36
IO3V0_20, NPERSTR0 AH16IO3V1_20 AF15IO3V2_20 AB12IO3V3_20 AF17IO3V4_20 AD16IO3V5_20 AF16IO3V6_20 AE16IO3V7_20 AH17
IO3V0_22, NPERSTR2 AE14IO3V1_22 AD15IO3V2_22 AC15IO3V3_22 AC14IO3V4_22 AB13IO3V5_22 AD14IO3V6_22 AB15IO3V7_22 AB14
U44
EPCQ1024L
S#C2 DQ1 D2W#/VPP/DQ2 C4
VSSB3
DQ0 D3CB2
HOLD#/DQ3 D4
VCCB4
NC1A2NC2A3NC3A4NC4A5NC5B1NC6B5NC7C1NC8C3
NC9 C5NC10 D1NC11 D5NC12 E1NC13 E2NC14 E3NC15 E4NC16 E5
R37110.0K
C8180.1uF
R8400
R809 DNI
R363499
R373 4.7K
R364 10.0K
CONFIGURATION
1SG280LU3F50E3VGS1
U43K
TDO BD24TMS BC22TCK AN22TDI AR22
OSC_CLK_1BA22
SDM_IO0,INIT_DONE,PWRMGT_PWM0,PWRMGT_SCLBD23SDM_IO1, AVSTX8_DATA2,AS_DATA1,SDMMC_CFG_DATA1,NAND_RE_NBB22
SDM_IO5, AS_NCSO0, SDMMC_CFG_CCLK, NAND_WE_N, MSEL0, CONF_DONEBC23SDM_IO3, AVSTX8_DATA3, AS_DATA2, SDMMC_CFG_DATA2, NAND_ADQ2BB23
NCONFIGAY22
SDM_IO4, AVSTX8_DATA1, AS_DATA0, SDMMC_CFG_CMD, NAND_ADQ1AN23SDM_IO2, AVSTX8_DATA0, AS_CLK, SDMMC_CFG_DATA0, NAND_ADQ0BE23
SDM_IO7, AS_NCSO2, NAND_ALE,MSEL1BE22
SDM_IO11, AVSTX8_VALID, PWRMGT_SDA, NAND_ADQ6BF22
NSTATUSBJ21
SDM_IO16, CONF_DONE, PWRMGT_SDABG23SDM_IO13, AVSTX8_DATA5, SDMMC_CFG_DATA5, NAND_CE_NAW24
SDM_IO9, AS_NCSO1, NAND_CLE, MSEL2BH22SDM_IO6, AVSTX8_DATA4, AS_DATA3, SDMMC_CFG_DATA3, NAND_ADQ3BA24
SDM_IO10, AVSTX8_DATA7, SDMMC_CFG_DATA7, NAND_ADQ5AY24SDM_IO8, AVST_READY, AS_NCSO3, SDMMC_CFG_DATA4, NAND_RBBE24
SDM_IO12, PWRMGT_PWM0, PWRMGT_SDA, NAND_WP_NBB24
SDM_IO15, AVSTX8_DATA6, SDMMC_CFG_DATA6, NAND_ADQ4BD25 SDM_IO14, AVSTX8_CLK, PWRMGT_SCL, NAND_ADQ7BG22
RREF_SDM BJ23
VREFP_ADC AR23VREFN_ADC AP23VSIGP_0 AU24VSIGN_0 AT24VSIGP_1 AR24VSIGN_1 AP24
RREF_BL AF38RREF_TL AD38RREF_TR AD12RREF_BR AF12
C3930.1uF
R6874.7K
R685 DNIR620 10.0K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Flash Interface
Ethernet Interface
S10 Banks 2 A/B/C
CFP4 INTERFACE
CFI Flash Clock
SFP+ INTERFACE
QSFP28 INTERFACE
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
ENET_MDCENET_MDIOENET_INTnENET_RSTn
ENET_SGMII_TX_PENET_SGMII_TX_N
ENET_SGMII_RX_PENET_SGMII_RX_N
CLK_S10BOT_100M_PCLK_S10BOT_100M_N
SFP0_RS1
eQSFP_modselL0eQSFP_LPmode0eQSFP_resetL0eQSFP_modprsL0eQSFP_intl0eQSFP_scl0eQSFP_sda0
eQSFP_modselL1eQSFP_resetL1
eQSFP_LPmode1eQSFP_scl1eQSFP_sda1eQSFP_modprsL1
eQSFP_intl1
SFP1_TX_FLTSFP1_RX_LOSSFP1_SDASFP1_SCL
SFP1_RS1
SFP1_RS0SFP1_TX_DISSFP1_MOD_ABSSFP0_RX_LOS
SFP0_SCL
SFP0_SDA
SFP0_TX_FLTSFP0_RS0
SFP0_TX_DISSFP0_MOD_ABS
FLASH_RDYBSYn0
FM_D1FM_D2
FLASH_CEn0
FLASH_CEn1FLASH_ADVn
FLASH_RDYBSYn1
CFP4_MDIO
CFP4_MDC
CFP4_PRTADR0
CFP4_PRTADR1CFP4_PRTADR2
CFP4_MOD_RSTnCFP4_MOD_LOPWRCFP4_TX_DIS
CFP4_MOD_ABS
CFP4_RX_LOSCFP4_GLB_ALRMn
FM_A14
FM_A15
FM_A21FM_A16
FM_A25
FM_A7
FM_A8
FM_A11
FM_A1
FM_A20FM_A19
FM_A17
FLASH_CLK
FM_A26
FLASH_OEn
FM_A12
FM_A18
FM_A23
FM_A22
FM_A9
FM_A5FM_A6
FM_A2
FM_A10FM_A3FLASH_RESETn
FM_A4FM_A13FLASH_WEnFM_A24
FM_D18FM_D21
FM_D17FM_D19
FM_D4
FM_D11FM_D7
FM_D10
FM_D13
FM_D12
FM_D31
FM_D29FM_D27
FM_D26FM_D20
FM_D16
FM_D22
FM_D25FM_D3
FM_D15
FM_D6
FM_D9
FM_D0
FM_D8
FM_D14FM_D24FM_D5
FM_D23FM_D30
FM_D28
FM_A[26:1] 14,15
FLASH_CEn0 14,15FLASH_CEn1 14,15
FM_D[31:0] 14,15
FLASH_WEn 14,15
FLASH_OEn 14,15
FLASH_RESETn 14,15FLASH_CLK 14,15FLASH_ADVn 14,15
FLASH_RDYBSYn1 14,15FLASH_RDYBSYn0 14,15
ENET_INTn 16,29ENET_RSTn 16ENET_SGMII_TX_P 16ENET_SGMII_TX_N 16ENET_SGMII_RX_P 16ENET_SGMII_RX_N 16
ENET_MDC 16ENET_MDIO 16
CFP4_MDIO 20
CFP4_GLB_ALRMn 20
CFP4_MDC 20
CFP4_RX_LOS 20CFP4_MOD_ABS 20CFP4_TX_DIS 20CFP4_MOD_LOPWR 20CFP4_MOD_RSTn 20
CFP4_PRTADR0 20CFP4_PRTADR1 20CFP4_PRTADR2 20
eQSFP_sda0 21eQSFP_scl0 21
eQSFP_modselL0 21eQSFP_resetL0 21eQSFP_LPmode0 21eQSFP_modprsL0 21eQSFP_intl0 21
SFP0_SCL 23SFP0_SDA 23
eQSFP_sda1 22eQSFP_scl1 22
SFP1_SDA 24SFP1_SCL 24
SFP1_MOD_ABS 24
SFP1_TX_DIS 24SFP1_RS0 24SFP1_RS1 24SFP1_RX_LOS 24SFP1_TX_FLT 24
eQSFP_modselL1 22eQSFP_resetL1 22eQSFP_LPmode1 22eQSFP_modprsL1 22eQSFP_intl1 22
SFP0_RS0 23SFP0_TX_DIS 23
SFP0_MOD_ABS 23SFP0_TX_FLT 23SFP0_RX_LOS 23SFP0_RS1 23
ENET_INTn 16,29ENET_INTn 16,29
CLK_S10BOT_100M_N 6CLK_S10BOT_100M_P 6
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C29 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C29 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C29 53Monday, March 13, 2017
BANK 2
A
BANK 2
C
BANK 2
B
1SG280LU3F50E3VGS1
U43CIO, LVDS2A_1N, DQ44AU28IO, LVDS2A_1P, DQ44AU29IO, LVDS2A_2N, DQ44AW29IO, LVDS2A_2P, DQ44AY29IO, LVDS2A_3N, DQ44BB28IO, LVDS2A_3P, DQ44BA29IO, LVDS2A_4N, DQSN44AV28IO, LVDS2A_4P, DQS44AW28IO, LVDS2A_5N, DQ44AV30IO, LVDS2A_5P, DQ44AU30IO, LVDS2A_6N, DQ44AT30IO, LVDS2A_6P, DQ44AT29IO, LVDS2A_7N, DQ45BA30IO, LVDS2A_7P, DQ45BA31IO, LVDS2A_8N, DQ45BB29IO, LVDS2A_8P, DQ45BB30IO, LVDS2A_9N, DQ45BC32IO, LVDS2A_9P, DQ45BC31IO, PLL_2A_CLKOUT1N, LVDS2A_10N, DQSN45BB32IO, PLL_2A_CLKOUT1P, PLL_2A_CLKOUT1, PLL_2A_FBN, LVDS2A_10P, DQS45BA32IO, LVDS2A_11N, DQ45AY32IO, RZQ_2A, LVDS2A_11P, DQ45AY31IO, CLK_2A_1N, LVDS2A_12N, DQ45AW31IO, CLK_2A_1P, LVDS2A_12P, DQ45AW30IO, CLK_2A_0N, LVDS2A_13N, DQ46BD31IO, CLK_2A_0P, LVDS2A_13P, DQ46BE31IO, LVDS2A_14N, DQ46BE29IO, LVDS2A_14P, DQ46BD29IO, PLL_2A_CLKOUT0N, LVDS2A_15N, DQ46BF30IO, PLL_2A_CLKOUT0P, PLL_2A_CLKOUT0, PLL_2A_FBP, PLL_2A_FB0, LVDS2A_15P, DQ46BF31IO, LVDS2A_16N, DQSN46BD30IO, LVDS2A_16P, DQS46BC30IO, LVDS2A_17N, DQ46BG28IO, LVDS2A_17P, DQ46BG29IO, LVDS2A_18N, DQ46BH30IO, LVDS2A_18P, DQ46BG30IO, LVDS2A_19N, DQ47BE28IO, LVDS2A_19P, DQ47BF29IO, LVDS2A_20N, DQ47BJ29IO, LVDS2A_20P, DQ47BJ30IO, LVDS2A_21N, DQ47BH28IO, LVDS2A_21P, DQ47BJ28IO, LVDS2A_22N, DQSN47BJ31IO, LVDS2A_22P, DQS47BH31IO, LVDS2A_23N, DQ47BF32IO, LVDS2A_23P, DQ47BE32IO, LVDS2A_24N, DQ47BG32IO, LVDS2A_24P, DQ47BH32
IO, LVDS2B_1N, DQ40BD36IO, LVDS2B_1P, DQ40BE36IO, LVDS2B_2N, DQ40BC35IO, LVDS2B_2P, DQ40BC36IO, LVDS2B_3N, DQ40BB34IO, LVDS2B_3P, DQ40BB33IO, LVDS2B_4N, DQSN40BD35IO, LVDS2B_4P, DQS40BD34IO, LVDS2B_5N, DQ40BC33IO, LVDS2B_5P, DQ40BD33IO, LVDS2B_6N, DQ40BF35IO, LVDS2B_6P, DQ40BF36IO, LVDS2B_7N, DQ41BF34IO, LVDS2B_7P, DQ41BG34IO, LVDS2B_8N, DQ41BJ34IO, LVDS2B_8P, DQ41BJ33IO, LVDS2B_9N, DQ41BG35IO, LVDS2B_9P, DQ41BH35IO, PLL_2B_CLKOUT1N, LVDS2B_10N, DQSN41BE34IO, PLL_2B_CLKOUT1P, PLL_2B_CLKOUT1, PLL_2B_FBN, LVDS2B_10P, DQS41BE33IO, LVDS2B_11N, DQ41BJ36IO, RZQ_2B, LVDS2B_11P, DQ41BJ35IO, CLK_2B_1N, LVDS2B_12N, DQ41BG33IO, CLK_2B_1P, LVDS2B_12P, DQ41BH33IO, CLK_2B_0N, LVDS2B_13N, DQ42AV36IO, CLK_2B_0P, LVDS2B_13P, DQ42AW36IO, LVDS2B_14N, DQ42AY33IO, LVDS2B_14P, DQ42AW33IO, PLL_2B_CLKOUT0N, LVDS2B_15N, DQ42BA35IO, PLL_2B_CLKOUT0P, PLL_2B_CLKOUT0, PLL_2B_FBP, PLL_2B_FB0, LVDS2B_15P, DQ42BB35IO, LVDS2B_16N, DQSN42AW35IO, LVDS2B_16P, DQS42AW34IO, LVDS2B_17N, DQ42AY36IO, LVDS2B_17P, DQ42BA36IO, LVDS2B_18N, DQ42BA34IO, LVDS2B_18P, DQ42AY34IO, LVDS2B_19N, DQ43AT32IO, LVDS2B_19P, DQ43AU32IO, LVDS2B_20N, DQ43AV32IO, LVDS2B_20P, DQ43AV33IO, LVDS2B_21N, DQ43AT34IO, LVDS2B_21P, DQ43AT35IO, LVDS2B_22N, DQSN43AR31IO, LVDS2B_22P, DQS43AR32IO, LVDS2B_23N, DQ43AU35IO, LVDS2B_23P, DQ43AV35IO, LVDS2B_24N, DQ43AU33IO, LVDS2B_24P, DQ43AU34
IO, LVDS2C_1N, DQ36 AY40IO, LVDS2C_1P, DQ36 BA40IO, LVDS2C_2N, DQ36 BA39IO, LVDS2C_2P, DQ36 BB39IO, LVDS2C_3N, DQ36 BB40IO, LVDS2C_3P, DQ36 BC40
IO, LVDS2C_4N, DQSN36 BD38IO, LVDS2C_4P, DQS36 BD39
IO, LVDS2C_5N, DQ36 BC38IO, LVDS2C_5P, DQ36 BB38IO, LVDS2C_6N, DQ36 BC37IO, LVDS2C_6P, DQ36 BB37IO, LVDS2C_7N, DQ37 BD40IO, LVDS2C_7P, DQ37 BE40IO, LVDS2C_8N, DQ37 BG38IO, LVDS2C_8P, DQ37 BG37IO, LVDS2C_9N, DQ37 BE38IO, LVDS2C_9P, DQ37 BE39
IO, PLL_2C_CLKOUT1N, LVDS2C_10N, DQSN37 BE37IO, PLL_2C_CLKOUT1P, PLL_2C_CLKOUT1, PLL_2C_FBN, LVDS2C_10P, DQS37 BF37
IO, LVDS2C_11N, DQ37 BF39IO, RZQ_2C, LVDS2C_11P, DQ37 BF40
IO, CLK_2C_1N, LVDS2C_12N, DQ37 BH37IO, CLK_2C_1P, LVDS2C_12P, DQ37 BH36IO, CLK_2C_0N, LVDS2C_13N, DQ38 AW39IO, CLK_2C_0P, LVDS2C_13P, DQ38 AW38
IO, LVDS2C_14N, DQ38 BA37IO, LVDS2C_14P, DQ38 AY37
IO, PLL_2C_CLKOUT0N, LVDS2C_15N, DQ38 AV40IO, PLL_2C_CLKOUT0P, PLL_2C_CLKOUT0, PLL_2C_FBP, PLL_2C_FB0, LVDS2C_15P, DQ38 AW40
IO, LVDS2C_16N, DQSN38 AY39IO, LVDS2C_16P, DQS38 AY38
IO, LVDS2C_17N, DQ38 AU37IO, LVDS2C_17P, DQ38 AU38IO, LVDS2C_18N, DQ38 AV38IO, LVDS2C_18P, DQ38 AV37IO, LVDS2C_19N, DQ39 AR34IO, LVDS2C_19P, DQ39 AP35IO, LVDS2C_20N, DQ39 AR36IO, LVDS2C_20P, DQ39 AP36IO, LVDS2C_21N, DQ39 AP33IO, LVDS2C_21P, DQ39 AN33
IO, LVDS2C_22N, DQSN39 AT36IO, LVDS2C_22P, DQS39 AT37
IO, LVDS2C_23N, DQ39 AR37IO, LVDS2C_23P, DQ39 AT38IO, LVDS2C_24N, DQ39 AR33IO, LVDS2C_24P, DQ39 AP34
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB Direct To S10
S10 Banks - 2 F/L/M/N
LA00_CC
LA00_CC
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
USB_FULLUSB_EMPTYUSB_OEnUSB_RESETnUSB_RDnUSB_WRnUSB_SCLUSB_SDAUSB_DATA0USB_DATA1USB_DATA2USB_DATA3USB_DATA4USB_DATA5USB_DATA6USB_DATA7USB_ADDR0USB_ADDR1
USB_FPGA_CLK
SPARE13SPARE14SPARE15SPARE16SPARE17SPARE18SPARE19SPARE20
SPARE1SPARE2SPARE3SPARE4SPARE5SPARE6SPARE7SPARE8SPARE9SPARE10SPARE11SPARE12
FBCLKM2CP1FBCLKM2CN1
FBCLKM2CN0FBCLKM2CP0
FACLKM2CN0FACLKM2CP0
FBPRSNT_NEXTB_SDAEXTB_SCL
FBPRSNT1V8_NEXTB_SDA1V8EXTB_SCL1V8
EXTB_SCL1V8EXTB_SDA1V8
FBPRSNT1V8_N
CLK_S10TOP_ADJ_PCLK_S10TOP_ADJ_N
RZQ_2M
1.8V3.3V
1.8V
USB_ADDR[1:0] 9
USB_SDA 9
USB_FULL 9USB_DATA[7:0] 9
USB_RESETn 9USB_OEn 9USB_RDn 9USB_WRn 9
USB_EMPTY 9
USB_SCL 9
SPARE[20:1] 14
FBLAN19 27FBLAP19 27FBLAP20 27FBLAN20 27FBLAN21 27FBLAP21 27FBLAP22 27FBLAN22 27
FBLAN0 27FBLAP0 27
FALAN026 FALAP026
FALAP526 FALAN526
FBPRSNT_N 8,11,27EXTB_SDA 27
FBPRSNT1V8_N 14EXTB_SCL 27
FBLAN17 27FBLAP17 27
FALAN1426 FALAP1426 FALAN1326 FALAP1326
FALAN1526 FALAP1526
FALAN926 FALAP926
FALAN126 FALAP126
FALAP1626 FALAN1626
FALAN1226 FALAP1226
FALAN626 FALAP626
FALAN1126 FALAP1126
FBLAN28 27FBLAP28 27
FBLAN31 27FBLAP31 27
FBLAP32 27FBLAN32 27
FBLAN33 27FBLAP33 27
FBLAN25 27FBLAP25 27
FBLAP26 27FBLAN26 27FBLAN27 27FBLAP27 27
FBLAP23 27FBLAN23 27
FBLAN18 27FBLAP18 27
FBLAN7 27FBLAP7 27
FBLAN11 27FBLAP11 27
FBLAN16 27FBLAP16 27FBLAP14 27FBLAN14 27
FBLAN12 27FBLAP12 27
FBLAN10 27FBLAP10 27
FBLAN3 27FBLAP3 27
FBLAN5 27FBLAP5 27
FBLAP6 27FBLAN6 27
FBLAP1 27FBLAN1 27
FBLAN2 27FBLAP2 27
FBLAN4 27FBLAP4 27
FBLAP9 27
FBLAN29 27FBLAP29 27
FBLAP30 27FBLAN30 27FBLAN24 27FBLAP24 27
FBLAN8 27FBLAP8 27
FBLAN9 27
FBLAN13 27FBLAP13 27
FBLAN15 27FBLAP15 27
FALAP726 FALAN726
FALAP426 FALAN426
FALAN826 FALAP826
FALAP326 FALAN326
FALAN1026 FALAP1026
FALAP226 FALAN226
CLK_S10TOP_ADJ_P 4CLK_S10TOP_ADJ_N 4
FBCLKM2CN0 27FBCLKM2CP0 27FBCLKM2CP1 27FBCLKM2CN1 27
FACLKM2CN0 26FACLKM2CP0 26USB_FPGA_CLK 8,9
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C30 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C30 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C30 53Monday, March 13, 2017
R379DNI
C3950.1uF R380DNI
BANK 2
FBANK 2
MBANK 2
LBANK 2
N
1SG280LU3F50E3VGS1
U43DIO, LVDS2F_1N, DQ32AT25IO, LVDS2F_1P, DQ32AU25IO, LVDS2F_2N, DQ32AW25IO, LVDS2F_2P, DQ32AV25IO, LVDS2F_3N, DQ32AV26IO, LVDS2F_3P, DQ32AV27IO, LVDS2F_4N, DQSN32AT26IO, LVDS2F_4P, DQS32AR26IO, LVDS2F_5N, DQ32AU27IO, LVDS2F_5P, DQ32AT27IO, LVDS2F_6N, DQ32AY26IO, LVDS2F_6P, DQ32AW26IO, LVDS2F_7N, DQ33AN26IO, LVDS2F_7P, DQ33AP26IO, LVDS2F_8N, DQ33AN25IO, LVDS2F_8P, DQ33AP25IO, LVDS2F_9N, DQ33AP29IO, LVDS2F_9P, DQ33AP28IO, PLL_2F_CLKOUT1N, LVDS2F_10N, DQSN33AR27IO, PLL_2F_CLKOUT1P, PLL_2F_CLKOUT1, PLL_2F_FBN, LVDS2F_10P, DQS33AR28IO, LVDS2F_11N, DQ33AP31IO, RZQ_2F, LVDS2F_11P, DQ33AP30IO, CLK_2F_1N, LVDS2F_12N, DQ33AN28IO, CLK_2F_1P, LVDS2F_12P, DQ33AN27IO, CLK_2F_0N, LVDS2F_13N, DQ34BA26IO, CLK_2F_0P, LVDS2F_13P, DQ34BA27IO, LVDS2F_14N, DQ34BB25IO, LVDS2F_14P, DQ34BA25IO, PLL_2F_CLKOUT0N, LVDS2F_15N, DQ34BB27IO, PLL_2F_CLKOUT0P, PLL_2F_CLKOUT0, PLL_2F_FBP, PLL_2F_FB0, LVDS2F_15P, DQ34BC27IO, LVDS2F_16N, DQSN34BC25IO, LVDS2F_16P, DQS34BC26IO, LVDS2F_17N, DQ34AY27IO, LVDS2F_17P, DQ34AY28IO, LVDS2F_18N, DQ34BD28IO, LVDS2F_18P, DQ34BC28IO, LVDS2F_19N, DQ35BF26IO, LVDS2F_19P, DQ35BE27IO, LVDS2F_20N, DQ35BD26IO, LVDS2F_20P, DQ35BE26IO, LVDS2F_21N, DQ35BF27IO, LVDS2F_21P, DQ35BG27IO, LVDS2F_22N, DQSN35BH25IO, LVDS2F_22P, DQS35BJ25IO, LVDS2F_23N, DQ35BG25IO, LVDS2F_23P, DQ35BH26IO, LVDS2F_24N, DQ35BH27IO, LVDS2F_24P, DQ35BJ26
IO, LVDS2L_1N, DQ8E27IO, LVDS2L_1P, DQ8D26IO, LVDS2L_2N, DQ8G27IO, LVDS2L_2P, DQ8F27IO, LVDS2L_3N, DQ8C27IO, LVDS2L_3P, DQ8B27IO, LVDS2L_4N, DQSN8F26IO, LVDS2L_4P, DQS8E26IO, LVDS2L_5N, DQ8B25IO, LVDS2L_5P, DQ8C26IO, LVDS2L_6N, DQ8D25IO, LVDS2L_6P, DQ8C25IO, LVDS2L_7N, DQ9L26IO, LVDS2L_7P, DQ9K27IO, LVDS2L_8N, DQ9M27IO, LVDS2L_8P, DQ9L27IO, LVDS2L_9N, DQ9H27IO, LVDS2L_9P, DQ9H26IO, PLL_2L_CLKOUT1N, LVDS2L_10N, DQSN9K26IO, PLL_2L_CLKOUT1P, PLL_2L_CLKOUT1, PLL_2L_FBN, LVDS2L_10P, DQS9J26IO, LVDS2L_11N, DQ9G25IO, RZQ_2L, LVDS2L_11P, DQ9F25IO, CLK_2L_1N, LVDS2L_12N, DQ9H25IO, CLK_2L_1P, LVDS2L_12P, DQ9J25IO, CLK_2L_0N, LVDS2L_13N, DQ10V30IO, CLK_2L_0P, LVDS2L_13P, DQ10U30IO, LVDS2L_14N, DQ10T30IO, LVDS2L_14P, DQ10T29IO, PLL_2L_CLKOUT0N, LVDS2L_15N, DQ10U28IO, PLL_2L_CLKOUT0P, PLL_2L_CLKOUT0, PLL_2L_FBP, PLL_2L_FB0, LVDS2L_15P, DQ10U29IO, LVDS2L_16N, DQSN10V27IO, LVDS2L_16P, DQS10V28IO, LVDS2L_17N, DQ10V26IO, LVDS2L_17P, DQ10V25IO, LVDS2L_18N, DQ10U27IO, LVDS2L_18P, DQ10T27IO, LVDS2L_19N, DQ11N25IO, LVDS2L_19P, DQ11P25IO, LVDS2L_20N, DQ11P26IO, LVDS2L_20P, DQ11R26IO, LVDS2L_21N, DQ11T25IO, LVDS2L_21P, DQ11U25IO, LVDS2L_22N, DQSN11R27IO, LVDS2L_22P, DQS11T26IO, LVDS2L_23N, DQ11M25IO, LVDS2L_23P, DQ11L25IO, LVDS2L_24N, DQ11N27IO, LVDS2L_24P, DQ11N26
IO, LVDS2M_1N, DQ4 U34IO, LVDS2M_1P, DQ4 U33IO, LVDS2M_2N, DQ4 T31IO, LVDS2M_2P, DQ4 R31IO, LVDS2M_3N, DQ4 T34IO, LVDS2M_3P, DQ4 R34
IO, LVDS2M_4N, DQSN4 T32IO, LVDS2M_4P, DQS4 R32
IO, LVDS2M_5N, DQ4 U32IO, LVDS2M_5P, DQ4 V32IO, LVDS2M_6N, DQ4 P33IO, LVDS2M_6P, DQ4 R33IO, LVDS2M_7N, DQ5 R36IO, LVDS2M_7P, DQ5 T35IO, LVDS2M_8N, DQ5 L36IO, LVDS2M_8P, DQ5 L35IO, LVDS2M_9N, DQ5 P36IO, LVDS2M_9P, DQ5 N36
IO, PLL_2M_CLKOUT1N, LVDS2M_10N, DQSN5 K37IO, PLL_2M_CLKOUT1P, PLL_2M_CLKOUT1, PLL_2M_FBN, LVDS2M_10P, DQS5 K36
IO, LVDS2M_11N, DQ5 P35IO, RZQ_2M, LVDS2M_11P, DQ5 P34
IO, CLK_2M_1N, LVDS2M_12N, DQ5 N35IO, CLK_2M_1P, LVDS2M_12P, DQ5 M35IO, CLK_2M_0N, LVDS2M_13N, DQ6 P38IO, CLK_2M_0P, LVDS2M_13P, DQ6 N37
IO, LVDS2M_14N, DQ6 R37IO, LVDS2M_14P, DQ6 P37
IO, PLL_2M_CLKOUT0N, LVDS2M_15N, DQ6 L39IO, PLL_2M_CLKOUT0P, PLL_2M_CLKOUT0, PLL_2M_FBP, PLL_2M_FB0, LVDS2M_15P, DQ6 K39
IO, LVDS2M_16N, DQSN6 J38IO, LVDS2M_16P, DQS6 J39
IO, LVDS2M_17N, DQ6 M38IO, LVDS2M_17P, DQ6 M37IO, LVDS2M_18N, DQ6 L37IO, LVDS2M_18P, DQ6 K38IO, LVDS2M_19N, DQ7 H40IO, LVDS2M_19P, DQ7 J40IO, LVDS2M_20N, DQ7 G39IO, LVDS2M_20P, DQ7 F39IO, LVDS2M_21N, DQ7 K40IO, LVDS2M_21P, DQ7 L40
IO, LVDS2M_22N, DQSN7 F40IO, LVDS2M_22P, DQS7 G40
IO, LVDS2M_23N, DQ7 H38IO, LVDS2M_23P, DQ7 G38IO, LVDS2M_24N, DQ7 E40IO, LVDS2M_24P, DQ7 D40
IO, LVDS2N_1N, DQ0 J34IO, LVDS2N_1P, DQ0 K34IO, LVDS2N_2N, DQ0 N32IO, LVDS2N_2P, DQ0 N31IO, LVDS2N_3N, DQ0 K33IO, LVDS2N_3P, DQ0 K32
IO, LVDS2N_4N, DQSN0 L31IO, LVDS2N_4P, DQS0 L32
IO, LVDS2N_5N, DQ0 N33IO, LVDS2N_5P, DQ0 M33IO, LVDS2N_6N, DQ0 M34IO, LVDS2N_6P, DQ0 L34IO, LVDS2N_7N, DQ1 F34IO, LVDS2N_7P, DQ1 E34IO, LVDS2N_8N, DQ1 J35IO, LVDS2N_8P, DQ1 H35IO, LVDS2N_9N, DQ1 F35IO, LVDS2N_9P, DQ1 G35
IO, PLL_2N_CLKOUT1N, LVDS2N_10N, DQSN1 G34IO, PLL_2N_CLKOUT1P, PLL_2N_CLKOUT1, PLL_2N_FBN, LVDS2N_10P, DQS1 G33
IO, LVDS2N_11N, DQ1 H36IO, RZQ_2N, LVDS2N_11P, DQ1 J36
IO, CLK_2N_1N, LVDS2N_12N, DQ1 H33IO, CLK_2N_1P, LVDS2N_12P, DQ1 J33IO, CLK_2N_0N, LVDS2N_13N, DQ2 D39IO, CLK_2N_0P, LVDS2N_13P, DQ2 E39
IO, LVDS2N_14N, DQ2 E38IO, LVDS2N_14P, DQ2 D38
IO, PLL_2N_CLKOUT0N, LVDS2N_15N, DQ2 D35IO, PLL_2N_CLKOUT0P, PLL_2N_CLKOUT0, PLL_2N_FBP, PLL_2N_FB0, LVDS2N_15P, DQ2 D34
IO, LVDS2N_16N, DQSN2 F36IO, LVDS2N_16P, DQS2 E36
IO, LVDS2N_17N, DQ2 F37IO, LVDS2N_17P, DQ2 E37IO, LVDS2N_18N, DQ2 H37IO, LVDS2N_18P, DQ2 G37IO, LVDS2N_19N, DQ3 C36IO, LVDS2N_19P, DQ3 D36IO, LVDS2N_20N, DQ3 C35IO, LVDS2N_20P, DQ3 B35IO, LVDS2N_21N, DQ3 B37IO, LVDS2N_21P, DQ3 C37
IO, LVDS2N_22N, DQSN3 A35IO, LVDS2N_22P, DQS3 A36
IO, LVDS2N_23N, DQ3 B38IO, LVDS2N_23P, DQ3 C38IO, LVDS2N_24N, DQ3 A37IO, LVDS2N_24P, DQ3 A38
C3941uF R3814.7K
U45
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
R3824.7K
R742100
C3960.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 to MAX V INTERFACE
S10 Banks - 3 A/B/CFPGA Configuration Interface
CAD Notes:place termination at S10
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
TEMP_ALERTnOVERTEMPn
FPGA_AVST_CLK TEMP_ALERTnOVERTEMPn
MAX5_BEn[3:0]MAX5_OEnMAX5_CSnMAX5_WEnMAX5_CLK
OVERTEMPn
CLKIN_SMA_3C_NCLKIN_SMA_3C_P
USER_DIP3USER_DIP4USER_DIP5USER_DIP6
CLKIN_SMA_3C_NCLKIN_SMA_3C_P
CLKOUT_SMA_3C_NCLKOUT_SMA_3C_P
CLKOUT_SMA_3C_NCLKOUT_SMA_3C_P
MAX5_OEnMAX5_CSnMAX5_WEnMAX5_CLKMAX5_BEn0MAX5_BEn1MAX5_BEn2MAX5_BEn3
I2C_1V8_SCLI2C_1V8_SDA
I2C_1V8_SCLI2C_1V8_SDA
USER_PB3
USER_PB6
S10_Unlock
USER_DIP0USER_DIP2USER_DIP1
CLK_50M_S10
FPGA_CONFIG_D1FPGA_CONFIG_D0
FPGA_CONFIG_D7FPGA_CONFIG_D6FPGA_CONFIG_D5FPGA_CONFIG_D4FPGA_CONFIG_D3FPGA_CONFIG_D2
FPGA_CONFIG_D12FPGA_CONFIG_D11FPGA_CONFIG_D10FPGA_CONFIG_D9FPGA_CONFIG_D8
FPGA_CONFIG_D15FPGA_CONFIG_D14FPGA_CONFIG_D13
FPGA_AVST_VALID
FPGA_PR_DONEFPGA_PR_ERROR
FPGA_PR_REQUEST
FPGA_CONFIG_D16FPGA_CONFIG_D17FPGA_CONFIG_D18FPGA_CONFIG_D19
FPGA_CONFIG_D20FPGA_CONFIG_D21FPGA_CONFIG_D22FPGA_CONFIG_D23FPGA_CONFIG_D24FPGA_CONFIG_D25FPGA_CONFIG_D26FPGA_CONFIG_D27FPGA_CONFIG_D28FPGA_CONFIG_D29FPGA_CONFIG_D30FPGA_CONFIG_D31
USER_PB0
USER_PB1
USER_PB7
USER_PB2
USER_IO4
USER_IO7
USER_IO6USER_IO5USER_IO9
USER_IO3USER_IO8
USER_IO2
USER_IO1USER_IO0
USER_LED0USER_LED1USER_LED2USER_LED3
USER_LED4USER_LED5
USER_LED6USER_LED7
USER_PB4
USER_PB5
CPU_RESETn
1.8V
2.5V
1.8V
OVERTEMPn 13,14TEMP_ALERTn 13,14
MAX5_BEn[3:0] 14MAX5_OEn 14MAX5_CSn 14MAX5_WEn 14MAX5_CLK 14
FPGA_PR_ERROR 14
CPU_RESETn 14,17
FPGA_CONFIG_D[31:0] 14
FPGA_PR_DONE 14FPGA_PR_REQUEST 14
USER_LED[7:0] 17USER_IO[9:0] 17
USER_DIP[6:0] 17USER_PB[7:0] 17S10_Unlock 17
I2C_1V8_SDA 6,14,18I2C_1V8_SCL 6,14,18
FPGA_AVST_CLK 14FPGA_AVST_VALID 14
CLK_50M_S104
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C31 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C31 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C31 53Monday, March 13, 2017
R38710.0K
R39049.9
R39249.9
R389160
R38510.0K
R38810.0K
BANK 3
A
BANK 3
C
BANK 3
B
1SG280LU3F50E3VGS1
U43EIO, LVDS3A_1N, DQ92, AVST_DATA0BD13IO, LVDS3A_1P, DQ92, AVST_DATA1BE13IO, LVDS3A_2N, DQ92, AVST_DATA2BF15IO, LVDS3A_2P, DQ92, AVST_DATA3BG15IO, LVDS3A_3N, DQ92, AVST_DATA4BE14IO, LVDS3A_3P, DQ92, AVST_DATA5BF14IO, LVDS3A_4N, DQSN92, AVST_DATA6BE16IO, LVDS3A_4P, DQS92, AVST_DATA7BF16IO, LVDS3A_5N, DQ92, AVST_DATA8BD16IO, LVDS3A_5P, DQ92, AVST_DATA9BC16IO, LVDS3A_6N, DQ92, AVST_DATA10BD14IO, LVDS3A_6P, DQ92, AVST_DATA11BD15IO, LVDS3A_7N, DQ93, AVST_DATA12BF12IO, LVDS3A_7P, DQ93, AVST_DATA13BG12IO, LVDS3A_8N, DQ93, AVST_DATA14BJ13IO, LVDS3A_8P, DQ93, AVST_DATA15BJ14IO, LVDS3A_9N, DQ93, AVST_DATA16BG13IO, LVDS3A_9P, DQ93, AVST_DATA17BG14IO, PLL_3A_CLKOUT1N, LVDS3A_10N, DQSN93, AVST_DATA18BH15IO, PLL_3A_CLKOUT1P, PLL_3A_CLKOUT1, PLL_3A_FBN, LVDS3A_10P, DQS93, AVST_DATA19BJ15IO, LVDS3A_11N, DQ93BH12IO, RZQ_3A, LVDS3A_11P, DQ93, AVST_VALIDBH13IO, CLK_3A_1N, LVDS3A_12N, DQ93, AVST_DATA20BH16IO, CLK_3A_1P, LVDS3A_12P, DQ93, AVST_DATA21BJ16IO, CLK_3A_0N, LVDS3A_13N, DQ94, AVST_DATA22AV15IO, CLK_3A_0P, LVDS3A_13P, DQ94, AVST_DATA23AW15IO, LVDS3A_14N, DQ94, AVST_DATA24BA15IO, LVDS3A_14P, DQ94, AVST_DATA25BA16IO, PLL_3A_CLKOUT0N, LVDS3A_15N, DQ94, AVST_DATA26AW14IO, PLL_3A_CLKOUT0P, PLL_3A_CLKOUT0, PLL_3A_FBP, PLL_3A_FB0, LVDS3A_15P, DQ94, AVST_DATA27AY14IO, LVDS3A_16N, DQSN94, AVST_DATA28BB14IO, LVDS3A_16P, DQS94, AVST_DATA29BA14IO, LVDS3A_17N, DQ94, AVST_DATA30BB15IO, LVDS3A_17P, DQ94, AVST_DATA31BC15IO, LVDS3A_18N, DQ94BB13IO, LVDS3A_18P, DQ94BC13IO, LVDS3A_19N, DQ95AV17IO, LVDS3A_19P, DQ95AV16IO, LVDS3A_20N, DQ95BA17IO, LVDS3A_20P, DQ95AY17IO, LVDS3A_21N, DQ95AY16IO, LVDS3A_21P, DQ95AW16IO, LVDS3A_22N, DQSN95AV18IO, LVDS3A_22P, DQS95AW18IO, LVDS3A_23N, DQ95BC17IO, LVDS3A_23P, DQ95BB17IO, LVDS3A_24N, DQ95AY18IO, LVDS3A_24P, DQ95, AVST_CLKAY19
IO, LVDS3B_1N, DQ88AP16IO, LVDS3B_1P, DQ88AP15IO, LVDS3B_2N, DQ88AU13IO, LVDS3B_2P, DQ88AV13IO, LVDS3B_3N, DQ88AU12IO, LVDS3B_3P, DQ88AT12IO, LVDS3B_4N, DQSN88AR13IO, LVDS3B_4P, DQS88AP12IO, LVDS3B_5N, DQ88AP14IO, LVDS3B_5P, DQ88AP13IO, LVDS3B_6N, DQ88AT14IO, LVDS3B_6P, DQ88AR14IO, LVDS3B_7N, DQ89AR18IO, LVDS3B_7P, DQ89AP18IO, LVDS3B_8N, DQ89AU14IO, LVDS3B_8P, DQ89AU15IO, LVDS3B_9N, DQ89AT16IO, LVDS3B_9P, DQ89AT15IO, PLL_3B_CLKOUT1N, LVDS3B_10N, DQSN89AR16IO, PLL_3B_CLKOUT1P, PLL_3B_CLKOUT1, PLL_3B_FBN, LVDS3B_10P, DQS89AR17IO, LVDS3B_11N, DQ89AN18IO, RZQ_3B, LVDS3B_11P, DQ89AN17IO, CLK_3B_1N, LVDS3B_12N, DQ89AU17IO, CLK_3B_1P, LVDS3B_12P, DQ89AT17IO, CLK_3B_0N, LVDS3B_13N, DQ90AV10IO, CLK_3B_0P, LVDS3B_13P, DQ90AW10IO, LVDS3B_14N, DQ90AY13IO, LVDS3B_14P, DQ90AW13IO, PLL_3B_CLKOUT0N, LVDS3B_15N, DQ90AV12IO, PLL_3B_CLKOUT0P, PLL_3B_CLKOUT0, PLL_3B_FBP, PLL_3B_FB0, LVDS3B_15P, DQ90AV11IO, LVDS3B_16N, DQSN90AY12IO, LVDS3B_16P, DQS90BA12IO, LVDS3B_17N, DQ90BA11IO, LVDS3B_17P, DQ90BA10IO, LVDS3B_18N, DQ90AW11IO, LVDS3B_18P, DQ90AY11IO, LVDS3B_19N, DQ91BC11IO, LVDS3B_19P, DQ91BD11IO, LVDS3B_20N, DQ91BB12IO, LVDS3B_20P, DQ91BC12IO, LVDS3B_21N, DQ91BB10IO, LVDS3B_21P, DQ91BC10IO, LVDS3B_22N, DQSN91BE11IO, LVDS3B_22P, DQS91BE12IO, LVDS3B_23N, DQ91BD10IO, LVDS3B_23P, DQ91BE10IO, LVDS3B_24N, DQ91BF10IO, LVDS3B_24P, DQ91BF11
IO, LVDS3C_1N, DQ84 BA21IO, LVDS3C_1P, DQ84 BA20IO, LVDS3C_2N, DQ84 BB20IO, LVDS3C_2P, DQ84 BC20IO, LVDS3C_3N, DQ84 BD21IO, LVDS3C_3P, DQ84 BC21
IO, LVDS3C_4N, DQSN84 AY21IO, LVDS3C_4P, DQS84 AW21
IO, LVDS3C_5N, DQ84 AW20IO, LVDS3C_5P, DQ84 AW19IO, LVDS3C_6N, DQ84 BA19IO, LVDS3C_6P, DQ84 BB19IO, LVDS3C_7N, DQ85 AR21IO, LVDS3C_7P, DQ85 AT21IO, LVDS3C_8N, DQ85 AU20IO, LVDS3C_8P, DQ85 AT20IO, LVDS3C_9N, DQ85 AP20IO, LVDS3C_9P, DQ85 AN20
IO, PLL_3C_CLKOUT1N, LVDS3C_10N, DQSN85 AP21IO, PLL_3C_CLKOUT1P, PLL_3C_CLKOUT1, PLL_3C_FBN, LVDS3C_10P, DQS85 AN21
IO, LVDS3C_11N, DQ85 AV20IO, RZQ_3C, LVDS3C_11P, DQ85 AV21
IO, CLK_3C_1N, LVDS3C_12N, DQ85 AT19IO, CLK_3C_1P, LVDS3C_12P, DQ85 AR19IO, CLK_3C_0N, LVDS3C_13N, DQ86 BE21IO, CLK_3C_0P, LVDS3C_13P, DQ86 BF21
IO, LVDS3C_14N, DQ86 BG20IO, LVDS3C_14P, DQ86 BF20
IO, PLL_3C_CLKOUT0N, LVDS3C_15N, DQ86 BD20IO, PLL_3C_CLKOUT0P, PLL_3C_CLKOUT0, PLL_3C_FBP, PLL_3C_FB0, LVDS3C_15P, DQ86 BD19
IO, LVDS3C_16N, DQSN86 BF19IO, LVDS3C_16P, DQS86 BE19
IO, LVDS3C_17N, DQ86 BB18IO, LVDS3C_17P, DQ86 BC18IO, LVDS3C_18N, DQ86 BD18IO, LVDS3C_18P, DQ86 BE18IO, LVDS3C_19N, DQ87 BG19IO, LVDS3C_19P, DQ87 BG18IO, LVDS3C_20N, DQ87 BH21IO, LVDS3C_20P, DQ87 BH20IO, LVDS3C_21N, DQ87 BH17IO, LVDS3C_21P, DQ87 BG17
IO, LVDS3C_22N, DQSN87 BJ20IO, LVDS3C_22P, DQS87 BJ19
IO, LVDS3C_23N, DQ87 BF17IO, LVDS3C_23P, DQ87 BE17IO, LVDS3C_24N, DQ87 BJ18IO, LVDS3C_24P, DQ87 BH18
D27
Amber_LED
R3861K
R391DNIJ631
2345
J61 1
2345
R38410.0K
J621
2 3 4 5
J641
2 3 4 5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 Banks - 3 I/J/L/K
LA17_CCHA17_CCHA00_CC
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
FACLKM2CN1FACLKM2CP1
FAPRSNT_NFACLKDIREXTA_SDA FACLKDIR1V8EXTA_SCL
FAPRSNT1V8_NEXTA_SDA1V8EXTA_SCL1V8
FAPRSNT1V8_N
FACLKDIR1V8EXTA_SDA1V8EXTA_SCL1V8
RZQ_3K
CLK_S10TOP_125M_NCLK_S10TOP_125M_P
1.8V3.3V
1.8V
FAHBP16 26FAHBN16 26
FACLKBIDIRN2 26FACLKBIDIRN3 26FACLKBIDIRP2 26FACLKBIDIRP3 26
FAHAP026 FAHAN026FAHAN1726 FAHAP1726
FAHAP1926 FAHAN1926
FAPRSNT_N 8,11,26EXTA_SDA 26
FACLKDIR 26FAPRSNT1V8_N 14
EXTA_SCL 26
FAHBN17 26FAHBP17 26
FAHBN18 26FAHBP18 26
FAHBN20 26FAHBP20 26
FAHBN21 26FAHBP21 26
FAHBN19 26FAHBP19 26
FAHBN12 26FAHBP12 26
FAHBN13 26FAHBP13 26FAHBP9 26FAHBN9 26FAHBN4 26FAHBP4 26
FAHBN5 26FAHBP5 26
FAHBN2 26FAHBP2 26
FAHBN3 26FAHBP3 26
FAHBN8 26FAHBP8 26
FAHBN11 26FAHBP11 26
FAHBN1 26FAHBP1 26
FAHBN0 26FAHBP0 26FAHBN7 26FAHBP7 26
FAHBP6 26FAHBN6 26
FAHBN10 26FAHBP10 26
FAHBN15 26FAHBP15 26
FAHBN14 26FAHBP14 26
FAHAN1526 FAHAP1526
FAHAN1226 FAHAP1226
FAHAP1326 FAHAN1326
FAHAP726 FAHAN726
FAHAN226 FAHAP226
FAHAP826 FAHAN826FAHAN1126 FAHAP1126
FAHAN526 FAHAP526
FAHAN126 FAHAP126FAHAP426 FAHAN426
FAHAN926 FAHAP926
FAHAN1626 FAHAP1626 FALAN33 26FALAP33 26
FALAP30 26FALAN30 26
FALAP31 26FALAN31 26
FALAN28 26FALAP28 26FALAN24 26FALAP24 26
FALAN29 26FALAP29 26
FALAP22 26FALAN22 26
FALAP23 26FALAN23 26
FALAP18 26FALAN18 26
FALAN19 26FALAP19 26
FALAN27 26FALAP27 26
FALAP26 26FALAN26 26
FALAP20 26FALAN20 26
FALAN21 26FALAP21 26
FAHAP2326 FAHAN2326FAHAN1826 FAHAP1826 FAHAN2126 FAHAP2126
FAHAN2226 FAHAP2226
FALAN25 26FALAP25 26
FALAN17 26FALAP17 26
FAHAN2026 FAHAP2026
FAHAN326 FAHAP326
FAHAP626 FAHAN626
FAHAN1426 FAHAP1426
FAHAP1026 FAHAN1026
FALAN32 26FALAP32 26
CLK_S10TOP_125M_N 7CLK_S10TOP_125M_P 7
FACLKM2CP1 26FACLKM2CN1 26
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C32 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C32 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
C32 53Monday, March 13, 2017
C3971uF C3990.1uF
R743100
C3980.1uF R395DNI
R3984.7KR396DNIU46
MAX3378_UCSP
VL B2IO VL1 A1IO VL2 A2IO VL3 A3IO VL4 A4
GND B4
VCCB1IO VCC1C1IO VCC2C2IO VCC3C3IO VCC4C4
TSB3
BANK 3
I
BANK 3
K
BANK 3
J
BANK 3
L
1SG280LU3F50E3VGS1
U43FIO, LVDS3I_1N, DQ60V21IO, LVDS3I_1P, DQ60V22IO, LVDS3I_2N, DQ60T21IO, LVDS3I_2P, DQ60R21IO, LVDS3I_3N, DQ60V23IO, LVDS3I_3P, DQ60V24IO, LVDS3I_4N, DQSN60U20IO, LVDS3I_4P, DQS60T20IO, LVDS3I_5N, DQ60R22IO, LVDS3I_5P, DQ60T22IO, LVDS3I_6N, DQ60U23IO, LVDS3I_6P, DQ60U22IO, LVDS3I_7N, DQ61N22IO, LVDS3I_7P, DQ61M22IO, LVDS3I_8N, DQ61L22IO, LVDS3I_8P, DQ61K22IO, LVDS3I_9N, DQ61R23IO, LVDS3I_9P, DQ61P23IO, PLL_3I_CLKOUT1N, LVDS3I_10N, DQSN61R24IO, PLL_3I_CLKOUT1P, PLL_3I_CLKOUT1, PLL_3I_FBN, LVDS3I_10P, DQS61P24IO, LVDS3I_11N, DQ61N23IO, RZQ_3I, LVDS3I_11P, DQ61M23IO, CLK_3I_1N, LVDS3I_12N, DQ61T24IO, CLK_3I_1P, LVDS3I_12P, DQ61U24IO, CLK_3I_0N, LVDS3I_13N, DQ62L24IO, CLK_3I_0P, LVDS3I_13P, DQ62M24IO, LVDS3I_14N, DQ62G24IO, LVDS3I_14P, DQ62F24IO, PLL_3I_CLKOUT0N, LVDS3I_15N, DQ62G23IO, PLL_3I_CLKOUT0P, PLL_3I_CLKOUT0, PLL_3I_FBP, PLL_3I_FB0, LVDS3I_15P, DQ62H23IO, LVDS3I_16N, DQSN62K23IO, LVDS3I_16P, DQS62J23IO, LVDS3I_17N, DQ62J24IO, LVDS3I_17P, DQ62K24IO, LVDS3I_18N, DQ62H22IO, LVDS3I_18P, DQ62G22IO, LVDS3I_19N, DQ63A24IO, LVDS3I_19P, DQ63B24IO, LVDS3I_20N, DQ63F22IO, LVDS3I_20P, DQ63E22IO, LVDS3I_21N, DQ63A26IO, LVDS3I_21P, DQ63A25IO, LVDS3I_22N, DQSN63D23IO, LVDS3I_22P, DQS63D24IO, LVDS3I_23N, DQ63B23IO, LVDS3I_23P, DQ63C23IO, LVDS3I_24N, DQ63E23IO, LVDS3I_24P, DQ63E24
IO, LVDS3J_1N, DQ56E11IO, LVDS3J_1P, DQ56F11IO, LVDS3J_2N, DQ56G10IO, LVDS3J_2P, DQ56H10IO, LVDS3J_3N, DQ56D10IO, LVDS3J_3P, DQ56D11IO, LVDS3J_4N, DQSN56G12IO, LVDS3J_4P, DQS56H12IO, LVDS3J_5N, DQ56F10IO, LVDS3J_5P, DQ56E10IO, LVDS3J_6N, DQ56F12IO, LVDS3J_6P, DQ56E12IO, LVDS3J_7N, DQ57J11IO, LVDS3J_7P, DQ57H11IO, LVDS3J_8N, DQ57K11IO, LVDS3J_8P, DQ57K12IO, LVDS3J_9N, DQ57K10IO, LVDS3J_9P, DQ57J10IO, PLL_3J_CLKOUT1N, LVDS3J_10N, DQSN57M12IO, PLL_3J_CLKOUT1P, PLL_3J_CLKOUT1, PLL_3J_FBN, LVDS3J_10P, DQS57L12IO, LVDS3J_11N, DQ57L10IO, RZQ_3J, LVDS3J_11P, DQ57L11IO, CLK_3J_1N, LVDS3J_12N, DQ57K13IO, CLK_3J_1P, LVDS3J_12P, DQ57J13IO, CLK_3J_0N, LVDS3J_13N, DQ58N13IO, CLK_3J_0P, LVDS3J_13P, DQ58P14IO, LVDS3J_14N, DQ58M13IO, LVDS3J_14P, DQ58M14IO, PLL_3J_CLKOUT0N, LVDS3J_15N, DQ58P15IO, PLL_3J_CLKOUT0P, PLL_3J_CLKOUT0, PLL_3J_FBP, PLL_3J_FB0, LVDS3J_15P, DQ58P16IO, LVDS3J_16N, DQSN58P13IO, LVDS3J_16P, DQS58P12IO, LVDS3J_17N, DQ58R16IO, LVDS3J_17P, DQ58R17IO, LVDS3J_18N, DQ58R14IO, LVDS3J_18P, DQ58R13IO, LVDS3J_19N, DQ59T19IO, LVDS3J_19P, DQ59U19IO, LVDS3J_20N, DQ59R18IO, LVDS3J_20P, DQ59R19IO, LVDS3J_21N, DQ59W18IO, LVDS3J_21P, DQ59V17IO, LVDS3J_22N, DQSN59T17IO, LVDS3J_22P, DQS59U17IO, LVDS3J_23N, DQ59U18IO, LVDS3J_23P, DQ59V18IO, LVDS3J_24N, DQ59T16IO, LVDS3J_24P, DQ59T15
IO, LVDS3K_1N, DQ52 M15IO, LVDS3K_1P, DQ52 N15IO, LVDS3K_2N, DQ52 N18IO, LVDS3K_2P, DQ52 P18IO, LVDS3K_3N, DQ52 K16IO, LVDS3K_3P, DQ52 L16
IO, LVDS3K_4N, DQSN52 K17IO, LVDS3K_4P, DQS52 L17
IO, LVDS3K_5N, DQ52 N17IO, LVDS3K_5P, DQ52 N16IO, LVDS3K_6N, DQ52 M18IO, LVDS3K_6P, DQ52 M17IO, LVDS3K_7N, DQ53 J14IO, LVDS3K_7P, DQ53 K14IO, LVDS3K_8N, DQ53 H17IO, LVDS3K_8P, DQ53 G17IO, LVDS3K_9N, DQ53 F15IO, LVDS3K_9P, DQ53 G15
IO, PLL_3K_CLKOUT1N, LVDS3K_10N, DQSN53 J15IO, PLL_3K_CLKOUT1P, PLL_3K_CLKOUT1, PLL_3K_FBN, LVDS3K_10P, DQS53 H15
IO, LVDS3K_11N, DQ53 L14IO, RZQ_3K, LVDS3K_11P, DQ53 L15
IO, CLK_3K_1N, LVDS3K_12N, DQ53 H16IO, CLK_3K_1P, LVDS3K_12P, DQ53 J16IO, CLK_3K_0N, LVDS3K_13N, DQ54 F16IO, CLK_3K_0P, LVDS3K_13P, DQ54 E16
IO, LVDS3K_14N, DQ54 D15IO, LVDS3K_14P, DQ54 C15
IO, PLL_3K_CLKOUT0N, LVDS3K_15N, DQ54 B15IO, PLL_3K_CLKOUT0P, PLL_3K_CLKOUT0, PLL_3K_FBP, PLL_3K_FB0, LVDS3K_15P, DQ54 A16
IO, LVDS3K_16N, DQSN54 B13IO, LVDS3K_16P, DQS54 B14
IO, LVDS3K_17N, DQ54 A15IO, LVDS3K_17P, DQ54 A14IO, LVDS3K_18N, DQ54 D16IO, LVDS3K_18P, DQ54 C16IO, LVDS3K_19N, DQ55 A12IO, LVDS3K_19P, DQ55 B12IO, LVDS3K_20N, DQ55 D14IO, LVDS3K_20P, DQ55 E14IO, LVDS3K_21N, DQ55 C12IO, LVDS3K_21P, DQ55 C13
IO, LVDS3K_22N, DQSN55 F14IO, LVDS3K_22P, DQS55 G14
IO, LVDS3K_23N, DQ55 D13IO, LVDS3K_23P, DQ55 E13IO, LVDS3K_24N, DQ55 H13IO, LVDS3K_24P, DQ55 G13
IO, LVDS3L_1N, DQ48 B20IO, LVDS3L_1P, DQ48 A19IO, LVDS3L_2N, DQ48 B17IO, LVDS3L_2P, DQ48 A17IO, LVDS3L_3N, DQ48 A21IO, LVDS3L_3P, DQ48 A20
IO, LVDS3L_4N, DQSN48 C18IO, LVDS3L_4P, DQS48 C17
IO, LVDS3L_5N, DQ48 B22IO, LVDS3L_5P, DQ48 A22IO, LVDS3L_6N, DQ48 B19IO, LVDS3L_6P, DQ48 B18IO, LVDS3L_7N, DQ49 E17IO, LVDS3L_7P, DQ49 F17IO, LVDS3L_8N, DQ49 D18IO, LVDS3L_8P, DQ49 E18IO, LVDS3L_9N, DQ49 D19IO, LVDS3L_9P, DQ49 E19
IO, PLL_3L_CLKOUT1N, LVDS3L_10N, DQSN49 C20IO, PLL_3L_CLKOUT1P, PLL_3L_CLKOUT1, PLL_3L_FBN, LVDS3L_10P, DQS49 D20
IO, LVDS3L_11N, DQ49 D21IO, RZQ_3L, LVDS3L_11P, DQ49 E21
IO, CLK_3L_1N, LVDS3L_12N, DQ49 C21IO, CLK_3L_1P, LVDS3L_12P, DQ49 C22IO, CLK_3L_0N, LVDS3L_13N, DQ50 J19IO, CLK_3L_0P, LVDS3L_13P, DQ50 J20
IO, LVDS3L_14N, DQ50 F19IO, LVDS3L_14P, DQ50 G19
IO, PLL_3L_CLKOUT0N, LVDS3L_15N, DQ50 K18IO, PLL_3L_CLKOUT0P, PLL_3L_CLKOUT0, PLL_3L_FBP, PLL_3L_FB0, LVDS3L_15P, DQ50 J18
IO, LVDS3L_16N, DQSN50 F21IO, LVDS3L_16P, DQS50 F20
IO, LVDS3L_17N, DQ50 H18IO, LVDS3L_17P, DQ50 G18IO, LVDS3L_18N, DQ50 H20IO, LVDS3L_18P, DQ50 G20IO, LVDS3L_19N, DQ51 H21IO, LVDS3L_19P, DQ51 J21IO, LVDS3L_20N, DQ51 L19IO, LVDS3L_20P, DQ51 K19IO, LVDS3L_21N, DQ51 L21IO, LVDS3L_21P, DQ51 K21
IO, LVDS3L_22N, DQSN51 L20IO, LVDS3L_22P, DQS51 M20
IO, LVDS3L_23N, DQ51 N21IO, LVDS3L_23P, DQ51 P21IO, LVDS3L_24N, DQ51 N20IO, LVDS3L_24P, DQ51 P20
R3974.7K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 XCVR Banks - 1C/D/E/F
External Clock Input
CFP4
QSFP28 IF0
QSFP28 IF1
LPBK
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
CLKIN_SMA_1C_N
CLKIN_SMA_1C_P
CLKIN_SMA_1C_NCLKIN_SMA_1C_P
GXBL_1F_RXP0GXBL_1F_RXN0
GXBL_1F_TXP0GXBL_1F_TXN0
GXBL_1F_TXP0GXBL_1F_TXN0
GXBL_1F_TXP1GXBL_1F_TXN1GXBL_1F_TXP2GXBL_1F_TXN2GXBL_1F_TXP3GXBL_1F_TXN3GXBL_1F_TXP4GXBL_1F_TXN4GXBL_1F_TXP5GXBL_1F_TXN5
GXBL_1F_TXN1GXBL_1F_TXP1
GXBL_1F_TXN2GXBL_1F_TXP2GXBL_1F_TXP3GXBL_1F_TXN3GXBL_1F_TXP4GXBL_1F_TXN4GXBL_1F_TXP5GXBL_1F_TXN5
GXBL_1F_RXN1GXBL_1F_RXP1
GXBL_1F_RXN2GXBL_1F_RXP2
GXBL_1F_RXN3GXBL_1F_RXP3GXBL_1F_RXP4GXBL_1F_RXN4GXBL_1F_RXP5GXBL_1F_RXN5
CLK_CFP4_644M_N5 CLK_CFP4_644M_P5
CLK_QSFP0_644MT_N5 CLK_QSFP0_644MT_P5
GXBL_1D_RXN021 GXBL_1D_RXP021
GXBL_1D_TXP021 GXBL_1D_TXN021
CLK_QSFP0_644MB_P5 CLK_QSFP0_644MB_N5
GXBL_1E_TXN0 22GXBL_1E_TXP0 22
CLK_GXBL1E_614MT_N 6CLK_GXBL1E_614MT_P 6
CLK_GXBL1E_614MB_P 6CLK_GXBL1E_614MB_N 6
CLK_GXBL1F_625M_P 6CLK_GXBL1F_625M_N 6
GXBL_1D_TXP121
GXBL_1D_RXP121 GXBL_1D_RXN121
GXBL_1D_TXN121
GXBL_1D_RXP321 GXBL_1D_RXN321
GXBL_1D_TXN321 GXBL_1D_TXP321
GXBL_1D_RXN421 GXBL_1D_RXP421
GXBL_1D_TXN421 GXBL_1D_TXP421
GXBL_1E_TXP1 22GXBL_1E_TXN1 22
GXBL_1E_TXP3 22GXBL_1E_TXN3 22GXBL_1E_TXN4 22GXBL_1E_TXP4 22
GXBL_1C_TXP019 GXBL_1C_TXN019
GXBL_1C_RXP019 GXBL_1C_RXN019
GXBL_1C_TXP119 GXBL_1C_TXN119
GXBL_1C_TXN319 GXBL_1C_TXP319
GXBL_1C_TXN419 GXBL_1C_TXP419
GXBL_1C_RXN119 GXBL_1C_RXP119
GXBL_1C_RXN319 GXBL_1C_RXP319GXBL_1C_RXP419 GXBL_1C_RXN419
GXBL_1E_RXP1 22GXBL_1E_RXN1 22
GXBL_1E_RXP4 22GXBL_1E_RXN4 22GXBL_1E_RXN3 22GXBL_1E_RXP3 22
GXBL_1E_RXN0 22GXBL_1E_RXP0 22
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B33 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B33 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B33 53Monday, March 13, 2017
C144868nF
J651
2345
C144368nF
BANK 1
DBANK 1
C
BANK 1
EBANK 1
F
1SG280LU3F50E3VGS1
U43AREFCLK_GXBL1C_CHTPAP41REFCLK_GXBL1C_CHTNAP40
GXBL1C_TX_CH5NBC46GXBL1C_TX_CH5PBC47
GXBL1C_RX_CH5N, GXBL1C_REFCLK5NBD44GXBL1C_RX_CH5P, GXBL1C_REFCLK5PBD45
GXBL1C_TX_CH4NBF48GXBL1C_TX_CH4PBF49
GXBL1C_RX_CH4N, GXBL1C_REFCLK4NBC42GXBL1C_RX_CH4P, GXBL1C_REFCLK4PBC43
GXBL1C_TX_CH3NBE46GXBL1C_TX_CH3PBE47
GXBL1C_RX_CH3N, GXBL1C_REFCLK3NBE42GXBL1C_RX_CH3P, GXBL1C_REFCLK3PBE43
GXBL1C_TX_CH2NBG46GXBL1C_TX_CH2PBG47
GXBL1C_RX_CH2N, GXBL1C_REFCLK2NBG42GXBL1C_RX_CH2P, GXBL1C_REFCLK2PBG43
GXBL1C_TX_CH1NBF44GXBL1C_TX_CH1PBF45
GXBL1C_RX_CH1N, GXBL1C_REFCLK1NBJ42GXBL1C_RX_CH1P, GXBL1C_REFCLK1PBJ43
GXBL1C_TX_CH0NBJ45GXBL1C_TX_CH0PBJ46
GXBL1C_RX_CH0N, GXBL1C_REFCLK0NBH40GXBL1C_RX_CH0P, GXBL1C_REFCLK0PBH41
REFCLK_GXBL1C_CHBPAT41REFCLK_GXBL1C_CHBNAT40
REFCLK_GXBL1D_CHTPAK41REFCLK_GXBL1D_CHTNAK40
GXBL1D_TX_CH5NAU46GXBL1D_TX_CH5PAU47
GXBL1D_RX_CH5N, GXBL1D_REFCLK5NAV44GXBL1D_RX_CH5P, GXBL1D_REFCLK5PAV45
GXBL1D_TX_CH4NAY48GXBL1D_TX_CH4PAY49
GXBL1D_RX_CH4N, GXBL1D_REFCLK4NAU42GXBL1D_RX_CH4P, GXBL1D_REFCLK4PAU43
GXBL1D_TX_CH3NAW46GXBL1D_TX_CH3PAW47
GXBL1D_RX_CH3N, GXBL1D_REFCLK3NAY44GXBL1D_RX_CH3P, GXBL1D_REFCLK3PAY45
GXBL1D_TX_CH2NBB48GXBL1D_TX_CH2PBB49
GXBL1D_RX_CH2N, GXBL1D_REFCLK2NAW42GXBL1D_RX_CH2P, GXBL1D_REFCLK2PAW43
GXBL1D_TX_CH1NBA46GXBL1D_TX_CH1PBA47
GXBL1D_RX_CH1N, GXBL1D_REFCLK1NBB44GXBL1D_RX_CH1P, GXBL1D_REFCLK1PBB45
GXBL1D_TX_CH0NBD48GXBL1D_TX_CH0PBD49
GXBL1D_RX_CH0N, GXBL1D_REFCLK0NBA42GXBL1D_RX_CH0P, GXBL1D_REFCLK0PBA43
REFCLK_GXBL1D_CHBPAM41REFCLK_GXBL1D_CHBNAM40
REFCLK_GXBL1E_CHTP AF41REFCLK_GXBL1E_CHTN AF40
GXBL1E_TX_CH5N AM48GXBL1E_TX_CH5P AM49
GXBL1E_RX_CH5N, GXBL1E_REFCLK5N AK44GXBL1E_RX_CH5P, GXBL1E_REFCLK5P AK45
GXBL1E_TX_CH4N AN46GXBL1E_TX_CH4P AN47
GXBL1E_RX_CH4N, GXBL1E_REFCLK4N AM44GXBL1E_RX_CH4P, GXBL1E_REFCLK4P AM45
GXBL1E_TX_CH3N AP48GXBL1E_TX_CH3P AP49
GXBL1E_RX_CH3N, GXBL1E_REFCLK3N AN42GXBL1E_RX_CH3P, GXBL1E_REFCLK3P AN43
GXBL1E_TX_CH2N AT48GXBL1E_TX_CH2P AT49
GXBL1E_RX_CH2N, GXBL1E_REFCLK2N AP44GXBL1E_RX_CH2P, GXBL1E_REFCLK2P AP45
GXBL1E_TX_CH1N AR46GXBL1E_TX_CH1P AR47
GXBL1E_RX_CH1N, GXBL1E_REFCLK1N AT44GXBL1E_RX_CH1P, GXBL1E_REFCLK1P AT45
GXBL1E_TX_CH0N AV48GXBL1E_TX_CH0P AV49
GXBL1E_RX_CH0N, GXBL1E_REFCLK0N AR42GXBL1E_RX_CH0P, GXBL1E_REFCLK0P AR43
REFCLK_GXBL1E_CHBP AH41REFCLK_GXBL1E_CHBN AH40
REFCLK_GXBL1F_CHTP AK38REFCLK_GXBL1F_CHTN AK37
GXBL1F_TX_CH5N AG46GXBL1F_TX_CH5P AG47
GXBL1F_RX_CH5N, GXBL1F_REFCLK5N AE42GXBL1F_RX_CH5P, GXBL1F_REFCLK5P AE43
GXBL1F_TX_CH4N AF48GXBL1F_TX_CH4P AF49
GXBL1F_RX_CH4N, GXBL1F_REFCLK4N AG42GXBL1F_RX_CH4P, GXBL1F_REFCLK4P AG43
GXBL1F_TX_CH3N AJ46GXBL1F_TX_CH3P AJ47
GXBL1F_RX_CH3N, GXBL1F_REFCLK3N AF44GXBL1F_RX_CH3P, GXBL1F_REFCLK3P AF45
GXBL1F_TX_CH2N AH48GXBL1F_TX_CH2P AH49
GXBL1F_RX_CH2N, GXBL1F_REFCLK2N AJ42GXBL1F_RX_CH2P, GXBL1F_REFCLK2P AJ43
GXBL1F_TX_CH1N AL46GXBL1F_TX_CH1P AL47
GXBL1F_RX_CH1N, GXBL1F_REFCLK1N AH44GXBL1F_RX_CH1P, GXBL1F_REFCLK1P AH45
GXBL1F_TX_CH0N AK48GXBL1F_TX_CH0P AK49
GXBL1F_RX_CH0N, GXBL1F_REFCLK0N AL42GXBL1F_RX_CH0P, GXBL1F_REFCLK0P AL43
REFCLK_GXBL1F_CHBP AM38REFCLK_GXBL1F_CHBN AM37
C144468nF
C143968nFC144068nF
C4010.1uF
C143868nF
C4000.1uF
C144568nF C144668nFC144168nF C144268nF
C143768nF
J661
2345
C144768nF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 XCVR Banks - 1K/L/M/N
External Clock Input
FMCB
FMCB
FMCB
SFP+ IF0
SFP+ IF1
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
CLKIN_SMA_1M_N
CLKIN_SMA_1M_P
FBM2CN10FBM2CP10
FBC2MP10FBC2MN10
FBM2CN4FBM2CP4
FBC2MN4FBC2MP4
FBM2CP5FBM2CN5
FBC2MP5FBC2MN5
FBM2CP6FBM2CN6
FBC2MP6FBC2MN6
FBM2CP7FBM2CN7
FBC2MP7FBC2MN7
FBM2CP8FBM2CN8
FBC2MP8FBC2MN8
FBM2CP9FBM2CN9
FBC2MP9FBC2MN9
FBC2MP11
FBM2CP11FBM2CN11
FBC2MN11FBC2MP12
FBM2CP12FBM2CN12
FBC2MN12FBC2MP13
FBM2CP13FBM2CN13
FBC2MN13FBC2MP14
FBM2CP14FBM2CN14
FBC2MN14FBC2MP15
FBM2CP15FBM2CN15
FBC2MN15CLK_FMCB_644M_NCLK_FMCB_644M_P
CLKIN_SMA_1M_NCLKIN_SMA_1M_P
FBGBTCLKM2_CP0FBGBTCLKM2_CN0
FBGBTCLKM2_CP1FBGBTCLKM2_CN1
FBC2MN4 27FBC2MP4 27
FBM2CN027 FBM2CP027
FBC2MN027 FBC2MP027
FBM2CP127 FBM2CN127
FBC2MN127 FBC2MP127
FBM2CN227 FBM2CP227
FBC2MP227 FBC2MN227
FBM2CP327 FBM2CN327
FBC2MN327 FBC2MP327
FBM2CN4 27FBM2CP4 27
FBC2MN5 27FBC2MP5 27
FBM2CP5 27FBM2CN5 27
FBC2MN6 27FBC2MP6 27
FBM2CN6 27FBM2CP6 27
FBC2MP7 27FBC2MN7 27
FBM2CP7 27FBM2CN7 27
FBC2MP8 27
FBM2CN8 27FBM2CP8 27
FBC2MN8 27
FBM2CP9 27FBM2CN9 27
FBC2MP9 27FBC2MN9 27
FBM2CN10 27FBM2CP10 27
FBC2MN10 27FBC2MP10 27
FBC2MN11 27
FBM2CP11 27FBM2CN11 27
FBC2MP11 27
FBM2CP12 27
FBC2MN12 27FBC2MP12 27
FBM2CN12 27
FBC2MN13 27
FBM2CP13 27FBM2CN13 27
FBC2MP13 27
FBM2CP14 27
FBC2MN14 27FBC2MP14 27
FBM2CN14 27
FBC2MP15 27FBC2MN15 27
FBM2CP15 27FBM2CN15 27
CLK_FMCB_644M_N 5CLK_FMCB_644M_P 5
CLK_SFP_644M_N5 CLK_SFP_644M_P5
CLK_GXBL1K_614M_N6 CLK_GXBL1K_614M_P6
CLK_GXBL1L_625M_P6 CLK_GXBL1L_625M_N6
GXBL_1K_RXN324 GXBL_1K_RXP324
GXBL_1K_RXN023 GXBL_1K_RXP023
FBGBTCLKM2CN0 27FBGBTCLKM2CP0 27
FBGBTCLKM2CP1 27FBGBTCLKM2CN1 27
GXBL_1K_TXP023 GXBL_1K_TXN023
GXBL_1K_TXP324 GXBL_1K_TXN324
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B34 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B34 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B34 53Monday, March 13, 2017
C14630.1uF
BANK 1
LBANK 1
K
BANK 1
MBANK 1
N
1SG280LU3F50E3VGS1
U43BREFCLK_GXBL1K_CHTPV38REFCLK_GXBL1K_CHTNV37
GXBL1K_TX_CH5NW46GXBL1K_TX_CH5PW47
GXBL1K_RX_CH5N, GXBL1K_REFCLK5NY44GXBL1K_RX_CH5P, GXBL1K_REFCLK5PY45
GXBL1K_TX_CH4NAB48GXBL1K_TX_CH4PAB49
GXBL1K_RX_CH4N, GXBL1K_REFCLK4NW42GXBL1K_RX_CH4P, GXBL1K_REFCLK4PW43
GXBL1K_TX_CH3NAA46GXBL1K_TX_CH3PAA47
GXBL1K_RX_CH3N, GXBL1K_REFCLK3NAB44GXBL1K_RX_CH3P, GXBL1K_REFCLK3PAB45
GXBL1K_TX_CH2NAD48GXBL1K_TX_CH2PAD49
GXBL1K_RX_CH2N, GXBL1K_REFCLK2NAA42GXBL1K_RX_CH2P, GXBL1K_REFCLK2PAA43
GXBL1K_TX_CH1NAC46GXBL1K_TX_CH1PAC47
GXBL1K_RX_CH1N, GXBL1K_REFCLK1NAD44GXBL1K_RX_CH1P, GXBL1K_REFCLK1PAD45
GXBL1K_TX_CH0NAE46GXBL1K_TX_CH0PAE47
GXBL1K_RX_CH0N, GXBL1K_REFCLK0NAC42GXBL1K_RX_CH0P, GXBL1K_REFCLK0PAC43
REFCLK_GXBL1K_CHBPY38REFCLK_GXBL1K_CHBNY37
REFCLK_GXBL1L_CHTPAB41REFCLK_GXBL1L_CHTNAB40
GXBL1L_TX_CH5NR46GXBL1L_TX_CH5PR47
GXBL1L_RX_CH5N, GXBL1L_REFCLK5NM44GXBL1L_RX_CH5P, GXBL1L_REFCLK5PM45
GXBL1L_TX_CH4NP48GXBL1L_TX_CH4PP49
GXBL1L_RX_CH4N, GXBL1L_REFCLK4NR42GXBL1L_RX_CH4P, GXBL1L_REFCLK4PR43
GXBL1L_TX_CH3NT48GXBL1L_TX_CH3PT49
GXBL1L_RX_CH3N, GXBL1L_REFCLK3NP44GXBL1L_RX_CH3P, GXBL1L_REFCLK3PP45
GXBL1L_TX_CH2NU46GXBL1L_TX_CH2PU47
GXBL1L_RX_CH2N, GXBL1L_REFCLK2NT44GXBL1L_RX_CH2P, GXBL1L_REFCLK2PT45
GXBL1L_TX_CH1NV48GXBL1L_TX_CH1PV49
GXBL1L_RX_CH1N, GXBL1L_REFCLK1NU42GXBL1L_RX_CH1P, GXBL1L_REFCLK1PU43
GXBL1L_TX_CH0NY48GXBL1L_TX_CH0PY49
GXBL1L_RX_CH0N, GXBL1L_REFCLK0NV44GXBL1L_RX_CH0P, GXBL1L_REFCLK0PV45
REFCLK_GXBL1L_CHBPAD41REFCLK_GXBL1L_CHBNAD40
REFCLK_GXBL1M_CHTP V41REFCLK_GXBL1M_CHTN V40
GXBL1M_TX_CH5N J46GXBL1M_TX_CH5P J47
GXBL1M_RX_CH5N, GXBL1M_REFCLK5N F44GXBL1M_RX_CH5P, GXBL1M_REFCLK5P F45
GXBL1M_TX_CH4N H48GXBL1M_TX_CH4P H49
GXBL1M_RX_CH4N, GXBL1M_REFCLK4N J42GXBL1M_RX_CH4P, GXBL1M_REFCLK4P J43
GXBL1M_TX_CH3N L46GXBL1M_TX_CH3P L47
GXBL1M_RX_CH3N, GXBL1M_REFCLK3N H44GXBL1M_RX_CH3P, GXBL1M_REFCLK3P H45
GXBL1M_TX_CH2N K48GXBL1M_TX_CH2P K49
GXBL1M_RX_CH2N, GXBL1M_REFCLK2N L42GXBL1M_RX_CH2P, GXBL1M_REFCLK2P L43
GXBL1M_TX_CH1N N46GXBL1M_TX_CH1P N47
GXBL1M_RX_CH1N, GXBL1M_REFCLK1N K44GXBL1M_RX_CH1P, GXBL1M_REFCLK1P K45
GXBL1M_TX_CH0N M48GXBL1M_TX_CH0P M49
GXBL1M_RX_CH0N, GXBL1M_REFCLK0N N42GXBL1M_RX_CH0P, GXBL1M_REFCLK0P N43
REFCLK_GXBL1M_CHBP Y41REFCLK_GXBL1M_CHBN Y40
REFCLK_GXBL1N_CHTP P41REFCLK_GXBL1N_CHTN P40
GXBL1N_TX_CH5N B44GXBL1N_TX_CH5P B45
GXBL1N_RX_CH5N, GXBL1N_REFCLK5N B40GXBL1N_RX_CH5P, GXBL1N_REFCLK5P B41
GXBL1N_TX_CH4N C46GXBL1N_TX_CH4P C47
GXBL1N_RX_CH4N, GXBL1N_REFCLK4N A42GXBL1N_RX_CH4P, GXBL1N_REFCLK4P A43
GXBL1N_TX_CH3N E46GXBL1N_TX_CH3P E47
GXBL1N_RX_CH3N, GXBL1N_REFCLK3N C42GXBL1N_RX_CH3P, GXBL1N_REFCLK3P C43
GXBL1N_TX_CH2N D48GXBL1N_TX_CH2P D49
GXBL1N_RX_CH2N, GXBL1N_REFCLK2N E42GXBL1N_RX_CH2P, GXBL1N_REFCLK2P E43
GXBL1N_TX_CH1N G46GXBL1N_TX_CH1P G47
GXBL1N_RX_CH1N, GXBL1N_REFCLK1N D44GXBL1N_RX_CH1P, GXBL1N_REFCLK1P D45
GXBL1N_TX_CH0N F48GXBL1N_TX_CH0P F49
GXBL1N_RX_CH0N, GXBL1N_REFCLK0N G42GXBL1N_RX_CH0P, GXBL1N_REFCLK0P G43
REFCLK_GXBL1N_CHBP T41REFCLK_GXBL1N_CHBN T40
C14640.1uF
J681
2345
J671
2345
C14610.1uFC14620.1uF
C4030.1uF
C4020.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 XCVR Banks - 4C/D/E/F
External Clock Input
2.4mm RF
MXP0
MXP1
MXP2
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
CLKIN_SMA_4C_N
CLKIN_SMA_4C_P
CLKIN_SMA_4C_NCLKIN_SMA_4C_P
CLK_SMA_706M_N5 CLK_SMA_706M_P5
GXBR_4C_TXP425 GXBR_4C_TXN425
GXBR_4C_TXN025 GXBR_4C_TXP025
GXBR_4C_RXP025 GXBR_4C_RXN025
GXBR_4C_TXP125 GXBR_4C_TXN125
GXBR_4C_RXP125 GXBR_4C_RXN125
GXBR_4C_TXN325
GXBR_4C_RXP325 GXBR_4C_RXN325
GXBR_4C_TXP325
GXBR_4C_RXP425 GXBR_4C_RXN425
GXBR_4D_TXN025 GXBR_4D_TXP025
GXBR_4D_RXN025 GXBR_4D_RXP025
GXBR_4D_RXN125
GXBR_4D_TXP125 GXBR_4D_TXN125
GXBR_4D_RXP125
GXBR_4D_RXP325 GXBR_4D_RXN325
GXBR_4D_TXP325 GXBR_4D_TXN325GXBR_4D_TXN425 GXBR_4D_TXP425
GXBR_4D_RXN425 GXBR_4D_RXP425
CLK_MXP1_706M_P5 CLK_MXP1_706M_N5
GXBR_4C_TXP225 GXBR_4C_TXN225
GXBR_4C_RXP225 GXBR_4C_RXN225
GXBR_4C_TXN525 GXBR_4C_TXP525
GXBR_4C_RXP525
CLK_GXBR4D_644M_N7 CLK_GXBR4D_644M_P7
GXBR_4C_RXN525
CLK_MXP2_706M_N 5CLK_MXP2_706M_P 5
GXBR_4E_TXN0 25GXBR_4E_TXP0 25
GXBR_4E_RXP0 25GXBR_4E_RXN0 25
CLK_GXBR4E_644M_N 7CLK_GXBR4E_644M_P 7
GXBR_4E_TXP1 25GXBR_4E_TXN1 25
GXBR_4E_RXP1 25GXBR_4E_RXN1 25
GXBR_4E_RXP3 25GXBR_4E_RXN3 25
GXBR_4E_TXP3 25GXBR_4E_TXN3 25
GXBR_4E_RXP4 25
GXBR_4E_TXN4 25GXBR_4E_TXP4 25
GXBR_4E_RXN4 25
GXBR_4F_TXP0 25GXBR_4F_TXN0 25
GXBR_4F_RXP0 25GXBR_4F_RXN0 25
GXBR_4F_TXP1 25
GXBR_4F_RXN1 25GXBR_4F_RXP1 25
GXBR_4F_TXN1 25
GXBR_4F_TXP3 25
GXBR_4F_RXP3 25
GXBR_4F_TXN3 25
GXBR_4F_RXN3 25
GXBR_4F_TXP4 25GXBR_4F_TXN4 25
GXBR_4F_RXP4 25GXBR_4F_RXN4 25
CLK_MXP3_706M_P 5CLK_MXP3_706M_N 5
CLK_GXBR4F_644M_P 7CLK_GXBR4F_644M_N 7
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B35 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B35 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B35 53Monday, March 13, 2017
C4040.1uFJ691
2345
J701
2345
C4050.1uF
BANK 4
CBANK 4
D
BANK 4
EBANK 4
F
1SG280LU3F50E3VGS1
U43GREFCLK_GXBR4C_CHTPAP9REFCLK_GXBR4C_CHTNAP10
GXBR4C_TX_CH5NBC4GXBR4C_TX_CH5PBC3
GXBR4C_RX_CH5N, GXBR4C_REFCLK5NBD6GXBR4C_RX_CH5P, GXBR4C_REFCLK5PBD5
GXBR4C_TX_CH4NBF2GXBR4C_TX_CH4PBF1
GXBR4C_RX_CH4N, GXBR4C_REFCLK4NBC8GXBR4C_RX_CH4P, GXBR4C_REFCLK4PBC7
GXBR4C_TX_CH3NBE4GXBR4C_TX_CH3PBE3
GXBR4C_RX_CH3N, GXBR4C_REFCLK3NBE8GXBR4C_RX_CH3P, GXBR4C_REFCLK3PBE7
GXBR4C_TX_CH2NBG4GXBR4C_TX_CH2PBG3
GXBR4C_RX_CH2N, GXBR4C_REFCLK2NBG8GXBR4C_RX_CH2P, GXBR4C_REFCLK2PBG7
GXBR4C_TX_CH1NBF6GXBR4C_TX_CH1PBF5
GXBR4C_RX_CH1N, GXBR4C_REFCLK1NBJ8GXBR4C_RX_CH1P, GXBR4C_REFCLK1PBJ7
GXBR4C_TX_CH0NBJ5GXBR4C_TX_CH0PBJ4
GXBR4C_RX_CH0N, GXBR4C_REFCLK0NBH10GXBR4C_RX_CH0P, GXBR4C_REFCLK0PBH9
REFCLK_GXBR4C_CHBPAT9REFCLK_GXBR4C_CHBNAT10
REFCLK_GXBR4D_CHTPAK9REFCLK_GXBR4D_CHTNAK10
GXBR4D_TX_CH5NAU4GXBR4D_TX_CH5PAU3
GXBR4D_RX_CH5N, GXBR4D_REFCLK5NAV6GXBR4D_RX_CH5P, GXBR4D_REFCLK5PAV5
GXBR4D_TX_CH4NAY2GXBR4D_TX_CH4PAY1
GXBR4D_RX_CH4N, GXBR4D_REFCLK4NAU8GXBR4D_RX_CH4P, GXBR4D_REFCLK4PAU7
GXBR4D_TX_CH3NAW4GXBR4D_TX_CH3PAW3
GXBR4D_RX_CH3N, GXBR4D_REFCLK3NAY6GXBR4D_RX_CH3P, GXBR4D_REFCLK3PAY5
GXBR4D_TX_CH2NBB2GXBR4D_TX_CH2PBB1
GXBR4D_RX_CH2N, GXBR4D_REFCLK2NAW8GXBR4D_RX_CH2P, GXBR4D_REFCLK2PAW7
GXBR4D_TX_CH1NBA4GXBR4D_TX_CH1PBA3
GXBR4D_RX_CH1N, GXBR4D_REFCLK1NBB6GXBR4D_RX_CH1P, GXBR4D_REFCLK1PBB5
GXBR4D_TX_CH0NBD2GXBR4D_TX_CH0PBD1
GXBR4D_RX_CH0N, GXBR4D_REFCLK0NBA8GXBR4D_RX_CH0P, GXBR4D_REFCLK0PBA7
REFCLK_GXBR4D_CHBPAM9REFCLK_GXBR4D_CHBNAM10
REFCLK_GXBR4E_CHTP AF9REFCLK_GXBR4E_CHTN AF10
GXBR4E_TX_CH5N AM2GXBR4E_TX_CH5P AM1
GXBR4E_RX_CH5N, GXBR4E_REFCLK5N AK6GXBR4E_RX_CH5P, GXBR4E_REFCLK5P AK5
GXBR4E_TX_CH4N AN4GXBR4E_TX_CH4P AN3
GXBR4E_RX_CH4N, GXBR4E_REFCLK4N AM6GXBR4E_RX_CH4P, GXBR4E_REFCLK4P AM5
GXBR4E_TX_CH3N AP2GXBR4E_TX_CH3P AP1
GXBR4E_RX_CH3N, GXBR4E_REFCLK3N AN8GXBR4E_RX_CH3P, GXBR4E_REFCLK3P AN7
GXBR4E_TX_CH2N AT2GXBR4E_TX_CH2P AT1
GXBR4E_RX_CH2N, GXBR4E_REFCLK2N AP6GXBR4E_RX_CH2P, GXBR4E_REFCLK2P AP5
GXBR4E_TX_CH1N AR4GXBR4E_TX_CH1P AR3
GXBR4E_RX_CH1N, GXBR4E_REFCLK1N AT6GXBR4E_RX_CH1P, GXBR4E_REFCLK1P AT5
GXBR4E_TX_CH0N AV2GXBR4E_TX_CH0P AV1
GXBR4E_RX_CH0N, GXBR4E_REFCLK0N AR8GXBR4E_RX_CH0P, GXBR4E_REFCLK0P AR7
REFCLK_GXBR4E_CHBP AH9REFCLK_GXBR4E_CHBN AH10
REFCLK_GXBR4F_CHTP AK12REFCLK_GXBR4F_CHTN AK13
GXBR4F_TX_CH5N AG4GXBR4F_TX_CH5P AG3
GXBR4F_RX_CH5N, GXBR4F_REFCLK5N AE8GXBR4F_RX_CH5P, GXBR4F_REFCLK5P AE7
GXBR4F_TX_CH4N AF2GXBR4F_TX_CH4P AF1
GXBR4F_RX_CH4N, GXBR4F_REFCLK4N AG8GXBR4F_RX_CH4P, GXBR4F_REFCLK4P AG7
GXBR4F_TX_CH3N AJ4GXBR4F_TX_CH3P AJ3
GXBR4F_RX_CH3N, GXBR4F_REFCLK3N AF6GXBR4F_RX_CH3P, GXBR4F_REFCLK3P AF5
GXBR4F_TX_CH2N AH2GXBR4F_TX_CH2P AH1
GXBR4F_RX_CH2N, GXBR4F_REFCLK2N AJ8GXBR4F_RX_CH2P, GXBR4F_REFCLK2P AJ7
GXBR4F_TX_CH1N AL4GXBR4F_TX_CH1P AL3
GXBR4F_RX_CH1N, GXBR4F_REFCLK1N AH6GXBR4F_RX_CH1P, GXBR4F_REFCLK1P AH5
GXBR4F_TX_CH0N AK2GXBR4F_TX_CH0P AK1
GXBR4F_RX_CH0N, GXBR4F_REFCLK0N AL8GXBR4F_RX_CH0P, GXBR4F_REFCLK0P AL7
REFCLK_GXBR4F_CHBP AM12REFCLK_GXBR4F_CHBN AM13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 XCVR Banks - 4K/L/M/N
External Clock Input
FMCA
FMCAFMCA
FMCA
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
CLKIN_SMA_4K_N
CLKIN_SMA_4K_P
CLKIN_SMA_4K_NCLKIN_SMA_4K_P
FAGBTCLKM2_CN0FAGBTCLKM2_CP0
FAGBTCLKM2_CP1FAGBTCLKM2_CN1
FAGBTCLKM2_CP2FAGBTCLKM2_CN2
FAGBTCLKM2_CP3FAGBTCLKM2_CN3
CLK_GXBR4L_644M_P7 CLK_GXBR4L_644M_N7
CLK_GXBR4M_625M_P 7CLK_GXBR4M_625M_N 7
FAC2MP026
FAM2CP026 FAM2CN026
FAC2MN026 FAC2MP126
FAM2CN126 FAM2CP126
FAC2MN126 FAC2MP226 FAC2MN226
FAM2CP226 FAM2CN226
FAC2MN326 FAC2MP326
FAM2CN326 FAM2CP326
FAM2CN426
FAC2MP426 FAC2MN426
FAM2CP426
FAM2CN526 FAM2CP526
FAC2MN526 FAC2MP526
FAM2CN626 FAM2CP626
FAC2MP626 FAC2MN626
FAM2CP726 FAM2CN726
FAC2MN726 FAC2MP726
FAM2CN826 FAM2CP826
FAC2MP826 FAC2MN826 FAC2MP926
FAM2CP926 FAM2CN926
FAC2MN926
FAM2CP1026
FAC2MP1026 FAC2MN1026
FAM2CN1026
FAC2MN1126 FAC2MP1126
FAM2CP1126 FAM2CN1126
FAM2CP12 26
FAC2MP12 26FAC2MN12 26
FAM2CN12 26
FAC2MN13 26FAC2MP13 26
FAM2CP13 26FAM2CN13 26FAM2CP14 26
FAC2MP14 26FAC2MN14 26
FAM2CN14 26
FAC2MP15 26
FAM2CP15 26FAM2CN15 26
FAC2MN15 26
FAM2CN16 26FAM2CP16 26
FAC2MP16 26FAC2MN16 26
FAM2CP17 26FAM2CN17 26
FAC2MN17 26FAC2MP17 26
FAM2CN18 26FAM2CP18 26
FAC2MN18 26FAC2MP18 26
FAM2CP19 26FAM2CN19 26
FAC2MN19 26FAC2MP19 26
FAC2MN20 26
FAM2CN20 26FAM2CP20 26
FAC2MP20 26
FAM2CN21 26
FAC2MN21 26FAC2MP21 26
FAM2CP21 26
FAC2MP22 26FAC2MN22 26
FAM2CN22 26FAM2CP22 26
FAC2MN23 26FAC2MP23 26
FAM2CP23 26FAM2CN23 26
CLK_FMCA_706M_N 5CLK_FMCA_706M_P 5
FAGBTCLKM2CP026 FAGBTCLKM2CN026
FAGBTCLKM2CN126 FAGBTCLKM2CP126
FAGBTCLKM2CN2 26FAGBTCLKM2CP2 26
FAGBTCLKM2CN3 26FAGBTCLKM2CP3 26
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B36 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B36 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B36 53Monday, March 13, 2017
J711
2345
C14700.1uF
J721
2345
C14710.1uF
C4070.1uF
C14720.1uF
C4060.1uF
C14650.1uF
C14670.1uFC14680.1uF
C14660.1uF
BANK 4
K
BANK 4
M
BANK 4
L
BANK 4
N
1SG280LU3F50E3VGS1
U43HREFCLK_GXBR4K_CHTPV12REFCLK_GXBR4K_CHTNV13
GXBR4K_TX_CH5NW4GXBR4K_TX_CH5PW3
GXBR4K_RX_CH5N, GXBR4K_REFCLK5NY6GXBR4K_RX_CH5P, GXBR4K_REFCLK5PY5
GXBR4K_TX_CH4NAB2GXBR4K_TX_CH4PAB1
GXBR4K_RX_CH4N, GXBR4K_REFCLK4NW8GXBR4K_RX_CH4P, GXBR4K_REFCLK4PW7
GXBR4K_TX_CH3NAA4GXBR4K_TX_CH3PAA3
GXBR4K_RX_CH3N, GXBR4K_REFCLK3NAB6GXBR4K_RX_CH3P, GXBR4K_REFCLK3PAB5
GXBR4K_TX_CH2NAD2GXBR4K_TX_CH2PAD1
GXBR4K_RX_CH2N, GXBR4K_REFCLK2NAA8GXBR4K_RX_CH2P, GXBR4K_REFCLK2PAA7
GXBR4K_TX_CH1NAC4GXBR4K_TX_CH1PAC3
GXBR4K_RX_CH1N, GXBR4K_REFCLK1NAD6GXBR4K_RX_CH1P, GXBR4K_REFCLK1PAD5
GXBR4K_TX_CH0NAE4GXBR4K_TX_CH0PAE3
GXBR4K_RX_CH0N, GXBR4K_REFCLK0NAC8GXBR4K_RX_CH0P, GXBR4K_REFCLK0PAC7
REFCLK_GXBR4K_CHBPY12REFCLK_GXBR4K_CHBNY13
REFCLK_GXBR4L_CHTPAB9REFCLK_GXBR4L_CHTNAB10
GXBR4L_TX_CH5NR4GXBR4L_TX_CH5PR3
GXBR4L_RX_CH5N, GXBR4L_REFCLK5NM6GXBR4L_RX_CH5P, GXBR4L_REFCLK5PM5
GXBR4L_TX_CH4NP2GXBR4L_TX_CH4PP1
GXBR4L_RX_CH4N, GXBR4L_REFCLK4NR8GXBR4L_RX_CH4P, GXBR4L_REFCLK4PR7
GXBR4L_TX_CH3NT2GXBR4L_TX_CH3PT1
GXBR4L_RX_CH3N, GXBR4L_REFCLK3NP6GXBR4L_RX_CH3P, GXBR4L_REFCLK3PP5
GXBR4L_TX_CH2NU4GXBR4L_TX_CH2PU3
GXBR4L_RX_CH2N, GXBR4L_REFCLK2NT6GXBR4L_RX_CH2P, GXBR4L_REFCLK2PT5
GXBR4L_TX_CH1NV2GXBR4L_TX_CH1PV1
GXBR4L_RX_CH1N, GXBR4L_REFCLK1NU8GXBR4L_RX_CH1P, GXBR4L_REFCLK1PU7
GXBR4L_TX_CH0NY2GXBR4L_TX_CH0PY1
GXBR4L_RX_CH0N, GXBR4L_REFCLK0NV6GXBR4L_RX_CH0P, GXBR4L_REFCLK0PV5
REFCLK_GXBR4L_CHBPAD9REFCLK_GXBR4L_CHBNAD10
REFCLK_GXBR4M_CHTP V9REFCLK_GXBR4M_CHTN V10
GXBR4M_TX_CH5N J4GXBR4M_TX_CH5P J3
GXBR4M_RX_CH5N, GXBR4M_REFCLK5N F6GXBR4M_RX_CH5P, GXBR4M_REFCLK5P F5
GXBR4M_TX_CH4N H2GXBR4M_TX_CH4P H1
GXBR4M_RX_CH4N, GXBR4M_REFCLK4N J8GXBR4M_RX_CH4P, GXBR4M_REFCLK4P J7
GXBR4M_TX_CH3N L4GXBR4M_TX_CH3P L3
GXBR4M_RX_CH3N, GXBR4M_REFCLK3N H6GXBR4M_RX_CH3P, GXBR4M_REFCLK3P H5
GXBR4M_TX_CH2N K2GXBR4M_TX_CH2P K1
GXBR4M_RX_CH2N, GXBR4M_REFCLK2N L8GXBR4M_RX_CH2P, GXBR4M_REFCLK2P L7
GXBR4M_TX_CH1N N4GXBR4M_TX_CH1P N3
GXBR4M_RX_CH1N, GXBR4M_REFCLK1N K6GXBR4M_RX_CH1P, GXBR4M_REFCLK1P K5
GXBR4M_TX_CH0N M2GXBR4M_TX_CH0P M1
GXBR4M_RX_CH0N, GXBR4M_REFCLK0N N8GXBR4M_RX_CH0P, GXBR4M_REFCLK0P N7
REFCLK_GXBR4M_CHBP Y9REFCLK_GXBR4M_CHBN Y10
REFCLK_GXBR4N_CHTP P9REFCLK_GXBR4N_CHTN P10
GXBR4N_TX_CH5N B6GXBR4N_TX_CH5P B5
GXBR4N_RX_CH5N, GXBR4N_REFCLK5N B10GXBR4N_RX_CH5P, GXBR4N_REFCLK5P B9
GXBR4N_TX_CH4N C4GXBR4N_TX_CH4P C3
GXBR4N_RX_CH4N, GXBR4N_REFCLK4N A8GXBR4N_RX_CH4P, GXBR4N_REFCLK4P A7
GXBR4N_TX_CH3N E4GXBR4N_TX_CH3P E3
GXBR4N_RX_CH3N, GXBR4N_REFCLK3N C8GXBR4N_RX_CH3P, GXBR4N_REFCLK3P C7
GXBR4N_TX_CH2N D2GXBR4N_TX_CH2P D1
GXBR4N_RX_CH2N, GXBR4N_REFCLK2N E8GXBR4N_RX_CH2P, GXBR4N_REFCLK2P E7
GXBR4N_TX_CH1N G4GXBR4N_TX_CH1P G3
GXBR4N_RX_CH1N, GXBR4N_REFCLK1N D6GXBR4N_RX_CH1P, GXBR4N_REFCLK1P D5
GXBR4N_TX_CH0N F2GXBR4N_TX_CH0P F1
GXBR4N_RX_CH0N, GXBR4N_REFCLK0N G8GXBR4N_RX_CH0P, GXBR4N_REFCLK0P G7
REFCLK_GXBR4N_CHBP T9REFCLK_GXBR4N_CHBN T10
C14690.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC / VSS sense lines need to berouted as wide traces to itssource regulatorPlace Resistor Pads overlapping (R402/403 and R482/489) so that only a resistor can be populated
FPGA VCCIO BANK 3L
CAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
VCCLSENSEVSS_SENSEVCC_SENSE
GNDSENSE
S10_VCC S10_VCC
S10_VCCH
S10_VCCRL
S10_VCCRR
S10_VCCT
S10_VCCERAM
S10_VCCH
FMCB_VADJ
1.8V
FAM2CVIO
FMCA_VADJ
S10_VCCERAM
FAREFB FAREFAFBREFA VCCIO_3L
FMCA_VADJ
VCCIO_3L
S10_VCCAPLL
2.4V
1.8V
1.8V
FBREFAFAREFA
FAREFA
FAREFB
S10_VCCPLLDIG_SDM
VCC_SENSE42VSS_SENSE42
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B37 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B37 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B37 53Monday, March 13, 2017
C7880.1uF
C6660.47uF
1SG280LU3F50E3VGS1
U43L
VCCA_PLL AF26VCCA_PLL AF25
VCCH_GXBR AN11
VCCPT AE22
VCCH_GXBL AN39VCCH_GXBL AJ39VCCH_GXBL AJ36VCCH_GXBL U39VCCH_GXBL N39VCCH_GXBL AA39
VCCH_GXBR AJ11VCCH_GXBR U11VCCH_GXBR N11VCCH_GXBR AA11VCCH_GXBL AB38VCCH_GXBL AH38
VCCR_GXBL1CAR41VCCR_GXBL1CAR40VCCR_GXBL1CAR39VCCR_GXBL1DAL41VCCR_GXBL1DAL40VCCR_GXBL1DAL39VCCR_GXBL1EAL38VCCR_GXBL1EAL37VCCR_GXBL1EAL36VCCR_GXBL1FAG41VCCR_GXBL1FAG40VCCR_GXBL1FAG39VCCR_GXBL1KAC41VCCR_GXBL1KAC40VCCR_GXBL1KAC39VCCR_GXBL1LW38VCCR_GXBL1LW37VCCR_GXBL1LW36VCCR_GXBL1MW41VCCR_GXBL1MW40VCCR_GXBL1MW39VCCR_GXBL1NR41VCCR_GXBL1NR40VCCR_GXBL1NR39
VCCR_GXBR4CAR9VCCR_GXBR4CAR11VCCR_GXBR4CAR10VCCR_GXBR4DAL9VCCR_GXBR4DAL11VCCR_GXBR4DAL10VCCR_GXBR4EAL14VCCR_GXBR4EAL13VCCR_GXBR4EAL12VCCR_GXBR4FAG9VCCR_GXBR4FAG11VCCR_GXBR4FAG10VCCR_GXBR4KAC9VCCR_GXBR4KAC11VCCR_GXBR4KAC10VCCR_GXBR4LW14VCCR_GXBR4LW13VCCR_GXBR4LW12VCCR_GXBR4MW9VCCR_GXBR4MW11VCCR_GXBR4MW10VCCR_GXBR4NR9VCCR_GXBR4NR11VCCR_GXBR4NR10
VCCERAM Y15VCCERAM W35VCCERAM W34VCCERAM W33VCCERAM W30VCCERAM W27VCCERAM W23VCCERAM W21VCCERAM W16VCCERAM W15VCCERAM V35VCCERAM V34VCCERAM V16VCCERAM V15VCCERAM V14VCCERAM U35VCCERAM AN35VCCERAM AN31VCCERAM AN16VCCERAM AN15VCCERAM AM35VCCERAM AM34VCCERAM AM27VCCERAM AM23VCCERAM AM20VCCERAM AM15VCCERAM AL35VCCERAM AL34VCCERAM AL16VCCERAM AL15VCCERAM AK35VCCERAM AK15
VCCT_GXBL1CAN41VCCT_GXBL1CAN40
VCCT_GXBL1DAJ41 VCCT_GXBL1DAJ40
VCCT_GXBL1EAE41 VCCT_GXBL1EAE40
VCCT_GXBL1FAJ38 VCCT_GXBL1FAJ37
VCCT_GXBL1KAA41 VCCT_GXBL1KAA40
VCCT_GXBL1LU38 VCCT_GXBL1LU37
VCCT_GXBL1MU41 VCCT_GXBL1MU40
VCCT_GXBL1NN41 VCCT_GXBL1NN40
VCCT_GXBR4CAN9VCCT_GXBR4CAN10
VCCT_GXBR4DAJ9 VCCT_GXBR4DAJ10
VCCT_GXBR4EAE9 VCCT_GXBR4EAE10
VCCT_GXBR4FAJ13 VCCT_GXBR4FAJ12
VCCT_GXBR4KAA9 VCCT_GXBR4KAA10
VCCT_GXBR4LU13 VCCT_GXBR4LU12
VCCT_GXBR4MU9 VCCT_GXBR4MU10
VCCT_GXBR4NN9 VCCT_GXBR4NN10
VCCPT AE21
VCCPLLDIG_SDM AT22
VCCH_GXBR AJ14
VCCH_GXBR T12VCCH_GXBR AH12
VCCPLL_SDM AU22
VCCADC AY23
VCCPT AG33VCCPT AG32VCCPT AG30VCCPT AG29VCCPT AG27VCCPT AG25VCCPT AG22VCCPT AG20VCCPT AG18VCCPT AG17VCCPT AE33VCCPT AE32VCCPT AE29VCCPT AE28VCCPT AE26VCCPT AE24
VCCPT AE18VCCPT AE17
VCCBAT AV22VCCFUSEWR_SDM AV23
C7920.1uF
C7900.1uF
FB6120ohm, 800mA
1 2
1SG280LU3F50E3VGS1
U43N
VREFB3JN0 U16
VCCIO2ABC29VCCIO2ABB31VCCIO2AAY30
VCCIO2BAY35VCCIO2BAV34VCCIO2BAT33
VCCIO2CAR35VCCIO2CAP37VCCIO2CAN34
VCCIO2FAU26VCCIO2FAT28VCCIO2FAP27
VCCIO2LV29VCCIO2LU26VCCIO2LT28
VCCIO2MT33VCCIO2MR35VCCIO2MN34
VCCIO2NL33VCCIO2NJ32VCCIO2NH34
VCCIO3ABB16VCCIO3AAY15VCCIO3AAW17
VCCIO3BAU16VCCIO3BAT13VCCIO3BAR15
VCCIO3CAU21VCCIO3CAR20VCCIO3CAP22
VCCIO3IU21VCCIO3IT23VCCIO3IP22
VCCIO3V AG14VCCIO3V AF14
VCCIO3V AF36VCCIO3V AG36
VCCIO_SDM AU23
VREFB2AN0 AV31
VREFB2BN0 AT31
VREFB2CN0 AN32
VREFB2FN0 AR29
VREFB2LN0 V31
VREFB2MN0 P31
VREFB2NN0 M32
VREFB3AN0 AU19
VREFB3BN0 AU18
VREFB3CN0 AP19
VREFB3IN0 V20
VREFB3KN0 P19
VCCIO3JT18VCCIO3JR15VCCIO3JN14
VCCIO3KM16VCCIO3KK15VCCIO3KJ17
VCCIO3LK20VCCIO3LH19VCCIO3LG21
VREFB3LN0 M19
VCCLSENSE AG24GNDSENSE AF24
C67210uF
C40910uF
C6730.47uF
FB5220ohm, 2.0A
1 2
R401 DNI
C6670.22uF
1SG280LU3F50E3VGS1
U43MVCCY34VCCY33VCCY32VCCY31VCCY30VCCY29VCCY28VCCY27VCCY26VCCY25VCCY24VCCY23VCCY22VCCY21VCCY20VCCY19VCCY18VCCY17VCCY16VCCAM33VCCAM32VCCAM31VCCAM30VCCAM29VCCAM28VCCAM26VCCAM25VCCAM24VCCAM19VCCAM18VCCAM17VCCAL32VCCAL30VCCAL29VCCAL27VCCAL26VCCAL25VCCAL24VCCAL23VCCAL22VCCAL21VCCAL19VCCAL17VCCAK34VCCAK33VCCAK32VCCAK31VCCAK29VCCAK28VCCAK27VCCAK26VCCAK24VCCAK23VCCAK22VCCAK21VCCAK19VCCAK18VCCAK17VCCAK16VCCAJ35VCCAJ31VCCAJ30VCCAJ29VCCAJ28VCCAJ26VCCAJ25VCCAJ24VCCAJ23VCCAJ21VCCAJ20VCCAJ19VCCAJ18VCCAJ16VCCAJ15
VCCAH21 VCCAH27 VCCAH28 VCCAH30 VCCAH31
VCCAH15
VCC AG28VCC AG23VCC AG19VCC AG15VCC AF35VCC AF32VCC AF31VCC AF30VCC AF29VCC AF27VCC AF22VCC AF21VCC AF20VCC AF19VCC AE34VCC AE31VCC AE27VCC AE23VCC AE19VCC AD33VCC AD31VCC AD30VCC AD29VCC AD28VCC AD26VCC AD25VCC AD24VCC AD23VCC AD21VCC AD20VCC AD19VCC AD18VCC AC32VCC AC31VCC AC30VCC AC28VCC AC27VCC AC26VCC AC25VCC AC23VCC AC22VCC AC21VCC AC20VCC AC18VCC AC17VCC AC16VCC AB33VCC AB32VCC AB30VCC AB29VCC AB28VCC AB27VCC AB25VCC AB24VCC AB23VCC AB22VCC AB20VCC AB19VCC AB18VCC AB17VCC AA35VCC AA34VCC AA32VCC AA31VCC AA30VCC AA29VCC AA27VCC AA26VCC AA25VCC AA24VCC AA22VCC AA21VCC AA20
VCC AA17VCC AA16VCC AA15VCC AA19
VCCAH22
VCCAH25
VCCAH18
VCCAH23
VCCAH20 VCCAH26
VCC L29VCC L30VCC M28VCC M29VCC M30
VCCP W31VCCP W19VCCP AN30VCCP AL20
C6680.1uF
R402 0
R4000.001
C4080.47uF
C7930.1uF
C7910.1uF
R403 0
C7890.1uF
C4100.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 GND
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
1.8VS10_VCCS10_VCCAPLL
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B38 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B38 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B38 53Monday, March 13, 20171SG280LU3F50E3VGS1
U43QGNDBE9GNDBE6GNDBE5GNDBE49GNDBE48GNDBE45GNDBE44GNDBE41GNDBE35GNDBE30GNDBE25GNDBE20GNDBE2GNDBE15GNDBE1GNDBD9GNDBD8GNDBD7GNDBD47GNDBD46GNDBD43GNDBD42GNDBD41GNDBD4GNDBD37GNDBD32GNDBD3GNDBD27GNDBD22GNDBD17GNDBD12GNDBC9GNDBC6GNDBC5GNDBC49GNDBC48GNDBC45GNDBC44GNDBC41GNDBC39GNDBC34GNDBC24GNDBC2GNDBC19GNDBC14GNDBC1GNDBB9GNDBB8GNDBB7GNDBB47GNDBB46GNDBB43GNDBB42GNDBB41GNDBB4GNDBB36GNDBB3GNDBB26GNDBB21GNDBB11GNDBA9GNDBA6GNDBA5GNDBA49GNDBA48GNDBA45GNDBA44GNDBA41GNDBA38GNDBA33GNDBA28GNDBA23GNDBA2GNDBA18GNDBA13GNDBA1GNDB8GNDB7GNDB49GNDB48GNDB47GNDB46GNDB43GNDB42GNDB4GNDB39GNDB36
GND B21GND B2GND B16GND B11GND AY9GND AY8GND AY7GND AY47GND AY46GND AY43GND AY42GND AY41GND AY4GND AY3GND AY25GND AY20GND AY10GND AW9GND AW6GND AW5GND AW49GND AW48GND AW45GND AW44GND AW41GND AW37GND AW32GND AW27GND AW22GND AW2GND AW12GND AW1GND AV9GND AV8GND AV7GND AV47GND AV46GND AV43GND AV42GND AV41GND AV4GND AV39GND AV3GND AV29GND AV24GND AV19GND AV14GND AU9GND AU6GND AU5GND AU49GND AU48GND AU45GND AU44GND AU41GND AU40GND AU39GND AU36GND AU31GND AU2GND AU11GND AU10GND AU1GND AT8GND AT7GND AT47GND AT46GND AT43GND AT42GND AT4GND AT39GND AT3GND AT23GND AT18GND AT11GND AR6GND AR5GND AR49GND AR48GND AR45GND AR44GND AR38GND AR30GND AR25GND AR2GND AR12GND AR1
GNDB31GNDB3GNDB26
GND AP8GND AP7GND AP47
1SG280LU3F50E3VGS1
U43OVCCPTN28VCCP28VCCA_PLLR28GNDY8GNDY7GNDY47GNDY46GNDY43GNDY42GNDY4GNDY39GNDY36GNDY35GNDY3GNDY14GNDY11GNDW6GNDW5GNDW49GNDW48GNDW45GNDW44GNDW32GNDW29GNDW28GNDW26GNDW25GNDW24GNDW22GNDW20GNDW2GNDW17GNDW1GNDV8GNDV7GNDV47GNDV46GNDV43GNDV42GNDV4GNDV39GNDV36GNDV33GNDV3GNDV19GNDV11GNDU6GNDU5GNDU49GNDU48GNDU45GNDU44GNDU36GNDU31GNDU2GNDU15GNDU14GNDU1GNDT8GNDT7GNDT47GNDT46GNDT43GNDT42GNDT4GNDT39GNDT38GNDT37GNDT36GNDT3GNDT14GNDT13GNDT11GNDR6GNDR5GNDR49GNDR48
GND R30GND R25GND R20GND R2GND R12GND R1GND P8GND P7GND P47GND P46GND P43GND P42GND P4GND P39GND P32GND P3GND P27GND P17GND P11GND N6GND N5GND N49GND N48GND N45GND N44GND N38GND N29GND N24GND N2GND N19GND N12GND N1GND M9GND M8GND M7GND M47GND M46GND M43GND M42GND M41GND M40GND M4GND M39GND M36GND M31GND M3GND M26GND M21GND M11GND M10GND L9GND L6GND L5GND L49GND L48GND L45GND L44GND L41GND L38GND L28GND L23GND L2GND L18GND L13GND L1GND K9GND K8GND K7GND K47GND K46GND K43GND K42GND K41GND K4GND K35GND K30GND K3
GNDR45GNDR44GNDR38
GND K25GND J9GND J6
1SG280LU3F50E3VGS1
U43RGNDAP46GNDAP43GNDAP42GNDAP4GNDAP39GNDAP38GNDAP32GNDAP3GNDAP17GNDAP11GNDAN6GNDAN5GNDAN49GNDAN48GNDAN45GNDAN44GNDAN38GNDAN37GNDAN36GNDAN29GNDAN24GNDAN2GNDAN19GNDAN14GNDAN13GNDAN12GNDAN1GNDAM8GNDAM7GNDAM47GNDAM46GNDAM43GNDAM42GNDAM4GNDAM39GNDAM36GNDAM3GNDAM22GNDAM21GNDAM16GNDAM14GNDAM11GNDAL6GNDAL5GNDAL49GNDAL48GNDAL45GNDAL44GNDAL33GNDAL31GNDAL28GNDAL2GNDAL18GNDAL1GNDAK8GNDAK7GNDAK47GNDAK46GNDAK43GNDAK42GNDAK4GNDAK39GNDAK36GNDAK30GNDAK3GNDAK25GNDAK20GNDAK14GNDAK11GNDAJ6GNDAJ5GNDAJ49GNDAJ48GNDAJ45GNDAJ44GNDAJ32GNDAJ27GNDAJ22GNDAJ2GNDAJ17GNDAJ1GNDAH8GNDAH7GNDAH47GNDAH46GNDAH43GNDAH42
GND AH36GND AH35GND AH34GND AH3GND AH29GND AH24GND AH19GND AH14GND AH13GND AH11GND AG6GND AG5GND AG49GND AG48GND AG45GND AG44GND AG31GND AG26GND AG21GND AG2GND AG16GND AG1GND AF8GND AF7GND AF47GND AF46GND AF43GND AF42GND AF4GND AF39GND AG38GND AF33GND AF3GND AF28GND AF23GND AF18GND AG12GND AF11GND AE6GND AE5GND AE49GND AE48GND AE45GND AE44GND AE39GND AE38GND AE35GND AE30GND AE25GND AE20GND AE2GND AE15GND AE11GND AE1GND AD8GND AD7GND AD47GND AD46GND AD43GND AD42GND AD4GND AD39GND AC38GND AD37GND AD32GND AD3GND AD27GND AD22GND AD17GND AD13GND AC12GND AD11GND AC6GND AC5GND AC49GND AC48GND AC45GND AC44GND AC37GND AC34GND AC29GND AC24GND AC2GND AC19GND AC13GND AC1GND AB8GNDAH4
GNDAH39 GND AB7
GND AH37
1SG280LU3F50E3VGS1
U43PGNDJ5GNDJ49GNDJ48GNDJ45GNDJ44GNDJ41GNDJ37GNDJ27GNDJ22GNDJ2GNDJ12GNDJ1GNDH9GNDH8GNDH7GNDH47GNDH46GNDH43GNDH42GNDH41GNDH4GNDH39GNDH3GNDH29GNDH24GNDH14GNDG9GNDG6GNDG5GNDG49GNDG48GNDG45GNDG44GNDG41GNDG36GNDG31GNDG26GNDG2GNDG16GNDG11GNDG1GNDF9GNDF8GNDF7GNDF47GNDF46GNDF43GNDF42GNDF41GNDF4GNDF38GNDF33GNDF3GNDF28GNDF23GNDF18GNDF13GNDE9GNDE6GNDE5GNDE49GNDE48GNDE45GNDE44GNDE41GNDE35GNDE30GNDE25GNDE20GNDE2GNDE15GNDE1GNDD9GNDD8GNDD7GNDD47GNDD46GNDD43GNDD42GNDD41GNDD4GNDD37GNDD32GNDD3GNDD27GNDD22GNDD17
GND C5GND C49GND C48GND C45GND C44GND C41GND C40GND C39GND C34GND C29GND C24GND C2GND C19GND C14GND C11GND C10GND C1GND BJ9GND BJ6GND BJ47GND BJ44GND BJ41GND BJ40GND BJ39GND BJ37GND BJ32GND BJ3GND BJ27GND BJ22GND BJ17GND BJ12GND BJ11GND BJ10GND BH8GND BH7GND BH6GND BH5GND BH49GND BH48GND BH47GND BH46GND BH45GND BH44GND BH43GND BH42GND BH4GND BH39GND BH34GND BH3GND BH29GND BH24GND BH2GND BH19GND BH14GND BH11GND BG9GND BG6GND BG5GND BG49GND BG48GND BG45GND BG44GND BG41GND BG40GND BG39GND BG36GND BG31GND BG26GND BG21GND BG2GND BG16GND BG11GND BG10GND BG1GND BF9GND BF8GND BF7GND BF47GND BF46GND BF43GND BF42GND BF41GND BF4GND BF38GND BF33GND BF3GND BF28
GNDD12GNDC9GNDC6
GND BF23GND BF18GND BF13
1SG280LU3F50E3VGS1
U43SGNDAB47GNDAB46GNDAB43GNDAB42GNDAB4GNDAB39GNDAB37GNDAB31GNDAB3GNDAB26GNDAB21GNDAB16GNDAE13GNDAE12GNDAB11GNDAA6GNDAA5GNDAA49GNDAA48GNDAA45GNDAA44GNDAA38GNDAA37GNDAA36GNDAA33GNDAA28GNDAA23
GND AA2GND AA18GND AA14GND AA13GND AA12GND AA1GND A9GND A6GND A5GND A47GND A46GND A45GND A44GND A41GND A40GND A4GND A39GND A33GND A3GND A28GND A23GND A2GND A18GND A13GND A11GND A10GND BH1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR - POWER INPUT
12V Power Input Connector
ADD DNI RESITOR TOOUTPUT, IN CASE NEEDEDFOR MIN LOAD.
Inrush Current 2ARamp Time 12ms
OC Setting 33A, Ramp Time 4msOC response Time 9.3ms
Slew Rate Controller Circuitplace very close to Cap
place very close to Cap
3.3V_STBY ramp time = 1.2ms
connect GNDsthrough a single via
UV: 9.65V/10.1325VOV: 14.475V/13.75125V
2.1M 215K 84.5K for UV 4V
CAD Notes:Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
EN_12V
PWR8_PWRGD
12V_P12V_N
12V_GATE
START
LT3082_SET
12V_VSENSE
PWR8_VSENSE_GND
PWR9_VSENSE_GND
12VIN_VSENSE
12VIN_VSENSE
PWR9_VSENSE
12V_VSENSE
PWR8_VSENSE
12V12V_IN
12V_IN
12V_IN
12V_DCIN
12V_DCIN
12V_DCIN
12V 5V
12V 3.3V 3.3V_PRE
12V_DCIN
12V_IN 3.3V_STBY
GND_3V3STBY
GND_3V3STBYGND_3V3STBY
PWR8_VSENSE 10,12PWR8_VSENSE_GND 10,12
START 11,12
EN_12V 11
PWR8_PWRGD 10PWR9_VSENSE 10PWR9_VSENSE_GND 10
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B39 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B39 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B39 53Monday, March 13, 2017
V94RSNS1 SNS 2
V14RSNS1 SNS 2
R4095.49M
R416499K
R4100.003
C424330uF
C4251uF
R404 4.99K
C14514.7nF
R411 100K
C415
0.01uF
R11638.3K
J103
PCIe 2x3 ATX
12V0 112V1 212V2 3
GND04GND15GND26
R414200k
U48FDMC8010
5
123
4
6 7 8
C145010uF1210
C4182.2nF
R4412.49K
R11810.0K
R429150
D31
LED_WE1206
U47FDMC8010
5123
4
678
C411DNI
R41510.0K
C43447uF20V
R770DNI
C1489DNI
R40720
R745
10
R75910.0K
D29
LED_WE1206
C417 0.1uF
R406 DNI
R76038.3K
C426DNI
D32
LED_WE1206
C41647uF20V
V106RSNS1 SNS 2
C41247uF20V
C4190.1uF
U50ISL6115AISET 1
ISEN 2
GATE 3
VSS 4
PWRON8
PGOOD7
CTIM6
VDD5
C4272.2uF
C421330uF
C144947UF
R440DNI
U81
LT3082
OUT0 1OUT1 2
NC13
SET 4NC25NC36
IN07IN18
EPAD_VOUT 9
V107RSNS1 SNS 2
R7461.00K
C420150uF7343P
R412
100K
C414 0.1uF
R41330.1K
R769100K
R76813.3K
C423330uF
V93RSNS1 SNS 2
V110RSNS1 SNS 2
U49
LTC4365
VIN4 VOUT 6
GATE
5
UV3GND 1
OV2FAULT 7SHDN8
GND 9
R67010.0K
SW7
1 2 3
654R4050
R431150
U12
LTM4624
VOUT1 D1VIN1E5
INTVccE4
GND4 E3
VOUT4 E2VOUT3 E1
FREQA4
RUNA3
TRACK/SSA2
GND2 D3
VOUT0 C1
PGOOD C2
GND1 C3
MODEC4
SVinC5 VOUT2 D2
NC1A5SGND B4
COMP A1
FB B1
GND0 B3NC2B2NC3B5
GND3 D4
VIN0D5
C422150uF7343P
V16RSNS1 SNS 2
C4130.1uF
R833150
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR - 12V to 3.3V
3.325V/32A3.3V_PRE ramp time = 2.2ms
connect GNDsthrough a single viaCAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
3V3_VFB
3V3_COMP
3V3_TRACK
3V3_VFB
3V3_COMP
3V3_TRACK
3V3_VSENSE3V3_VSENSE_GND
3V3_DIFFOUT
3V3_VFB
3V3_PWRGD
3V3_PWRGD
EN_3V3
EN_3V3
3.3V_PRE
3.3V_PRE
12V
GND_3V3
GND_3V3
GND_3V3
GND_3V3
GND_3V3
GND_3V3
GND_3V3
3V3_VSENSE12,52 3V3_VSENSE_GND12,52EN_3V311
3V3_PWRGD10
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B40 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B40 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B40 53Monday, March 13, 2017
C752100uF1206
C76347pF
C755100uF1206
U82LTM4630AEV#PBF
VOUT
1_0A1
VOUT
1_1A2
VOUT
1_2A3
VOUT
1_3A4
VOUT
1_4A5
VOUT
1_5B1
VOUT
1_6B2
VOUT
1_7B3
VOUT
1_8B4
VOUT
1_9B5
VOUT
1_10
C1VO
UT1_1
1C2
VOUT
1_12
C3VO
UT1_1
3C4
VFB1 D5
SW1 G2
PGOOD1 G9
COMP1 E6
RUN1 F5
TRACK1 E5
VOUTS1 C5
VOUT2_0 A8VOUT2_1 A9VOUT2_2 A10VOUT2_3 A11VOUT2_4 A12VOUT2_5 B8VOUT2_6 B9VOUT2_7 B10VOUT2_8 B11VOUT2_9 B12
VOUT2_10 C9VOUT2_11 C10VOUT2_12 C11VOUT2_13 C12
VFB2 D7
SW2 G11
PGOOD2 G8
COMP2 E7
RUN2 F9
TRACK2 D8VOUTS2 C8
VIN10M2VIN11M3VIN12M4VIN13M5VIN14M6VIN15M7VIN16M8VIN17M9VIN18M10VIN19M11
VIN0L2VIN1L3VIN2L4VIN3L5VIN4L6VIN5L7VIN6L8VIN7L9VIN8L10VIN9L11
VIN25
K2VIN
24K3
VIN23
K4VIN
22K9
VIN21
K10
VIN20
K11
VIN31
J2VIN
30J3
VIN29
J4VIN
28J9
VIN27
J10VIN
26J11
GND0A6GND1A7GND2B6GND3B7GND4D1GND5D2GND6D3GND7D4GND8D9GND9D10GND10D11GND11D12GND12E1
GND1
3E2
GND1
4E3
GND1
5E4
GND1
6E1
0GN
D17
E11
GND1
8E1
2GN
D19
F1GN
D20
F2GN
D21
F3GN
D22
F10
GND2
3F1
1GN
D24
F12
GND2
5G1
GND2
6G3
GND2
7G1
0GN
D28
G12
GND2
9H1
GND3
0H2
GND3
1H3
GND3
2H4
GND3
3H5
GND3
4H6
GND3
5H7
GND3
6H9
GND3
7H1
0GN
D38
H11
GND3
9H1
2
GND5
3M1
2GN
D52
M1GN
D51
L12
GND4
0J1
GND4
1J5
GND4
2J8
GND4
3J12
GND4
4K1
GND4
5K5
GND4
6K6
GND4
7K7
GND4
8K8
GND4
9K1
2GN
D50
L1
SGND
0C7
SGND
1D6
SGND
2F6
SGND
3F7
SGND
4G6
SGND
5G7
FSETC6
PHASMDG4
DIFFP E8DIFFN E9
CLKO
UTG5
MODE
-PLLIN
F4
TEMP
J6
INTVCCH8
EXTVCCJ7
DIFFOUT F8
V99
C753100uF1206
C75610uF1210
V100
C764470uFtc7343
C7664.7nF
C75710uF1210
C765470uFtc7343
C762DNI
C75810uF1210
C7604.7uF
C75910uF1210
R672
121K 1%
V109RSNS1 SNS 2
R67413.3K
C768100pF
R673 140K
C754100uF1206
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
connect GNDsthrough a single via
PWR 12V to VCCT/1.8V/2.4V
VCCT_GXB
1.804V/8A
Fsw = 650KHzTss=(Css/1.3uA)*0.6=4.6ms
connect GNDsthrough a single via
1.119V/9A
2.4V
CAD Notes:
CAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
PWR7_PWRGDPWR5_PWRGD
S10_1p8V_FB
VCCT_FBVCCT_DACOUT
PWR5_VSENSEPWR5_VSENSE_GND
EN_VCCT_GXB
1V8_DACOUT
VCCT_GXB_SENSE_N
VCCT_GXB_SENSE_P
EN_1V8GND_4620
GND_4620 GND_4620 GND_4620
GND_4620
12V
12V
GND_4620
S10_VCCT
1.8V_PRE
3.3V
GND_2V4
2.4V
GND_2V4
S10_VCCT_GXB_SENSE
S10_VCCT_GXB_SENSE
S10_VCCT
1V8_DACOUT 12,13
PWR7_PWRGD 10
EN_VCCT_GXB 11,52VCCT_GXB_SENSE_N 12,13VCCT_GXB_SENSE_P 12,13
VCCT_DACOUT 12,13
PWR5_PWRGD 10PWR5_VSENSE_GND 10,12,52PWR5_VSENSE 10,12,52
EN_1V8 11
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B41 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B41 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B41 53Monday, March 13, 2017
C45010uF
R683DNI
U62B
LTM4620AEY#PBF
VIN1M2VIN2M3VIN3M4VIN4M5VIN5M6VIN6M7VIN7M8VIN8M9VIN9M10VIN10M11VIN11L2VIN12L3
VOUT1_1 A1VOUT1_2 A2VOUT1_3 A3VOUT1_4 A4VOUT1_5 A5VOUT1_6 B1VOUT1_7 B2VOUT1_8 B3VOUT1_9 B4
VOUT1_10 B5VOUT1_11 C1VOUT1_12 C2VOUT1_13 C3VOUT1_14 C4VIN13L4
VIN14L5VIN15L6VIN16L7VIN17L8VIN18L9VIN19L10VIN20L11VIN21J2VIN22J3VIN23J4VIN24J9VIN25J10VIN26J11VIN27K2VIN28K3VIN29K4VIN30K9VIN31K10VIN32K11
VOUT2_1 A8VOUT2_2 A9VOUT2_3 A10VOUT2_4 A11VOUT2_5 A12VOUT2_6 B8VOUT2_7 B9VOUT2_8 B10VOUT2_9 B11
VOUT2_10 B12VOUT2_11 C9VOUT2_12 C10VOUT2_13 C11VOUT2_14 C12
R461 200k
C461 47pF
V67RSNS 1SNS2
R66666.5K
C7502.2uF
C462100uF
U62A
LTM4620AEY#PBF
COMP1 E6
DIFFP E8
PGOOD1 G9
TEMPJ6
MODE-PLLINF4
RUN1F5
VFB2 D7RUN2F9
CLKOUT G5
FSETC6
SW1 G2
SW2 G11VFB1 D5
PGOOD2 G8
PHASMDG4
TRACK1E5TRACK2D8
DIFFOUT F8
DIFFN E9COMP2 E7
INTVCCH8EXTVCCJ7
VOUTS1C5VOUTS2C8
V88RSNS1 SNS 2
R665200k
C455100uF
C44822uF
C463100uF
C454100uF
C74910uF
V24RSNS1 SNS 2
C4534.7uF
C4570.01uF R464150K
R556 69.8K
C464100uF
C44922uF
C459 47pFC458100uF
U80
EP5348UI
NC(SW
)01
NC(SW
)113
NC(SW
)214
NC0
3
PGND 2
VFB 4
AGND 5
VOUT0 6VOUT1 7
NC1
8NC
29
ENABLE10
AVIN11PVIN12
R547
0.001
R554 316K
C451100uF
R459 30.1K
C44522uF
C4560.01uF
U62C
LTM4620AEY#PBF
GND1A6GND2A7GND3B6GND4B7GND5D1GND6D2GND7D3GND8D4GND9D9GND10D10GND11D11GND12D12GND13E1GND14E2GND15E3GND16E4GND17E10GND18E11GND19E12GND20F1GND21F2GND22F3GND23F10
SGND1C7SGND2D6SGND3G6SGND4G7SGND5F6SGND6F7
GND24 F11GND25 F12GND26 G1GND27 G3GND28 G10GND29 G12GND30 H1GND31 H2GND32 H3GND33 H4GND34 H5GND35 H6GND36 H7GND37 H9GND38 H10GND39 H11GND40 H12GND41 J1GND42 J5GND43 J8GND44 J12GND45 K1GND46 K5GND47 K6GND48 K7GND49 K8GND50 K12GND51 L1GND52 L12GND53 M1GND54 M12
R68410.0K
J91
WE_PWR_Terminal_5.08mm
1 1
2 2
C44710uF
C7515pF
C452100uF
C7470.1uF
R460100K
C444100pF
C7482.2uF
C44622uF
V66RSNS 1SNS2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ASEL = OPEN, I2C address = b'100 1111'ASEL = LOW, I2C address depends on pull down value.
PWR - VCC LTM46770.85V/131A
Reprogram to 0.9V output (A10 interposer)
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
LTM4677_ASEL
LTM4677_COMP
VCC_SENSE
LTM4677_GPIO1
LTM4677_COMP
VSS_SENSE
VCC_SENSEPWR1_VSENSE
PWR1_VSENSE_GND
LTM4677_FSWPHCFG
LTM4677_VOUT0CFGLTM4677_VTRIM0CFG
LTM4677_VOUT1CFGLTM4677_VTRIM1CFG
EN_VCC
LTM4677_SYNCLTM4677_SHARE_CLKVCC_ALERTnLT_SCLLT_SDALTM4677_GPIO0LTM4677_GPIO1LTM4677_WP LTM4677_GPIO0
PM_ALERTB
VCC_ALERTn
GND_VCC GND_VCC
GND_VCC
GND_VCC
12V S10_VCC
GND_VCC
S10_VCC
LTM4677_VDD33
LTM4677_INTVCC
1.8V
GND_VCC
GND_VCC
LTM4677_SYNC43LTM4677_COMP43
VCC_ALERTn28EN_VCC11,52
LT_SDA12,18LT_SCL12,18
LTM4677_GPIO043
PWR1_VSENSE10,12,52PWR1_VSENSE_GND10,12,52
VCC_SENSE37VSS_SENSE37
LTM4677_GPIO111
PM_ALERTB12
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B42 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B42 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B42 53Monday, March 13, 2017
C47110uF1210
C475100uF1206
C47210uF1210
C487100uF1206
R484 18.0K
R6280
R486 3.24K
C465DNI
R479 10.0K
C1480470uFtc7343
V85
R483 DNI
C47310uF1210
C486100uF1206
C466DNI
C474100uF1206
V31V29
C485100uF1206
R465DNI
C482DNI
R481 0
C4810.01uF
R467DNI
R478 10.0KR477DNI
R482 DNI
R489 DNI
R469 1K
R4744.02K
C1475470uFtc7343
C483470uFtc7343
V25
C674DNI
V28
R470 10.0K
C488100uF1206
V32
V27
R480 DNI
C1473150uF7343P
U63LTM4677EY#PBF
VOUT0_0A1VOUT0_1A2VOUT0_2A3
VOUT0_9D1
ISNS0b-E1
ISNS0b+F1
ISNS1
b-G1
ISNS1
b+H1
VOUT
1_0J1
VOUT
1_1J2
VOUT
1_2J3
VOUT
1_3K1
VOUT0_3B1VOUT0_4B2VOUT0_5B3
VOUT0_10D2
ISNS0a-E2
ISNS0a+F2
ISNS1
a-G2
ISNS1
a+H2
VOUT
1_4K2
VOUT
1_5K3
VOUT
1_6L1
VOUT
1_7L2
VOUT0_6C1VOUT0_7C2VOUT0_8C3
VOUT0_11D3
GND0
A4GN
D1A6
GND2
A7GN
D3A8
VOUT
1_8L3
VOUT
1_9M1
VOUT
1_10
M2VO
UT1_1
1M3
GND4
A9GN
D5A1
0GN
D6B4
GND7
B5
ASEL G4
FSWPHCFG H4
GND8
B6GN
D9B7
GND1
0B8
GND1
1B9
GPIO0 E4
GPIO1 F4
SNUB0A5
GND1
2C4
TSNS0bC5TSNS0aD5
ALERT E5
RUN0 F5
VOUT0CFG G5
VTRIM0CFG H5
TSNS
1aJ5
TSNS
1bK5
GND1
3C6
SNUB
1M5
GND1
4C7
GND1
5C8
GND1
6C9
SDA D6SCL E6
RUN1 F6
VOUT1CFG G6
VTRIM1CFG H6
VDD25 J6
WP K6GN
D17
D4
GND1
9E3
GND2
0F3
GND2
1F1
0GN
D22
G3GN
D23
G10
SYNC E7
GND4
4M9
GND4
5M1
0
SHARE_CLK H7
VDD33 J7
GND2
4G1
1GN
D25
G12
GND3
8L8
GND3
7L7
GND3
9L9
GND2
6H3
COMP0bD8COMP0aE8
SGND
2F7
SGND
3F8
COMP
1aH8
COMP
1bJ8
GND2
7H1
0GN
D28
J4
GND4
3M8
VOSNS0+D9
VOSNS0-E9
INTVCC0 F9INTVCC1 G9
VOSN
S1H9
VORB
1J9
GND2
9J10
GND3
4L4
GND3
5L5
GND3
0K4
SW0B10
DNC2
E11
VORB0+D10
VORB0-E10
GND3
6L6
GND3
1K7
GND3
2K8
GND3
3K9
DNC1
C10
SW1
L10
GND4
0M4
VIN0_3B12 VIN0_2B11 VIN_1A12 VIN0_0A11
DNC4
K10
SVIN_1F12
GND4
1M6
DNC3
H11
VIN1_0
H12
VIN1_1
J11VIN
1_2J12
VIN1_3
K11
VIN0_8E12 VIN0_7D12 VIN0_6D11 VIN0_5C12 VIN0_4C11
SVIN_0F11
GND4
2M7
VIN1_4
K12
VIN1_5
L11VIN
1_6L12
VIN1_7
M11
VIN1_8
M12
SGND
0G7
SGND
1G8
GND1
8D7
R466 DNI
C1474470uFtc7343
V30
R487 1.65K
R471 10.0K
C467150uF7343P
R472 DNI
R468 DNI
C480DNI
R488 3.24K
C477100uF1206
C46910uF1210
R473 DNI
V26
R485 1.65K
C476100uF1206
C46810uF1210
R490 0
R475 DNI
R820DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR - VCC LTM4650 1
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
LTM4650_1_FSET
LTM4677_SYNC
LTM4677_CLKOUT
LTM4677_CLKOUTLTM4650_1_SYNC
LTM4650_VFB
LTM4650_COMP
LTM4677_COMP
LTM4677_GPIO0
LTM4650_COMP
LTM4650_RUNLTM4650_TRACK
LTM4650_VFB
LTM4650_COMPLTM4650_RUN
LTM4650_TRACK
LTM4677_GPIO0
LTM4650_1_INTVCC
GND_VCC
LTM4650_EXTVCC
GND_VCC
GND_VCC
LTM4650_1_INTVCC5V
GND_VCC
S10_VCC
LTM4650_1_INTVCC
GND_VCC
GND_VCC
GND_VCCGND_VCC
LTM4677_INTVCC
GND_VCC
5V LTM4650_EXTVCC
GND_VCCGND_VCC
12V
S10_VCC
LTM4650_1_INTVCCGND_VCC
12V
GND_VCC
LTM4677_SYNC42
LTM4650_1_SYNC44LTM4650_VFB44,45
LTM4650_RUN44,45LTM4650_TRACK44,45
LTM4677_COMP42
LTM4650_COMP44,45
LTM4677_GPIO042
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B43 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B43 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B43 53Monday, March 13, 2017
R4910
R51210.0K
V36
R507 0
C495470uFtc7343
R503 DNI
R492
121K 1%
R5082K
U64LTM4650EY
VOUT
1_0A1
VOUT
1_1A2
VOUT
1_2A3
VOUT
1_3A4
VOUT
1_4A5
VOUT
1_5B1
VOUT
1_6B2
VOUT
1_7B3
VOUT
1_8B4
VOUT
1_9B5
VOUT
1_10
C1VO
UT1_1
1C2
VOUT
1_12
C3VO
UT1_1
3C4
VFB1 D5
SW1 G2
PGOOD1 G9
COMP1 E6
RUN1 F5
TRACK1 E5
VOUTS1 C5
VOUT2_0 A8VOUT2_1 A9VOUT2_2 A10VOUT2_3 A11VOUT2_4 A12VOUT2_5 B8VOUT2_6 B9VOUT2_7 B10VOUT2_8 B11VOUT2_9 B12
VOUT2_10 C9VOUT2_11 C10VOUT2_12 C11VOUT2_13 C12
VFB2 D7
SW2 G11
PGOOD2 G8
COMP2 E7
RUN2 F9
TRACK2 D8VOUTS2 C8
VIN10M2VIN11M3VIN12M4VIN13M5VIN14M6VIN15M7VIN16M8VIN17M9VIN18M10VIN19M11
VIN0L2VIN1L3VIN2L4VIN3L5VIN4L6VIN5L7VIN6L8VIN7L9VIN8L10VIN9L11
VIN25
K2VIN
24K3
VIN23
K4VIN
22K9
VIN21
K10
VIN20
K11
VIN31
J2VIN
30J3
VIN29
J4VIN
28J9
VIN27
J10VIN
26J11
GND0A6GND1A7GND2B6GND3B7GND4D1GND5D2GND6D3GND7D4GND8D9GND9D10GND10D11GND11D12GND12E1
GND1
3E2
GND1
4E3
GND1
5E4
GND1
6E1
0GN
D17
E11
GND1
8E1
2GN
D19
F1GN
D20
F2GN
D21
F3GN
D22
F10
GND2
3F1
1GN
D24
F12
GND2
5G1
GND2
6G3
GND2
7G1
0GN
D28
G12
GND2
9H1
GND3
0H2
GND3
1H3
GND3
2H4
GND3
3H5
GND3
4H6
GND3
5H7
GND3
6H9
GND3
7H1
0GN
D38
H11
GND3
9H1
2
GND5
3M1
2GN
D52
M1GN
D51
L12
GND4
0J1
GND4
1J5
GND4
2J8
GND4
3J12
GND4
4K1
GND4
5K5
GND4
6K6
GND4
7K7
GND4
8K8
GND4
9K1
2GN
D50
L1
SGND
0C7
SGND
1D6
SGND
2F6
SGND
3F7
SGND
4G6
SGND
5G7
FSETC6
PHASMDG4
DIFFP E8DIFFN E9
CLKO
UTG5
MODE
-PLLIN
F4
TEMP
J6
INTVCCH8
EXTVCCJ7
DIFFOUT F8
R494100K
Q2
NDS7002A
R4958.25K1%
V35
C1479470uFtc7343
U65
LT1801CMS8#PBF
OUTA1
-IN A2
+IN A3
V-4 +IN B 5-IN B 6
OUT B 7V+ 8
R4970
V33
C4972.2uF
R498DNI
R49360.4K1%
C47010uF1210
R5110
C500100uF1206
C1478470uFtc7343
C1476150uF7343P
C48910uF1210
R509 0
R5000
R629DNI
R502200
R499 80.6K
C49010uF1210
C499100uF1206
C1477470uFtc7343
C501470uFtc7343
C49110uF1210
R5060
R49620.0K
C498 1uF
R501DNI
C494100uF1206
R505 0
C677DNI
V34
R504DNI
C49210uF1210
R510DNI
C493100uF1206
C496DNI
C502DNI
C484470uFtc7343
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR - VCC LTM4650 2
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
LTM4650_1_SYNCLTM4650_2_SYNC
LTM4650_VFB
LTM4650_COMPLTM4650_RUNLTM4650_TRACK
LTM4650_VFB
LTM4650_COMPLTM4650_RUN
LTM4650_TRACK
LTM4650_2_FSET
GND_VCC
S10_VCC
S10_VCC
LTM4650_2_INTVCCGND_VCC
12V
LTM4650_2_INTVCC
GND_VCC
LTM4650_EXTVCC
GND_VCC
GND_VCC
GND_VCC
LTM4650_1_SYNC43LTM4650_2_SYNC45LTM4650_VFB43,45LTM4650_COMP43,45LTM4650_RUN43,45LTM4650_TRACK43,45
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B44 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B44 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B44 53Monday, March 13, 2017
C509470uFtc7343
V37
C5102.2uF
C1482470uFtc7343V40
C50310uF1210
C1483470uFtc7343
R516 80.6K
C478470uFtc7343
C676DNI
C50510uF1210
C511 1uF
V39
C50610uF1210
U66LTM4650EY
VOUT
1_0A1
VOUT
1_1A2
VOUT
1_2A3
VOUT
1_3A4
VOUT
1_4A5
VOUT
1_5B1
VOUT
1_6B2
VOUT
1_7B3
VOUT
1_8B4
VOUT
1_9B5
VOUT
1_10
C1VO
UT1_1
1C2
VOUT
1_12
C3VO
UT1_1
3C4
VFB1 D5
SW1 G2
PGOOD1 G9
COMP1 E6
RUN1 F5
TRACK1 E5
VOUTS1 C5
VOUT2_0 A8VOUT2_1 A9VOUT2_2 A10VOUT2_3 A11VOUT2_4 A12VOUT2_5 B8VOUT2_6 B9VOUT2_7 B10VOUT2_8 B11VOUT2_9 B12
VOUT2_10 C9VOUT2_11 C10VOUT2_12 C11VOUT2_13 C12
VFB2 D7
SW2 G11
PGOOD2 G8
COMP2 E7
RUN2 F9
TRACK2 D8VOUTS2 C8
VIN10M2VIN11M3VIN12M4VIN13M5VIN14M6VIN15M7VIN16M8VIN17M9VIN18M10VIN19M11
VIN0L2VIN1L3VIN2L4VIN3L5VIN4L6VIN5L7VIN6L8VIN7L9VIN8L10VIN9L11
VIN25
K2VIN
24K3
VIN23
K4VIN
22K9
VIN21
K10
VIN20
K11
VIN31
J2VIN
30J3
VIN29
J4VIN
28J9
VIN27
J10VIN
26J11
GND0A6GND1A7GND2B6GND3B7GND4D1GND5D2GND6D3GND7D4GND8D9GND9D10GND10D11GND11D12GND12E1
GND1
3E2
GND1
4E3
GND1
5E4
GND1
6E1
0GN
D17
E11
GND1
8E1
2GN
D19
F1GN
D20
F2GN
D21
F3GN
D22
F10
GND2
3F1
1GN
D24
F12
GND2
5G1
GND2
6G3
GND2
7G1
0GN
D28
G12
GND2
9H1
GND3
0H2
GND3
1H3
GND3
2H4
GND3
3H5
GND3
4H6
GND3
5H7
GND3
6H9
GND3
7H1
0GN
D38
H11
GND3
9H1
2
GND5
3M1
2GN
D52
M1GN
D51
L12
GND4
0J1
GND4
1J5
GND4
2J8
GND4
3J12
GND4
4K1
GND4
5K5
GND4
6K6
GND4
7K7
GND4
8K8
GND4
9K1
2GN
D50
L1
SGND
0C7
SGND
1D6
SGND
2F6
SGND
3F7
SGND
4G6
SGND
5G7
FSETC6
PHASMDG4
DIFFP E8DIFFN E9
CLKO
UTG5
MODE
-PLLIN
F4
TEMP
J6
INTVCCH8
EXTVCCJ7
DIFFOUT F8
C513100uF1206
C50410uF1210
C508100uF1206
C1484150uF7343P
C512100uF1206
R515DNI
C507100uF1206
C514470uFtc7343
V38
R5130
R5170
R514
121K 1%
C675DNI
C1481470uFtc7343
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR - VCC LTM4650 3
TON_RISE 4ms
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
LTM4650_2_SYNCLTM4650_3_SYNC
LTM4650_VFB
LTM4650_COMPLTM4650_RUNLTM4650_TRACK
LTM4650_VFB
LTM4650_COMPLTM4650_RUN
LTM4650_TRACK
LTM4650_3_FSET
12V S10_VCC
S10_VCC
LTM4650_3_INTVCCGND_VCC
LTM4650_3_INTVCC
GND_VCC
LTM4650_EXTVCC
GND_VCC
GND_VCC
GND_VCC
GND_VCC
S10_VCC
LTM4650_2_SYNC44
LTM4650_VFB43,44LTM4650_COMP43,44LTM4650_RUN43,44LTM4650_TRACK43,44
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B45 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B45 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B45 53Monday, March 13, 2017
C51510uF1210
C1486470uFtc7343
C519100uF1206
C1488470uFtc7343
C525100uF1206
C653330uF
V41
C51710uF1210
R519
121K 1% C1487470uFtc7343
C51610uF1210
C524100uF1206
C5222.2uF
C654220uF
V43
C51810uF1210
R521 80.6K
C523 1uF
C679DNI
C655220uF
C479470uFtc7343
C521470uFtc7343
J94
DNI
C526470uFtc7343
V42
C651330uF
U67LTM4650EY
VOUT
1_0A1
VOUT
1_1A2
VOUT
1_2A3
VOUT
1_3A4
VOUT
1_4A5
VOUT
1_5B1
VOUT
1_6B2
VOUT
1_7B3
VOUT
1_8B4
VOUT
1_9B5
VOUT
1_10
C1VO
UT1_1
1C2
VOUT
1_12
C3VO
UT1_1
3C4
VFB1 D5
SW1 G2
PGOOD1 G9
COMP1 E6
RUN1 F5
TRACK1 E5
VOUTS1 C5
VOUT2_0 A8VOUT2_1 A9VOUT2_2 A10VOUT2_3 A11VOUT2_4 A12VOUT2_5 B8VOUT2_6 B9VOUT2_7 B10VOUT2_8 B11VOUT2_9 B12
VOUT2_10 C9VOUT2_11 C10VOUT2_12 C11VOUT2_13 C12
VFB2 D7
SW2 G11
PGOOD2 G8
COMP2 E7
RUN2 F9
TRACK2 D8VOUTS2 C8
VIN10M2VIN11M3VIN12M4VIN13M5VIN14M6VIN15M7VIN16M8VIN17M9VIN18M10VIN19M11
VIN0L2VIN1L3VIN2L4VIN3L5VIN4L6VIN5L7VIN6L8VIN7L9VIN8L10VIN9L11
VIN25
K2VIN
24K3
VIN23
K4VIN
22K9
VIN21
K10
VIN20
K11
VIN31
J2VIN
30J3
VIN29
J4VIN
28J9
VIN27
J10VIN
26J11
GND0A6GND1A7GND2B6GND3B7GND4D1GND5D2GND6D3GND7D4GND8D9GND9D10GND10D11GND11D12GND12E1
GND1
3E2
GND1
4E3
GND1
5E4
GND1
6E1
0GN
D17
E11
GND1
8E1
2GN
D19
F1GN
D20
F2GN
D21
F3GN
D22
F10
GND2
3F1
1GN
D24
F12
GND2
5G1
GND2
6G3
GND2
7G1
0GN
D28
G12
GND2
9H1
GND3
0H2
GND3
1H3
GND3
2H4
GND3
3H5
GND3
4H6
GND3
5H7
GND3
6H9
GND3
7H1
0GN
D38
H11
GND3
9H1
2
GND5
3M1
2GN
D52
M1GN
D51
L12
GND4
0J1
GND4
1J5
GND4
2J8
GND4
3J12
GND4
4K1
GND4
5K5
GND4
6K6
GND4
7K7
GND4
8K8
GND4
9K1
2GN
D50
L1
SGND
0C7
SGND
1D6
SGND
2F6
SGND
3F7
SGND
4G6
SGND
5G7
FSETC6
PHASMDG4
DIFFP E8DIFFN E9
CLKO
UTG5
MODE
-PLLIN
F4
TEMP
J6
INTVCCH8
EXTVCCJ7
DIFFOUT F8
R520DNI
J92
DNI
V45
C65610uF
R522DNI
R5180
C1485150uF7343P
C678DNI
C652330uF
V44
C520100uF1206
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
connect GNDsthrough a single via
PWR - VCCERAM, VCCH, VCCPT0.907V/18A
VCCH_GXBVCCA_PLL
connect GNDsthrough a single via
VCCERAM
1.804V/17A
Fsw = 650KHzTss=(Css/1.3uA)*0.6=4.6ms
Fsw = 650KHzTss=(Css/1.3uA)*0.6=4.6ms
CAD Notes:
CAD Notes:
Margin to 0.95V output (A10 interposer)
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
VCCERAM_SENSE_N
VCCERAM_SENSE_P
EN_VCCERAM
PWR2_PWRGD
PWR2_VSENSE_GNDPWR2_VSENSE
VCCERAM_DACOUT
EN_VCCH_GXB
PWR6_PWRGD
PWR6_VSENSE_GNDPWR6_VSENSE
VCCH_DACOUT
VCCH_GXB_SENSE_P
VCCH_GXB_SENSE_N
S10_VCCERAM_SENSE
S10_VCCERAM
S10_VCCERAM
GND_VCCERAM
12V12V
12V12V
GND_VCCH
S10_VCCH
GND_VCCH
GND_VCCHGND_VCCH
GND_VCCH
GND_VCCHS10_VCCH_GXB_SENSE
S10_VCCH
GND_VCCERAM
GND_VCCERAM
GND_VCCERAM
GND_VCCERAM
GND_VCCERAM
S10_VCCERAM_SENSE
S10_VCCH_GXB_SENSE
VCCERAM_SENSE_N 12,13VCCERAM_SENSE_P 12,13EN_VCCERAM 11,52VCCERAM_DACOUT 12,13
PWR2_PWRGD 10
VCCH_GXB_SENSE_N 12,13VCCH_GXB_SENSE_P 12,13
EN_VCCH_GXB 11,48,52VCCH_DACOUT 12,13
PWR6_PWRGD 10
PWR6_VSENSE_GND10,12,52 PWR6_VSENSE10,12,52
PWR2_VSENSE 10,12,52PWR2_VSENSE_GND 10,12,52
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B46 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B46 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B46 53Monday, March 13, 2017
R5270.001
C555100pF
J83
WE_PWR_Terminal_5.08mm
1 1
2 2
C545100uF
R533200k
V52RSNS 1SNS2
C537100uF
C56010uF
U68B
LTM4620AEY#PBF
VIN1M2VIN2M3VIN3M4VIN4M5VIN5M6VIN6M7VIN7M8VIN8M9VIN9M10VIN10M11VIN11L2VIN12L3
VOUT1_1 A1VOUT1_2 A2VOUT1_3 A3VOUT1_4 A4VOUT1_5 A5VOUT1_6 B1VOUT1_7 B2VOUT1_8 B3VOUT1_9 B4
VOUT1_10 B5VOUT1_11 C1VOUT1_12 C2VOUT1_13 C3VOUT1_14 C4VIN13L4
VIN14L5VIN15L6VIN16L7VIN17L8VIN18L9VIN19L10VIN20L11VIN21J2VIN22J3VIN23J4VIN24J9VIN25J10VIN26J11VIN27K2VIN28K3VIN29K4VIN30K9VIN31K10VIN32K11
VOUT2_1 A8VOUT2_2 A9VOUT2_3 A10VOUT2_4 A11VOUT2_5 A12VOUT2_6 B8VOUT2_7 B9VOUT2_8 B10VOUT2_9 B11
VOUT2_10 B12VOUT2_11 C9VOUT2_12 C10VOUT2_13 C11VOUT2_14 C12
U69A
LTM4620AEY#PBF
COMP1 E6
DIFFP E8
PGOOD1 G9
TEMPJ6
MODE-PLLINF4
RUN1F5
VFB2 D7RUN2F9
CLKOUT G5
FSETC6
SW1 G2
SW2 G11VFB1 D5
PGOOD2 G8
PHASMDG4
TRACK1E5TRACK2D8
DIFFOUT F8
DIFFN E9COMP2 E7
INTVCCH8EXTVCCJ7
VOUTS1C5VOUTS2C8
C547100uF
C53822uF
C55022uF
C5420.01uF
C561DNI
R530100K
C564100uF
V55RSNS 1SNS2
V46RSNS 1SNS2
C539100uF
R5310.001C55322uF
U68C
LTM4620AEY#PBF
GND1A6GND2A7GND3B6GND4B7GND5D1GND6D2GND7D3GND8D4GND9D9GND10D10GND11D11GND12D12GND13E1GND14E2GND15E3GND16E4GND17E10GND18E11GND19E12GND20F1GND21F2GND22F3GND23F10
SGND1C7SGND2D6SGND3G6SGND4G7SGND5F6SGND6F7
GND24 F11GND25 F12GND26 G1GND27 G3GND28 G10GND29 G12GND30 H1GND31 H2GND32 H3GND33 H4GND34 H5GND35 H6GND36 H7GND37 H9GND38 H10GND39 H11GND40 H12GND41 J1GND42 J5GND43 J8GND44 J12GND45 K1GND46 K5GND47 K6GND48 K7GND49 K8GND50 K12GND51 L1GND52 L12GND53 M1GND54 M12
C53110uF
C558100uF
R534100K
C536100pF
U69B
LTM4620AEY#PBF
VIN1M2VIN2M3VIN3M4VIN4M5VIN5M6VIN6M7VIN7M8VIN8M9VIN9M10VIN10M11VIN11L2VIN12L3
VOUT1_1 A1VOUT1_2 A2VOUT1_3 A3VOUT1_4 A4VOUT1_5 A5VOUT1_6 B1VOUT1_7 B2VOUT1_8 B3VOUT1_9 B4
VOUT1_10 B5VOUT1_11 C1VOUT1_12 C2VOUT1_13 C3VOUT1_14 C4VIN13L4
VIN14L5VIN15L6VIN16L7VIN17L8VIN18L9VIN19L10VIN20L11VIN21J2VIN22J3VIN23J4VIN24J9VIN25J10VIN26J11VIN27K2VIN28K3VIN29K4VIN30K9VIN31K10VIN32K11
VOUT2_1 A8VOUT2_2 A9VOUT2_3 A10VOUT2_4 A11VOUT2_5 A12VOUT2_6 B8VOUT2_7 B9VOUT2_8 B10VOUT2_9 B11
VOUT2_10 B12VOUT2_11 C9VOUT2_12 C10VOUT2_13 C11VOUT2_14 C12
C54347pF
C52822uF
C557100uF
C56247pF
V47RSNS 1SNS2
C55410uF
C52922uF
C556100uF
R528150K
C5524.7uF
U68A
LTM4620AEY#PBF
COMP1 E6
DIFFP E8
PGOOD1 G9
TEMPJ6
MODE-PLLINF4
RUN1F5
VFB2 D7RUN2F9
CLKOUT G5
FSETC6
SW1 G2
SW2 G11VFB1 D5
PGOOD2 G8
PHASMDG4
TRACK1E5TRACK2D8
DIFFOUT F8
DIFFN E9COMP2 E7
INTVCCH8EXTVCCJ7
VOUTS1C5VOUTS2C8
R526100K
C566100uF
C544100uF
C54822uF
U69C
LTM4620AEY#PBF
GND1A6GND2A7GND3B6GND4B7GND5D1GND6D2GND7D3GND8D4GND9D9GND10D10GND11D11GND12D12GND13E1GND14E2GND15E3GND16E4GND17E10GND18E11GND19E12GND20F1GND21F2GND22F3GND23F10
SGND1C7SGND2D6SGND3G6SGND4G7SGND5F6SGND6F7
GND24 F11GND25 F12GND26 G1GND27 G3GND28 G10GND29 G12GND30 H1GND31 H2GND32 H3GND33 H4GND34 H5GND35 H6GND36 H7GND37 H9GND38 H10GND39 H11GND40 H12GND41 J1GND42 J5GND43 J8GND44 J12GND45 K1GND46 K5GND47 K6GND48 K7GND49 K8GND50 K12GND51 L1GND52 L12GND53 M1GND54 M12
J79
WE_PWR_Terminal_5.08mm
1 1
2 2
V48RSNS1 SNS 2
C53010uF
C5630.01uF
R524118K1%
C535DNI
C565100uF
C532100uF
C567100uF
R53230.1K
C54922uF
C533100uF
C52722uF
C551100uF
C5344.7uF
R525
392K
V51RSNS 1SNS2
C546100uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR - VCCR_GXB
connect GNDsthrough a single via
connect GNDsthrough a single via
1.119V/19AVCCRL_GXB
VCCRR_GXB
1.119V/19A
Fsw = 650KHzTss=(Css/1.3uA)*0.6=4.6ms
Fsw = 650KHzTss=(Css/1.3uA)*0.6=4.6ms
CAD Notes:
CAD Notes: Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
VCCRL_GXB_SENSE_N
VCCRR_GXB_SENSE_N
VCCRR_GXB_SENSE_P
VCCRL_GXB_SENSE_P
EN_VCCRL_GXB
PWR3_PWRGD
PWR3_VSENSE_GNDPWR3_VSENSE
VCCRL_DACOUT
EN_VCCRR_GXB
PWR4_PWRGD
PWR4_VSENSE_GNDPWR4_VSENSE
VCCRR_DACOUT
S10_VCCRR
S10_VCCRR_GXB_SENSE
S10_VCCRR
GND_VCCRL
GND_VCCRR
S10_VCCRL
GND_VCCRLS10_VCCRL_GXB_SENSE
S10_VCCRL
12V12V
12V12V
GND_VCCRR
GND_VCCRR
GND_VCCRR
GND_VCCRR GND_VCCRR
GND_VCCRL
GND_VCCRLGND_VCCRL
GND_VCCRL
S10_VCCRL_GXB_SENSE
S10_VCCRR_GXB_SENSE
EN_VCCRL_GXB 11,52
VCCRL_GXB_SENSE_N 12,13VCCRL_GXB_SENSE_P 12,13EN_VCCRR_GXB 11,52
VCCRR_GXB_SENSE_N 12,13VCCRR_GXB_SENSE_P 12,13
VCCRR_DACOUT 12,13VCCRL_DACOUT 12,13
PWR3_PWRGD 10PWR4_PWRGD 10
PWR4_VSENSE_GND10,12,52 PWR4_VSENSE10,12,52
PWR3_VSENSE_GND 10,12,52PWR3_VSENSE 10,12,52
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B47 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B47 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B47 53Monday, March 13, 2017
C57522uF
U71B
LTM4620AEY#PBF
VIN1M2VIN2M3VIN3M4VIN4M5VIN5M6VIN6M7VIN7M8VIN8M9VIN9M10VIN10M11VIN11L2VIN12L3
VOUT1_1 A1VOUT1_2 A2VOUT1_3 A3VOUT1_4 A4VOUT1_5 A5VOUT1_6 B1VOUT1_7 B2VOUT1_8 B3VOUT1_9 B4
VOUT1_10 B5VOUT1_11 C1VOUT1_12 C2VOUT1_13 C3VOUT1_14 C4VIN13L4
VIN14L5VIN15L6VIN16L7VIN17L8VIN18L9VIN19L10VIN20L11VIN21J2VIN22J3VIN23J4VIN24J9VIN25J10VIN26J11VIN27K2VIN28K3VIN29K4VIN30K9VIN31K10VIN32K11
VOUT2_1 A8VOUT2_2 A9VOUT2_3 A10VOUT2_4 A11VOUT2_5 A12VOUT2_6 B8VOUT2_7 B9VOUT2_8 B10VOUT2_9 B11
VOUT2_10 B12VOUT2_11 C9VOUT2_12 C10VOUT2_13 C11VOUT2_14 C12
C6020.01uF
R539
316K
U71A
LTM4620AEY#PBF
COMP1 E6
DIFFP E8
PGOOD1 G9
TEMPJ6
MODE-PLLINF4
RUN1F5
VFB2 D7RUN2F9
CLKOUT G5
FSETC6
SW1 G2
SW2 G11VFB1 D5
PGOOD2 G8
PHASMDG4
TRACK1E5TRACK2D8
DIFFOUT F8
DIFFN E9COMP2 E7
INTVCCH8EXTVCCJ7
VOUTS1C5VOUTS2C8
C5820.01uF
C605100uF
C607100uF
C585100uF
C587100uF
U71C
LTM4620AEY#PBF
GND1A6GND2A7GND3B6GND4B7GND5D1GND6D2GND7D3GND8D4GND9D9GND10D10GND11D11GND12D12GND13E1GND14E2GND15E3GND16E4GND17E10GND18E11GND19E12GND20F1GND21F2GND22F3GND23F10
SGND1C7SGND2D6SGND3G6SGND4G7SGND5F6SGND6F7
GND24 F11GND25 F12GND26 G1GND27 G3GND28 G10GND29 G12GND30 H1GND31 H2GND32 H3GND33 H4GND34 H5GND35 H6GND36 H7GND37 H9GND38 H10GND39 H11GND40 H12GND41 J1GND42 J5GND43 J8GND44 J12GND45 K1GND46 K5GND47 K6GND48 K7GND49 K8GND50 K12GND51 L1GND52 L12GND53 M1GND54 M12
V60RSNS 1SNS2
C59722uF
C57622uF
V63RSNS 1SNS2
R546150K
R540150K
C581DNI
C598100uF
V56RSNS 1SNS2
C579100uF
U70C
LTM4620AEY#PBF
GND1A6GND2A7GND3B6GND4B7GND5D1GND6D2GND7D3GND8D4GND9D9GND10D10GND11D11GND12D12GND13E1GND14E2GND15E3GND16E4GND17E10GND18E11GND19E12GND20F1GND21F2GND22F3GND23F10
SGND1C7SGND2D6SGND3G6SGND4G7SGND5F6SGND6F7
GND24 F11GND25 F12GND26 G1GND27 G3GND28 G10GND29 G12GND30 H1GND31 H2GND32 H3GND33 H4GND34 H5GND35 H6GND36 H7GND37 H9GND38 H10GND39 H11GND40 H12GND41 J1GND42 J5GND43 J8GND44 J12GND45 K1GND46 K5GND47 K6GND48 K7GND49 K8GND50 K12GND51 L1GND52 L12GND53 M1GND54 M12
R543
0.001C600DNI
V65RSNS 1SNS2
C58347pF
C59910uF
U70B
LTM4620AEY#PBF
VIN1M2VIN2M3VIN3M4VIN4M5VIN5M6VIN6M7VIN7M8VIN8M9VIN9M10VIN10M11VIN11L2VIN12L3
VOUT1_1 A1VOUT1_2 A2VOUT1_3 A3VOUT1_4 A4VOUT1_5 A5VOUT1_6 B1VOUT1_7 B2VOUT1_8 B3VOUT1_9 B4
VOUT1_10 B5VOUT1_11 C1VOUT1_12 C2VOUT1_13 C3VOUT1_14 C4VIN13L4
VIN14L5VIN15L6VIN16L7VIN17L8VIN18L9VIN19L10VIN20L11VIN21J2VIN22J3VIN23J4VIN24J9VIN25J10VIN26J11VIN27K2VIN28K3VIN29K4VIN30K9VIN31K10VIN32K11
VOUT2_1 A8VOUT2_2 A9VOUT2_3 A10VOUT2_4 A11VOUT2_5 A12VOUT2_6 B8VOUT2_7 B9VOUT2_8 B10VOUT2_9 B11
VOUT2_10 B12VOUT2_11 C9VOUT2_12 C10VOUT2_13 C11VOUT2_14 C12
C596100pF
C57710uF
C60347pF
C58922uF
C56822uF
J89
WE_PWR_Terminal_5.08mm
1 1
2 2
C604100uF
C584100uF
R54469.8K
V57RSNS 1SNS2
J86
WE_PWR_Terminal_5.08mm
1 1
2 2
R545
316K
R535
0.001
C59122uF
C57022uF
C594100uF
C574100uF
U70A
LTM4620AEY#PBF
COMP1 E6
DIFFP E8
PGOOD1 G9
TEMPJ6
MODE-PLLINF4
RUN1F5
VFB2 D7RUN2F9
CLKOUT G5
FSETC6
SW1 G2
SW2 G11VFB1 D5
PGOOD2 G8
PHASMDG4
TRACK1E5TRACK2D8
DIFFOUT F8
DIFFN E9COMP2 E7
INTVCCH8EXTVCCJ7
VOUTS1C5VOUTS2C8
C593100uF
R537100K C573100uF
C580100pF
C59510uF
C57110uF
C592100uF
C572100uF
C5904.7uF
C5694.7uF
C606100uF
V64RSNS 1SNS2
C586100uF
R53869.8K
R542100K C58822uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FMCA VADJ/VCCIO
PWR - FMC A
Install only one1.2V
R578 1.35VR580
VCCIO FMCA SELECT
1.5VNONEInstalled
FMCA Voltage
1.8VR582(Default)
connect GNDsthrough a single via
1.8V/1.504V/1.348V/1.2V/9A
3.3V Enable Circuit
SS -> 15nF * 0.065 = 1msFsw = 1.2MHz
1.8V Enable Circuit
1.8V ramp time 4ms
CAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
FMCA_ADJ_VFB
FMCA_VADJ_PWRGDFMCA_ADJ_VFB
EN_VCCIO
S10_1V8_SENSE_P
S10_1V8_SENSE_N
EN_VCCH_GXB
EN_VCCIO
FMCA_VADJ
GND_FMCA
GND_FMCA
GND_FMCA
GND_FMCA
GND_FMCA
3.3V_PRE
12V
3.3V_PRE 3.3V
12V
S10_1.8V_SENSE1.8V_PRE 1.8V
S10_1.8V_SENSE
1.8V
GND_FMCA
EN_VCCIO 11,49,52FMCA_VADJ_PWRGD 10
PWR7_PWRGD 10,41EN_VCCH_GXB 11,46,52
S10_1V8_SENSE_P 12,13S10_1V8_SENSE_N 12,13
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B48 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B48 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B48 53Monday, March 13, 2017
V69RSNS 1SNS2
R5770
R7490
R572
DNI
C622
47uf U93FDMC2514
5123
4
R574DNI
R581 316K
C626
0.015u
F
R583 160K
C628DNI
R4630.001
R576DNI
R744160K
R579 649K
C62047uf
U74
EN63A0QI
VOUT0 20VOUT1 21VOUT2 22VOUT3 23VOUT4 24VOUT5 25VOUT6 26VOUT7 27VOUT8 28
PVIN039PVIN140PVIN241PVIN342PVIN443PVIN544PVIN645PVIN746PVIN847PVIN948PVIN1049PVIN1150PVIN1251
PGND0 32PGND1 33PGND2 34PGND3 35PGND4 36PGND5 37PGND6 38
PGND(THRM) 77
POK 58VFB 63
ENABLE59 AVIN60S_OUT 57
AGND61
NC11NC22NC33NC44NC55NC66NC77NC88NC99NC1010NC1111NC1212NC1313NC1414NC1515NC1616NC1717NC1818NC1919
NC29 29NC30(SW)30 30NC30(SW)31 31
NC(SW)70 70NC(SW)71 71
NC72 72NC73 73NC74 74NC75 75NC76 76
SS65EN_PB69
EAOUT 64
S_IN56
BGND55
VDDB54
VSENSE 66
FQADJ68
NC(XREF) 67
M/S62
NC52 52NC53 53
R5714.42K
R568 0
C61747pF
R7300
U94
LTC4365
VIN4 VOUT 6
GATE
5
UV3GND 1
OV2FAULT 7SHDN8
GND 9
C62147uf
R7480
V23RSNS 1SNS2
C61947uf
C630
0.01uF
R578 DNI
V22RSNS 1SNS2
U76FDMC2514
5123
4
R56512K
R582 0
R561
0
C6290.22uF R575100K
R5630
R580 DNI
C819DNIC820
47nF
C821100uF1206
R731DNI
C745 0.1uF
R564160K
C627100uF1206
R560DNI
R732100K
U77
LTC4365
VIN4 VOUT 6
GATE
5
UV3GND 1
OV2FAULT 7SHDN8
GND 9
C618
47uf
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VFB=0.75VIFB=5nA
PWM mode for better Ripple performanceFsw = 1.9MHzSS -> 22nF * 80kOhm = 1.8msec
2.5V
PWR - FMC B/2.5V
2.525V/1A
connect GNDsthrough a single via
SS -> 15nF * 0.065 = 1msFsw = 1.2MHz
FMCB VADJ/VCCIO
Install only one1.2V
R603 1.35VR605
VCCIO FMCA SELECT
1.5VNONEInstalled
FMCB Voltage
1.8VR607(Default)
connect GNDsthrough a single via
1.8V/1.504V/1.348V/1.2V/9A
CAD Notes:
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
2V5_PWRGD
EN_VCCIO
FMCB_VADJ_PWRGDFMCB_ADJ_VFB
EN_VCCIO
FMCB_ADJ_VFB
2V5_VSENSE
2V5_VSENSE_GND
3.3V_PRE
3.3V_PRE
2.5V
GND_FMCB
GND_FMCB
GND_FMCB
GND_FMCB
GND_FMCB
3.3V_PRE FMCB_VADJ
GND_2V5 GND_2V5
GND_2V5
GND_2V5
GND_FMCB
2.5V
EN_VCCIO 11,48,522V5_PWRGD 10
FMCB_VADJ_PWRGD 10
2V5_VSENSE_GND 122V5_VSENSE 12
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B49 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B49 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B49 53Monday, March 13, 2017
V111RSNS1 SNS 2
C63347uf
R60184.5K
C63947UFC63847UF
C636
47uf R5870
R599 0
V112RSNS1 SNS 2
R609560
C63247uf
C641
0.015u
F
R58912K
R600 DNI
R594 0
R588160K
R603 DNI
C63447pF
C64015pF
R598
DNIR595 0
R607 0
V70RSNS 1SNS2
C642 22nF
R596200k
R586
0
V86RSNS 1SNS2
R604 649K
U79
EN6337
NC(SW
)11
NC(SW
)22
NC3
3NC
44
VOUT0 5VOUT1 6VOUT2 7VOUT3 8VOUT4 9VOUT5 10VOUT6 11
NC(SW
)1212
PGND0 13PGND1 14PGND2 15PGND3 16PGND4 17PGND5 18
PVIN019
NC25
25NC
2424
NC23
23NC
2222
PVIN221 PVIN120
NC(SW
)3838
NC(SW
)3737
NC(SW
)3636
NC(SW
)3535
NC(SW
)3434
AVIN33
AGND 32
VFB 31SS30
RLLM29
POK 28
ENA27
SYNC/LLM26
PGND6 39
R602DNI
R605 DNI R606 316K
R585DNI
U78
EN63A0QI
VOUT0 20VOUT1 21VOUT2 22VOUT3 23VOUT4 24VOUT5 25VOUT6 26VOUT7 27VOUT8 28
PVIN039PVIN140PVIN241PVIN342PVIN443PVIN544PVIN645PVIN746PVIN847PVIN948PVIN1049PVIN1150PVIN1251
PGND0 32PGND1 33PGND2 34PGND3 35PGND4 36PGND5 37PGND6 38
PGND(THRM) 77
POK 58VFB 63
ENABLE59 AVIN60S_OUT 57
AGND61
NC11NC22NC33NC44NC55NC66NC77NC88NC99NC1010NC1111NC1212NC1313NC1414NC1515NC1616NC1717NC1818NC1919
NC29 29NC30(SW)30 30NC30(SW)31 31
NC(SW)70 70NC(SW)71 71
NC72 72NC73 73NC74 74NC75 75NC76 76
SS65EN_PB69
EAOUT 64
S_IN56
BGND55
VDDB54
VSENSE 66
FQADJ68
NC(XREF) 67
M/S62
NC52 52NC53 53
R592160K
C6430.22uF
R608 160K
R591DNI
C744 0.1uF
R5974.42KC729 0.1uF
C63547uf
C63722uF
C631
47uf
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Decoupling 1
FPGA VCCIO BANKS 2L/2N
0201 0402
0201 0402
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
S10_VCC
S10_VCCERAM
S10_VCCRR
S10_VCCRL
S10_VCCAPLL
FMCB_VADJ
S10_VCCRR
S10_VCCRL
S10_VCC
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B50 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B50 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B50 53Monday, March 13, 2017
C10090.1uF
C15560.1uF
C13300.1uF
C12790.22uF
C109247nF
C1108100uF
C9010.01uF
C14050.01uF
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0.01uF
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22nF
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0.01uF
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C15260.1uF
C1194100uF
C12550.22uF
C107947nF
C13410.1uF
C91147nF
C98922nF
C13030.1uF
C8370.22uF
C10550.01uF
C95322nF
C8560.22uF
C9730.01uF
C107222nF
C12680.22uF
C13610.01uF
C13160.1uF
C9780.01uF
C15550.1uF
C12870.1uF
C10080.1uF
C137322nF
C13290.1uF
C12780.22uF
C108547nF
C15440.1uF
C1189100uF
C14980.01uF
C11690.1uF
C106822nF
C10170.22uF
C9620.01uF
C10221uF
C12560.22uF
C13420.1uF
C13630.01uF
C8440.22uF
C15270.1uF
C13040.1uF
C91247nF
C13640.01uF
C99222nF
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C13620.01uF
C13170.1uF
C10930.1uF
C95222nF
C9790.01uF
C8570.22uF
C107322nF
C13950.01uF
C1179100uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Decoupling 2
FPGA VCCIO BANKS 3I/3J/3L
0201 0402
0201 0402
0201
0402
0402 0201
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
S10_VCCT
S10_VCCH
FMCA_VADJ
1.8V
S10_VCC
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B51 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B51 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B51 53Monday, March 13, 2017
C697330uF
C11320.01uF
C1248330uF
C121647nF
C9440.22uF
C117147nF
C683220uF
C11230.01uF
C708100uF
C66522nF
C11250.01uF
C6611uF
C719100uF
C11270.01uF
C11680.1uF
C12120.01uF
C11220.01uF
C6601uF
C709100uF
C92047nF
C10210.22uF
C11970.01uF
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C117347nF
C1237220uF
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C11740.22uF
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C114722nF
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C12030.01uF
C1244100uF
C689220uFC1119
0.01uF
C115947nF
C725100uF
C11300.01uF
C1034330uF
C114022nF
C10150.1uF
C11210.01uF
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C78322nF
C1242220uF
C12151uF
C694220uF
C114622nF
C1114330uF
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C12040.01uF
C10264.7uF
C1245330uF
C722330uF
C115022nF
C1192330uF
C11370.01uF
C115847nF
C688220uF
C10910.1uF
C11800.47uF
C114122nF
C727100uF
C115247nF
C10160.1uF
C123247nF
C693330uF
C94022nF
C1115100uF
C724330uF
C11280.01uF
C691220uFC1138
0.01uF
C116047nF
C11360.01uF
C114222nF
C9240.22uF
C11831uF
C99947nF
C696220uF
C1035100uF
C728330uF
C658100uF
C9370.01uF
C1246100uF
C690330uF
C717100uF
C122222nF
C9430.1uF
C116347nF
C11064.7uF
C695220uF
C929100uF
C1193100uF
C94247nF
C11290.01uF
C681330uF
C11160.01uF
C1247100uF
C692220uF
C91847nF
C11040.47uF
C11950.01uF
C116147nF
C698220uF
C9450.47uF
C116447nF
C12170.01uF
C11770.22uF
C682220uF
C6594.7uF
C12190.1uF
C11240.01uF
C11200.01uF
C720100uF
C11170.01uF
C707100uF
C1190330uF
C123022nF
C12130.01uF
C11960.01uF
C6630.1uF
C9231uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
place two V very close to decoupling cap location
place decoupling cap under FPGA
Fast Discharge and V-Senseplace two V very close to decoupling cap location
place two V very close to decoupling cap locationplace two V very close to decoupling cap location
place two V very close to decoupling cap location
place two V very close to decoupling cap location
place two V very close to decoupling cap location
place decoupling cap under FPGA
place decoupling cap under FPGA
place decoupling cap under FPGA
place decoupling cap under FPGA
place decoupling cap under FPGA
place decoupling cap under 1.8V regulator
place two V very close to decoupling cap locationplace decoupling cap under 3.3V regulator
CAD Notes:
For Socket board:DNI C644 (0.01uF)
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
PWR1_VSENSE
PWR1_VSENSE_GND
PWR7_VSENSE
PWR7_VSENSE_GND
PWR2_VSENSE
PWR2_VSENSE_GND
PWR3_VSENSE
PWR3_VSENSE_GND
PWR4_VSENSE
PWR4_VSENSE_GND
PWR5_VSENSE
PWR5_VSENSE_GND
PWR6_VSENSE
PWR6_VSENSE_GND
3V3_VSENSE
3V3_VSENSE_GND
EN_VCC
EN_VCCRL_GXB
EN_VCCERAM
EN_VCCRR_GXB
EN_VCCT_GXB
EN_VCCH_GXB
EN_VCCIO
EN_VCCIO
EN_VCCIO
EN_VCCIO
EN_VCCH_GXB
S10_VCC
1.8V_PRE
S10_VCCERAM
S10_VCCRL
S10_VCCRR
S10_VCCT
S10_VCCH 3.3V_PRE
S10_VCC3.3V_STBY
S10_VCCRL3.3V_STBY
S10_VCCERAM3.3V_STBY
S10_VCCRR3.3V_STBY
S10_VCCT3.3V_STBY
S10_VCCH3.3V_STBY
FMCA_VADJ3.3V_STBY
FMCB_VADJ3.3V_STBY
2.5V3.3V_STBY
3.3V3.3V_STBY
1.8V3.3V_STBY
PWR1_VSENSE 10,12,42PWR2_VSENSE 10,12,46PWR2_VSENSE_GND 10,12,46PWR7_VSENSE 10,12PWR7_VSENSE_GND 10,12
PWR1_VSENSE_GND 10,12,42
PWR4_VSENSE 10,12,47PWR4_VSENSE_GND 10,12,47
PWR3_VSENSE 10,12,47PWR3_VSENSE_GND 10,12,47
PWR6_VSENSE_GND 10,12,46PWR6_VSENSE 10,12,46PWR5_VSENSE 10,12,41PWR5_VSENSE_GND 10,12,41
3V3_VSENSE 12,403V3_VSENSE_GND 12,40EN_VCC 11,42EN_VCCRL_GXB 11,47EN_VCCRR_GXB 11,47EN_VCCERAM 11,46EN_VCCT_GXB 11,41EN_VCCH_GXB 11,46,48EN_VCCIO 11,48,49
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B52 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B52 53Monday, March 13, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
B52 53Monday, March 13, 2017
R695 10
R69110.0K
U85FDMC2514
5
123
4
V74RSNS1 SNS 2
V83RSNS1 SNS 2
R7280.5
V81RSNS1 SNS 2
R71910.0K
Q6FDV305N
C6470.01uF
R77910
R69610.0K
R692 10
R713 10
R7080.5 R832 DNI
R822 DNI
R69910.0K
C6460.01uF
U86FDMC2514
5
123
4
Q14FDV305N
R825 DNI
Q11FDV305N
R829 DNI
V84RSNS1 SNS 2
R831 DNI
R721 10
R7730.5
R700 10
V103RSNS1 SNS 2
Q12FDV305N
C6490.01uF
R72210
R7200.5
R6970.5
U102FDMC2514
5
123
4
C7670.01uF
R70310.0K
R72610
V77RSNS1 SNS 2
R704 10
V104RSNS1 SNS 2
U91FDMC2514
5
123
4
R69010
V71RSNS1 SNS 2
R78010.0K
Q13FDV305N
V80RSNS1 SNS 2
R70610
C6440.01uF
U92FDMC2514
5
123
4
V72RSNS1 SNS 2
R826 DNI
R77110
C6450.01uF
R7240.5R7010.5
Q7FDV305N
R6930.5
R7820.5
R72310.0K
V76RSNS1 SNS 2
R71010
R781 10
V75RSNS1 SNS 2
R7120.5
R72710.0K
U87FDMC2514
5
123
4
Q8FDV305N
U99FDMC2514
5
123
4
Q10FDV305N
Q3FDV305N
R823 DNI
R828 DNI
V78RSNS1 SNS 2
R725 10
R69410
R7050.5
R830 10
R71810
R70710.0K
U88FDMC2514
5
123
4
V79RSNS1 SNS 2
R729 10
R77210.0K
R69810
Q4FDV305N
V73RSNS1 SNS 2
C6480.01uF
U83FDMC2514
5
123
4
R71110.0K
Q5FDV305N
U90FDMC2514
5
123
4
R824 DNI
U84FDMC2514
5
123
4
R827 DNI
R774 DNI
V82RSNS1 SNS 2
R70210
R709 10
C6500.01uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Revision HistoryDESCRIPTIONVer. DATE PAGES
C1 Add current measurement for 1.8V rail in LT solution (S10_1V8_SENSE_P/N)Add system thermal management solution (MAX1619)Don't swap transceiver p/n polarity for CFP4/QSFP28 interfaces
Change CLK_S10TOP_ADJ to default 100MHz, VCC to default 0.89V
Connect CPU_resetn to global input pin of S10
MAX10 U97 replace U11 to output clocks (USB_FPGA_CLK/USB_MAX5_CLK)
C1C1C1C1
C1C1Use DYN-EP-TL15R1 liquid cooling module
C1Clean up non-RoHS parts
C1 Use PM0_VDD33 rail to pullup LT_SCL/LT_SDA
C1 VCC regulator sense voltage from S10 VCCLSENSE pins
Copyright (c) 2016, Intel Corporation. All Rights Reserved.Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
C1 Install R64, R65, R819, C109, DNI U11, C119-C121, R793, C106C1 Change R59 to 0ohm
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
A53 53Monday, April 17, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
A53 53Monday, April 17, 2017
Title
Size Document Number Rev
Date: Sheet o f150-0321312-C1 C1
Stratix 10 GX SI Development Kit (6XX-44410R)
A53 53Monday, April 17, 2017