s emb t8-arch_itfio
TRANSCRIPT
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RMR©2012
Maths is not everything
Embedded Systems4 - Hardware Architecture
CPUInput/Output mechanisms
Memory Buses and Aux I/O
Input/Output interfacesPower Management
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RMR©2012
Maths is not everything
UART
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Maths is not everything
Asynchronous Transmission
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Máquina A Máquina B
Tx A Rx B
Tx BRx A
Bit Time
Least Significant BitMost Significant Bit
Stop BitsStart Bit
65H ⇔ ‘e’
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Maths is not everything
DB9 pinout of a DTE
DTE vs DCEPinout of a DCE?Common ground?Noise effects?
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Maths is not everything
RS-232 transmission example
How do peers agree on timing?
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Maths is not everything
SPI
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Maths is not everything
Serial Peripheral Interface
What is it?
Basic SPI
Capabilities
Protocol
Pros and Cons
Uses
Serial Peripheral Interface
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What is SPI?
Serial bus protocolFast, easy to use, and simpleVery widely usedNot “standardized”
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SPI Basics
A 4-wire communications busTypically communicate across short distancesSupports
Single master
Multiple slaves
SynchronizedCommunications are “clocked”
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SPI Capabilities
Always full-duplexCommunicates in both directions simultaneously
Transmitted (or received) data may not be meaningful
Multiple Mbit/s transmission speeds0-50 MHz clock speeds not uncommon
Transfer data in 4 to 16 bit charactersSupports multiple slaves
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SPI bus wiring
Bus wiresMaster-Out, Slave-In (MOSI)
Master-In, Slave-Out (MISO)
System Clock (SCLK)
Slave Select/Chip Select (SS1#, …, SS#n or CS1, …, CSn)
Master asserts slave/chip select lineMaster generates clock signalShift registers shift data in and out
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SPI signal functions
MOSI – carries data out of master to slaveMISO – carries data out of slave to master
Both MOSI and MISO are active during every transmission
SS# (or CS) – unique line to select each slave chipSCLK – produced by master to synchronize transfers
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SPI uses a “shift register” model of communications
Master shifts out data to Slave, and shifts in data from Slave
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Two bus configuration models
Master and multiple independent slaves
Master and multiple daisy-chained slaves
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SPI clocking: there is no “standard way”
Four clocking “modes”Two phases
Two polarities
Master and selected slave must be in the same modeDuring transfers with slaves A and B, Master must
Configure clock to Slave A’s clock mode
Select Slave A
Do transfer
Deselect Slave A
Configure clock to Slave B’s clock mode
Select Slave B
Do transfer
Deselect Slave B
Master reconfigures clock mode on-the-fly!
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SPI timing diagram
Timing Diagram – Showing Clock polarities and phases
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SPI example: decode what’s happening
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SPI tradeoffs: the pros and cons
ProsFast for point-to-point connections
Easily allows streaming/constant data inflow
No addressing in protocol, so it’s simple to implement
Broadly supported
ConsSlave select/chip select makes multiple slaves more complex
No acknowledgement (can’t tell if clocking in garbage)
No inherent arbitration
No flow control (must know slave speed)
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I2C
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I2C bus
Inter-Integrated Circuit
Two wire serial bus specification
Designed for low-cost, medium data rate applications.
Several microcontrollers come with built-in I2C controllers.Invented by Philips in the early 1980s
The division is now NXPWas a patented protocol, but patent has now expired
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I2C bus architecture
I2C
Standardizes peripheral classes
SCK, SDA
Philips/NXP
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I2C details
Two-wire serial protocol with addressing capability
Speeds up to 3.4 MbpsWhat limits I2C to such small speeds?
Multi-master architecture
Open collector bus driver
Pull-up resistors
Multi-master, Multi-slaveUses bus arbitration
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I2C physical layer
Two linesSDA (serial data)
SCL (serial clock)
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master 1 master 2
slave 1 slave 2
SCL
SDAdata line
clock line
SDL
+
SCL
+
Open collector designSimple interfacing for multi-voltage
Supports bus arbitration
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I2C signaling
Sender pulls down bus for 0.Sender listens to bus---if it tried to send a 1 and heard a 0, someone else is simultaneously transmitting.Transmissions occur in 8-bit bytes.
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I2C clock
Not a “traditional” clockNormally is kept “high” using a pull-upPulsed by the master during data transmission
Master could be either the transmitter or receiver
Slave device can hold clock low if needs more time
Allows for flow control
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I2C transaction
Transmitter/receiver differs from master/slave
Master initiates transactions
Slave responds
Transmitter sets data on SDL line, slave acks
For a read, slave is transmitter
For a write, master is transmitter
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I2C bus transactions: start and stop conditions
Master pulls SDA low while SCL is highNormal SDA changes only happen when SCL is low
Master pulls SDA high while SCL is highAlso used to abort transactions
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I2C address transmission
Data is always sampled on the rising clock edgeAddress is 7 bitsAn 8-th bit indicated read or write
High for read
Low for write
Addresses assigned by Philips/NXPFor a fee
Was covered by patent
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I2C data transmission
Transmitted just like address (8 bits)For a write, master transmits, slave acknowledgesFor a read, slave transmits, master acknowledgesTransmission continues
Subsequent bytes sent
Continue until master creates stop condition
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Maths is not everything
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008
Way
ne W
olf
I2C bus arbitration
Sender listens while sending address.When sender hears a conflict, if its address is higher, it stops signaling.Low-priority senders relinquish control early enough in clock cycle to allow bit to be transmitted reliably.
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Maths is not everything
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olf
I2C transmissions
multi-byte write
read from slave
write, then read
S adrs 0 data data P
S adrs 1 data P
S adrs 0 data S adrs 1 data P
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Maths is not everything
I2C bus transactions: data transfer