rutherford appleton laboratory particle physics department a novel cmos monolithic active pixel...

Rutherford Appleton Laboratory Particle Physics Department A Novel CMOS Monolithic Active Pixel Sensor with Analog Signal Processing and 100% Fill factor J.P. Crooks 3 , J.A. Ballin 1 , P.D. Dauncey 1 ,A-M. Magnan 1 , Y. Mikami 2 , O. Miller 2 ,M. Noy 1 , V. Rajovic 2 , M. Stanitzki 3 , K.D. Stefanov 3 , R. Turchetta 3 , M. Tyndel 3 , E.GiulioVillani 3 , N. K. Watson 2 , J. A. Wilson 2 1 :Imperial College London, 2 :University of Birmingham, 3 : STFC Rutherford Appleton Laboratory Pixels small enough: at most one particle/pixel 1-bit ADC/pixel: Digital ECAL Example: ECAL – Terapixel APS for ILC SORMA West 2008 Berkeley, California USA INMAPS process: Deep P-Well implant to shield N-Well housing readout electronic Potential barrier between P ++ -Well and Epitaxial reflects back generated charge into the active layer Dramatic improvement in charge collection New INMAPS process New INMAPS process Pixel simulation standard process Pixel simulation standard process Detector Microphotograph and laser setup used for Detector Microphotograph and laser setup used for testing (right). testing (right). Laser test results on INMAPS and NO INMPAS test Laser test results on INMAPS and NO INMPAS test pixel (left). pixel (left). Laser test results Laser test results Laser IR (1064nm, 2μm minimum shutter size, 4ns pulse) Laser scans clearly indicate that the INMAPS process increases charge collection efficiency Further investigations ongoing Source test results Source test results Test with radioactive sources validate the usefulness of INMAPS process Further tests ongoing to understand unexpected threshold spread New sensor submission planned summer 08 Source test results: Source test results: 55 55 Fe (right) and Fe (right) and β β source (left) source (left) on INMAPS test pixel on INMAPS test pixel INMAPS test results INMAPS test results INMAPS test results INMAPS test results Two different readout implemented at pixel level: Pre-shape and Pre-sample (160 and 189 transistors respectively) Two different capacitor arrangements DC power consumption approximately 10μW 0.18μm CMOS process ≈ 144mV ≈ 202mV ≈ 9.5μm Study of optimal diodes location and size carried out on the new process 12μm epitaxial layer thickness Rs t Vr st Shaper PreRst Buﬀe r s.f Cf b Ci n Buﬀe r s.f Vth + Vth - Reset Sampl e Csto re Pream p Shape r Rs t Cp re Cf b Rf b Ri n Ci n Vth + Vth - Pre-Shape Pixel Analog Front End Low gain / High Gain Comparator Pre-Sample Pixel Analog Front End Low gain / High Gain Comparator Hit Logi c 150 ns 150 ns 450 ns Hit Logi c Self Reset Trim&Mas k SRAM SR Trim&Mas k SRAM SR Hit Outpu t Hit Outpu t Pixel Readout Topology Analog Pixel Readout Topology Analog Each digital block serves 42 pixels from one row, split into groups of 6 pixels After a hit, for each row the logic stores timestamp, pattern number and pattern in SRAM 28224 pixels, approximatel6 8x10 6 transistors 1x1cm 2 total surface Dead area 250μm / 2mm Pixel Readout Topology Digital Pixel Readout Topology Digital INMAPS simulation results INMAPS simulation results In a complex pixel design a standard MAPS solution leads to low charge collection efficiency Approximately 50% of the generated charge is collected by the readout N-Wells MAPS digital calorimeter concept MAPS digital calorimeter concept Pixel collection Charge (e - ) <Q> 87 Q max 362 Q min 1 5 Q stdev 107 Pixel collection Charge (e - ) <Q> 401 Q max 656 Q min 1 261 Q stdev 95 Pre-shape (left) and pre-sample Pre-shape (left) and pre-sample (right) pixel layout (right) pixel layout 5050 μm 2 MAPS pixels SiD 16mm 2 area cells Contacts: [email protected] Contacts: [email protected]

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Rutherford Appleton LaboratoryParticle Physics Department

A Novel CMOS Monolithic Active Pixel Sensor with Analog Signal Processing and 100% Fill factor

J.P. Crooks3, J.A. Ballin1, P.D. Dauncey1,A-M. Magnan1, Y. Mikami2, O. Miller2,M. Noy1, V. Rajovic2, M. Stanitzki3, K.D. Stefanov3, R. Turchetta3, M. Tyndel3, E.GiulioVillani3, N. K. Watson2, J. A. Wilson2

1:Imperial College London, 2:University of Birmingham, 3: STFC Rutherford Appleton Laboratory

Pixels small enough: at most one particle/pixel 1-bit ADC/pixel: Digital ECAL Example: ECAL – Terapixel APS for ILC

SORMA West 2008 Berkeley, California USA

INMAPS process: Deep P-Well implant to shield N-Well housing readout electronic Potential barrier between P++-Well and Epitaxial reflects back generated charge into the active layer Dramatic improvement in charge collection

New INMAPS process New INMAPS process

Pixel simulation standard processPixel simulation standard process

Detector Microphotograph and laser setup used for testing (right).Detector Microphotograph and laser setup used for testing (right).Laser test results on INMAPS and NO INMPAS test pixel (left).Laser test results on INMAPS and NO INMPAS test pixel (left).

Laser test resultsLaser test results Laser IR (1064nm, 2μm minimum shutter size, 4ns pulse) Laser scans clearly indicate that the INMAPS process increases charge collection efficiency Further investigations ongoing

Source test results Source test results Test with radioactive sources validate the usefulness of INMAPS process Further tests ongoing to understand unexpected threshold spread New sensor submission planned summer 08

Source test results: Source test results: 5555Fe (right) and Fe (right) and ββ source (left) on INMAPS test pixel source (left) on INMAPS test pixel

INMAPS test resultsINMAPS test resultsINMAPS test resultsINMAPS test results

Two different readout implemented at pixel level: Pre-shape andPre-sample (160 and 189 transistors respectively) Two different capacitor arrangements DC power consumption approximately 10μW 0.18μm CMOS process

≈ 144mV≈ 202mV

≈ 9.5μm

Study of optimal diodes location and size carried out on the new process 12μm epitaxial layer thickness

Rst

Vrst

Shaper

PreRst

Buffer

s.f

Cfb

CinBuffer

s.f

Vth+Vth-

Reset

Sample

Cstore

Preamp Shap

Rst

Cpre

Cfb

Rfb

RinCinVth+Vth-

Pre-Shape Pixel Analog Front End

Low gain / High Gain

Comparator

Pre-Sample Pixel Analog Front End

Low gain / High Gain

Comparator

Hit Logic

150ns

450ns

Hit Logic

Self Reset

Trim&Mask

SRAM SR

Trim&Mask

SRAM SR

Hit Output

Pixel Readout Topology AnalogPixel Readout Topology Analog

Each digital block serves 42 pixels from one row, split into groups of 6 pixels After a hit, for each row the logic stores timestamp, pattern number and pattern in SRAM 28224 pixels, approximatel6 8x106 transistors 1x1cm2 total surface Dead area 250μm / 2mm

Pixel Readout Topology Digital Pixel Readout Topology Digital

INMAPS simulation resultsINMAPS simulation results

In a complex pixel design a standard MAPS solution leads to low charge collection efficiency Approximately 50% of the generated charge is collected by the readout N-Wells

MAPS digital calorimeter conceptMAPS digital calorimeter concept

Pixel collection Charge (e-)

<Q> 87

Qmax 362

Qmin1 5

Qstdev 107

Pixel collection

Charge (e-)

<Q> 401

Qmax 656

Qmin1 261

Qstdev 95