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Use your computer to test digital ICs and eliminate your troubleshooting guesswork!

HOW DO YOU TEST IC'S? IF YOU'RE A DIGI- tal enthusiast on a tight budget, then you probably go about it the low -cost way: You set up your breadboard, a handful of jumpers. a power supply, and a measuring instrument such as a logic probe or oscilloscope. Manual operation of such a

crude setup can quickly become te- dious- especially when the circuit being tested has multiple edge -sensitive inputs.

There's a bigger problem with such a

setup, however. Since you must perform the tests one gate at a time or one latch at a

time, you can expect to find only the most obvious failures. The more subtle types of failures -such as interaction between separate circuits within the same pack- age -are best found by some kind of automated tester.

If you have a computer, you can easily build an automated tester for digital IC's. The tester we' Il describe permits automat- ic testing of digital integrated circuits with up to sixteen pins. The host may be an eight -bit or a sixteen -bit microcomputer

and can have either separate input and output data busses or a bidirectional data bus. While the author's prototype was built as a tester for TTL IC's, the princi- ples that we'll discuss apply equally well to other popular logic families.

Although the tester well describe was designed for use with an S -100 system. you should be able to adapt the circuit for virtually any computer. We should note here that using the tester will require some programming proficiency. While the article will describe what the software has to do, actual program instructions are not included.

Figure I shows the basic idea behind the IC testing scheme. A host computer is used as a stimulus generator: it sends data patterns, called stimuli, to the circuit under test. Each stimulus is sixteen bits wide -one bit is assigned to each pin of the test circuit. After the stimulus is sent, the host will accept a response (also sixteen bits wide) from the circuit under test and will perform an analysis of that re-

sponse. Response analysis begins with a comparison between the actual response and sonic known expected response. If they are equal, the host continues with the next stimulus. What happens if they're not equal depends on the software that is used by the host system.

Stimulus generation How do we determine the set of stimuli

that we want the host system to generate? We must ensure that the set of stimuli fora given type of integrated circuit is both valid and complete. At first glance, you might think that a set of stimuli that presents every possible bit combination to the input pins of the circuit under test would meet those requirements. Those stimuli could be created very easily simply by causing the host to "count through" the input pins. Consider the simple hex inverter with six input pins and six output pins. Using bit -masking techniques. the host could "count through" those six input bits from zero to sixty-three and thereby

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63

FLOYD L. OATS

Use your computer to test digitallC's and eliminate your troubleshooting guesswork!

HOW DO YOUTEST IC ' S? IFYOU'RE A DIGI-

tal enthusiast on a tight budget , then youprobably go about it the low-cost way: Youset up your breadboard, a handful of jum-pers, a power supply, and a measuringinstrument such as a logic probe or os-cilloscope. Manual operation of such acrude setup ca n qui ckl y becom e te-dious-especially when the circuit beingtested has multiple edge-se nsitive inputs.

There's a bigger problem with such asetup, however: Since you must performthe tests one gate at a time or one latch at atime, you can expect to find only the mostobvious failures. The more subtle types offailures-such as interact ion betweeneparate circuits within the same pack-

age-arebest found by some kind of auto-mated tester.

If you have a compu ter, you can easilybuild an automated tester for digitaI IC's .The tester we' ll describe perm its automat-ic testing of digital integrated circuits withup to sixteen pins. The host may be aneight-bit or a sixteen-bit microcomputer

and can have either separate input andoutput data busses or a bi-directional databus. While the author's prototype wasbuilt as a tester forITL Ie's, the princi-ples that we' ll discuss apply equally wellto other popular logic families.

Although the tester we'll describe wasdesigned for use with an S-IOO system,you should be able to adapt the circuit forvirtually any computer. We should notehere that using the tester will require someprogramming proficiency. While the arti-cle will describe what the software has todo, actual program instructions are notincluded.

Figure I shows the basic idea behind theIC testing scheme. A host computer isused as astimulus generator :It sends datapatterns, calledstimuli, to the circuit un-der test. Each stimulus is sixteen bitswide-r-one bit is assigned to each pin ofthe test circuit. After the stimulus is sent,the host will accept a response (also six-teen bits wide) from the circuit under testand will perform an analysis of that re-

sponse. Response analysis begins with acomparison between the actual responseand some known expected response. Ifthey are equal, the host continues with thenext stimulus. What happens if they're notequal depends on the software that is usedby the host system.

Stimulus generationHow do we determine the set of stimuli

that we want the host system to generate?We must ensure that the set of stimuli for agiven type of integrated circuit is bothvalid and complete. At first glance, youmight think that a set of stimuli that pre-sents every possible bit combination to theinput pins of the circuit under test wouldmeet those requirements. Those stimulicould be created very easily simply bycausing the host to"count through" theinput pins. Consider the simple hex inver-ter with six input pins and six output pins.Using bit-masking techniques. the hostcould "count through" those six inputbits from zero to sixty-three and thereby

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HOST COMPUTER

STIMULUS GENERATOR

RESPONSE ANALYZER

16817 STIMULUS IC UNDER TEST

16-SIT RESPONSE

FIG. 1 -THE IC TESTER SENDS a 16 -bit stimulus to the IC to be tested. and then examines the response.

present sixty-four stimuli for the hex inverter.

That counting scheme does generate a

complete and valid set of stimuli for IC's that contain nothing but raw gating. But it falls short with IC's that have edge -sensitive inputs. For example, counting through the input pins of an ordinary flip - flop allows the clock pin to change simultaneously with the data pin(s) at some counts. Those counts lead to an indeterminate response of the flip -flop, rendering the set of counting stimuli invalid.

Let's assume further that the clock pin is assigned to, say. the fourth significant bit of the stimulus generator and a data pin is assigned to the second or third significant bit. Due to the nature of the up -count function. the clock pin will change only when the data pin is high -the stimuli set is incomplete as well as invalid. In that particular case, the problem is partially solved by counting downward. But with multiple edge -sensitive inputs, the problem quickly becomes unmanageable. As we'll see, we'll need to use methods other than the counting stimuli to overcome those difficulties.

Response analysis Once we present the stimulus to an IC,

we have to look at the response. Response analysis includes all 16 pins of the test circuit. You might wonder why we want to look at all 16 pins -after all, we don't

have to look at the input pins to determine the output response. There are two reasons why we do look at all pins. First. it is simpler from the software standpoint -it eliminates the extra steps required to ex- clude certain pins from analysis. The second and better reason is that if we examine the input pins of the test circuit, we can detect failures associated with input loading problems. Also, we can verify that the stimulus was actually presented to the test circuit. In other words, we can give the tester self -diagnostic capability.

If the host is going to analyze the response of an IC, it has to know what type of response to expect. The only way it can know what to expect is if we teach it. A set of good responses can be generated by presenting stimuli to an IC that is known to function properly. The responses along with the stimuli used to produce them can then be stored on disk or tape for future use.

Functional description Figure 2 is a block diagram of the tester;

it should help to make our description of the schematic (Fig. 3) clearer. As shown in both figures. data or stimuli from the host system comes into a set of latches made up of ICI, 1C2, IC4, and IC5. (In eight -bit systems, eight data lines and the lower eight address lines are used to feed the stimulus latches.) As shown in Fig. 3, the STIMULUS LOAD signal (which enables

8

the latches) is connected to all four latch IC's. Therefore, it's essential that all sixteen stimulus bits be presented to the latches simultaneously. The use of eight address lines to carry stimulus information causes the tester to occupy 256 memory locations. (In 8 -bit systems, that corresponds to 256 bytes. In I6 -bit system, those 256 locations correspond to 512 bytes.)

The outputs of the four 4 -bit latches are fed to sixteen isolation switches. SI S16. Only the switches that feed the input pins of the IC to be tested will he closed. Switches connected to the output pins of the test circuit will be open to prevent interference between stimulus latches and output signals. Switches connected to the power supply pins will be open to prevent possible damage to stimulus latches.

The lines from the isolation switches go to test socket SOI. As you can see from the schematic, the isolation- switch numbers correspond to the test -circuit pin that they feed. For example, switch SII feeds pin II of test socket SOI. That makes determining the switch positions a little easier.

The power supply consists of a five -volt regulator (IC11), filter capacitor Cl, and a

power- supply -source socket, S03. (The regulator can be omitted from many systems that contain central five -volt power supplies.) Notice that the voltage is wired into S03 according to standard con- vention: Va. on pin 14, and ground on pin 7.

Power is supplied to the IC under test by a pair of movable jumpers connected from the power -supply -source socket, S03, to the power -supply -select socket. SO2 (which is wired in parallel with the test socket). If, for example, you wanted to test a 7475, you would connect a jumper from pin 14 of SO3 to pin 5 of SO2. You would also jumper pin 7 of SO3 to pin 12 of SO2.

Response data are accepted by the host

HOST COMPUTER

S DATA LINES

B LEAST-SIGNIFICANT ADDRESS LINES

MOST-SIGNIFICANT ADDRESS LINES

16 BIT STIMULUS LATCH

EN

CONTROL LINES

ADDRESS DECODER

ISOLATION SWITCHES AND JUMPER OPTIONS

IC

UNDER TEST

BUS DRIVER, MULTIPLEXER

EN

FIG. 2 -BLOCK DIAGRAM OF THE IC TESTER shows how the host computer's data. address. arid control lines are used to control the tester.

HOST COMPUTER

FIG. 1- THE IC TESTER SENDS a 16·blt stimulus to the IC to be tested, and then examines theresponse.

STIMULUSGENERATOR 16·BITSTIMULUS ICUNOER ｔｾｓｔ I ｽｾＬＮ ,.:.-'

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present sixty-four stimuli for the hex in-verter.

That counting scheme does generate acomplete and valid set of stimuli for Ie'sthat contain noth ing but raw gating. But itfalls short with Ie's that have edge-sen-sitive inputs . For example , countingthrough the input pins of an ordinary flip-flop allowsthe clock pin to change simul-taneously with the data pines) at somecounts. Those counts lead to an indeter-minate response oft he flip-flop, renderingthe set of counting stimuli invalid.

Let's assume further that the clock pinis assigned to, say, the fourth significantbit of the stimulus generator and a data pinis assigned to the second or third signifi-cant bit. Due to the nature of the up-countfunction, theclock pin will change onlywhen the data pin is high-the stimuli setis incomplete as well as invalid. In thatparticular case, the problem is partiallysolved by counting downward. But withmultiple edge -sensitive inputs, the prob-lem quickly becomes unmanageable. Aswe'll see, we' ll need to use methods otherthan the counting stimuli to overcomethose difficult ies .

Response analysisOnce we present the stimulu s to an IC,

we have to look at the response . Responseanalysis includes all 16 pins of the testcircuit. You might wonder why we want tolook at all 16 pins- after all, we don 't

have to look at the input pins to determinethe output response. There are two rea-sons why we do look at all pins. First, it issimpler from the software standpoint-i teliminates the extra steps required to ex-clude certain pins from analysis. The sec-ond and better reason is that if we examinethe input pins' of the test circuit, we candetect failures associated with input load-ing problems. Also, we can verify that thestimulus was actually preserited to the testcircuit. In other words, we can give thetester self-diagnostic capability.

If the host is going to analyze the re-sponseofan IC, it has to know what typeof response to expect. The only way it canknow what to expect is if we teach it. A setof good responses can be generated bypresenting stimuli to an IC that is knownto function properly. Theresponsesalongwith the stimuli used to produce them canthen be stored on disk or tape for futureuse .

Functional descriptionFigure 2 is a block diagram of the tester;

it should help to make ourdescriptionofthe schematic (Fig. 3) clearer. As shownin both figures, data or stimuli from thehost system comes into a set of latchesmade up of ICI , IC2, IC4 , and IC5. (Ineight-bit systems, eight data lines and thelower eight address lines are used to feedthe stimulus latches.) As shown in Fig. 3,the ｓｾｉｍｕｌｕｓ LOAD signal (which enables

the latches) is connected to all four latchIe's. Therefore, it 's essential that all six-teen stimulus bits bepresentedto thelatches simultaneously. The use of eightaddress lines to carry stimulus informa-tion causes the tester to occupy 256 mem-ory locations. (In 8-b it systems , thatcorresponds to 256 bytes. In 16-bit sys-tem, those 256 locationscorrespondto512bytes.)

The outputs of the four 4-bit latches arefed to sixteen isolation switches .SI-SI6.Only the switches that feed the input pinsof the IC to be tested will beclosed.Switches connected to the output pins ofthe test circuit will be open to preventinterference between stimulus latches andoutput signals. Switches connected to thepower supply pins will be open to preventpossible damage to stimulus latches.

The lines from the isolation switches goto test socket SOl. As you can see fromthe schematic, the isolation-swi tch num-berscorrespondto the test-circuit pin thatthey feed. For example, switch SII feedspin 11 of test socket SOl. That makesdetermi ning the switch positions a littleeasier.

The power supply consists of a five-voltregulator (ICll), filter capacitor Cl, and apower-supply-source socket,S03. (Theregulatorcan be omitted from many sys-tems that contain central five-volt powersupplies .) Notice that the voltage is wiredinto S03 according to standardcon-vention:Veeon pin 14, and ground on pin7.

Power is supplied to the IC under test bya pair of movablejumpersconnected fromthe power-supply-source socket,S03, tothe power-s up ply-se lec tsocket, S02(which is wired in parallel with the testsocket).If, for example, you wanted to testa 7475, you would connect a jumper frompin 14ofS03to pin 5 of S0 2. You wouldalso jumper pin 7 ofS03to pin 12ofS02.

Response data are accepted by the host

...8 DATA LINES > ISOLATION

16·BIT "- SWITCHES IC BUS16·BITSTIMULUS .> STIMULUS :> UNDER RESPONSE> I-

ｾ STIMULUS AND DRIVER.TEST MULTIPLEXER

8 LEAST-SIGNIFICANT LATCH JUMPER v -ADDRESS LINES V .OPTIONS

EN ENHOST iCOMPUTER

B ｍｏｓｔＧｓｉｇｎｉｆｉｃｾADDRESS LINES /

ADDRESSDECODER

CONTROL LINES >v

Ｏｾ16·BITRESPONSE (2 SETS OF 8 BITS) BACK TO HOST COMPUTER i

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615<: FIG. 2-BLOCK DIAGRAM OF THE IC TESTER shows how the host computer 's data, address, andCC control lines are used to control the tester.

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FIG. 3 -IC TESTER SCHEMATIC. If you use a 16 -bit system, you do not have to use address lines for the stimulus input -use the 16 data lines instead. Note that to make building and troubleshooting easier, you should use DIP switches for S1 -S16.

one byte at a time. Pins 1 -8 of the test socket SOI are gated to the host system through drivers made up of IC7 and part of IC3. Pins 9 -I6 are gated through portions of IC's 3 and 6. The two sets of drivers are

enabled by control signals from ICS. Control logic, made up of IC8, 1C9.

and ICIO develops signals that control the loading of the stimulus latches and the gating of response data to the host. The

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eight most significant address lines are brought into an address- recognition circuit consisting of IC9 and part of ICIO. Two address lines. Al2 and A13, are inverted before being applied to 1C9. That selective inversion controls the address range of the memory space occupied by

RESPONSE OUTPUT

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STIMULUS INPUT

FIG.3-IC TESTERSCHEMATIC. If you use a 16·bitsystem, you do not have to useaddress lines for thestimulus input-use the 16 data lin es instead. Note that to make building and troubleshootlnq easier,you should use DIP switches for 51-516.

one byte at a time. Pins 1-8 of the testsocket501 are gated to the host systemthrough drivers made upofIC?and part ofIC3. Pins 9- 16are gated through portionsof IC 's 3 and 6. The two sets of drivers are

enabled by control signals from IC8 .Control logic. made up of IC8. IC9.

and ICIOdevelops signals that contro l theloading of the stimulus latches and thegating of responsedata to the host. The

eight most significant address lines arebrought into anaddress-recognition cir-cuit consis ting of IC9 and part of IClO.Two address lines.Al2 and Al3, are in-verted before being applied to IC9. Thatselective inversion contro ls the addressrange of the memory space occupied by

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CONNECTIONS TO HOST COMPUTER

FIG. 4 -THE AUTHORS PROTOTYPE was wire- wrapped on an S -100 prototyping board Parts placement and construction technique are not critical.

the tester. In this case, the address range chosen is CFOOH through CFFFH. (Note that an "H" indicates that a number is written in hexadecimal form.) While there are two inverters shown in the schematic, any number of inverters may be used. They are placed so that. when the address lines are designating the memory area assigned to the tester, all inputs to IC9 are high. That, presents a high to IC8 pin 6, partially enabling it. Pins 4 and 5, fed by inverted I /O- status lines, must be low to complete the enabling of 1C8. Those lines will be low when the address lines carry a

memory address as opposed to an input/ output port address (the latter being indi- cated by a high on IC6 pin 12 or 14). In systems where all input/output areas are memory- mapped and there are no separate input/output functions. pins 4 and 5

of 1C8 should be directly grounded. When IC8 is enabled, it will decode the

inputs on pins I, 2, and 3 into an active - low signal on one of eight output pins. When SMEMR, the memory-read status signal, is high (and Mws-r, the memory- write enable signal, is low), pin 12 or 13

will be low, depending on the state of AO. If AO is low, IC8 pin 13 will gate pins I

through 8 of the test circuit to the response lines. When AO is high, IC8 pin 12 will gate pins 9 through 16 of the test circuit to the response lines.

To write to the stimulus latches, ?Awn is brought high while SMEMR is low. That causes either pin 10 or II of IC8 to go low. Since AO is part of the stimulus information. the STIMULUS U)AD signal must be insensitive to the state of AO. This is ac- complished by the diodes DI and D2 connected to IC8 pins IO and I I -they permit the STIMULUS LOAD signal to be generated

by win without regard to the condition of AO.

Construction You can build the tester using either

printed -circuit or wire-wrap techniques. Component layout is not critical and there is no need to be concerned with special considerations such as lead lengths and extensive decoupling. The author's prototype was wire- wrapped on an S -100 plugboard. It is recommended that you use a board that is configured for your computer system.

We recommend that you use DIP switches for the isolation switches: It keeps the board much neater and. thus, easier to troubleshoot. Be sure to label the switch numbers. Mount the DIP switch packages and all of the IC's in wire-wrap sockets. The power -supply jumper sockets SO2 and S03 should also be empty wire-wrap sockets. For the test socket, SOI , you might want to use a "zero insertion force" type socket. Do not substitute

PARTS LIST IC1, IC2. IC4, IC5- 74LS75 4 -bit bistable

latch IC3. IC6. IC7 -74367 hex bus dnver IC8- 74LS138 3 -to -8 line decoder,multi-

plexer IC9- 74LS30 8 -input positive HANO gate ICIO- 74LSO4 hex inverter Dl. D2 -1N914 R1. R2 -2000 ohms St -S16 SPST switch (DIP switches are

recommended) C1 -2011,F. 10 volts, electrolytic Miscellaneous: IC sockets, plugboard. wire -wrap wire. hardware, power- supply jumper wires. 5 -volt DC power source. etc.

LS -type IC's tor 1C3, IC6, and IC7. If your 8 -bit system has separate input

and output data busses, the data -output lines should be fed to the stimulus latches while the data -input lines should be fed from the response output of the tester. In sixteen -bit systems, the stimulus latches may be loaded from the sixteen data lines rather than using the lower eight address lines as part of the stimulus. And, of course. the response drivers may be tied to the sixteen data lines instead of being multiplexed into two sets of eight.

If your host computer system uses a

bidirectional data bus instead of separate input and output busses, then the data lines (but. of course, not the address lines) into the stimulus latches and the data lines from the response drivers may be connected to the unified bus.

Using a host computer with sixteen -bit organization simplifies the control circuit by permitting the AO input (IC8 pin 1) to be grounded (since its only purpose is to split the sixteen response lines into two groups.) Pins 12 and IO of IC8 could be left open. and the output from pin 13

would gate all sixteen response drivers. The control circuit shown was designed

for an eight bit host with sixteen address bits. In hosts which have fewer than sixteen address bits, there will be fewer than eight lines feeding into IC9. Consider a

system with only fourteen address bits. The eight least- significant address bits will be assigned as stimulus bits. leaving only six bits for the address recognition function. The two unused pins of IC9 may be connected together and tied to + 5 volts through a one -kilohm resistor.

When we continue. we'll begin by testing the tester. R -E

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.. .. • .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. e ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. ... .. .. .. .... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . ... .. .. .. .. .. .. .. ... .. .. .. .. ... .. .. .. .. .. .. .. .... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... ... .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ... .. ..... .. .. .. .. .. .. .. .. .. ..

.. .. .. ... .. • .. .. .. .. .. .. .. .. .. • .. .. • .. .. .. .. .. • • .. .. .. .. .. .. .. • .. .. .. .. .. .. .. .. .. • .. .. .. .. e.- .... .. .. .. .. .. -- ," .... .. .. .. .. ... .. .. .. .. .. ... .. .. .. .. .. .. .. .. ... .. ... .. ... .. .. .... .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. • .. • .. .. .. e .... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ...... .. .. .. .. ... .. .. ... .. ... .. .. .. ... .. .. .. ... .. .. ... ... .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. .. .. .... .. .. . .. .. . .. .. ... .. .. .. . .. .. .. .. .. . .. .. .. .. .. . .. .. .. .... ::::::: : :-: -: ＺＭ［ＺＺｾ :-:: :-:-; ;-:::::::: :-.-:-.;.:::::;: .. :.::

FIG. 4-THE AUTHOR'S PROTOTYPEwas wire-wrapped on an S·100 prototyping board. Parts place-ment and construction technique are not critical.

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the tester. In this case, the address rangechosen is CF00H through CFFFH . (Notethat an "H" indica tes that anumber iswritten in hexadecimalform.) While thereare two inverters shown in the schematic ,any number of inverters may be used .They are placed so that , when the addresslines are designating the memory area as-signed to the tester, all inputs to IC9 arehigh. That , presents a high to ICS pin 6,partia lly enabling it. Pins 4 and 5, fed byinverted I/O-status lines, must be low tocompletethe enabling of ICS. Those lineswill be low when the addre ss lines carry amemory address as oppo sed to an input/output port addres s (the latter being indi-cated by a high on IC6 pin 12 or 14). Insystems where all input/output areas arememory-mapped and there are110 sepa-rate input/output functions, pins 4 and 5of ICS should be directly grounded.

When ICS is enabled, it will decode theinputs on pins I, 2, and 3 into an active-low signal on one of eight output pins.When SMEMR, the memory-read statussignal, is high (andMWRT, the memory-write enable signal, is low), pin 12 or 13will be low, depending on the state of A0.If A0 is low, ICS pin 13 will gate pins Ithrough Sof the test circu it to the responselines. When A0 is high , ICS pin 12 willgate pins 9 through 16 of the test circuit tothe response lines.

To write to the stimulus latches,MWRT

is brought high whileSMEMR is low. Thatcauses either pinIO or I I of ICS to go low.Since A0 is part of the stimulus informa-tion, theSTIMULUS LOAD signal must beinsensitive to the state of A0. This is ac-co mplished by the diode s DI and 0 2 con-nectedto ICS pinsIO and II- they permittheST IMU LUS LOAD signal to be generated

by MWRT without regard to the conditionof A0.

Construction

You can build the tester usingeitherprinted-circuit or wire-wrap techniques.Component layout is not critical and thereis no need to be concerned with specialconsiderations such as lead lengths andextensive decouplin g. The author's pro-totype was wire-wra pped on anS-IOOplugboard .It is recommendedthat youuse a board that is configured for yourcomputer system.

We recommendth at you useDIPswitches for the isolation switches : Itkeeps the board much neater and, thus,easier to troubleshoot. Be sure to label theswitch numbers. Mount the DIP switchpackages and all of theIe's in wire-wrapsocke ts. The power-suppl y jumper sock-ets S02 andS03 should also be emptywire-wrap sockets. For the test socke t,SO I, you might want to use a"zero inser-tion force" type socket. Do not substitute

PARTS LISTIC1, IC2, IC4, IC5-74LS75 4-bit bistable

latchIC3, IC6, IC7-74367 hex bus driverIC8-74LS138 s-e-a line decoder/multi-

plexerIC9-74lS30 8-input positive NAND gateIC1G-74LS04 hex inverterD1, D2-1N914Rl , R2-2000 ohmsSl -S16 SPST switch (DIP switches are

recommended)C1-20I-lF, 10 volts, electrolyticMiscellaneous: IC sockets, plugboard,wire-wrap wire, hardware, power-supplyjumper wires, +5-volt DC power source,etc.

LS-type Ie's for IC3, IC6, and IC?If your S-bit system has separate input

and output data busses, the data-outputlines should be fed to the stimulus latcheswhile the data-input lines should be fedfrom the response output of the tester. Insixteen-bit systems, the stimulus latchesmay be loaded from the sixteen data linesrather than using the lower eight addresslines as part of the stimulus. And, ofcourse, the response drivers may be tied tothe sixteen data lines instead of beingmultiplexed into two sets of eight.

If your host computer system uses abidirectional data bus instead of separateinput and output busses, then the datalines (but, of course,notthe address lines)into the stimulus latches and the data linesfrom the response drivers may be con-nected to the unified bus.

Using a host computer with sixteen-bitorganization simplifies the control circuitby permitting theAD input (ICS pin I) tobe grounded (since its only purpose is tosplit the sixteen response lines into twogroups.) Pins 12 and 10 of ICS could beleft open, and the output from pin 13would gate all sixteen response drivers.

The control circuit shown was designedfor an eight bit host with sixteen addressbits. In hosts which have fewer than six-teen address bits, there will be fewer thaneight lines feeding into IC9. Consider asystem with only fourteen address bits.The eight least-signi ficant address bitswill be assigned as stimulus bits. leavingonly six bits for the address recog nitionfunction. The two unused pins of IC9 maybe connected together and tied to+ 5volts through a one-kilohm resistor.

When we continue, we' ll begin by test-ing the tester. R-E

66



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Goo Pat' siesta FLOYD L. OATS

This month we'll test the IC tester and then we'll look at some options that you can add.

Part 2 usT MONTH, WE DE-

scribed the IC- tester circuit and the theory behind how it works. Now it's time to make sure that it does work. After we do that, we'll look at some options that you can add to your tester. For example, we'll build a low - budget logic analyzer -it works by ex- panding your oscilloscope display to 16

traces.

Testing the tester Most of the components and wiring are

located in the data paths so the inherent self -diagnostic feature of the tester can be utilized as a debugging aid for the finished project. After the device is built and connected to the host computer, preliminary testing can begin.

For the purpose of discussion, we will assume that the device has been mapped into memory addresses CFOOH through CFFFH (as it is shown in the schematic). Note: An "H" indicates that a number is written in hexadecimal form.

Open all the isolation switches (SI S16) and make sure that the test socket is empty and that there are no power-- supply jumpers between SO3 and SO2. Read the sixteen response bits by per- forming memory reads on addresses CFOOH and CFOIH. Both of those addresses should return FFH, indicating that the response is equal to sixteen "I" bits. Next, close all the isolation switches and write sixteen zeros in the stimulus latches by writing 00 into address CFOOH. Read the response as before and look for sixteen zero bits. Now write all ones in the stimulus latches by writing FFH into memory address CFFFH and check for a response of all ones. as before. At this point, the tester is in a configuration where all stimulus information should be exactly dupli- cated on the response lines.

The next test will require a short program to send counting stimuli to the tester. After each stimulus is sent to the latches, the response is accepted and compared with the stimulus for equality. If

single -bit failures are observed during the the test. the components and wiring associated with that particular bit should be checked carefully. If the hit patterns don't change or if they don't even resemble the correct patterns. the control circuitry might be at fault. Any discrepancies noted up to this point must be repaired before proceeding with further tests.

The final series of tests will verify the wiring of the isolation switches. Starting with all switches closed. open one switch and send a stimulus of all zeros. The response should be all zeros except for a single "I" hit. which should correspond to the open switch. Now close the switch just tested and open the next switch, then perform a similar stimulus/response test on this switch. Continue in this fashion until all sixteen switches have been tested. The final test is started with all switches open and is similar to the previous test in that one switch at a time is tested. This time the switches will be closed one at a time. Send test patterns of all zeros and

This month we'll test the /e tester and then we'll/ook at some options that you can add.

Part 2 LAST MONTH , WE DE-

scr ibed the IC-testercircuit and the theory behind how itworks. Now it's time to make sure that itdoeswork. After we do that , we'11 look atsome options that you can add to yourtester. For example, we'll build a low-budget logic analyzer-it works by ex-panding your oscilloscope display to 16traces.

Testing the testerMost of thecomponents and wiring are

located in the data paths so the inherentself-diagnostic feature of the tester can beｵｴｩｬｩｺ･､ｾ｡ｳ a debugging aid for the finishedproject. After the device is built and con-nected to the host computer, preliminarytesting can begin.

For the purpose of discussion, we willassume that the device has been mappedinto memory addressesCF00H throughCFFFH (as it is shown in the schematic).Note: An "H " indicates that a number iswritten in hexadecimal form.

Open all th e isolation swit ches(SI- SI6) and make sure that the test sock-et is empty and that there are no power-supply jumpers betweenS03 and S02.Read the sixteen response bits by per-forming memory reads on addressesCF00H and CF0IH . Both of those ad-dresses should return FFH, indicating thatthe response is equal to sixteen " I" bits .Next, close all the isolation switches andwrite sixteen zeros in the stimulus latchesby writing 00 into address CF00H. Readthe response as before and look for sixteenzero bits. Now write all ones in the stim-ulus latches by writing FFH into memoryaddress CFFFH and check for a responseof all ones, as before. At this point, thetester is in a configuration where all stim-ulus information should be exactly dupli-cated on the response lines.

The next test will require a short pro-gram to send counting stimuli to the test-er. After each stimulus is sent to thelatches , the response is accepted and com-pared with the stimulus for equality. If

single-bit failures are observed during thethe test, the components and wiring asso-ciated with that particular bit should bechecked carefully. If the bit patterns don'tchange or if theydon't even resemble thecorrect patterns, the control ci rcuitrymight be at fault. Any discrepancies notedup to this point must be repaired beforeproceeding with further tests.

The final series of tests will verify thewiring of the isolation switches. Startingwith all switches closed, open one switchand send a stimulus of all zeros . TIle re-sponse should be all zeros except for asingle "I" bit, which should correspondto the open switch. Now close the switchjust tested and open the next switch, thenperform a similar stimulus/response teston this switch. Continue in this fashionuntil all sixteen switches have been tested .The final test is started with all switchesopen and is similar to the previous test inthat one switch at a time is tested. Thistime the switches will be closed one at atime. Send test patterns of all zeros and

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83



84

2

3

C 4

C 5

C 6

C C

SERIAL DATA INPUT DS

Of

o

D2

03

MODE

GROUND

74LS95

v«

Of

D2

03

CK1 SHIFT RIGHT

CK1 -SHIFT LEFT

14

13

C 12

11

C 10

C 9

8

OPERATION MODE

INPUTS

CK1 CK2 Dg D OUTPUTS

al Ot Ot 03

PARALLEL LOAD H X : X I L L L L

H X 1 X H H H H H

SHIFT RIGHT L 1 X I X L q0 q1 q2

L 1 X H X H qo al q2

MODE CHANGE t L X X X NO CHANGE

t H X X X UNDETERMINED . X L X X NO CHANGE

X H X X UNDETERMINED

I LOW VOLTAGE ONE SETUP TIME PRIOR TO HIGH TO LOW CLOCK TRANSITION

LOWER CASE LETTERS REPRESENT STATE OF REFERENCED OUTPUT ONE SETUP TIME PRIOR TO

HIGH TO-LOW CLOCK TRANSITION t LOW TO HIGH TRANSITION

HIGH-TO LOW TRANSITION

FIG. 5 -THE 74LS95. Before you test any IC. you have to prepare a function table. That's not only because you have to determine a valid and complete set of stimuli. but you also have to determine what kind of response you should expect.

look for a response of all ones except tor the single closed switch.

Using the tester In order to test an IC, the isolation

switches and the power- supply jumpers must be configured for the specific circuit to be tested. The switches assigned to input pins of the test circuit must be closed and those assigned to output pins and power supply pins must be open. The actual test is done by comparing the set of test responses with a set of known good responses.

The best way to obtain a set of good responses is to issue stimuli to an IC (of the type you want to test) that you know to be good. You can save the responses for future comparison. Actually you should save both stimuli and responses since the patterns issued during the test must exactly match those used to create the initial patterns. A less attractive way of obtain- ing good response data is to issue patterns to a circuit thought to be good and then manually examine the response data to see if it is correct.

Let's consider the steps involved in testing the SN74LS95, a four -bit shift register with parallel -load capability. Figure 5

shows the pinout for that I4 -pin IC along with a table that describes the circuit's functions. The MODE input (pin 6) deter-

mines the mode in which the circuit is operating (parallel load or shift), and also determines which of the two clocks is permitted to change the register contents. The function table reveals that there are edge transitions in the mode -change area that will cause indeterminate results. Those transitions should be avoided during the testing process because they represent invalid stimuli.

Fourteen -pin ICs should be mounted in the I6 -pin socket such that pins 8 and 9 of the I6 -pin socket are empty. (Con- sequently. pin 14 of the IC is connected to pin 16 of the test socket and to SI6.) Fig- ure 6 shows that and also indicates the required position of each isolation switch for that particular IC. The + 5 -volt power - supply jumper must be connected from S03 pin 14 to SO2 pin 16. The ground jumper goes from S03 pin 7 to SO2 pin 7. Set up the switches and power- supply jumpers. insert the IC into the test socket. and testing can begin.

The 74LS95 has multiple edge -sensitive inputs. As we mentioned pre- viously, counting through the inputs does not generate suitable (complete and valid) stimuli for that IC. We shall use what amounts to a smaller and somewhat simpler set of test patterns as shown in Table 1

Table I indicates that several patterns

are issued to the 74LS95 before each response is read. For example, consider line 12 of the table. A stimulus of 0228H is sent, bringing ck2. MODE, and D, high. That is followed by 0068H on line 13. which brings cß:2 low. A response is then accepted; it and should equal 9028H on line 14.

How does the host know when to accept a response'? The software driver can take advantage of the fact that the isolation switches for the two power- supply pins are known to be open and that. consequently, those two pins are not sensitive to stimuli. Bits 7 and 16 can be used to imbed control -flag bits into the test data. Those can be used to tell the host whether to generate a stimulus, expect a response, call a subroutine, etc.

For example. when the ground line (bit 7) is made high, as on line 16. it indicates (to the author's test software) that a response is to be taken after the pattern is sent. When the + 5 -volt line is made high as on line 18, the software driver will call a

subroutine to clear the 74LS95 before sending the test pattern on line 18. Notice that line 15 brings bits 16 and 7 of the test circuit low. The software driver writes that pattern and then proceeds to the next pattern on line 16. The pattern on line 16 has bit seven high (ground pin), causing the driver to accept a response (line 17) after sending the 0070H pattern. When both supply lines are high as on line thirty, it signifies "end of test." That use of power supply pins is one way, but not the only way. of simplify the passage of control parameters to the software.

Because the SN74LS95 does not have a

separate CLEAR pin. the clear subroutine (Table 1, lines I -4) must use the parallel - load capability of the circuit to load all zeros into the internal register. The response should be tested after the clear subroutine since a failure here will cause subsequent failures in the main body of the test. It is good general practice to flag the earliest possible failure in a series of tests. especially if the software is going to perform a complete and exhaustive failure analysis.

Options If you build the tester on a prototyping

board designed for your host system. you will almost certainly find that there is plenty of space left on the board for possible expansion. For example, an 18 -pin socket may be added for the purpose of testing specific I8 -pin circuits such as the popular 2114 RAM series. (The power supply pins would be permanently wired to the power- supply lines, while the other sixteen pins would be wired parallel to the sixteen test socket pins.) Pin correspon- dence between the test socket and the 18-

pin socket can be assigned in any conve- nient order.

The addition of a PROM or EPROM

I : LOWVOLTAGE ONE SETUP TIMEPRIOR TO HIGH·TO·LOW CLOCK TRANSITIONLOWER CASE LEITERSREPR ESENT STATE OF REFERENCED OUTPUTONESETUP TIMEPRIOR TO

HIGH·TD·LOW CLOCKTRANSITIONt : LOW·TD·HIGHTRANSITIONｾＺ HIGH·TO·LOW TRANSITION

FIG. 5-THE 74LS95. Before you test any IC, you have to prepare a function table . That's not onlybecause you have to determine a valid and complete set of stimuli, but you also have to determine whatkind of respo nse you should expect.

INPUTS OUTPUTS'OPERATION

- -Oe 0, °2 °3MOOE CK1 CK2 Os On

H X ｾ X I L L L LPARALLEL LOAD H X ｾ X H H H H H

L ｾ X I X L aO a1 a2SHIFTRIGHT L ｾ X H X H qO q1 q2MODE CHANGE t L X X X NOCHANGE

t H X X X UNDETERMINEDｾ X L X X NO CHANGEｾ X H X X UNDETERMI NED

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84

look for a response of all ones,except forthe single closed switch.

Using the testerIn order to test an IC, the isolation

switches and the power-supply jumpersmust be configured for the specific circuitto be tested . The switches assigned toinput pins of the test circuit must be closedand those ass igned tooutput pins andpower supply pins must be open. The ac-tual test is .done by comparing the set oftest responses with a set of known goodresponses ,

The best way to obtain a set of goodresponses is to issue stimuli to an IC (ofthe type you want to test) that you know tobe good, You can save the responses forfuture comparison.Actually you shouldsave both stimuli and responses since thepatterns issued during the test must exact-ly match those used to create the initialpatterns . A less attractive way of obtain-ing good response data is to issue patternsto a circuit though t to be good and thenmanually examine the response data tosee if it is correc t.

Let's consider the steps involved in test-ing the SN74LS95, a four-bit shift registerwith parallel-load capability. Figure 5shows the pinout for that 14-pin IC alongwith a table that describes the circuit'sfunctions. TheMODE input (pin 6) deter-

mines the mode in which the circuit isoperating (parallel load or shift), and alsodetermines which of the ' two clocks ispermittedto change the register contents ,The function table reveals that there areedge transitions in the mode-change areathat will cau se ind eterminate result s ,Those transition s should be avoided dur-ing the testing process because they repre-sent invalid stimuli,

Fourteen-pinIC's should be mounted inthe 16-pin socket such that pinsSand 9 ofthe 16-pin socket are em pty, (Co n-sequently, pin 14 of the IC is connected topin 16 of the testsocketand toSI6,) fig -ure 6 shows that and also indicates therequired position of each isolation switchfor that particular Ie.The +5-volt power-supply jumper must be connec ted fromS03 pin 14 to S02 pin 16. The groundjumper goes fromS03pin 7 toS02pin 7.Set up the switches and power-supp lyjumpers, insert the IC into the test socket,and testing can begin.

The 74LS95 hasmultiple edge-sen-sit ive inputs. As wementioned pre-viously, counting through the inputs doesnot generate suitable (complete and valid)stimuli for that IC. We shall use whatamounts to a smaller and somewhat sim-pler set of test patterns as shown in TableI.

Table I indicates that several patterns

are issued to the 74LS95 before each re-sponse is read. For example, consider line12 of the table. A stimulus of 022SH issent, bringingCK2. MODE, and ｄｾ high .That is followed by 006SH on line 13,which brings cK2low. A response is thenaccepted; it and should equal 902SH online 14.

How does the host know when to accepta response? The software driver can takeadvantage of the fact that the isolationswitches for the two power-supply pins areknown to be open and that, consequently,those two pins are not sensitive to stimuli.Bits 7 and 16 can be used to imbed con-trol-flag bits into the test data. Those canbe used to tell the host whether to generatea stimulus, expect a response, call a sub-routine, etc.

For example, when the ground line (bit7) is made high , as on line 16, it indicates(to the author's test software) that a re-sponse is to be taken after the pattern issent. When the+5-volt line is made highas on line IS, the software driver will call asubroutine to clear the 74LS95 beforesending the test pattern on line IS. Noticethat line 15 brings bits 16 and 7 of the testcircu it low. The software driver writes thatpattern and then proceeds to the next pat-tern on line 16. The pattern on line 16 hasbit seven high (ground pin), causing thedriver to accept a response (line 17) aftersending the 0070H pattern . When bothsupply lines are high as on line thirty, itsignifies"end of test. " That use of powersupply pins is one way, but not the onlyway, of simplify the passage of controlparameters to the software.

Because the SN74LS95 does not have aseparateCLEAR pin, the clear subroutine(Table I, lines 1-4) must use the parallel-load capability of the circuit to load allzeros into the internal register. The re-sponse should be tested after the clearsubroutine since a failure here will causesubsequent failures in the main body ofthetest. It is good general practice to flagthe earliest possible failure in a series oftests,especially if the software is going toperform a comp lete and exhaustive failureanalysis.

Opt ionsIf you build the tester on a prototyping

boarddesignedfor your host system, youwill almost certainly find that there isplenty of space left on the board for possi-ble expansion. For example, an IS-pinsocket may be added for the purpose oftesting specific IS-pin circuits such as thepopu lar 2114 RAM series . (The powersupply pins would be permanently wiredto the power-supply lines, while the othersixteen pins would be wired parallel to thesixteen test socket pins.) Pin correspon-dence between the test socket and the IS-pin socket can be assigned in any conve-nient order.

The addition of a PROM or EPROM



SN7495 PIN 14 13 12 11 10 9 8 7 6 5 4 3 2 1

FUNCTION .5V OD 01 02 03 CK1 CK2 NC NC GD MODE 03 D2 D1 00 OS

SWITCH NUMBER S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 Si

AND POSITION d o- a. d er o- +o o.+ wo- .4 t - t. +.- +e. -o-.p-

FIG. 6- SWITCH SETUP for test ng the 7495 4-bit shift register.

programmer is practical because there are already sixteen latches on the board. If you add another SN74LS75 you'll have enough latches for the data and address lines of a 4K PROM. A square- or rec- tangular -wave generator may be added by selecting a bit and placing it under software control. Parameters describing the desired wave could be passed to software which would then compute the loop varia- bles required to create the wave on the chosen bit line. Squarewave monitoring could be done by bringing the external wave into a bit line and letting the software sample the line. Those are just a few of the many ways to expand the IC tester.

Oscilloscope adapter The logic analyzer is a very useful tool.

But because it's also rather expensive, most hobbyists do not have access to one. However, we'll offer an alternative to the logic analyzer: an adapter for your oscilloscope that allows it to display 16 sig-

nais. Of course. its linearity and general quality of presentation won't match that of the logic analyzer. And it won't imitate the varied and complex functions of a

logic analyzer. But it can be built from inexpensive, common logic- components. So for a very small expense, you can add a

valuable tool for testing digital IC's to your testbench. Perhaps more important, the oscilloscopeadapter logic analyzer can be an excellent tutorial aid.

The author's display -adapter prototype was developed as an expansion of the digital IC tester that was presented last month, and it uses TM IC's. However, the oscilloscope adapter can be built as a stand- alone unit, and the ideas can be applied to other logic families as well as TTL.

A look at the circuit The oscilloscope adapter's circuit (its

schematic is shown in Fig. 7) uses a counter /multiplexer /converter scheme to time- share sixteen digital signals onto a single

oscilloscope channel. The display counter, IC12 (a 74LS191

synchronous up /down counter), selects one of the sixteen channels for display. As it counts, each channel is selected in proper sequence -channel I is displayed on top, and channel 16 on the bottom.

A 74150 I -of -16 data selector /multiplexer, ICII accepts the sixteen digital inputs from the tester. It selects one of them to pass to its output (pin I0). The selected input depends on the contents of the display counter.

The inverting buffer /drivers, IC13, along with its associated resistors, form a

5 -bit 32 -state digital -to- analog (D /A) converter. It combines the four display - counter bits and the single, selected channel bit into one of thirty -two discrete voltage steps -two voltage levels for each displayed channel. The output signal to the oscilloscope swings through more than four volts of the available 5 -volt power-supply range.

TABLE 1

SIGNAL TYPE

HEX VALUE

BIT VALUES

ACTION 01 Stimulus 0220 0000 0010 0010 0000 - Bring cki and Moor high

CLEAR 02 Stimulus 0020 0000 0000 0010 0000 - Drop c2 (load zeros) 03 Stimulus 0040 0000 0000 0100 0000 - Drop MODE, then test 04 Response 8000 1000 0000 0000 0000 - All pins low except Va

05 Stimulus 8020 1000 0000 0010 0000 - Clear, then bring MODE high 06 Stimulus 0222 0000 0010 0010 0010 - Bring CK2 MODE. Do high 07 Stimulus 0062 0000 0000 0110 0010 - Drop CK2, then test 08 Response CO22 1100 0000 0010 0010 - Vcc, 00, MODE, Do high

PARALLEL 09 Stimulus 0224 0000 0010 0010 0100 - Bring CK2, MODE, D, high LOAD 10 Stimulus 0064 0000 0000 0110 0100 - Drop CK2, then test TEST 11 Response A024 1010 0000 0010 0100 - Vcc. 01, MODE, D, high

12 Stimulus 0228 0000 0010 0010 1000 - Bring MODE, D2 high 13 Stimulus 0068 0000 0000 0110 1000 - Drop CK2 then test 14 Response 9028 1001 0000 0010 1000 - Vtt, 02, MODE, D2 high 15 Stimulus 0230 0000 0010 0011 0000 - Bring CK2 MODE, D3 high 16 Stimulus 0070 0000 0000 0111 0000 - Drop ETC?. then test 17 Response 8830 1000 1000 0011 0000 - V«, 03, MODE, D3 high

18 Stimulus 8401 1000 0100 0000 0001 - Clear, then bring cKD, high 19 Stimulus 0041 0000 0000 0100 0001 - Drop -CR then test 20 Response C001 1100 0000 0000 0001 - V«, 00, D, high 21 Stimulus 0400 0000 0100 0000 0000 - Bring cK, high o, low

SHIFT 22 Stimulus 0040 0000 0000 0100 0000 - Drop cK+ then test TEST 23 Response A000 1010 0000 0000 0000 - Vcc. O, high

24 Stimulus 0401 0000 0100 0000 0001 - Bring cc7 o, high 25 Stimulus 0041 0000 0000 0100 0001 - Drop cK, then test 26 Response D001 1101 0000 0000 0001 - V«, Q. 02, D, high 27 Stimulus 0400 0000 0100 0000 0000 - CK1 high and D, low 28 Stimulus 0040 0000 0000 0100 0000 - Drop cC, then test 29 Response A800 1010 1000 0000 0000 - V«. O,. 03 high 30 Stimulus 8040 1000 0000 0100 0000 . END OF TEST

85

SN7495 PIN 14 13 12 11 10 9 8 7 6 5 4 3 2 1-FUNCTION +5V °0 °1 °2 °3 CK1 CK2 NC NC GO MODE 0 3 O2 0 1 00 Os

SWITCH NUMBER S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 Sl

ｾｾｾｾｾCi) Ci) Q

ｾ0 0 0 0 0 0

ｾＧＳAND POSITION

ｾ -0+G- ｾｾｾ -0+0- -<>+0- ｾ -0-.0- -0+0-

FIG. 6-SWITCH SETUP for testing the 7495 4-blt shift register.

programmeris practical becausethere are nals . Ofcourse,its linearity and general oscilloscopechannel .alreadysixteen latches on the board . If quality of presentationwon't match that The display counter, ICI2 (a 74LSI91you addanotherSN74LS7S, you' ll have of the logic analyzer. And itwon't imitate synchronous up/downcounter), selectsenoughlatches for the data and address the varied andcomplex functions of a one of the sixteen channels for display. Aslines of a 4KPROM. A square-or rec- logic analyzer. But itcall be built from it counts, eachchannelis selected in prop-tangu lar-wavegenerator may be added by inexpensive,commonlogic-components. er sequence---channel I is disp layed onselectinga bit andplacing it undersoft- So for a very small expense , you can add a top, and channe l 16 on the bottom .ware control. Parameters describingthe valuable tool for testing digital IC's to A 741S0 l-of-16 data selector/multi-desiredwave could be passed to software your testbenc h. Perhaps moreimportant, plexer, ICI I accept s the sixteen digitalwhich would thencomputethe loop varia- the oscilloscope-adapterlogic ana lyze r inputs from the tester.It selec ts one ofbles required to create the wave on the can be an excelle nt tutorial aid. them to pass to its output (pin 10). Thechosenbit line . Squarewavemonitoring The author's disp lay-adapterprototype selectedinput dependson thecontentsofcould be' done by bringing the external wasdevelopedas anexpansionof the digi- the disp lay counter.wave into a bit line and letting the software tallC tester that waspresentedlastmonth, The inverting buffer/drivers, ICI3,samp le the line.Thoseare just a few of the and it usesTTL IC's . However, the os- along with itsassociatedresistors, form amany ways toexpandthe IC tester. cilloscopeadaptercan be built as a stand- S-bi t 32-state dig ital -to-analog (D /A)

Oscilloscope adapteralone unit , and the ideas can be applied to converter.It combinesthe four display-otherlogic families as well as TTL. counter bits and the single, selected chan-

The logic analyzeris a very useful tool.A look at the circu it

nel bit into one of thirty-twodiscretevolt-But because it's also rather expensive, age steps-two voltage levels for eachmost hobbyists do not have access to one . The oscilloscopeadapter'scircui t (its displayed channel. The output signal toHowever,we'll offer an alternative to the schematic is shown in Fig. 7) uses a coun - the oscilloscope swings through morelogic analyzer: an adapter for your os- ter/multiplexer/converter scheme to time- than four volts of the availab le S-voltci lloscopethat allows it to disp lay 16 sig- share sixteen digital signals onto a single power-supply range.

TABLE 1

BIT VALUESSIGNAL HEX

/16..13A

TYPE VALUE 12..9 8..5 4..1 \ ACTION01 Stimulus 0220 0000 0010 0010 0000 - Bring ｾｋＲ andMODE high

CLEAR 02 Stimulus 0020 0000 0000 0010 0000 - DropCK2 (load zeros)03 Stimulus 0040 0000 0000 0100 0000 - DropMO DE, then test04 Response 8000 1000 0000 0000 0000 - All pins lowexceptVee

05 Stimulus 8020 1000 0000 0010 0000 - Clear, then bringMO DE high06 Stimulus 0222 0000 0010 0010 0010 - BringCK2 . MODE, 0 0 high07 Stimulus 0062 0000 0000 0110 0010 - DropCK2, then test08 Response C022 1100 0000 0010 0010 - Vee,00, MODE, DO high

PARALLEL 09 Stimulus 0224 0000 0010 0010 0100 - BringCK2, MO DE, 0 1 highLOAD 10 Stimulus 0064 0000 0000 0110 0100 -Drop CK2, then testTEST 11 Response A024 1010 0000 0010 0100 - Vee,Q1 , MODE, 01 high

12 Stimulus 0228 0000 0010 0010 1000 - Bri ngCK2. MODE, 0 2 high13 Stimulus 0068 0000 0000 0110 1000 - DropCK2 . then test14 Response 9028 1001 0000 0010 1000 - Vee,0 2 , MODE, 0 2 high15 Stimulus 0230 0000 0010 0011 0000 - BringCK2. MO DE, D3 high16 Stimulus 0070 0000 0000 0111 0000 - Drop CK2 , then test17 Response 8830 1000 1000 0011 0000 - Vee,Q3 ' .MO DE, 0 3 high

18 Stimulus 8401 1000 0100 0000 0001 - Clear, thenbring CK 1, Os high19 Stimulus 0041 0000 0000 0100 0001 - DropCK 1, then test20 Response C001 1100 0000 0000 0001 - Vee,Qo , Os high21 Stimulus 0400 0000 0100 0000 0000 - Bring CK 1.high o, low

SHIFT 22 Stimulus 0040 0000 0000 0100 0000 - DropCK1 , then testTEST 23 Response A000 1010 0000 0000 0000 - Vee,Q1 high

24 Stimulus 0401 0000 0100 0000 0001 - BringCK 1. Os high25 Stimulus 0041 0000 0000 0100 0001 - DropCK1, then test 026 Response 0001 1101 0000 0000 0001 - Vcc- Qo, Q2 , Os high 027 Stimulus 0400 0000 0100 0000 0000 - CK 1 highandOs low 028 Stimulus 0040 0000 0000 0100 0000 - Drop CK1 , then test OJ

m29 Response A800 1010 1000 0000 0000 - Vee,Q 1, Q3 high JJ

30 Stimulus 8040 1000 0000 0100 0000 - END OF TEST ｾ

<0co.j:>.

85



86

INPUTS (FROM TEST SOCKET)

8-

+5V

t24

2

4

5

6

7

u

9

10

11

12

13

14

15

IC11 74150

OUTPUT

GATA INPUTS

DATA SELECT

STB GND

10 0

o 3 o- 2 o 0-1-

23

v 22

21

20

0-19 10

17 o 16 o

-79 12

TRIGGER INPUT o

TRIGGER QUALIFIER INPUT

+5V

+5V

14

517 ZERO REF

ICU 1406 R6

330n

H9

3302

R10 330n

3 2 6 7

+5V

A B C D

OUTPUT CLK

'IC12 74LS191

EN GND DN/UP

14

OUTPUT TO SCOPE

0 SCOPE TRIGGER OUTPUT

FIG. 7- OSCILLOSCOPE ADAPTER SCHEMATIC. 1C12 selects which of ICU's Inputs gets sent to the output buffer. The resistor network at the output of the buffer establishes 32 discrete voltage steps - two for each channel. 1C14 is a trigger qualifier; its optional. but suggested. Jumper JUl is used to take the qualifier in and out of the circuit.

A trigger must be supplied by the logic system or device being observed. The trigger is needed both to act as a clock for the display counter and to initiate a hori- zontal oscilloscope sweep. The trigger signal is applied to pin II of IC13; sixteen of those trigger pulses are required to generate a complete 16 -trace image on the scope. In complex digital systems, a single signal that can act as a suitable trigger is not always available -you may need an optional trigger qualifier so that you can create an acceptable trigger. A qualifier gate, such as what is shown for ICI4, can be used. We recommend that you add such a qualifier gate along with a provi- sion to enable it simply by the insertion of a jumper.

Switch S17 is an optional zero-refer- ence switch. It is used to place a low logic -level on the least- significant input leg of the converter. When the switch is closed, the scope will display the 16 base lines. By momentarily closing the switch, you can quickly identify a steady -state channel as steady high or steady low. The switch is also useful in linearity tests.

Construction You probably have enough room left on

your original IC tester board to build the display adapter. Since the wiring or component layout is not critical, practically any construction technique may be used with good results.

There are many possible component substitutions that can be made in the TTL design. For example, the counter does not have to be a 74LS191: It can be another kind of synchronous counter like the 74LSI63 or the 74LSI93. Or it may be a

standard (as opposed to low -power Schot- tky) TTL counter like the 74191. If substitutions are made, be sure to check the pinout of the new IC and document the changes where necessary. The use of rip- ple counters such as the 7493 is not recommended in this circuit -they tend to introduce excessive channel- switching transients. The 7406 may be substituted by other open- collector hex inverters including the 7416, and the 7405.

One final construction note: Assuming that you are building the circuit as an expansion of the IC tester, each display channel should be connected to its corresponding pin on the test socket. In other words, channel I should display the signal on pin I of test socket SOI and so on. That makes using the analyzer easier.

Using the display adapter For illustration purposes, let's set up

the IC tester so that we can examine the waveshapes associated with the 74LS138 one -of -eight decoder. Table 2 lists the proper stimulus patterns. The trigger should be jumpered from the stimulus latch side of the isolation switch for pin 8

to pin 11 of IC13 in Fig. 7, and the scope should be set to trigger from the positive edge of an external signal. Isolation switches SI S6 should be closed, and switches S7 S16 should be open.

Notice that the first two stimulus patterns will send a clock pulse to the display counter and trigger the oscilloscope, re- spectively. As shown in Fig. 8, the counter counts on the leading edge of the trigger pulse and the display begins on the trailing edge. That eliminates the channel- switching lines and lets us see a clean display.

Program your host computer to generate the looping stimulus patterns in Table 2 and run the test on a 74LSI38. Connect the oscilloscope test leads to the adapter and, with the test running, we are ready to observe digital waveforms.

Set the vertical- sensitivity control to I

TABLE 2

STIMULUS COMMENT (HEX)

0020 Trigger low. count counter 00A0 Trigger high, trigger scope 00A1 00A2 00A3 Test patterns 00A4 00A5 00A6 00A7

Loop back to first stimulus

volt/division and set the timebase to the fastest sweep. The exact sweep speed required for observation will depend on the speed at which the host system emits stimuli. Decrease the sweep speed and carefully observe the counting stimuli on channels one, two, and three, to determine when the proper speed is found. (It will probably be necessary to decalibrate the timebase to display the entire interval between triggers.) If the display shows four or eight traces with connecting steps, then the sweep is too slow but is close to the correct speed. If the display resembles multiple downward staircase waveforms, then the sweep is far too slow. Once the timebase is adjusted, the vertical sensitivity can be adjusted (and decalibrated) so that the sixteen channels cover the entire face of the scope, giving maximum channel separation. The display should resemble that shown in Fig. 9.

(continued on page III)

Loop back to first stimulus

Trigger low, count counterTrigger high. trigger scope

Test patterns

TABLE 2

COMMENTSTIMULUS(HEX)

002000A000A1OOA2OOA300A4OOA500A6OOA7

volt/division and set the timebase to thefastest sweep. The exact sweep speed re-quired for observation will depend on thespeed at which the host system emitsstimuli. Decrease the sweep speed andcarefully observe the counting stimuli onchannels one, two; and three , to deter-mine when the proper speed is found.(Itwill probably be necessary to decalibratethe timebase to display the entire intervalbetween triggers.)If the display showsfour or eight traces withconnectingsteps,then the sweep is too slow but is close tothe correct speed . If the display resemble smultiple downward staircase waveforms,then the sweep is far too slow. Once thetimebaseis adjusted , the vertical sen-sitivity can be adjusted (anddecalibrated)so that the sixteen channe ls cover the en-tire face of the scope, giving maximumchannel separatio n. The display shouldresemble that shown in Fig. 9.

(continued on page 111)

Using the display adapterFor illustration purposes, let' s set up

the IC tester so that we can examine thewaveshapes associated with the 74LSI38one-of-eight decoder. Table 2 lists thepro per stimulus patterns. The triggershould be ju mpered from the stimuluslatch side of the isolation switch for pin 8to pin II of ICl3 in Fig. 7, and the scopeshould be set to trigger from the positiveedge of an external signal. Isolationswi tches SI-S6 should be closed , andswitches S7-S16 should be open.

Notice that the first two stimulus pat-terns will send a clock pulse to the displaycounter and trigger the oscilloscope , re-spectively. As shown in Fig. 8, the coun-ter counts on the leading edge of thetrigger pulse and the display begins on thetrailing edge . That eliminates the chan-nel-switching lines and lets us see a cleandisplay.

Program your host computer to gener-ate the looping stimulus patterns in Table2 and run the test on a 74LS138. Connectthe osci lloscope test leads to the adapterand, with the test running , we are ready toobserve digital waveforms.

Set the vertical-sensitivity control to I

R343K

R422K

R511K

R72.7K

R65.6K

OUTPUT TOSCO PE

SC OPE·TRIGGEROUTPUT

Cl K 14

+5V

16

+5V

11

13

your original IC tester board to build thedisplay adapter. Since the wiring or com-ponent layout is not critical, practicallyany construction technique may be usedwith good results.

There are manypossible componentsubsti tutions that can be made in the TTLdesign. Forexample, the counter does nothave to be a 74LS191: It can be anotherkind of synchro no us counterlike the74LSI63 or the 74LS193. Or it may be astandard (asopposedto low-power Schot-tky) TTL counter like the 74191. If sub-stitutions are made, be sure to check thepinout of the new IC and document thechanges where necessary. The use of rip-ple counters such as the 7493 is not rec-ommended in this circuit-they tend tointroduceexcessivechanne l-switchingtransients. The 7406 may be substitutedby other open-collector hex inverters in-cluding the 7416, and the 7405 .

One final cons tructio n note:Assumingthat you are building the circuit as anexpansion of the IC tester, each displaychannel should be connected to its corre-_sponding pin on the test socket. In other 'words, channel l should display the signalon pin I of test socke t SOI and so on. Thatmakes using the analyzer easier.

3 2 6 7

ｾOUTPUT

'IC1274lS191

-=TRIGGER INPUT

I JUI+5V

TRIGG" {QUALIFIERINPUT

-=

+5V

24

0 ICll

1 74150

2 OUTPUT 10

34

A 155

INPUTS 6(FROM 7 OATA 14TEST 8 INPUTS BSOCKET)

9 OATASELECT

10 C13

111213 0

11

1415

Constructio nYouprobably have enough room left on

FIG. 7-0SCILLOSCOPE ADAPTER SCHEMATIC. IC12selects which of IC11'sInputs gets sent to theoutput buffer. The resistor network at the output of the buffer establishes 32 discrete voltage steps-two for each channel. IC14is a trigger qualifier; it's optional, but suggested. Jumper JU1 is used to takethe qualifier in and out of the circuit.

A triggermust be supplied by the logicsystem or device. being observe d. Thetrigger is needed both to act as a clock forthe display counter and to initiate a hori-zontal oscilloscopesweep. Thetrigger-signalis applied to pin II of ICl3 ; sixteenof those trigger pulses are required to gen-erate a complete l6-trace image on thescope . In complex digital systems, a sin-gle signal that can act as a suitable triggeris not always available-you may need anoptional trigger qualifier so that you cancreate anacceptable trigger. A qualifiergate , such as what is shown for ICI4, canbe used . We recommend that you addsuch a qualifier gate along with a provi-sion to enable it simply by the insertion ofa jumper.

Switc h S17 is an optional zero-refer-ence switch. It is used to place a lowlogic-level on the least-significant inputleg of the converter. When the switch isclosed, the scope will display the 16 baselines. By momentari ly closing the switch,you canquickly ident ify a steady-statechannel as steady high or steady low. Theswitch is also useful in linearity tests.

(f)oZoa:ow-.JW

oo-ca:

86



DIGITAL IC TESTER

continued from page 86

You can use the display adapter to view signals that originate outside of the tester. With the test socket empty and the poWCr supply jumpers removed, open the isolation switches and jumper the system sig-

TRIGGER INPUT

CHANNEL

,i QNE CHANNEL CYCLE

SWITCHING i I

1 1

INTERVAL

DISPLAY I i

COUNTER IIC12) INPUT I I I t

I DISPLAY I

CYCLE FIG S -THE COUNTER COUNTS on the leading odge of a logic trigger. but the scope triggers on the trailing edge. That eliminates the channel - switching lines from the display.

PARTS LIST

All resistors are ta -watt, 5 °e R3- 43.000 ohms R4- 22.000 ohms R5- 11.000 ohms R6 -5600 ohms R7 -2700 ohms R8- R12 - -330 ohms R13 -1500 ohms Semiconductors ICI1 -74150 1 -of -16 selector multiplexer IC12-74LS191 binary synchronous up

down counter IC13 -7406 hex inverting buffer IC14 -7420 dual 4 -input NAND gate Other components S17 --SPST switch

should be evenly spaced. and all displayed signals should repeat themselves exactly between triggers. Thc qualifier can be useful in dealing with complex systems, but proper qualification hinges on your

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a oft

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For Home or Business WHAT WHEN .. HOW

ruts. f -u nC VJtrIIL J ..tJP'C Vt.JrLA1 snowing me wayetorms generate° oy the / %Lola* test circuit. While it may not be the most eloquent logic analyzer, It can be an excellent teaching or learning tool.

nal(s) to the test socket pin(s). Bring in a

suitable trigger. crank up the system. and you are ready to observe the chosen signals and their relationship to each other. Be aware that the displayed signals are now driving the additional load presented by the circuitry connected to the test socket -that includes the output drivers, the multi -channel adapter, and. perhaps, additional expansion hardware. System signals that are heavily loaded might not be able to drive that additional load.

The selection or generation of a trigger is most crucial in creating a stable and meaningful display. The trigger pulses

familiarity with the logic system. In general. under -qualified triggers tend to create brilliant but jittery displays. On the other hand. over -qualified triggers yield diminished or even non -existent displays.

In situations where trigger selection is relatively simple. the multi -channel adapter can become a tutorial aid. You can learn a lot by observing signals in a properly operating digital device. As you continue to use the adapter and really get a

good "feel" for it. you will probably find many additional uses for the adapter. We'll find even more uses for the IC tester when we continue. R -E

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_1 111

FIG.9-THE OSCILLOSCOPE DISPLAY showing the waveforms generated by the 74LS138test circuit.While it may not be the most eloqu ent logic analyzer, it can be an excellent teaching or learning tool.

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oodOJm:IJ

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PARTS LIST

All resistors are V.-watt, 5%R3-43.000 ohmsR4- 22,OOOohmsR5-11.000 ohmsR6-5600 ohmsR7- 2700 ohmsR8-R12- 330 ohmsR13-1500 ohmsSemiconductorsIC11-74150 1-01·16 selector/multiplexerIC1 2- 74LS191 binary synchronous up/

down counterIC13-7406 hex inverting bufferIC14-7420 dual 4-input NAND gateOther componentsS17- SPST switch

should be evenly spaced, and all displayed.signals should repeat themselves exactlybetween triggers. The qualifier can beuseful in dealing with complex systems,but proper qualification hinges on your

familiarity with the logic system. In gen-era l, under- qual if ied tri ggers tend tocreatebrilliant but jittery disp lays. On theother hand , over-qua lified triggers yielddim inished or even non-existent disp lays.

In situations where trigger selec tion isre lat ive ly simple, the multi-channeladapter can become a tutor ial aid. You canlearn a lot byobservingsignals in a prop-erly operatingdigital device. As you con-tinue to use theadapterand really get agood"feel" for it, you will probably findmany additional uses for the adapter.We'll find even more uses for the Ie testerwhen we continue. R-E

nal(s) to the testsocketpin(s). Bring in asuitab le trigger, crank up the system, andyou are ready toobservethe chosen sig-nals and their relationship to eachother.Be aware that the displayed signals arenow driving the additional load presentedby the circuitry connected to the test sock-et- that includes the output drivers, themulti-channel adapter, and ,perhaps, ad-ditional expansion hardware. System sig-nals that are heavily loaded might not beable to drive that addi tiona l load.

The selec tion or generation of a triggeris most cruc ial in creating a stable andmeaningful display. Thetrigger pulses

DICITAL rc TESTERcontinued from page 86

I 9NE CHANNELI I CYCLE I

TRIGG ER :.: -I I

ｉｎｐｕｔｾｾCHANNEL --.l ｾ I ISWITCHING I I I I

INTERVAL ｾｲＭＭＮｲｌ

DISPLAY I I I ICO UNTER I I I I

ocm INPUT I I I I

I I'" DISPLAYED - I ICYCLE

FIG. 8-THE COUNTERCOUNTS on the leadingedge of a logic trigger, but the scope triggers onthe trailing edge. That eliminates the channel-switching lines from the display.

You can use the displayadapterto viewsigna ls that originate outside of the tester.With the test socket empty and the power 'supply jumpers removed, open the isola-tion switches and jumper the system sig-



: - . - ---- F. - _ >11l1

::. :t,:.:: :. .: .. 1," .; . t . ::-:: r i ;`` O _ tr :y.'i:; . q` . ̀ >.

F r te FLOYD L. OATS

coø'P"1; We've already seen that the IC tester we've been building can be used for more than just testing digital ICs. This month we'll add an EPROM programmer.

Part 3 IN THE FIRST TWO parts of this article,

we looked at a circuit that could be used - along with your computer -to test digital IC's. We then added a low- budget logic analyzer to the tester: It worked by allow- ing you to view 16 digital signals on a

single -trace oscilloscope. This month, we'll expand the circuit even further by lidding EPROM- programming capability.

Before we go on, we should add some cautions: The circuit was designed to be used with an S -I00 bus computer. With modifications, it can be used with essen- tially any computer. In either case, some programming experience is essential: While the software that is required is de- scribed, the actual, complete programs are not presented.

EPROM programmer the digital IC tester -along with your

computer -can be used to program and verify virtually any 24 -pin member of the

2700 EPROM family. That includes everything from the original 2704/2708 through and including the 2732. Al- though the circuit can be modified to program 28 -pin devices such as the 2764, we will not cover that here.

Figure 10 shows the pinouts for some of the various styles of 24 -pin EPROM's. You'll want to refer to it as we talk about the different types of EPROM's available. We should add one more caution, though: Before you try to program any EPROM, make sure you have the manufacturer's data sheets. Pinouts, voltage requirements, and programming sequences can vary from one manufacturer to another, and from older devices to newer ones. Double checking is the safest and surest way to avoid problems.

Before we can discuss the EPROM programmer circuit, we have to know what we want it to do. So let's first consider how the 2708 -a typical three -supply EPROM -is programmed. (Note that

when we say "three- supply" or "single - supply." we are referring to the number of power supplies required for READ operation -we do not include the programming- voltage supply.)

To program the 2708, its Z/wF pin is brought to + 12 volts and is held at that voltage throughout the programming operation. (That causes the eight data lines to become input -data lines). An EPROM address, and the data to be stored in that address, are then presented to the EPROM. Both the address and data lines must be held in their valid state while a

program pulse is applied to the program pin.

That + 25 -volt program pulse has a

pulse width between 100 microseconds and I millisecond. After the pulse is terminated, the next (sequential) address, along with the contents to be stored there, are sent to the EPROM and another program pulse is issued. After all addresses have been pulsed, we say we have corn-

65

FLOYD L. OATS

We've already seen that the Ie tester we've been building can be used for more than justtesting digitaIIC's. This month we'll add an EPROM programmer.

Part 3 IN THE FIRST TWO

parts of this article,we looked at a circuit that could be used-along with yourcomputer-to test digitalIC's. We then added a 'low-budget logicanalyzer to the tester:It worked by allow-ing you to view 16 digital signals on asingle-traceoscilloscope.This month,we'll expand the circuit even further byaddingEPROM-programmingcapability.

Before we go on , we should add somecautions: The circuit was designed to beused with an S-100 bus computer. Withmodifications, it can be used with essen-tially any computer. In either case, someprogrammingexperienceis essential:While the software that is required is de-scribed, the actual , complete programsare not presented.

EPROM programmerThe digital ICtester-alongwith your

computer-canbe used to program andverify virtually any 24-pin member of the

2700 EPROM family. That includes ev-erything from the original 2704 /2708through and including the 2732. Al-though the circuit can be modified to pro-gram 28-pin devices such as the 2764,Wf;

will not cover that here .Figure 10shows the pinouts for some of

the various styles of 24-pin EPROM's .You'll want to refer to it as we talk aboutthe different types of EPROM's available.We should add one more caution, though:Before you try to program any EPROM,make sure you have the manufacturer'sdata sheets. Pinouts, voltage require-ments, and programming sequences canvary from one manufacturer to another,and from older devices to newer ones.Double checking is the safest and surestway to avoid problems .

Before we can discuss the EPROM pro-grammer circuit , we have to know whatwe want it to do. So let's first considerhow the 2708-a typical three-supplyEPROM-is programmed. (Note that

when we say"three-supply"or "single-supply," we are referring to the number ofpower supplies required for READ

operation-wedo not include the-pro-gramming-voltage supply.)

To program the 2708, itsCSIWE pin isbrought to + 12 volts and is held at thatvoltage throughout the programming op-eration. (That causes the eight data linesto become input-data lines). An EPROMaddress, and the data to be stored in thataddress,are then presentedto theEPROM. Both the address and data linesmust be held in their valid state while aprogram pulse is applied to the programpin.

That +25-volt program pulse has apulse width between 100 microsecondsand 1 millisecond . After the pulse is ter-minated, the next (sequential) address,along with the contents to be stored there,are sent to the EPROM and another pro-gram pulse is issued. After all-addresseshave been pulsed, we say we' have com-

zｾms::OJmJJ

65



66

20 21 PIN 18 19 22 24 ,TYP

2704 2708 2758 2716 2732

PROGRAM PROGRAM

CIJIPGMI CF /IPGMI CE /IPGM)

V0D D

All All

gl/WE

äF E

in UT/VN

vee

v B

vK All

vu AS

AS

A9 A9

Vcc

vcc vcc vcc vcc

FIG. 10-PIN FUNCTIONS VARY from one type of EPROM to another. Wh'le you can use this as a guide, make sure you have the manufacturer's data sheet for any EPROM you want to program.

pleted a single pass. It is necessary to make enough passes

to bring the total program -pulse time to at least 100 milliseconds per address. That means that if your pulse width is, say, 500 microseconds. then at least two hundred passes must be made.

The 2708 is only one kind of EPROM -a three -supply type. Now we'll look at the programming procedure for a

typical single -supply EPROM: the 2716. To enter the 2716's programming

mode, pin 20. the output -enable pin (M. pin 18) is brought to + 5 volts. and the programming -voltage pin (VPP, pin 21) is brought to + 25 volts. The address and corresponding data are presented to the IC and held valid while a fifty- millisecond high -level TTL pulse is sent to the ZTJP(;M pin. (Note that, as opposed to the 2708, we program with a TTL -level pulse -the programming voltage applied to pin 21

remains constant at 25 volts. We should note. however, that the programming voltage can be switched. if desired.)

Only a single pulse is required to com- pletely program a location. Unlike the 2708. sequential addressing is not necessary and only the addresses being written need be pulsed. Therefore, since all of the address locations in new (or erased) EPROM's are set to I, to program a 2716, only the addresses that need to be changed to zero bits are "burned in." Those addresses that need to be set to one are

programmed by simply passing over the location.

The EPROM -programmer circuit Because the EPROM programmer

(whose schematic is shown in Fig. 11) is being built as an add -on to the digital IC tester, we have to map up to four kilobytes of EPROM address into 256 memory- mapped locations. (You will recall that the IC tester uses eight address lines to carry stimulus information and thus oc- cupies 256 memory locations.)

We overcome that problem by using a

D -type flip -flop (IC15) to store the most - significant bits of the EPROM address. and by implementing a three -phase program/verify cycle (which we'll describe in more detail shortly). When we combine IC15 with the sixteen stimulus latches (ICI -IC4), we obtain thirteen address lines and eight data lines. That's enough to accommodate up to 8K of EPROM space.

The three -phase cycle is shown in Fig. 12. In the first phase. enabled by A5 being high. the EPROM upper address (As -Al2) is loaded into IC15. In the second phase, the eight least- significant address bits (Ao--Al) along with eight data bits (Dß --Ds) are loaded into the stimulus latches (ICI -IC4. Fig. 2)) and a "burn" interval is initiated. In the third phase, the burn interval is terminated and the programmer is restored to its idle state (which is de-

fined as both of the flip -flops in IC16 being reset).

Referring back to Fig. 11 (and to fig. 3 in Part I), you'll notice that five of the upper stimulus latches (Ao A4) are fed to IC15. The A5 latch is sent to pin 1 of IC17. The STIMULUS WAD signal is inverted to an active -low pulse by IC17 -f and then applied to both flip -flops of IC16 as a

clock. Assume the programmer to be in the

idle state, awaiting a phase -one load. If A5

is high (X3 low), pin 2 of ICI6 is con- ditioned to set one of its flip -flops on the trailing edge of the stimulus -load pulse. (We'll call that flip -flop. ICI6 -a, the LOAD flip -flop.) When the WAD flip -flop sets. it will clock pin nine of ICI5, thereby cap- turing the EPROM upper address. The LOAD flip -flop primes the second flip -flop of IC16 to set and, through IC17 -b, condi- tions its own reset. (We'll call the second flip -flop. ICI6 -b, the rn-P flip -flop for TTL Pulse.)

The second phase starts with the next stimulus load pulse, which will now reset the LOAD flip -flop and set the second (rrt.P) flip -flop to initiate the burn interval (see Fig. 12). rrt-P activates the program/ verify controls and also maintains a low into the LOAD flip -flop through IC17 -e.

The LOAD flip -flop being reset causes the i-TIP flip -flop to reset on the next stimulus load (phase three). The burn interval is terminated and the turned to its idle state. We should note that IC15 still retains the bits captured during phase one.

During a program cycle. the TTLP flip - flop supplies a TTL pulse for programming those EPROM's that require only a

TTL -level pulse. The signal also controls the high -voltage pulse needed by many EPROM's. For example, the TTLP signal controls the base of QI through IC17 -c and lCl7 -d. Transistor QI controls VPP, the programming voltage. When QI is turned on, it will drop about two volts and pass the remaining 26 volts to the EPROM. When pin 6 of lC3 is low, diode D3 returns the program pin to ground. Capacitor C4 limits the overshoot on the emitter of QI to acceptable levels.

Switch S24 is useful in testing and troubleshooting QI and associated circuitry- when closed, it will hold VPP high without regard to the state of rttP.

Closing switch S25 will uncondi- tionally hold the programmer in the idle state thereby disabling the entire circuit. A quick -arming power -on reset function is provided by CI, R15, and R16.

Personality module As shown in Fig. 11, the signals and

voltages developed are sent to the EPROM socket (SO5) through a switching and distribution network (S18 -S24, and SO4). Socket SO4, the personality module socket, accepts a personality

FIG.1Q-PIN FUNCTIONS VARYfrom one type of EPROMto another. While you can use this as a guide,make sure you have the manufacturer's data sheet for any EPROM you want to program.

ｔｙｾ lB 19 20 21 22 24

2704 PROGRAM VOO CS,wE Vaa Vss Vee2708 PROGRAM Voo Cs,wE Vaa A9 Vee275B Cl:/(PGM) AR or Vpp A9 Vee2716 CE/(PGM) Ala or Vpp A9 Vee2732 U /(PGM) Ala O1/Vpp Al l A9 Vee

24A7 SEE TABLE

2 23

A6 AB3 22

A5

4 21A4

20A3 SEE TABLE

6 19A2

18Al

8 17AO 07

16DO 06

10 15

01 0511 14

02 0412 13

VSS(GNO) 03

enoZoa:I-oW....IW

6is-ca:

66

pieted a singlepass.It is necessary to make enough passes

to bring the totalprogram-pulsetime to atleast 100 milliseconds per address. Thatmeans that if your pulse width is, say, 500microseconds , then at least two hundredpasses must be made .

The 2708 is only one kind ofEPROM-athree-supplytype. Now we'lllook at theprogrammingprocedure for atypical single-supply EPROM : the 2716.

To enter the 2716's programmingmode, pin 20, theoutput-enablepin (OE,pin 18) is brought to+5 volts, and theprogramming-voltage pin (Vpp, pin 21) isbrought to +25 volts. The address andcorresponding data are presented to the ICand held valid while a fifty-millisecondhigh-level TTL pulse is sent to theCElPGM

pin. (Note that , as opposed to the 2708,we program with a TTL-level pulse-theprogramming voltage applied to pin 21remains constant at 25 volts. We shouldnote, however, that the programming volt-agecan be switched, if desired .)

Only a single pulse is required to com-pletely program a location. Unlike the2708, sequential addressing is not neces-sary and only the addresses being writtenneed be pulsed. Therefore , since all of theaddress locations in new (or erase d)EPROM's are set to I, to program a 2716,only the addresses that need to be changedto zero bits are " burned in." Those ad-dresses that need to be set to one are

programmedby simply passing over thelocation.

The EPROM-programmer circuitBec ause theEPROM programmer

(whose schematic is shown in Fig.11) isbeing built as an add-on to the digital ICtester, we have to map up to four kilobytes .of EPROM addressinto 256 memory-mapped location s. (You will recall thatthe IC tester uses eight address lines tocarry stimulus information and thus oc-cupies 256 memory locations.)

We overcome that problem by using aD-type flip-flop (ICl 5) to store the most-significant bits of the EPROM address,and by implement ing a three-phase pro-gram/verify cycle (which we'll describein more detail shortly). When wecombineIC15 with the sixteen stimulus latches(lCI-IC4), we obtain thirteen addre sslines and eight data lines. That's enoughto accommodate up to 8K of EPROMspace .

The three-phase cycle is shown in Fig.12. In the first phase , enabled byAS beinghigh, the EPROM upper address(AS-AIZ)

is loaded into ICI5 . In the second phase,the eight least-signi ficant address bits(A 0-A7) along with eight data bits(D0-DS)

are loaded into the stimulus latches(ICI-IC4, Fig. 2)) and a"bum" intervalis initiated . In the third phase, the buminterval isterminatedand theprogrammeris restored to its idle state (which is de-

fined as both of the flip-flops in ICI6being reset).

Referring back to Fig.11 (and to Fig. 3in Part I), you' ll notice that five of theupper stimulus latches(AD-A4) are fed toICl5 . TheAS latch is sent to pin 1ofI Cl7.The STIMULUS LOAD signal is inverted toan active-low pulse byICl7-f and thenapplied to both flip-flops of IC16 as aclock.

Assume theprogrammerto be in theidle state, awaiting a phase-one load. IfAS

is high (AS low), pin 2 of IC16 is con-ditioned to set one of its flip-flops on thetrailing edge of the stimulus-load pulse.(We' ll call that flip-flop,ICI6-a, theLOAD

flip-flop.) When theLOAD flip-flop sets, itwill clock pin nine of IC15, thereby cap-turing the EPROM upper address. TheLOAD flip-flop primes the second flip-flopofIC16to set and , throughICl7-b, condi-tions its own reset. (We'll call the secondflip-flop, ICI6-b, the TTLP flip-flop forITL Pulse.)

The second phase starts with the nextstimulus load pulse, which will now resetthe LOAD flip-flop and set thesecond(TTLP) flip-flop to initiate the bum interval(see Fig. 12).TTLP activates the program/verify controls and also maintains alowinto the LOAD flip-flop through ICl7-e.

The LOAD flip-flop being reset causestheTTLP flip-flop to reset on the next stim-ulus load (phase three). The bum intervalis terminated and theprogrammeris re-turned to its idle state. Weshould note thatICI5 still retains the bits captured duringphase one .

During a program cycle, theTTLP flip-flop supplies a TTL pulse for program-ming those EPROM's that require only aTTL-level pulse. The signal also controlsthe high-voltage pulse needed by manyEPROM's. For example, theTTLP signalcontrols the base of QI throughICl7-cand ICl7-d. TransistorQl controls VPI"

the programming voltage. When Ql isturned on, it will drop about two volts andpass the remaining 26 volts to theEPROM. When pin 6ofIC3 is low, diodeD3 returns the program pin to ground.Capacitor C4 limits the overshoot on theemitter of QI toacceptablelevels.

Switch S24 is useful in testing and trou-bleshooting QI and associatedcircuitry-when closed, it will hold VPP high with-out regard to the state ofTTLP.

Closing switch S25 will uncondi-tionally hold theprogrammerin the idlestate thereby disabling the entire circuit.A quick-armingpower-on reset functionis provided by CI , R15, and R16.

Personality moduleAs shown in Fig. 11, the signals and

voltages developedare sent to theEPROM socket(S05) through a switch-ing and distribution network(SI8-S24,and S04). SocketS04, the personalitymodule socket, acceptsa personality



INPUTS FROM

IC TESTER

No A70

1

i S

] 11

o

10

f

7

i_o

Mo

A20

A20

At

No - ST MULOS LOAO

!ISO-

'SEE TEXT

13

tl

]

.SV

10

CLEAR Vrç

Dl 01

04 0 Ol IC1 of

71515 7 03 07

0, 0,

ONO CLR T f

2 Al2

° (PII OM

o TEST 2

n °

10 All

7 Alf

{ N

2 Al

1/6 014 SV to

1C17 to VA

ICIO 14 IQ74lf74

TTLP

C2 20r67 ]SV

OS 104742

-1{V

PIS Non 1/7 Vs

C1

1071 33V

0 104733

2

2

o o 12

{v

104 t2

PERSONALITY NODULE

o o o

0

SIN 014 CS

1117 2.75 ] 35 n 700 2.7R nV VN y

1{740{

Iv

FIG. 11 -EPROM PROGRAMMER SCHEMATIC. Note that some EPROM's require a 21 -volt (instead of 25-26 volt) programming voltage. When programming such devices, you can either use a variable power -supply. or you can substitute a voltage divider (or trimmer potentiometer) for R21.

STIMULUS LOAD

STROBE

ONE PROGRAMIVERIFY CYCLE

2

5 IC17[

ISMS

12V

SV

V44

VA,. 21V

03 111114

C 021 344 10R

Cher a program or verify function. The personalitymodule outputs (pins

I -5) feed what may be termed the "variable" EPROM pins. Figure 13 defines the personality module and the program/verify configuration needed for each EPROM. We'll discuss those configurations in more detail later.

VALID, Construction It is recommended -but not essen-

Icxx tial -that the programmer be built on the PIN 5 r tom- same board with the IC tester. Component

placement, general signal routing, and

Icxx construction method are not critical and PINS INTERVAL

t____ are therefore left to your discretion. Don't forget that the EPROM programmer needs an external source of + 28 volts at

1 2 3 about 100 mA. (A variable power supply FIG. 12 -THE THREE -PHASE cycle required to program or verify a single EPROM address. The is preferred.) program or verily function Is selected by the programmer's switches. (See Fig. 13.) Most of the signal connections to the IC

tester can be seen in Fig. 11. The EPROM module that is custom made for each style appropriate jumpers. We'll get to the spe- socket data -lines are connected to the iso- of EPROM. (The personality module can cifics of the jumpers shortly.) The switch- lation side (test -socket side) of the isola- be made on a DIP header, and consists of es (SI8 -S23) are configured to select ei- tion switches so that they may be

67

111 +16V

ＺＺｾ ! RIBlOon

14 ln W13 +12V11 i C3 l-'0510 I 2O"F'35V lN47429B ";"

76

0-12

5 ｾ- 16V

4 S05

3 EPROM R19TEST 390n

2 112W

1 5V

23 ｾｃＲ22 12O"F' ｾｾｾＴＷＳＳl B

+ 35V

ｾ '?";"

19

1

20 21 24+12V

-5V ｾｾｊｾｾｾ +5V

ｾｾ0- 15 S19/"o---l

4 +12V V,*5 bJ6 0-

713

S21 Vpp

...! --o +5V +!iV

S04 0-W Wc-1PERSONALI TY

ｾｾMODULE

11

ｾ｜ＱVpp ' 25V

ｓＸＰｾＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＭＬ

H LP

HLP

'S EETEXT R112.7K

R152.7K

S25

i C5

I 20"F'35V

+5V

FIG. 11-EPROM PROGRAMMER SCHEMATIC. Note that some EPROM's require a 21-volt (instead of2&-26 volt) programming voltage. When programming such devices, you can either use a variablepower-supply, or you can substitute a voltage divider (or trimmer potentiometer) for R21 .

ｾＭＭＭＭＭＭｏｎｅ PROGRAM/VERIFY CYCLE - - - - .

STIMULUSLOAO

ther a program or verify function .The personality-module outputs (pins

1-5) feed what may be termed the " varia-ble" EPROM pins. Figure 13 defines thepersonality module and the program/ver-ify configuration needed for eachEPROM. We'll discuss those configura-tions in more detail later.

1 2 3FIG. 12-THE THREE-PHASE cyc le required to program or verify a sing le EPROM address. Theprogram or verify function is selected by the programmer's switches. (See Fig. 13.)

r---i 1 ｾ______________---ll--- BURN ｾ＾ＭＮＮＮＮＮＮＡＮＭ

INTERVAL . .-----

zｾms::OJmJJ

ConstructionIt is recommended-butnot essen-

tial-that theprogrammerbe built on thesame board with the IC tester.Componentplacement, general signal rout ing , andconstructionmethod are not critical andare therefore left to your discretion. Don'tforge t that the EPROM programmerneeds an external source of+28 volts atabout 100 rnA. (A variable power supplyis preferred .)

Mostofthesignal connections to the ICtester can be seen in Fig. II. The EPROMsocket datalines areconnectedto the iso-lation side (test-socket side) of the isola-tion switches sothat they may be

II---ii'----....,....---lll--

appropriatejumpers. We'll get to the spe-cifics of thejumpers shortly.) The switch-es (SI8-S23)are configured to select ei-

-VALID-

ICXX -.,..__PIN 5

ICXXPINg

module that is custom made for each styleof EPROM. (The personality module canbe made on a DIP header, and consists of

67



68

PARTS LIST

All resistors are -watt. 5 °° unless stated otherwise

R14 -1000 ohms R15. R17 -2700 ohms R16 -3300 ohms R18 -100 ohms, watt R19 -390 ohms, ', watt R20 -5600 ohms R21- 10,000 ohms Capacitors C2, C3. C5-20 F. 35 volts. electrolytic C4-33 pF. ceramic disc Semiconductors IC15- 74LS174 hex 0 -type flip -flop IC16- 74LS74 dual D -type flip -flop IC17 -7406 hex inverting buffer driver IC18- 74LS367 hex bus driver Q1- 2N3904 D3-1N914 D4-1N4733 D5- 1N4742 LED1- standard green LED LED2- standard red LED Other components S18-25 -SPST switch (DIP switches pre-

ferred) Miscellaneous: IC sockets, jumper

header, etc.

connected to the stimulus latches for programming or disconnected for program verifying. The least- significant address bits. AO through A7. are connected to the most -significant byte of the stimulus latches and five of those (AG-A4), also go to IC15. The address lines are connected directly to the latches.

The personalitymodule socket (SO4) will accept a 16 -pin header plug, which must be pre-wired for a particular type of EPROM (according to the data shown in Fig. 13.) As an example. consider the 2732 entry in that figure: Pin one is wired to pin twelve, pin two to pin eleven, pin three to pin thirteen. etc. Once you install

the jumpers on the header, label it "2732." If you can manage, you might want to squeeze the switch settings for pmgram /verify selection on the label.

Diagnostic indicator Figure 14 shows an option you can add

to the programmer to give both a visual and a software indication of the programmer's current phase. It can be very helpful for debugging and troubleshooting, and can be used by software to continuously monitor the state of the programmer for self -diagnostic purposes

When a signal is active, its line to the test socket is low and the corresponding LED is illuminated. The host system may determine the current phase by simply reading the test socket and examining pins 9 and 10.(If you use this option, the isolation switches for test socket pins 9 and IO

will have to be open while the programmer is in use. Switch S25 must be closed when the programmer is not in use.)

Testing the programmer Preliminary tests designed to check out

the wiring and logic of the programmer are made with the EPROM socket empty and the 28 -volt supply removed. Set up the IC tester with the test socket vacant, the power- supply jumpers removed, isolation switches for pins 9 and 10 open, and all other isolation switches closed. Open all eight of the programmer's switches (S18 -S25) and, if practical, power the device up and down several times and verify that the power -on reset forces the idle condition.

All stimulus patterns can be viewed in terms of test -socket pins since. from the standpoint of the host computer, the ex- panded tester still appears as merely a 16-

pin test socket. Referring to figure 15, the first stimulus pattern of the three -phase

EPROM TYPE

PERSONALITY MODULE JUMPERS PROGRAM VERIFY

VERIFY PROCEDURE

2704. 2708 1 - 12 S18 S20 V1 OR V2

2 - 16 S21 S23

3 -15 4 -14 5 -13

2758 1 - 12 S19 S20

2 - 13 S21 S21 V1

3 - 15 S24 S24 4 -10 s -7

2716 1 - 12 S19 S20

2 - 13 S21 S21 V1 OR V2

3 - 15 S24

5 -7 5 - 10'

2732 1 - 12 S21 S23

3 - 13 S24 V2

2732A 5 - 10

ï OU MAY WANT TO ADD A SWITCH TO AVOID CHANGING JUMPERS

FIG. 13- PERSONALITY MODULE AND SWITCH configurations for various EPROM's. See the text for more information on verify procedures VI (load. load, load, read) and V2 (load. load. read. load).

LOAD FROM IC16, PIN6

5V

TT LP

FROM IC16, PIN 8

1E01

5V

1.6 74LS3117

LED?

TO TEST

SOCKET

(Sot) PIN 9

/fly

1/6 74LS317

1 E 141S367

TO TEST SOCKET

(S01) PIN 10

FIG. 14 -FOR A VISUAL INDICATION of the programmer's current phase. you can add this diagnostic logic.

program /verify cycle will contain the upper EPROM address on the lines assigned to test -socket pins 9-13. The AS bit must be high to enable this phase -one load, so the line assigned to pin 14 must also be high to enable the address -register (ICI5) load and the phase advance. The second and third patterns are identical and will direct the EPROM lower address to pins 9 -16 and data to be programmed to pins I -8. Although many of the patterns may never actually reach the test socket. the host computer will "think" that an IC is being tested.

We can begin by testing the phase -advance logic. Using a stimulus with the AS

bit high. send the pattern repeatedly and check for the phases to progress according to Fig. 15. Starting in the idle condition. send the same stimulus once more and then change the pattern so that As is low. Send this new pattern ten or twelve times and observe that the phase is properly advanced to the idle state but the new pattern is not able to cause any further activity. It should he apparent that the issuance of two or more consecutive stimuli with AS low will guarantee that the programmer goes to the idle state. The software can use that principle to implement a "restore" function.

For the remaining tests. you will need to insert a personality module for a 4K EPROM and set up the DIP switches to program. Make sure the switches agree with the personalitymodule style (see Fig. 13) and leave the EPROM socket empty. Send stimuli which will load various bit patterns into the address register and check the appropriate bits on the EPROM socket itself. Make the phase - two and -three bit patterns different from the first to be certain that the upper address bits are captured only during phase

'YOU MA Y WANT TOADD A SWITCH TOAVOID CHANG ING JUMPERSFIG. i3-PERSONALITY MODULE AND SWITCHconfigurations for various EPROM's. See the text formore Information on verify procedures Vi (load, load, load, read) and V2 (load, load, read, load).

PERSONALITYMODULE VERIFY

EPROMTYPE JUMPERS PROGRAM VERIFY PROCEDURE

2704,2708 1- 12 S18 S20 VI OR V22 - 16 S21 S233 - 154 - 145 - 13

2758 1-12 S19 S202 - 13 S21 S21 V13 -15 S24 S244 -105 -7

2716 1-12 S19 S202 - 13 S21 S21 VI OR V23 -15 S245 -7

5-10'

2732 1 - 12 S21 S233 - 13 S24 V2

*2732A 5 - 10

.

FIG. i4-FOR A VISUAL INDICATIONof the pro-grammer's current phase, you can add this diag-nostic log ic.

TOTESTSOCKET(S01)PIN 9

1/6 74LS367

+5V - - """": ::..j

TTLPFROMIC16,PI N8 0-------,

program/verify cycle will contain the up-per EPROM address on the lines assignedto test-socket pins 9-13 . TheAS bit mustbe high to enable this phase-one load, sothe line assigned to pin 14 must also behigh to enable the address-register(lCl5)load and the phase advance. The secondand third patterns are identical and willdirect the EPROM lower address to pins9- 16 and data to be programmed to pins1-8. Although many of the patterns maynever actually reach the test socket, thehost computer will" think" that an IC isbeing tested.

We can begin by testing the phase-ad-vance logic. Using a stimulus with theAS

bit high, send the pattern repeatedly andcheck for the phases to progress accordingto Fig. IS. Starting in the idle condition ,send the same stimulus once more andthen change the pattern so thatAS is low.Send this new pattern ten or twelve timesand observe that the phase is properlyadvanced to the idle state but the newpattern is not able to cause any furtheractivity. It should be apparent that theissuance of two or more consecutive stim-uli with AS low will guarantee that theprogrammer goes to the idle state. Thesoftware can use that principle to imple-ment a " restore" function.

For the remaining tests, you will needto insert a personality module for a 4KEPROM and set up the DIP switches toprogram. Make sure the switches agreewith the personal ity-module style (seeFig. 13) and leave the EPROMsocketempty. Send stimuli which will load vari-ous bit patterns into the address registerand check the appropriate bits on theEPROM socket itself. Make the phase-two and -three bit patterns different fromthe first to be certain that the upper ad-dress bits are captured only during phase

LOADFROM ICl6,PIN6

+5V

the jumper s on the header , label it" 2732." If you can manage, you mightwant to squeeze the switch settings forprogram/ver ify selection on the label.

Diagnostic indicatorFigure 14 shows an option you can add

to the programmer to give both a visualand a software indication of the program-mer's current phase.It can be very helpfulfor debugging and troubleshooting, andcan be used by software tocontinuouslymonitor the state of the programmer forself-diagnostic purposes.

When a signal is active, its line to thetest socket is low and the correspondingLED is illuminated. The host system maydetermine the current phase by simplyreading the test socket and examin ing pins9 and 10.(If you use thisoption, the isola-tion switches for test socket pins 9 and 10will have to be open while the program-mer is in use . Switch S25 must be closedwhen the programmeris not in use .)

Testing the programmerPreliminary tests designed to check out

the wiring and logic of the programmerare made with the EPROM socket emptyand the 28-volt supply removed. Set upthe Ie tester with the test socket vacant,the power-supplyjumpersremoved, isola-tion switches for pins 9 and 10 open, andall other isolation switches closed . Openall eight of the programmer's switches(SI8-S25)and , if practical , power the de-vice up and down several times and verifythat the power-on reset forces the idle con-dition .

All stimulus patterns can be viewed interms of test-socket pins since , from thestandpoint of the hostcomputer, the ex-panded tester still appears as merely a 16-pin test socket. Referring to figure IS, thefirst stimulus pattern of the three-phase

PARTS LIST

All resistors are Y4-watt, 5% unlessstated otherwise

Ri 4-1000 ohmsR15, R1 7- 2700 ohmsR16-3300 ohmsRiB-i00 ohms, Y2 wattRi9-390 ohms, Y2 wattR2G-5600 ohmsR2i-i0,OOO ohmsCapacitorsC2, C3, C5-20 fl.F, 35 volts, electrolyticC4-33 pF,ceramic discSemiconductorsICi5-74LS174hex Ootype flip-flopIC16-74LS74 dual Ootype flip-flopICi7-7406 hex inverting butter/driverIC18-74LS367 hex bus driverQi-2N390403--1N9i4D4-1N473305-1N4742LEOi-standard green LEDLE02-standard red LEOOther componentsS18-25-SPST switch (DIPswitchespre-

ferred)Miscellaneous: IC sockets , jumper

header, etc.

connectedto the stimulus latches for pro-gramming or disconnectedfor programverifying . The least-significan t addressbits, AO through A7, are connected to themost-significant byte of the stimuluslatches and five of those(M -A4), also go toICIS. The address lines areconnecteddi-rectiy to the latches.

The personality-modulesocket (S04)will accept a 16-pin header plug, whichmust be pre-wired for aparticulartype ofEPROM (according to the data shown inFig. 13.) As an example ,consider the2732 entry in that figure: Pin one is wiredto pin twelve, pin two to pin eleven, pinthree to pin thirteen, etc. Once you install

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68



ENABLE PHASE-ONE LOAD (A)

EPROM DATA

EPROM ADDRESS (UPPER 5 BITS)

DO

0

02

D3

04

DS

06

D7

Al ¡

A6

AS

Sol TEST

SOCKET

EPROM ADDRESS

A3 (LOWER 8 BITS)

D

FUNCTION STIMULUS PATTERNS

WRITE 56 INTO ADDRESS 398

2300 - PHASE ONE 9856 - PHASE TWO 1

9856 - PHASE THREE I i

,i, 398 = 56

`-TJ WRITE 74

INTO ADDRESS 39A

2300 - PHASE ONE

9A74 - PHASE TWO 9A74 - PHASE THREE

,it 39A . 14 i__.

c

FIG. 15-THE SOFWARE views the programmer as an IC under test. The first pattern sent is assigned to the EPROM lines as shown in a. while the second and third patterns are assigned to the lines shown in b. Sample bit patterns (in hexadecimal form) used to program two EPROM address locations are shown In c.

one. Next, vary the phase -two and -three patterns and check the data and lower - address bits, again on the EPROM socket By testing the bits on the socket, the wiring is checked out as well as the source logic.

For the next test, an 820 -ohm, 2 -watt resistor is needed. (If you don't have that unusual item you can combine four 3300 - ohm 1 -watt resistors in parallel.) In either case, take notice that the resistor(s) will become very warm to the touch.

With the programmer in the idle condition, apply + 28 volts to the collector of Q1 and observe QI's emitter for a voltage near ground potential. Close switch S24. and the emitter should go to about 27 volts. Now connect the resistor, which constitutes a typical load. from the emitter to ground and look for a voltage of 25 or 26 volts. If Q1 has been substituted for. and is dropping four volts or more. the substitution is not acceptable.

Leave S24 closed and the load connected for ten minutes or longer and then open S7. The emitter should return to near ground potential. With switch S7 open. cycle the device through the phases and confirm that transistor QI's emitter is con- trolled by rrt.P.

For the final hardware test. close switch S8 and make sure that the programmer is locked into the idle condition regardless of attempts to cycle it from the host computer. Now, with S8 closed and the EPROM socket empty, make sure the IC tester and any other expansion devices

still function pmperly.

Using the programmer Before you can use the programmer,

you'll have to write some software to control it. A relatively simple (and popular) method is to store the intended EPROM contents in a main memory area and use software to transfer that data to the programmer (while keeping the address and data bits properly distributed and main- taining good program -pulse width).

The program will have to send the proper set of bits to the device during each phase and must control the program pulse width by means of a delay between phase two and phase three. Programming is more complex for the three -supply EPROM's because the source data is transferred to the EPROM a number of times as multiple passes are made. Don't forget that only a single pulse per address is permitted with single -supply EPROM types and the pulse width must be 50 milliseconds, ± 10 %.

Figure 15 may be helpful in determining the address- and data -bit distribution among the three phases. Examples of exact stimuli for programming two locations are shown. Using that figure. you can de- velop software that will create and issue the appropriate patterns. You can leave the delay between phases two and three at a

very low value for now. Check that the programmer is in the idle state when the software is initiated and that the software leaves the programmer in the idle state at

completion. If your program doesn't do that, it is not observing the three -phase cycle requirements.

Once the raw program is developed to your satisfaction, you can work on adjust- ing the pulse width. You can do that easily with the aid of an oscilloscope by simply measuring rrt -P and changing the software delay accordingly.

If you don't have an oscilloscope, use a clock or watch to measure the time it takes to transfer one or two kilobytes. Run the program with the EPROM socket empty. and adjust the software delay until the run time is 100 seconds, ± 3

seconds. The EPROM verify software is easier to

create because there are no delays or multiple passes involved. The three -phase cycle is used to load the addresses. but the data patterns have no significance since the isolation switches to the EPROM data lines will be open during the verify operation.

There are two verify procedures. vt and v2 specified in Fig. 13: In the vt process, the host reads pins I -8 of the test socket during the idle state after having executed the three -phase cycle to load the EPROM address. In the v2 process. the read is performed during phase three, and one more load is done to complete the cycle. Normally, the contents of the EPROM is either read into a main memory area for examination or compared with a memory area to verify the EPROM contents.

When you have the hardware and software debugged, you are ready to test the programmer with an EPROM in the socket and the VPP supply connected. The first thing you'll want to check is that the EPROM is erased. Power the programmer down, insert an EPROM and the associated personality module, set up the DIP switches for verify (using Fig. 13), and open the isolation switches for test socket pins one through eight. Power the programmer up and run the verify software, checking for FFH patterns in all addresses.

Power may be removed from the programmer while the DIP switches are changed between program and verify. but be careful that VPP is not applied to the EPROM while the five volt supply is removed. Set up the programmer switches for the program function and close the isolation switches for pins one through eight of the test socket. With the desired EPROM data loaded into the main memory source -area and the programmer in the idle condition. bring up the 28 -volt supply and execute the EPROM program software. After the program runs, remove the 28 -volt supply and set up the DIP and isolation switches for verify. Run the verify software and if the EPROM contents prove to be good, you have now suc- cessfully programmed an EPROM and the project has passed its final test. R -E

69

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completion . If your program doesn' t dothat, it is not observing the three-phasecycle requirements.

Once the raw program is developed toyour satisfaction, you can work on adjust-ing the pulse width . Youcan do that easilywith the aid of an oscilloscope by simplymeasuringTILP and changing the soft-ware delay accordingly.

If you don't have anoscilloscope,usea clock or watch to measure the time ittakes to transfer one or two kilobytes.Run the program with the EPROMsocket empty, and adjust the software de-lay until the run time is 100 seconds,± 3seconds .

The EPROM verify software is easier tocreate because there are no delays or mul-tiple passes involved. The three-phase cy-cle is used to load the addresses, but thedata patterns have no significance sincethe isolation switches to the EPROM datalines will be open during the verify opera-tion.

There are two verify procedures ,vi andV2 specified in Fig. 13: In theVI process,the host reads pins 1-8 of the test socketduring the idle state after having executedthe three-phase cycle to load the EPROMaddress. In thev: process, the read isperformed during phase three, and onemore load is done to complete the cycle.Normally, the contents of the EPROM iseither read into a main memory area forexamination or compared with a memoryarea to verify the EPROM contents.

When you have the hardware and soft-waredebugged,you are ready to test theprogrammer with an EPROM in the sock-et and the VPPsupply connected . The firstthing you'll want to check is that theEPROM is erased . Power the programmerdown, insert an EPROM and the associ-ated personality module, set up the DIPswitches for verify (using Fig. 13), andopen the isolation switches for test socketpins one through eight. Power the pro-grammer up and run the verify software,checking for FFH patternsin all ad-dresses .

Power may be removed from the pro-grammerwhile the DIP switches arechanged between program and verify, butbe careful that VPP is not applied to theEPROM while the five volt supply is re-moved. Set up theprogrammerswitchesfor the program function and close theisolation switches for pins one througheight of the test socket. With the desiredEPROM data loaded into the main memo-ry source-area and the programmer in theidlecondition,bring up the 28-volt supplyand execute the EPROM program soft-ware. After the program runs, remove the28-volt supply and set up the DIP andisolation switches for verify. Run the ver-ify software and if the EPROM contentsprove to be good , you have now suc-cessfully programmedan EPROM andthe project has passed its final test.R-E

still function properly.

Using the programmerBefore you can use the programmer,

you'll have to write some software to con-trol it. A relatively simple (and popular)method is to store the intended EPROMcontents in a main memory area and usesoftware to transfer that data to the pro-grammer(while keeping the address anddata bits properly distributed and main-taining goodprogram-pulsewidth).

The program will have to send the prop-er set of bits to the device during eachphase and must control the program pulsewidth by means of a delay between phasetwo and phase three .Programmingismore complex for the three-supplyEPROM's becausethe source data istransferred to the EPROM a number oftimes as multiple passes are made .Don'tforget that only a single pulse per addressis permitted withsingle-supplyEPROMtypes and the pulse width must be 50milliseconds, ± 10%.

Figure 15 may be helpful in determin-ing the address- and data-bit distributionamong the three phases . Examples of ex-act stimuli forprogrammingtwo locationsare shown. Using that figure, you can de-velop software that will create and issuethe appropriate patterns . Youcan leavethedelay between phases two and three at avery low value for now. Check that theprogrammeris in the idle state when thesoftware is initiated and that the softwareleaves theprogrammerin the idle state at

FUNCTION STIMU LUS PATTERNS

WR ITE56 2300 PHASE ONE ....INTOADDRESS 9B56 - PHASETWO h 39B = 56398 9856- PHASETHREE '----r"'WRITE 74 2300 - PHASE ONE fltINTOADDRESS 9A74- PHASE TWO h 39A = 7439A 9A74 PHASE THREE

'j ,

A7

01 A6

ENABLE PHASE·DNELOAD (A)

EPROMA4

EPROMX DATA ADDRESSA3 (LOWER 8 BITS)

EPROMADDRESS 05 A2(UPPER 5 BITS)

06 A1

A8 07 AO

a b

one. Next, vary the phase-two and -threepatterns and check the data and lower-address bits, again on the EPROM socket.By testing the bits on the socket, the wir-ing is checked out as well as the sourcelogic.

For the next test, an 820-ohm, 2-wattresistor is needed . (If youdon'thave thatunusual item you cancombinefour 3300-ohmYz-watt resistors inparallel.)In eithercase, take notice that the resistor(s) willbecome very warm to the touch.

With the programmerin the idle con-dition, apply+28 volts to the collector ofQl and observeQl's emitterfor a voltagenear ground potential. Close switch524,and the emitter should go to about 27volts. Now connect the resistor, whichconstitutes a typical load, from the emitterto ground and look for a voltage of 25 or26 volts. If Ql has been substituted for,and is dropping four volts or more, thesubstitution is not acceptable .

Leave 524 closed and the load con-nected for ten minutes or longer and thenopen 57. The emitter should return to nearground potential. With switch 57 open,cycle the device through the phases andconfirm thattransistorQl'semitter is con-trolled byTILP.

For the final hardware test, close switch58 and make sure that the programmer islocked into the idlecondition regardlessof attempts to cycle it from the host com-puter. Now, with 58 closed and theEPROM socket empty, make sure the ICtester and any other expansion devices

c

FIG. 15-THE SOFWARE views the programmer as an Ie under test. The first pattern sent Is assignedto the EPROM lines as shown In 8, while the second and third patterns are assigned to the lines shownin b. Sample bit patterns (in hexadecimal form) used to program two EPROM address locations areshown In c.

69



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