roadmap past, present and future - linx consulting · april 2016 spcc p.gargini paolo gargini ....

April 2016 P.GarginiSPCC

Paolo GarginiPaolo Gargini Chairman ITRS2.0Chairman ITRS2.0

Fellow IEEE, Fellow IFellow IEEE, Fellow I--JSAPJSAPIntel Fellow (1995Intel Fellow (1995--2012)2012)

Roadmap Past, Present and

Future

11


Multiple StoriesMultiple Stories1.1. IntroductionIntroduction2.2. 1998. ITRS 1.01998. ITRS 1.0

1.1. Equivalent ScalingEquivalent Scaling

3.3. 2000. NNI. 2000. NNI. 4.4. 2005. Nanoelectronics Research Initiative (NRI)2005. Nanoelectronics Research Initiative (NRI)5.5. 20052005--6. MPU power limits6. MPU power limits6.6. 2006. More than Moore2006. More than Moore

1.1. Heterogeneous IntegrationHeterogeneous Integration

7.7. 2010.First Selection of post CMOS devices2010.First Selection of post CMOS devices8.8. 2011. Equivalent scaling fully in production2011. Equivalent scaling fully in production9.9. 2014. Scaling acceleration2014. Scaling acceleration10.10. 20142014--15.ITRS 2.015.ITRS 2.011.11. 2015. Post CMOS map of devices2015. Post CMOS map of devices12.12. 2016. IRDS2016. IRDS13.13. 20172017--2021.3D POWER Scaling2021.3D POWER Scaling

22


International Electron Device Meeting, December 1975

Second Update of Moore’s Law

2

4

7

9

13

1

3

56

8

101112

141516

0

191817

20

1961

1959

1960

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

1976

1977

1978

1979

1980

1965

1975

Log 2

of th

e nu

mbe

r of

com

pone

nts p

er in

tegr

ated

func

tion

Year

2X/Year

2X/2Year

33

April 2016 P.GarginiSPCC 44


MooreMoore’’s Law and Dennards Law and Dennard’’s s Scaling Laws ConvergenceScaling Laws Convergence

50% AREA READUCIONGENERATION TO GENERATION

50%

=> 30% LINEAR FEATURE REDUCTION

S=0.7


First Age of Scaling(Self-aligned Silicon Gate)

Phase 1

66


IC Industry at a GlanceIC Industry at a Glance (1975(1975--2003)2003)

Driver Cost/transistor -> 50% Reduction

How 2x Density/2 years (Moore)

Method Geometrical Scaling (Dennard)

77


The Incredible Shrinking Silicon The Incredible Shrinking Silicon Technology of the 90Technology of the 90’’ss

0.35 0.35 µµ

GateGate

SalicideSalicide

SpacerSpacer

SalicideSalicide

1995 0.250.25

Salicide

GateGate SpacerSpacer

Salicide

1997 0.180.18µµ

GateGate SpacerSpacer

Salicide

Salicide

1999


Gate Dielectric ScalingGate Dielectric Scaling

1

2

3To

x eq

uiva

lent

(nm

)

4 8 12

Monolayers

4

0

1999

2001

2003

2005

1997 NTRS

You Are Here!

Silicon substrate

1.2nm SiO2

Gate

99

From My Files






7.7. 2010.First Selection of post CMOS devices2010.First Selection of post CMOS devices8.8. 2011. 2011. Equivalent scaling fully in productionEquivalent scaling fully in production9.9. 2014. Scaling acceleration2014. Scaling acceleration10.10. 20142014--15.ITRS 2.015.ITRS 2.011.11. 2015. Post CMOS map of devices2015. Post CMOS map of devices12.12. 2016. IRDS2016. IRDS13.13. 20172017--2021.3D POWER Scaling2021.3D POWER Scaling

1111


Tutorial for SEMI P.Gargini

1998 ITRS Update

• Participation extended to: EECA, EIAJ, KSIA, TSIA at WSC on April 23,1998

• 1st Meeting held on July 10/11,1998 in San Francisco

• 2nd meeting held on December 10/11,1998 at SFO• 50% of tables in 1997 NTRS required some changes• 1998 ITRS Update posted on web in April 1999

1212


ITRS 1.0

1313

1998


Second Age of Scaling(Equivalent Scaling)

Phase 2

1414


The Ideal MOS TransistorThe Ideal MOS Transistor

From My Files

Fully SurroundingMetal Electrode

High-KGate Insulator

Fully Enclosed,DepletedSemiconductor

Low ResistanceSource/Drain

DrainSourceMetal Gate Insulator

Band EngineeredSemiconductor

1515


ITRS 7/11/1998


IC Industry at a GlanceIC Industry at a Glance (2003(2003-->2021)>2021)

Driver Cost/transistor-> 50% Reduction


Method Equivalent Scaling ( ITRS1.0)

1717


1991 Micro Tech 2000Workshop Report

1994NTRS1992NTRS 1997NTRS

The Start of the ITRS

Japan KoreaEurope Taiwan USA

http://www.itrs2.net

2001 ITRS1999 ITRS1998 ITRSUpdate

2000 ITRSUpdate

2002 ITRSUpdate


High-k/Metal-Gate(year 2000)


Four year pace of introduction of Equivalent Scaling into production

2020


Incubation TimeIncubation TimeEarly

InventionFocusedResearch

IntroductionManufacturing

Strained Silicon 1992 1998 2003

HKMG 1996 1998 2007

Raised S/D 1993 1998 2009

MultiGates 1988 2000 2011<11 years

DrainSourceMetal Gate Insulator

1998

2121


IEEE, ISSCC: Transistor’s 60th year commemorative supplement

2525







2727


NRI Funded UniversitiesNRI Funded Universities Finding the Next Switch Finding the Next Switch

UC Los AngelesC BerkeleyUC IrvineUC Sana BarbaraStanfordU DenverPortland StateU Iowa

Notre Dame PurdueIllinois-UC Penn StateMichigan UT-DallasCornell GIT

UT-Austin Rice Texas A&MUT-Dallas ASU Notre DameU. Maryland NCSU Illinois UC

ColumbiaHarvardPurdueUVAYaleUC Santa BarbaraStanfordNotre DameU. Nebraska/LincolnU. MarylandCornellIllinois UCCaltechUC BerkeleyMITNorthwesternBrownU Alabama

SUNY-Albany GIT HarvardPurdue RPI ColumbiaCaltech MIT NCSUYale UVA

Over 30 Universities in 20 States

SPIN

TUNNEL FET

GRAPHENESPIN LOGIC

GRAPHENE

2929


Dec 2010

3030







3636


MM+MtM=Heterogeneous IntegrationMM+MtM=Heterogeneous Integration2006

More than Moore: Diversification

Mor

e M

oore

: M

inia

turiz

atio

n

Combining SoC and SiP: Heterogeneous IntegrationBas

elin

e C

MO

S:

CP

U, M

emor

y, L

ogic

BiochipsSensorsActuators

HVPowerAnalog/RF Passives

130nm

90nm

65nm

45nm

32nm

22nm

16 nm...V

Information Processing

Digital contentSystem-on-chip

(SoC)

Beyond CMOS

Interacting with people and environment

Non-digital contentSystem-in-package

(SiP)

2006

3737


On January 9, 2007 Steve Jobs announced the iPhone at the Macworld convention, receiving substantial media attention,[16] and that it would be released later that year. On June 29, 2007 the first iPhone was released.

iPhoneJune 2007


TabletApril 2010

A WiFi-only model of the tablet was released in April 2010, and a WiFi+3G model was introduced about a month later







4141


2D 3D

4242


22 nm Tri-Gate Transistor

Gates Fins

Mark Bohr, Kaizad Mistry, May 2011 4343


How many more technology generationscan

Equivalent Scaling be extended for ?

Question

4444


Multigate FET Offers a Simple Way for Scaling and Improving Performance

5 4 3

Semicon Japan, December 6, 2013

4545

April 2016 P.GarginiSPCCMark Bohr, August 11, 2014

4646


4747


Fin FETMoore’s Law Acceleration

4848


4949


5

7

10Te

chno

logy

Nod

e (n

m)

2017 2015 2013

14

2019

2013 ITRS5151

2021

3

1

Technology Node ScalingTechnology Node ScalingToday’s Challenge


Micron/ Intel 20-nm 64G MLC NAND Flash

5353


NAND Relative Wafer Cost

5454


Vertical Logic Architecture

5959


3DMoore’s Law Acceleration

6060


3D Architecture

6161







6262


Third Age of Scaling(3D Power Scaling)

Phase 3

6363


IC Industry at a GlanceIC Industry at a Glance (2021(2021-->203X)>203X)

Driver Cost/transistor & power reduction


Method 3D Power Scaling (ITRS2.0)

6464


The Different Ages of ScalingThe Different Ages of Scaling (Different methods for different times) (Different methods for different times)

①①

Geometrical Scaling (1975Geometrical Scaling (1975--2003)2003)①①

Reduction of horizontal and vertical physical dimensions in Reduction of horizontal and vertical physical dimensions in conjunction with improved performance of planar transistors conjunction with improved performance of planar transistors

②②

Equivalent Scaling (2003~2021)Equivalent Scaling (2003~2021)①①

Reduction of only horizontal dimensions in conjunction with Reduction of only horizontal dimensions in conjunction with introduction of new materials and new physical effects. New introduction of new materials and new physical effects. New vertical structures replace the planar transistorvertical structures replace the planar transistor

③③

3D Power Scaling (2021~203X)3D Power Scaling (2021~203X)①①

Transition to complete vertical device structures. Transition to complete vertical device structures. Heterogeneous integration in conjunction with reduced Heterogeneous integration in conjunction with reduced power consumption become the technology driverspower consumption become the technology drivers

6565


More Moore Beyond Moore

More than Moore

Heterogeneous Integration

System Integration

Customized FunctionalityOP

SYSTEM

APPLETS

Outside System Connectivity

Beyond 2020

ITRS 2012

6666


1991 Micro Tech 2000Workshop Report

1994NTRS1992NTRS 1997NTRS

21th Anniversary of TRS

Japan KoreaEurope Taiwan USA


2001 ITRS1999 ITRS1998 ITRSUpdate

2000 ITRSUpdate

2002 ITRSUpdate

2004 ITRSUpdate

2006 ITRSUpdate2003 ITRS 2005 ITRS 2007 ITRS

2008 ITRSUpdate

2010 ITRSUpdate2009 ITRS 2012 ITRS

Update2011 ITRS

2013 ITRS

6767


Dec 2015 P.Gargini RC4

Beyond 2020

Outside System Connectivity Outside System Connectivity

System Integration System Integration

Heterogeneous Integration Heterogeneous Integration

Beyond Moore Beyond CMOS

More than Moore Heterogeneous Components

More Moore More Moore

Manufacturing Factory Integration

Themes Focus Teams April 2014

3 Dec 2015 P.Gargini RC4

More Moore Beyond Moore

More than Moore

Heterogeneous Integration

System Integration

Customized Functionality O P S Y S T E M

A P P L E T S

Outside System Connectivity

Beyond 2020

ITRS 2012

2

April 2014

From ITRS to ITRS 2.0

6868


ITRS 2.0



Q: How do we get back to Q: How do we get back to exponential performance scaling?exponential performance scaling?

IEEE Rebooting Computing InitiativeIEEE Rebooting Computing Initiative

7171


NAND FlashYear of Production 2015 2016 2020 2022 2024 2028 20302D NAND Flash uncontacted poly 1/2 pitch – F (nm) 15 14 12 12 12 12 12

3D NAND minimum array 1/2 pitch - F(nm) 80nm 80nm 80nm 80nm 80nm 80nm 80nm

Number of word lines in one 3D NAND string 32 32-48 64-96 96-128 128-192 256-384 384-512

Dominant Cell type (FG, CT, 3D, etc.) FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D

Product highest density (2D or 3D) 256G 384G 768G 1T 1.5T 3T 4T

3D NAND number of memory layers 32 32-48 64-96 96-128 128-192 256-384 384-512

Maximum number of bits per cell for 2D NAND 3 3 3 3 3 3 3

Maximum number of bits per cell for 3D NAND 3 3 3 3 3 3 3

7777


DRAM TECHNOLOGYYEAR OF PRODUCTION 2015 2017 2019 2021 2024 2027 2030Half Pitch (Calculated Half pitch) (nm) 24 20 17 14 11 8.4 7.7

DRAM cell size (µm2) 0.00346 0.00240 0.00116 0.00078 0.00048 0.00028 0.00024

DRAM cell FET structure RCAT+Fi n RCAT+Fin VCT VCT VCT VCT VCT

Cell Size Factor: a 6 6 4 4 4 4 4

Array Area Efficiency 0.55 0.55 0.5 0.5 0.5 0.5 0.5

Vint (support FET voltage) [V] 1.1 1.1 1.1 1.1 0.95 0.95 0.95

Support min. Vtn (25C, Gm,max , Vd =55mV) 0.40 0.40 0.40 0.40 0.37 0.37 0.37

Minimum DRAM retention time (ms) 64 64 64 64 64 64 64

DRAM soft error rate (fits) 1000 1000 1000 1000 1000 1000 1000

Gb/1chip target 8G 8G 16G 16G 32G 32G 32G

7878


ConclusionsConclusions

““Geometrical ScalingGeometrical Scaling”” led the IC Industry for 3 decadesled the IC Industry for 3 decades

ITRS 1.0ITRS 1.0

Cooperative and distributed research and manufacturing methods Cooperative and distributed research and manufacturing methods highlighted by highlighted by ITRS ITRS emerged as cost effective means of reducing costs emerged as cost effective means of reducing costs since the midsince the mid--90s90s

FCRP, NRI, Sematech, IMEC and Government organizations actively FCRP, NRI, Sematech, IMEC and Government organizations actively cooperated in cooperated in advanced researchadvanced research

““Equivalent ScalingEquivalent Scaling”” saved the Semiconductor Industry since saved the Semiconductor Industry since the beginning of the previous decadethe beginning of the previous decade

Preliminary evaluation of postPreliminary evaluation of post--CMOS candidates published in 2010CMOS candidates published in 2010

ITRS 2.0ITRS 2.0

““3D Power Scaling3D Power Scaling”” is the next phase of (accelerated) is the next phase of (accelerated) scalingscaling

Post CMOS devices and emerging architectures are being Post CMOS devices and emerging architectures are being jointly evaluatedjointly evaluated-->ITRS/IEEE RC>ITRS/IEEE RC-->IRDS>IRDS

8181

roadmap past, present and future - linx consulting · april 2016 spcc p.gargini paolo gargini ....

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