risc

Project 2 Design of Reconfigurable Digital Machines

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ECE 5570 Design of Reconfigurable Digital

Machines

Design of 16 Bit RISC Processor

Chandra Shekar Patil


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Contents

1) Project Objectives

2) RISC Processors

3) Instructions

a) Instruction Set

I. Execute instructions

II. Internal Register Instructions

III. External Memory Instructions

IV. Branch Instructions

4) Block Diagram

a) Arithmetic Logic Unit

b) Register Banks

c) Control and Status Registers

d) External Bus Interface

5) Integrated State Machine

6) Conclusion

7) Appendix

a) VHDL Code

b) Design Summary

c) User Constraint File

d) Pin Out Report


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1. Project Objectives

The objective of the Project 2 is to design, simulate, build, and demonstrate the

correct operation of a simple 8-bit RISC processor core along with an external bus

to facilitate testing and debugging.

The Implemented RISC Processor shall contain the following feature

• The list of commands to be implemented is specified in table 1.

• No interrupts will be available.

• The instructions must consist of either two, or four 8-bit words.

• The number of memory cycles to fetch and execute an instruction must be

limited to six

• The Control Unit finite state machine FSM should have the following

states: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF),

Execute (EX), Write Result (WR).

• A virtual program/data memory should be implemented on the solder-less

breadboard using DIP-switches and Bar-LEDs.

• A single-step logic module should be added to your processor in order to

facilitate debugging and the demonstration of the performance of your

design.

2. RISC Processors

RISC stands for Reduced Instruction Set Code, IBM Introduced the first RISC

architecture in 1970’s. As the name indicates the RISC processors have reduced

number of instruction code, in the sense there are few basic instructions than

many instructions doing complicated process. These controllers are used in

various applications due to their speed and simplicity.

In this project we design a 16 bit RISC processor which borrows some ideas from

32 bit controllers from Rensas® technology.

Project 2

3. Instructions

The instructions set for the 16 bit processor are

The op-code is 16 bit wide and the immediate data input is also 16 bit wide. As

shown in the figure.1 the most significant 4 bits and the least significant 4

plays major role in determining the type of the instruction. The instruction set is

designed in such a way that no two instructions share a common op

each instruction are very unique.

Figure 1 Op

MSB: Most significant bit of the opcode it is a hex number specific to the each

instructions

mmmm: Is a hex number which denotes the destination register in most of the

operations where registers are involved, otherwise it is a constant hex number for

op-code which does not inv

nnnn: Is a hex number which represents the register number which will be used

a secondary register for the particular operation like LSL instruction

zzzz: Is a hex number which represents the second register used

operation like ADD instruction

Table 1 gives more details about individual code design.

a. Instructions Set

The instruction set are divided in to 4 different categories such as

I. Execute instructions

II. Internal Register Instructions

III. External Memory Instructions


Design of Reconfigurable Digital Machines

instructions set for the 16 bit processor are designed as shown in the figure 1.

code is 16 bit wide and the immediate data input is also 16 bit wide. As

the most significant 4 bits and the least significant 4


designed in such a way that no two instructions share a common op

each instruction are very unique.

Figure 1 Op-code format (16 bit)

bit of the opcode it is a hex number specific to the each

Is a hex number which denotes the destination register in most of the


code which does not involve registers like CMP instruction.

Is a hex number which represents the register number which will be used

ter for the particular operation like LSL instruction.

Is a hex number which represents the second register used

operation like ADD instruction

Table 1 gives more details about individual code design.

The instruction set are divided in to 4 different categories such as

Execute instructions

Internal Register Instructions

l Memory Instructions

Branch Instructions


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designed as shown in the figure 1.

code is 16 bit wide and the immediate data input is also 16 bit wide. As

the most significant 4 bits and the least significant 4 bits


designed in such a way that no two instructions share a common op-code and

bit of the opcode it is a hex number specific to the each

Is a hex number which denotes the destination register in most of the


Is a hex number which represents the register number which will be used as

.

Is a hex number which represents the second register used in a particular


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Table 1: Instruction Set

Clas

sify

Mnemonic HEX Op-code (16 bits) Name Function States Flags

EX No memory

access

OVF,S,Z,CY,

BR,M

1 CMP 0M00 0000_mmmm_0000_0000 Complement Rm Rm:= not(Rm) IF/ID/EX

2 CLR 0M10 0000_mmmm_0001_0000 Clear Rm Rm:= 0 IF/ID/EX

3 AND 1MNZ 0001_mmmm_nnnn_zzzz AND Rm,Rn,Rz Rm:= Rn and Rz IF/ID/EX

4 OR 2MNZ 0010_mmmm_nnnn_zzzz OR Rm,Rn,Rz Rm:= Rn or Rz IF/ID/EX

5 XOR 3MNZ 0011_mmmm_nnnn_zzzz XOR Rm,Rn,Rz Rm:= Rn XOR Rz IF/ID/EX

6 INC 0M20 0000_mmmm_0010_0000 Increment Rm Rm:= Rm PLUS 1 IF/ID/EX OVF,Z,S

7 ADD 4MNZ 0100_mmmm_nnnn_zzzz Add w/o carry Rm, Rn, Rz Rm:= Rn + Rz IF/ID/EX OVF,Z,S

8 ADC 5MNZ 0101_mmmm_nnnn_zzzz Add w/ carry Rm, Rn, Rz Rm:= Rn + Rz + CY IF/ID/EX CY,Z,S

9 SUB 6MNZ 0110_mmmm_nnnn_zzzz Subtract w/o borrow

Rm, Rn, Rz

Rm:= Rn - Rz IF/ID/EX OVF,Z,S

10 SUBB 7MNZ 0111_mmmm_nnnn_zzzz Subtract w/ borrow Rm,

Rn, Rz

Rm:= Rn – Rz - BW IF/ID/EX BR,Z,S

11 LSL 0MN1 0000_mmmm_nnnn_000

1

Logic shift left Rm, n Rm:= LSL(Rm), n IF/ID/EX Z,S

12 LSR 0MN2 0000_mmmm_nnnn_001

0

Logic shift right Rm, n Rm:= LSR(Rm), n IF/ID/EX Z,S

13 ASL 0MN3 0000_mmmm_nnnn_001

1

Arithmetic shift left Rm,

n

Rm:= ASL(Rm),n IF/ID/EX Z,S

14 ASR 0MN4 0000_mmmm_nnnn_010

0

Arithmetic shift right Rm,

n

Rm:= ASR(Rm),n IF/ID/EX Z,S

15 MUL 8MNZ 1000_mmmm_nnnn_zzzz Signed multiply Rm, Rn,

Rz

Rm:= Rn x Rz IF/ID/EX Z,S

MT No memory

access

16 MOV 0MN5 0000_mmmm_nnnn_010

1

Move Rm, Rn Rm:= Rn IF/ID/EX

17 LDIL 0M30 0000_0mmm_0011_0000

iiii_iiii_iiii_iiii

Load Rm (R0 to R7), imm Rm:= #imm IF/ID/EX

18 LDIH 0M40 0000_1mmm_0100_0000

iiii_iiii_iiii_iiii

Load Rm (R8 to R15),

imm

Rm:= #imm IF/ID/EX

19 NOP 9000 1001_0000_0000_0000 No operation Do nothing IF/ID/EX

LS Memory

Access

20 LDR 0MN6 0000_mmmm_nnnn_011

0

Load Rm, mem(Rn) Rm:= mem(Rn) IF/OF/ID/EX

21 LDD 0MN7 0000_mmmm_nnnn_011

1

Load double Rm,

mem(Rn)

Rm:= mem(Rn)

double

IF/OF/ID/EX

22 STR 0MN8 0000_mmmm_nnnn_100

0

Store Rm, mem(Rn) mem(Rn):= Rm IF/OF/ID/EX

/WR

23 STD 0MN9 0000_mmmm_nnnn_100

1

Store double Rm,

mem(Rn)

mem(Rn):= Rm

double

IF/OF/ID/EX

/WR

BR PC, SPC, PSW

24 CBR 9100 1001_0001_0000_0000

dddd_dddd_dddd_dddd

Conditional branch (F),

addr

PC:=addr if F=1,

otherwise update

PC

IF/ID/EX

25 BRA 9200 1001_0010_0000_0000

dddd_dddd_dddd_dddd

Branch, addr PC:= addr IF/ID/EX

26 BRS 9300 1001_0011_0000_0000

dddd_dddd_dddd_dddd

Branch to subroutine,

addr

SPC:=PC,

SPSW:=PSW, M=1

IF/ID/EX M=1

27 RTS 9400 1001_0100_0000_0000

Return from subroutine PC:=SPC,

PSW:=SPSW, M=0

IF/ID/EX M=0


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I. Execution Instructions

This set of instructions 1 to 15 – Table 1 do not need any memory access

and execute the operation in just Execute State of the state machine. Figure

2 shows the post route simulation for one of this instruction CMP, the

operation is performed on register 7. First the register 7 is loaded a data

followed by register 8 and the register 7 is complemented.

The wave form contains the following signals,

/stm_prt/CLK : Clock input

/stm_prt/ack : acknowledgement from the memory unit

/stm_prt/ex_ctrl : internal execute control signal

/stm_prt/da_i : data line

/stm_prt/in_fet_opcode: internal op-code information (op-code and

operand)

/stm_prt/in_de_opcode: Op-code

/stm_prt/in_de_imm: Immediate data

/stm_prt/in_de_m: target output register

/stm_prt/in_de_n: secondary register 1

/stm_prt/in_de_z: secondary register 2

/stm_prt/rm: Resltant data to be stored in Rm

/stm_prt/in_exe_bank1(m): Individual register m in bank 1

Figure 2

II. Memory Transfer Instructions:

The memory transfer Instructions loads an individual memory register with

the immediate data (LDIL, LDIH). This group also contains instruction to

transfer memory in between individual registers- MOV. As shown in the

figure 2, both LDIL and LDIH instructions are executed, as described in the

waveforms, the data “5555” is loaded in to the register 7 using LDIL

instruction and further LDIH instruction is executed to load the data “7856”

in to register 8.


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III. Load & Store Instructions.

This instruction group contains instruction used to read and write data into

the external memory. These instructions contain the 16 bit address of the

target memory in the nnnn register. Figure 3 shows the detailed waveforms

of the LDD instructions, this instruction will load the double data into the

register pair specified mmmm. In this case R7 will contain the address of

the memory, when LDD is executed the data from the memory location

specified in R7 i.e. “CCBB” and the next location which is “AA55” are loaded

in to R6 and R5 respectively

Figure 3


This group consists of instructions necessary to take the program execution

sequence to a different memory locations, this group contains conditional

and unconditional branch statements. Other than branch this group also

contains the RTS statement. Figure 4 shows the instructions executed in the

below sequence

> BRS 0x7787 (PC = 0000) Contents after execution.

> LDIL R7 0xFFFF (PC = 7768)

> LDIH R7 0xA55A (PC = 7769)

> INC R7 (PC = 776A)

> RTS (PC = 0001)

Figure 4

Also in the above figure it could be observed that the bank 2 registers are used

while in subroutine.

Project 2

4. Block Diagram

The design of the RISC processor core consisted of several parts that

desired result. The block diagram of the design is as shown Figure 5

Control Logic

Drives the operations of the RISC processor, the control logic contains a

finite state machine whose operation is explained in

logic contains two blocks i.e. Instruction Decoder and External Bus Interface

Instruction Decoder:

machine Hex code, this block’s output determine the further operations to

be performed. This result is interpreted by the control logic which would

determine the states of the I/O signals of this block.

External Bus Interface

external memory by using signals that c

� External memory

� An ACK# switch facilitates single


The design of the RISC processor core consisted of several parts that worked in tandem to produce t

desired result. The block diagram of the design is as shown Figure 5

Figure 5

perations of the RISC processor, the control logic contains a

finite state machine whose operation is explained in Section 5. The control


The instruction decoder is responsible to decode the


formed. This result is interpreted by the control logic which would

determine the states of the I/O signals of this block.

External Bus Interface: This block facilitates the reading from and writing to

external memory by using signals that communicate with the control logic

External memory address is represented by switches and LED’s.

An ACK# switch facilitates single-stepping


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worked in tandem to produce the

perations of the RISC processor, the control logic contains a

Section 5. The control


The instruction decoder is responsible to decode the


formed. This result is interpreted by the control logic which would

acilitates the reading from and writing to

h the control logic.

is represented by switches and LED’s.

Project 2

CPU

The CPU operation can be broken down in to the following basic blocks.

Register Bank: The RISC processor contains two sets of register bank the

register banks are toggled based on the sub routines. The bank 1 is the

main register bank and it is used as the target register bank while the

program flow is in main control, the processor switch

size of the registers is 16 bit each.

Control Registers: The control registers contain two 16 bit registers which

keeps the track of the program counter(PC) and the program status word

(PSW). The PSW registers contain the status of t

logic operations.

ALU:

The arithmetic logic unit consists of blocks which are used to perform

operations like OR, AND, XOR

and multiplier. The ALU block is invoked by the control logi

instruction decoders output.

Integrated State Machine:

The finite state machine designed has the states as described in the Figure 6


operation can be broken down in to the following basic blocks.

The RISC processor contains two sets of register bank the



program flow is in main control, the processor switches to the bank 2. The

size of the registers is 16 bit each.

The control registers contain two 16 bit registers which


(PSW). The PSW registers contain the status of the previous airthmatic or


operations like OR, AND, XOR and arithmetic blocks like adder, sub tractor

and multiplier. The ALU block is invoked by the control logic based on the

instruction decoders output.


Figure 6


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operation can be broken down in to the following basic blocks.

The RISC processor contains two sets of register bank the



es to the bank 2. The

The control registers contain two 16 bit registers which


he previous airthmatic or


and arithmetic blocks like adder, sub tractor

c based on the



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Below are the states for the finite state Machines

Instruction Fetch (IF): In this state the instruction is fetched from the external

data bus and passed on to the next state as shown in the Figure 7.

Instruction Decoder (ID): The instruction decode state decodes the instructions

and pass it on to the next state, based on the type of instruction the next state is

decided. For example if the instruction required a immediate data then the OPC

state is executed otherwise the next state will be EX.

Op-Code Fetch OPC: This state is reached if only the processor requires additional

data as input. After this state the fetched data will be passed on to the next state

which is EX.

Execute EX: This state executes the operation based on the instructions; this state

invokes the CPU’s components as required by the opcode.

Write WR: The WR state will write data on to the external memory, this state is

invoked if the instruction requires external memory operation.

6. Conclusion

The 16 bit RISC processor was successfully implemented, we had difficulty in

getting the external bus signal right. The major challenge faced in this project was

the implementation of state machine.

As a part of learning we understood the internals of a RISC processor and its

configuration of internal blocks for example: The integration of the Instruction

Decoder to the control logic and also we understood how the state machine could

be used to implement the processor logic.


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Appendix

risc

Documents

rn rz rm

instructions mmmm

rn xor rz rm

rz xor rm

notrm rm

rz increment rm

zzzz complement rm clear

number of instruction