risc-v: enabling a new era of open data-centric computing ... · undertake any obligation to...
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1 ©2018 Western Digital Corporation or its affiliates. All rights reserved. #LetDataThrive ©2018 Western Digital Corporation or its affiliates. All rights reserved. #LetDataThrive
RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures
Martin Fink, Chief Technology Officer
Western Digital Corporation
May 8, 2018
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2 ©2018 Western Digital Corporation or its affiliates. All rights reserved. #LetDataThrive
Forward-Looking Statements Safe Harbor | Disclaimers
This presentation contains certain forward-looking statements that involve risks and uncertainties, including, but not
limited to, statements regarding: the RISC-V Foundation and its initiatives; our contributions to and investments in
the RISC-V ecosystem; the transition of our devices, platforms and systems to RISC-V architectures; shipments of
RISC-V processor cores; our business strategy, growth opportunities and technology development efforts; market
trends and data growth and its drivers. Forward-looking statements should not be read as a guarantee of future
performance or results, and will not necessarily be accurate indications of the times at, or by, which such
performance or results will be achieved, if at all. Forward-looking statements are subject to risks and uncertainties
that could cause actual performance or results to differ materially from those expressed in or suggested by the
forward-looking statements.
Additional key risks and uncertainties include the impact of continued uncertainty and volatility in global economic
conditions; actions by competitors; business conditions; growth in our markets; and pricing trends and fluctuations in
average selling prices. More information about the other risks and uncertainties that could affect our business are
listed in our filings with the Securities and Exchange Commission (the “SEC”) and available on the SEC’s website at
www.sec.gov, including our most recently filed periodic report, to which your attention is directed. We do not
undertake any obligation to publicly update or revise any forward-looking statement, whether as a result of new
information, future developments or otherwise, except as otherwise required by law.
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3 ©2018 Western Digital Corporation or its affiliates. All rights reserved. #LetDataThrive
The Evolving Role of Data Creating the data-driven economy
Ric
hn
ess
Data as communication
Data as a record
Data as efficiency
Data as currency
Value
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Diverse and Connected Data Types Tight coupling between Big Data and Fast Data
Fast Data
Performance
Big Data
Scale
Mobility
Real-time Results
Smart Machines
Insight
Prediction
Prescription
Batch Analytics
Streaming Analytics
Artificial Intelligence
Machine Learning
Data Aggregation
Modeling
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Big Data
Fast Data
From General Purpose to Purpose Built Architectures designed for Big Data, Fast Data applications
General purpose compute-centric architecture
Expanding applications and workloads
Devices
Platforms
Systems
Solutions
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General Purpose Architectures No Longer Sufficient Big Data and Fast Data workloads exceed capability of uniform resource ratios
General Purpose Compute Architecture
S/PDIF jack
VGA port
DVI-D port
USB ports
LAN port
Audio jacks
S/PDIF-out
PCIe x16 slot
PCIe x1 slots
Mini-card socket
Memory slots
Buzzer
Power
Chipset
Front panel
SATA 1~4
Jumpers
Front audio Battery USB 5~8
WLAN LED USB 1~4
System fan Processor CPU fan • Predetermined ratios of:
– OS/App Processor
– Specialty Processor
– Memory
– Storage
– Interconnect
• Overhead of “PC” logic
• CPU-centric
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Western Digital RISC-V Core
• First Western Digital RISC-V core
• 2-way, superscalar, mostly in-order core with 9 stages pipeline: – Support for RV32IMC
– 1 Load/Store pipe
– 1 MLY
– 1 DIV
– 4 ALU engines
• Performance targets @ 28nm: – Dhrystone >2 MIPS/MHz
– Coremark > 3 CM/MHz
– 1 GHz operation
• Core part was fun, uncore was all the work
RV32IMC
PIC
Debug
Power Mgmt
Write Buffer
I$ D$
Bus Interface Unit
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• Multi-purpose SoC for consumer SSD applications
• First RISC-V based SoC for NAND controller applications
• Advantages: – Full advantage of open source
software ecosystem for RISC-V
– Instruction optimization for NAND media handling
– Freedom of power and performance optimization for end application
NAND Controller SoC
Host subsystem
Error Correction (ECC)Engine
PHY I/F
Main CPU Datapath CPU
NAND Channels
NAND Channels
to NAND
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RISC-V and Interface Control Points
• RISC-V in embedded: – Free and open IP connectivity buses enabling plug and play of proprietary and open source IPs
• RISC-V in enterprise: – Datacenter CPUs with smart, fast and open peripherals buses enable new compute paradigms
essential for AI workloads
Open source IPs
Open buses
Embedded Enterprise
CPU cores
CPU uncore
CPU CPU CPU GP-GPU ASIC or FPGA
Smart & Fast Peripheral Bus
DRAM
DDR I/F
Persistent memory
NVM I/F
NIC
SSD
Asic (Inference)
Persistent Memory
Asic (Inference)
………
Cohere
ncy b
us
……
……
……
……
Share
d p
ers
iste
nt
mem
ory
CPU
ASIC
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General Purpose Architectures No Longer Sufficient Big Data and Fast Data workloads exceed capability of uniform resource ratios
General Purpose Transportation
General Purpose Compute Architecture
S/PDIF jack
VGA port
DVI-D port
USB ports
LAN port
Audio jacks
S/PDIF-out
PCIe x16 slot
PCIe x1 slots
Mini-card socket
Memory slots
Buzzer
Power
Chipset
Front panel
SATA 1~4
Jumpers
Front audio Battery USB 5~8
WLAN LED USB 1~4
System fan Processor CPU fan
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11 ©2018 Western Digital Corporation or its affiliates. All rights reserved. #LetDataThrive
General Purpose Architectures No Longer Sufficient Big Data and Fast Data workloads exceed capability of uniform resource ratios
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General Purpose Architectures No Longer Sufficient Big Data and Fast Data workloads exceed capability of uniform resource ratios
Fast Data
Big Data
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Workload Diversity Demands Diverse Technologies and Architectures
Storage HDD SSD
Fast Data
Big Data
Performance-centric scale
Capacity-centric scale
Compute
Storage SOC General Purpose CPU GPU FPGA ASIC
Memory NVM DRAM SRAM
Storage Semantic Data Flow
Memory Semantic Data Flow
Interconnect
Storage-centric architecture
Purpose-built data-centric architectures
Memory-centric architecture
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Data-Centric Environments Big Data and Fast Data workloads need independent scaling of resources
• Massive Storage
• Moderate Processing
Analytics Machine Learning
Security Detection
Event Correlation Blockchain
Big Data Fast Data
• Massive Storage
• Massive Specialty Processing
• Large Memory
• Specialty Processing
• High-bandwidth interconnect
• Large Memory and Specialty Processing
• High-bandwidth interconnect
• Large Specialty Processing
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Independent Scaling Demands Openness Rapid adoption of new open source technologies and standards
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Data-Centric Applications at the Edge Environments require modular technologies and dense integration to optimize space, weight and power consumption
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RISC-V Meets the Needs of Big Data and Fast Data
Move Compute to Data Memory Centric Compute
• Highly scalable main memory
• Minimize data movement
• Heterogeneous processor support
• Scalable accelerators/offload engines
• CPU for device, platform, system
• Minimize data movement
• Offload workload to “smart” storage
• Localized machine learning
Big Data Fast Data
• Open and free
• Enables modular chip designs
• From 16 to 128-bit
• Scales from embedded to enterprise
• Direct integration with specialty accelerators
• Extensible ISA (for special purpose functions)
Provides a foundation for purpose-built, data-centric compute environments
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Design Logic Synthesis
Place and Route
Hardware Implementation
Hardware Design Lifecycle
HDL
Netlist (i.e., list of electronic
components and connections)
Bitstream FPGA
GDSII ASIC
Gerber PCB
Open Source Software Licenses
Open Source Hardware Licenses
Ⓜ
Ⓜ
Legal protections with copyrights, mask works and patents
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Permissive vs Copyleft Licenses define the potential community
• Harder obligations
- Source code sharing
- No DRM
- Less corporate adoption
• Disallows proprietary silos
• May be incompatible with other components
• Easier obligations
- Attribution
- More corporate adoption
• Allows for proprietary silos
Permissive License
Goal: Broad use
of code
Copyleft License
Goal: Reciprocity
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RISC-V Enables Purpose-Built Environments for Big Data and Fast Data Applications
Storage HDD SSD
Fast Data
Big Data
Performance-centric scale
Capacity-centric scale
Compute
Storage SOC General Purpose CPU GPU FPGA ASIC
RISC-V
Memory NVM DRAM SRAM
Storage Semantic Data Flow
Memory Semantic Data Flow
Interconnect
Storage-centric architecture
Purpose-built data-centric architectures
Memory-centric architecture
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RISC-V Meets the Needs of Big Data and Fast Data
Fast Data
Big Data
Genomics
Predictive Analytics
Autonomous Machines
Safety & Security
Private Exchange
Machine Learning
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Western Digital ships in excess of
1 Billion cores per year
…and we expect to double that.
Driving Momentum
22 ©2018 Western Digital Corporation or its affiliates. All rights reserved.
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Accelerating the RISC-V Ecosystem Western Digital to contribute one billion cores annually to fuel RISC-V
1
2
3
4
Support development of open source IP building blocks for the community
Actively partner and invest in the ecosystem
Accelerate development of purpose-built processors for a broad range of Big Data and Fast Data environments
Multi-year transition of Western Digital devices, platforms and systems to RISC-V purpose-built architectures
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Big Data and Fast Data need purpose-built environments
Openness and ecosystem enable best-in-class innovation
Western Digital brings the momentum of >1B cores per year
Innovating for a Data-Centric World
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