RISC stands for reduced instruction set computer. The clock rates ranges from 20 to 120 MHZ depending upon technology implemented. The RISC processors are hardiwred controlled. It uses 32-bit instructions which is very less when compared to CISC. There are also limited addressing modes(3-5) The memory access cycle is split into pineplined units therefore sepearted instruction and data cache is used. This benefits internal data forwarding and eliminates unncessary storage of immediate results. Thus it is faster. By using hardwired control unit, the no of clocks per instruction is reduced to 1.From architecture we can see that RISC uses sepearte instruction and data caches and their access paths are different. Whereas in CISC processor there is unified cache for holding both instructions and data. Also they share same path for data and instructions. The microprogrammed memory control in CISC processors slow down the instruction execution. Properties of RISC: 1. Registe to register operations: The register sets are organized into overlapping windows. The window is divided into three fixed-size areas.Parameter registers hold parameter passed down from the procedure that called the current procedure.Local register used for local variables assigned by the compiler.Temp registers of current procedure are physically same as parameter register of called procedure. Thus this overlap permits parameters to be passed without actual movement of data.2. One instruction per cycle: A machine cycle defined as time it takes to fetch two operands from registers, performs an ALU operation and stores the result in a register.Due to this 1 instruction/cycle RISC is not complicated and execute faster.3.Hardwired instrucitons: with one cycle per instruction there is no need for microinstructions. The machine instructions can be hardwired. These instructions are executed faster than instructions implemented with microinstructions since it is not necessary to access a microprogram control memeory during instruction execution.4. It provides reduced number of instructions 32 bit therefore design is simplified.5. Simple addressing modes used such as PC addressing and relative addressing.6. Simple instruction format.7.Pipelining: the figure shows four-way instruction pipelining. At a time 4 commands can be executed. From the figure we can see that during instruciton1 decode the second instruction is fetched parallely. this is called as pipeling.Addressing: PC relative: opcode field specifies operation. Condition field specifiesone of many possible branch conditions and address field specifies the signed offset which is to be added to the contents of PC to calculate new address when the branch condition is satisfied.