review question (last week) 1.with the aid of diagrams, explain the significant difference between...
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Review Question (last week)
1. With the aid of diagrams, explain the significant difference between Von Neumann and Harvard Architecture.
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Von Neumann Architecture
a computer architecture with one memory/storage for both instructions and data.
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Harvard Architecture
a computer architecture with physically separate storage and signal pathways for instructions and data.
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PART 2:
Foundation to Computer Architecture
CHAPTER 3:A TOP-LEVEL VIEW OF COMPUTER
FUNCTION AND INTERCONNECTION
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Review of Previous Lecture
• The evolution of computers has been characterized by increasing processor speed, decreasing component size, increasing memory size, and increasing I/O capacity and speed.
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Review of Previous Lecture
• One factor responsible for the great increase in processor speed is the shrinking size of microprocessor components; this reduces the distance between components and hence increases speed.
• However, the true gains in speed in recent years have come from the organization of the processor, including heavy use of pipelining and parallel execution techniques and the use of speculative execution techniques (tentative execution of future instructions that might be needed).
• All of these techniques are designed to keep the processor busy as much of the time as possible.
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Review of Previous Lecture
• A critical issue in computer system design is balancing the performance of the various elements so that gains in performance in one area are not handicapped by a lag in other areas.
• In particular, processor speed has increased more rapidly than memory access time.
• A variety of techniques is used to compensate for this mismatch, including caches, wider data paths from memory to processor, and more intelligent memory chips.
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Program Concept
• Hardwired systems are inflexible• General purpose hardware can do different
tasks, given correct control signals• Instead of re-wiring, supply a new set of
control signals
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What is a program?
• A sequence of steps• For each step, an arithmetic or logical
operation is done• For each operation, a different set of control
signals is needed
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Function of Control Unit
• For each operation a unique code is provided– e.g. ADD, MOVE
• A hardware segment accepts the code and issues the control signals
• We have a computer!
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Components
• The Control Unit and ALU constitute the Central Processing Unit
• Data and instructions need to get into the system and results out– Input/output
• Temporary storage of code and results is needed– Main memory
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Computer Components:
Top Level View
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Instruction Cycle
• Two steps:– Fetch– Execute
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Fetch Cycle
• Program Counter (PC) holds address of next instruction to fetch
• Processor fetches instruction from memory location pointed by PC
• Increment PC– Unless told otherwise
• Instruction loaded into Instruction Register (IR)• Processor interprets (DECODE) instruction and
performs required actions
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Execute Cycle
• Processor-memory– data transfer between CPU and main memory
• Processor I/O– Data transfer between CPU and I/O module
• Data processing– Some arithmetic or logical operation on data
• Control– Alteration of sequence of operations– e.g. jump
• Combination of above
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Example of Program
Execution
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Instruction Cycle State Diagram
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Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
• Program– e.g. overflow, division by zero
• Timer– Generated by internal processor timer– Used in pre-emptive multi-tasking
• I/O– from I/O controller
• Hardware failure– e.g. memory parity error
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Program Flow Control
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Interrupt Cycle
• Added to instruction cycle• Processor checks for interrupt– Indicated by an interrupt signal
• If no interrupt, fetch next instruction• If interrupt pending:– Suspend execution of current program – Save context– Set PC to start address of interrupt handler routine– Process interrupt– Restore context and continue interrupted program
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Transfer of Control via Interrupts
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Instruction Cycle with Interrupts
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Program TimingShort I/O Wait
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Program TimingLong I/O Wait
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Instruction Cycle State Diagram
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Instruction Cycle (with Interrupts) - State Diagram
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Multiple Interrupts
• Disable interrupts– Processor will ignore further interrupts whilst processing
one interrupt– Interrupts remain pending and are checked after first
interrupt has been processed– Interrupts handled in sequence as they occur
• Define priorities– Low priority interrupts can be interrupted by higher
priority interrupts– When higher priority interrupt has been processed,
processor returns to previous interrupt
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Multiple Interrupts - Sequential
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Multiple Interrupts – Nested
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Time Sequence of Multiple Interrupts
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Connecting
• All the units must be connected• Different type of connection for different type
of unit– Memory– Input/Output– CPU
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Computer Modules
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Memory Connection
• Receives and sends data• Receives addresses (of locations)• Receives control signals – Read– Write– Timing
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Input/Output Connection(1)
• Similar to memory from computer’s viewpoint• Input– Receive data from peripheral– Send data to computer
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Input/Output Connection(2)
• Similar to memory from computer’s viewpoint• Output– Receive data from computer– Send data to peripheral
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Input/Output Connection(3)
• Receive control signals from computer• Send control signals to peripherals– e.g. spin disk
• Receive addresses from computer– e.g. port number to identify peripheral
• Send interrupt signals (control)
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CPU Connection
• Reads instruction and data• Writes out data (after processing)• Sends control signals to other units• Receives (& acts on) interrupts
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Buses
• There are a number of possible interconnection systems
• Single and multiple BUS structures are most common
• e.g. Control/Address/Data bus (PC)• e.g. Unibus (DEC-PDP)
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What is a Bus?
• A communication pathway connecting two or more devices
• Usually broadcast • Often grouped– A number of channels in one bus– e.g. 32 bit data bus is 32 separate single bit
channels• Power lines may not be shown
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Data Bus
• Carries data– Remember that there is no difference between
“data” and “instruction” at this level• Width is a key determinant of performance– 8, 16, 32, 64 bit
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Address bus
• Identify the source or destination of data• e.g. CPU needs to read an instruction (data)
from a given location in memory• Bus width determines maximum memory
capacity of system– e.g. 8080 has 16 bit address bus giving 64k
address space
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Control Bus
• Control and timing information– Memory read/write signal– Interrupt request– Clock signals
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Bus Interconnection Scheme
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Big and Yellow?
• What do buses look like?– Parallel lines on circuit boards– Ribbon cables– Strip connectors on mother
boards• e.g. PCI
– Sets of wires
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Physical Realization of Bus Architecture
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Single Bus Problems
• Lots of devices on one bus leads to:– Propagation delays• Long data paths mean that co-ordination of bus use can
adversely affect performance• If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to overcome these problems
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Traditional (ISA)(with cache)
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High Performance Bus
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ADDITIONAL NOTES
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Bus Types
• Dedicated– Separate data & address lines
• Multiplexed– Shared lines– Address valid or data valid control line
• Advantage - fewer lines (saves space and, usually cost)– Disadvantages• More complex control• Reduction in performance
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Bus Arbitration
• More than one module controlling the bus• e.g. CPU and DMA controller• Only one module may control bus at one time• Arbitration may be centralised or distributed
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Centralised or Distributed Arbitration
• Centralised– Single hardware device controlling bus access• Bus Controller• Arbiter
– May be part of CPU or separate• Distributed– Each module may claim the bus– Control logic on all modules
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Timing
• Co-ordination of events on bus• Synchronous– Events determined by clock signals– Control Bus includes clock line– A single 1-0 is a bus cycle– All devices can read clock line– Usually sync on leading edge– Usually a single cycle for an event
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Synchronous Timing Diagram
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Asynchronous Timing – Read Diagram
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Asynchronous Timing – Write Diagram
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PCI Bus
• Peripheral Component Interconnection• Intel released to public domain• 32 or 64 bit• 50 lines
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PCI Bus Lines (required)
• Systems lines– Including clock and reset
• Address & Data– 32 time mux lines for address/data– Interrupt & validate lines
• Interface Control• Arbitration– Not shared– Direct connection to PCI bus arbiter
• Error lines
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PCI Bus Lines (Optional)
• Interrupt lines– Not shared
• Cache support• 64-bit Bus Extension– Additional 32 lines– Time multiplexed– 2 lines to enable devices to agree to use 64-bit transfer
• JTAG/Boundary Scan– For testing procedures
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PCI Commands
• Transaction between initiator (master) and target
• Master claims bus• Determine type of transaction– e.g. I/O read/write
• Address phase• One or more data phases
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PCI Read Timing Diagram
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PCI Bus Arbiter
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PCI Bus Arbitration
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15 minutes Break....
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Quiz
• Differentiate between a hardwired and micro-programmed (general purpose hardware) implementations in control unit.
• [Bezakan antara pelaksanaan ‘hardwired’ dan ‘micro-programmed’ dalam unit kawalan.]
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Next: Another Significant Component