review article...

Hindawi Publishing CorporationActive and Passive Electronic ComponentsVolume 2012, Article ID 926753, 11 pagesdoi:10.1155/2012/926753

Review Article

Recent Subthreshold Design Techniques

Mohsen Radfar, Kriyang Shah, and Jugdutt Singh

Centre for Technology Infusion, La Trobe University, Melbourne, VIC 3086, Australia

Correspondence should be addressed to Mohsen Radfar, [email protected]

Received 2 March 2012; Revised 30 April 2012; Accepted 5 May 2012

Academic Editor: Yu-Te Liao

Copyright © 2012 Mohsen Radfar et al. This is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properlycited.

Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in VeryLarge Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowestpower consumption has been the primary motivation for increase in research in this area although other goals, such as lowestenergy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies thatprovide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digitaldesign methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-thresholddesign methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general reviewof sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.

1. Introduction

Subthreshold digital circuits are now well known to ultralow-power designers and have frequently and successfully beenused for applications such as implanted sensors and mobileperipheral processors. However, performance degradationand high sensitivity to Process/Voltage/Temperature (PVT)variations are the primary challenges that have confinedsubthreshold circuit implementations to low-activity appli-cations.

There are many recent review papers covering thesubjects of sub/near-threshold digital design and theirchallenges. The goal of this review, however, is to covera boarder range of designs, to show the interrelation ofdifferent solutions for low-power digital design and reviewthe recent updates and new advances in ultralow-power era.

Some of useful and comprehensive reviews are as follows.Authors in [1] presented a detailed review that discussedthe advantages/disadvantages of subthreshold design, andmathematical equations required for the subthreshold cir-cuits. The paper also covered variation problems brieflyand presented subthreshold design techniques for StaticRandom Access Memories (SRAM) design followed by

design techniques for multiprocessing. These discussionsmake [1] one of the most inclusive early papers.

In [2] authors have focused on variations and leakagereduction, to a greater extent, and besides DC-DC convertershave also been discussed.

In one of the recent reviews, authors (see [3]) presenteda detailed review of subthreshold design by exploringsubthreshold modelling methods, a few leakage reductiontechniques, a short discussion about pipelining/parallelising,and a good review of SRAM. A discussion on other devicetechnologies like Double metal-oxide-semiconductor field-effect transistors (D-MOSFETs) has also been included,which will not be included in this review.

Low-power designers constantly need more evidence toconsider subthreshold/near-threshold design as a reliabletechnique to overcome all challenges. This review has col-lected all important recent works in this area and has consid-ered previous reviews. Considering the above reviews, givingfurther thorough explanation of subthreshold definitionsand formulations has been left out of the scope of this paper.As a result this paper starts from challenges that have come tolight since the above-mentioned reviews and will explain therecent advances. Subsequently, this study will compare their

2 Active and Passive Electronic Components

results to find out effectiveness of these solutions and finallywill draw attentions to remaining challenges.

Subthreshold challenges are discussed in Section 2.Recent solutions for coping with PVT variations are dis-cussed in Section 2.1 and in two domains of logic and SRAMdesign. Section 2.2 covers recent solutions for handling per-formance degradation problem. Section 3 makes a discussionabout the papers that were reviewed. Section 4 proposessome future directions coming out from this review, andSection 5 concludes the paper.

2. Subthreshold Challenges

Due to ultralow voltages, subthreshold design has to usuallydeal with two major challenges namely subthreshold PVTvariations and performance degradation. The following sub-sections will address each of these challenges with the aid ofrecent studies.

2.1. Challenge 1: PVT Variation

2.1.1. Logic Design. This subsection discusses techniques thateither worsen the variations or eliminate them. The possibleside effects of these techniques while decreasing variationshave also been considered. Also, delay/performance varia-tions due to PVT variations are discussed in this subsection.

Stacking has been widely used to increase the thresholdand hence decrease the subthreshold leakage [4]. However,some drawbacks in this technique that cause variations areimportant and discussed as follows.

Firstly, although stacked devices exhibit lower currentvariability, they have a higher probability of logic failuredue to insufficient output swing especially at lower supplyvoltages [5].

It is well known that insufficient output swing can becompensated by upsizing the stacked devices and authors in[5] took its advantage to make up for degraded output levelsin stacked devices. The failure rate of 0.13% was targetedand the proposed 32-bit adder with constant yield sizingworked for lower voltages until 300 mV [5]. In addition tomaking up for PVT variations, upsizing also reduces DrainInduced Barrier Lowering (DIBL) effects and as a result leadsto lower power consumption [6]. In fact, an upsize by severalnanometres at 32 nm node in a Fan Out of 4 (FO4) invertercan reduce energy per operation by 65% at 10 MHz in 0.3 Vand by two orders of magnitude at 10 kHz in smaller than0.2 V [6].

The second problem in stacking is the reduction incurrent due to stacked devices which results in loss of speedin subthreshold region. This, however, can be offset bybody biasing [7]. For example, in [7] authors proposedcomplementary hybrid latch flip-flop (CHLFF) for ultralow-power applications and Forward Body Bias (FBB) was usedto increase the speed of the PMOS (p-channel MOSFET)stacked network. It was found that reducing the supplyvoltage to 0.3 V in an NMOS (n-channel MOSFET) stackedflip-flop (FF) causes some failures in corners. After applyingFBB to PMOS network, the supply voltage could be reduced

to 0.23 V, and the speed was increased three times (to 5 MHz)and the power consumed was 0.159 μW. The same idea wasalso applied to a sense-amplifier-based flip-flop (SAFF) in [7]and the improved Complementary SAFF (CSAFF) workedproperly for supply voltages of even less than 0.3 V andconsumed 0.144 μW with double the speed (of 5 MHz).

In lower frequencies (∼100 KHz), however, ForwardAdaptive Body Bias (ABB) increases minimum-energy dueto threshold voltage reduction [8]. Instead, reverse ABB wasused in [8] for an 8-bit multiplier and at low frequencieswith 0.2 V power supply. Moreover, it was proved to bemore efficient (70% less energy overhead) than adaptivesupply voltage scaling (AVS). It was also found that globalPT variations might suggest a wrong frequency estimationof minimum-energy point. This may result in an improperdevice/Vth selection specific for low-power (LP) or general-purpose (GP) design and lead to energy overhead higherthan 200% at the worst-case corner for energy [8].

The papers reviewed so far have examined differenttechniques using special circuits like Flip-Flops (FF), adders,or multipliers. Following papers, however, have consideredmore extensive circuits like processors. Their performance iscompared in Table 1. For example, the above claims aboutBody Biasing (BB) can be verified by looking at [9] whichuses three BB voltages: forward, zero, and reverse BBproduced by a BB Generator with a PV monitor which is aninverter (temperature variations were not studied). BB alsowas utilised to prevent failure caused by NMOS/PMOS mis-matches which in practice modulates the β-ratio adaptivelyin sub-Vth region such that the switching threshold (VM) willbe close to 1/2VDD. The inverter VM is compared against tworeference voltages. If VM < VREF1, signifying that the NMOSis stronger than the PMOS, forward BB will be then appliedto the PMOS network. Conversely, if VM > VREF2, the NMOSnetwork is forward body biased. It was also pointed outthat the application of BB can successfully alter the β-ratioand decrease the distribution of VM , leading to increasedrobustness in subthreshold circuit [9].

Authors in [10] used the same idea and proposed aconfigurable Vth balancer using BB to reduce the Vth mis-match between NMOS and PMOS transistors, so that boththe functional and the timing/speed yields were increased.This speed improvement was because both the PMOS andNMOS transistors were forward-biased when the balancerwas turned on. The Vth balancer, however, applies FBBat Typical-Typical, Fast-Fast, and Slow-Slow corners whichaccounts for a faster design but FBB could have beencancelled in such corners, especially the Fast-Fast one, tosave more energy and to be able to scale voltage even more.Voltage and Temperature variations results are also missing.The logic gates with more than four parallel transistors orfour-stacked transistors were discarded from cell library todecrease leakage current variability, and ratioed logics weresubstituted with nonratioed logics [10].

Although the above-mentioned studies decreased voltagefor specific circuits, more discussion is needed on use ofDynamic Voltage Scaling (DVS) in GP designs. DVS isconsidered inferior to Dynamic Frequency Scaling (DFS)at facing variability in subthreshold voltages when energy

Active and Passive Electronic Components 3

Table 1: Comparison of effect of different techniques for further power-performance improvements.

CriteriaReferences

[9] [10] [11] [12]

Technique ABB Vth balancing by BB Frequency scaling ABB and W + L sizing

Technology 0.13 μm 65 nm 0.13 μm 0.13 μm

Circuit 8× 8 FIR Filter JPEG coprocessorGeneral-purpose sen-sor processor

8-bit processor

Frequency98 KHz at 280 mV240 Hz at 85 mV

2.5 MHz at 400 mV 833 KHz at 200 mV 77–354 KHz

PerformanceImpact

2.6x faster at 200 mV1.25x faster at 1.2 V

Delay improvement from14 ns to 10 ns

1.09x faster due to li-brary selection

3.6x improvement at 300 mV

Energy/PowerImpact

40 nW at 85 mV0.75 pJ per cycle at 400 mV1.0 pJ per cycle at 450 mV

2.6 pJ/instructionat 360 mV

3.5 pJ/inst at 350 mV at 354 KHz515 fJ/inst at 290 mV at 77 KHz

Min voltage(mV)

85 [13] 350 200 140 (24% reduction to zero BB)

Min energyvoltage (mV)

85 350 360350 (total)290 (core)

ProsMismatchprevention

Mismatch prevention, fastFrequencyoptimisation

Preventing PT variations,L sizing

ConsTemp variations notaddressed

Not energy conservative,VT variations not addressed

Temp variations andmismatches were notfully investigated

A complicated off-chip BBsystem

efficiency is the key performance criterion [11]. In fact, it isnot limited to the choice of DVS and DFS only. A study in[11] clarifies that many of the area optimal and performanceoptimal designs, at super threshold voltages, are not suitablefor subthreshold voltages (therefore their library was re-characterised for subthreshold operations and, to maximisethe robustness, some cells were eliminated from it).

It was also reported in [12] that DVS is more energy-efficient for high target frequencies (i.e., GP designs) whileABB is more energy efficient for low target frequencies (low-power designs) over the frequency range of 30–300 kHz. Infact, [12] verifies [11] for use of DFS and approves thatDVS should be substituted in subthreshold design with moreenergy efficient techniques. Authors in [12] have again usedABB for eliminating performance variations. It was alsoproved that energy decreases by applying a Reverse BB (RBB)and increases with a FBB for subthreshold circuits.

Recent studies show that one should certainly considerthe effect of sizing in addition to BB and stacking. TheBody Biasing techniques are usually chip level whilst sizingcan be applied at both chip or block level and also alonggate width or length. For selection of the most appropriateone (chip/block, Width/Length), [12, 14] investigate someexperiments at VDD = 300 mV. It was shown that a processorwith W sizing (Proc B) and another one with both W + Lsizing (Proc C), along critical paths, are 22% and 85% faster,respectively, than a processor with minimum sizing (Proc A).But for Proc C this improvement came at %14 energy penaltywith respect to Proc A that could alternatively be achieved bya ∼7% energy penalty with increasing VDD by 20–30 mV inProc A. This suggests that although L sizing is superior toW sizing, it is only appropriate for block-level performancetuning, and not as an entire chip performance variationssolution.

Beside sizing, it has to be pointed out that a processorimplemented in a 0.18 μm technology is 7.7 times larger thana similar processor in a 65 nm technology, but analysisdiscloses that total energy is reduced by 647 times [4]. Thisis a very desirable trade-off, especially when the size of aproduct is determined by the battery size. Moreover, in [8]authors verified the same idea by stating that minimumenergy level is 30% higher in 45 nm technology (at 30 MHz)than in 130 nm technology (at 0.7 MHz).

2.1.2. SRAM Design. Although the mentioned techniquesgenerally decrease the power usage in processors by about20%, but still SRAM maintains a large proportion of powerconsumption in chips from 30% in runtime to 90% instandby time [4]. This is because usually more area (morethan 50%) is allocated to on-chip caches with every newprocessor generation. And, That is due to the attractive char-acteristics of SRAMs such as low activity and high transistordensity [15] and also due to power and performance optimi-sation as a result of placing memory as close as possible toprocessor.

Low-Power applications like wireless mobiles or sensorprocessors usually need to have two modes of working,that is, high performance and low-power/standby. The lattermode is usually the source of leakage power consumption,which mostly happens in SRAMs (especially in standbytime). It is well known in low-power design that when theactivity and voltage reduce, leakage and PVT variations willbecome the most important factors, as before. This rule isapplicable to SRAMs too and this section continues witha review of recent techniques in dealing with these issues.It is worth pointing out that leakage reduction techniquesalways help tackling PVT variations in SRAM because theyusually make SRAMs more robust and error free; therefore


some leakage reduction techniques have also been reviewed.Table 2 compares the most important criteria for SRAMdesigns.

Again, starting from stacking, authors in [4] furtherreduce leakage in the bitcell by stacking in the cross-coupledinverters of SRAM as well as other retentive gates. It wasfound that the leakage sensitivity to number of stackeddevices becomes linear for more than two stacked ones.Therefore, a stack height of two was utilised. Moreover, it wasshown that length increase of the devices in the cross-coupledinverters leads to a more area-efficient reduction in leakage.It was also observed that IMEM (Instruction MEMory) andDMEM (Data MEMory) consume 89% of the standby powerwhile the CPU consumes only 7% of the power when itis power gated. A particular architecture was proposed forstoring frequently used procedures in Instruction Read OnlyMemory (IROM) while storing application specific instruc-tions in IMEM. Because ROM can be power gated duringstandby mode, it is beneficial to put as many instructionsin IROM as possible. For further leakage reduction, in [4],a specific entry in DMEM is power gated only if a specialfree-list indicates that the entry is idle.

Apart from gating, sizing and stacking and, as will be seenin following papers, usually various write/read assists areused for preventing subthreshold region failures in SRAMs.

Write/read assists that are designed for subthresholdregion, however, might severely impact high-voltage perfor-mance [16]. To address this fact, authors in [16] proposedan SRAM with a reconfigurable three different write-assistarchitecture. By combining different circuits optimized forboth subthreshold and superthreshold voltages and employ-ing reconfigurability to switch between them, their SRAMoperated from 1.2 V down to 250 mV. Effectiveness of UltraDVS (UDVS) was also examined in [16]. Consider a memoryin low-power mode (0.4 V) and accessed every 2 μs with eachaccess causing active energy consumption. It was observedthat leakage power decreased 40x by scaling from 1.2 V(without UDVS) to 0.4 V (with UDVS). But UDVS circuitryconsumed energy as well and energy consumption in bothwith and without UDVS during low-power mode becameequal just after five accesses (or 10 μs). As a result, only if asystem stays in the low-power mode longer than 10 μs, then itis more beneficial to utilise UDVS, otherwise it will consumemore energy.

The work done in [17] (which has already been reviewedin review papers [2, 3]) is similar to [16]. A buffered readwas employed to guarantee read stability, and for enablingsubthreshold write and read, a peripheral control on boththe bit-cell voltage and the read-buffer’s foot voltage wasperformed without degrading the bit-cell’s density. Authorsalso amended the Sense Amplifiers (SAs) and, by meansof redundancy, the problem of area-offset tradeoff in SAswas mitigated, which in return decreased read errors by 5xcompared to upsizing.

Instead of using the traditional differential structure,authors in [18] used a single-ended cell with a full transmis-sion gate at one side. By the elimination of the second bitline,the cost of having one additional wordline was balanced.One obvious benefit of this design was the ability of the

bitline to be driven from rail to rail removing the necessity ofsense amplifier (which usually leads to density and variabilityproblems in differential designs). Furthermore, the noise wasisolated, during a read operation, to the single bitline whichmade this design essentially more robust to read failures thandifferential design. During the write operation, the supplyvoltage was gated on the feedback inverter to make up for thedegraded write margins. Upsizing was also utilised to handleprocess variations.

Continuing the discussion about read assists, in [19]four operational modes Retention, Read, Write, and a newproposed mode called Accessed Retention mode (AR-mode),for the SRAM cell were defined. This new mode signifiedthose SRAM cells when they were located on an accessed rowbut they were not selected to be read or written, which is anapproach similar to [16, 17]. These cells did not dischargetheir bitlines, hence saved energy. It also increased the readnoise margin of the accessed cell. In addition, it was shownthat using RBB in subthreshold region the design led to a lowleakage current for all nonselected cells. Furthermore, due tothe super-threshold voltage setting for the selected cells (forread operation) the cell access time was reduced dramaticallywhile the stability of the AR-mode cells was maintained.

Moving to write assists, in [15] authors offered a differen-tial 10T bitcell that efficiently split read and write operationsand as a result achieved high cell stability. The write assisttransistors in the cell were boosted to make up for weakwritability. Each four columns were connected to a commonground voltage driver with dynamic-threshold MOS tolessen process variations. The driver’s pull-down device wasforward-biased during read to increase the drive current.

As it was seen before, in some SRAMs other cells sharinga word line are subject to hold stability problem while acell is being written [15]. Some solutions, that implementadjacent bits as the same logic word, make the SRAMsexposed to multiple bit-soft errors (which is more critical insubthreshold SRAMs). The offered column-by-column writecontrol in [15] caused the hold stability of adjacent cells notto be affected during a write. Dynamic Differential CascadeVoltage Switch Logic (DCVSL) scheme was also used for readaccess. In this scheme, bitline leakage noise is offset by thedrive current of a keeper, providing large bitline swing. Whileholding, bitline leakage subthreshold current was consider-ably decreased because of stacked bitline leakage path.

In [9], however, instead of using read/write assists, aSchmitt-Trigger-(ST-) based 10-transistor SRAM cell wasproposed with the idea of making the characteristics of theinverter pair of the bitcell near the ideal inverter whichis fundamental for a robust cell operation. The positivefeedback from extra transistors adaptively altered the VM ofthe inverter depending on the direction of input transition(0 → 1 input transition or vice versa). The proposed STbitcell took advantage of differential operation and delivereda better noise immunity.

Although cell design plays an important role in decreas-ing delay and energy, the SRAM architecture is also anothereffective part. Multi-tier SRAMs in System On Chip (SOC)design is a common technique to prevent costly out of chipmemory accesses as well as to increase performance.


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Besides, the low speed of subthreshold SRAMs limits theability of subthreshold cores whose speed is usually morethan subthreshold SRAMs [22]. As a result, a discussionabout optimum subthreshold SRAM architecture is neces-sary.

Authors in [22] observed that optimal L1 size increasesfrom 64 KB to 128 KB for targets below 76 MHz since L2starts to relatively consume more energy. Even though alarger L1 causes more energy per access, the energy savedfrom decreasing L2 accesses (in lower frequencies andbecause of larger L1) outweighs any increase in the L1. More-over, it was observed that optimal energy consumption isobtained at near-threshold region (400–500 mV) and at afrequency of ∼15 MHz–50 MHz.

Another example is [23] in which by means of a multi-level SRAM, a high-performance design has become possible.The proposed design supported ultra VDD scaling from anominal to sub/near threshold voltages. In order to reduceoff-chip traffic and improve performance and energy effi-ciency, a large on-chip frame memory (FM) of 10Mbit wasembedded, which allowed keeping Video Graphics Array(VGA) frames. However, as discussed before, when dealingwith VDD scaling, usual SRAMs cannot work reliably below700 mV. Therefore, a Hybrid Memory Architecture (HMA)was proposed to decrease the access rate from processorsto the FM by employing the data locality in the scratchpadmemory (SM). Within the proposed HMA, there existedthree characterized memories to hold the data: (1) ACCUregister: short-term data; (2) SM: intermediate-term data;(3) FM: long-term data.

On the other hand, near-threshold operation in logicdecreases frequency compared to super-threshold one. Thisspeed degradation, however, suggests several new and inter-esting design opportunities about memory system selection[24]. Firstly, memory technologies (like 130 nm or 180 nmdevices as discussed in Logic Design Section 2.1.1) anddesigns that are slower and more energy efficient cansubstitute timing critical memory designs. This will help todecrease the total energy of the chip while memory is work-ing in super-threshold voltage and logic in near-threshold.Furthermore, multiple accesses to memory can be carriedout in one near-threshold clock cycle of logic. This meansthat more parallel data can be fetched and be processed inone cycle. And finally, the slower memory possibility allowscaches, register files, and other elements that are originallydesigned to compensate long memory latency, to be turnedoff or removed. Therefore, a pipeline was implemented sothat in a single cycle of the Single Instruction Multiple Data(SIMD) pipeline, multiple memory access was possible. Itwas also showed that wider SIMD widths do not alwaysprovide less energy consumption because of the additionalhardware and increase of critical path delay.

2.2. Challenge 2: Performance Degradation. As stated inintroduction, performance decrease is another challenge insubthreshold circuits which is usually addressed by whetherparallelism or pipelining. As it will be seen later, pipeliningis popular in super-threshold designs because it usuallyneeds many circuitries for controlling the pipeline which

when operated in subthreshold voltages will result in a leakysystem. As a result, near-threshold voltage operation wasconsidered for pipelined circuits by many researchers. Inthe super-threshold region, energy is extremely sensitive toVDD due to the quadratic dependence of active energy onVDD. Therefore, voltage scaling down to the near-thresholdvoltages yielded 10x energy reduction at the expense ofnearly 10x performance decrease [25]. Interestingly, energyreduces by only∼2x when VDD is scaled down from the near-threshold region to the subthreshold region, but at the sametime delay rises dramatically by 50–100x. As a result, authorsin [25] concluded that huge amount of performance couldbe recovered by just backing off a bit and working in near-threshold region.

More about near-threshold design: authors in [26] alsofound that the rate of delay change with respect to supplyvoltage change (δtd/δV) is very huge in near-thresholdregime. A 200 mV change in supply voltage from 0.3 V to0.5 V leads to approximately 30x change in performance. Theconcept was proved by offering a two VDD design that wereonly 50 mV apart and as suggested a small voltage supplyrise caused very considerable speedup. Dual-VDD assignmentwas applied at the level of entire rows in the layout in orderto restrict the surplus cost of dual voltage distribution andno level shifters were utilised because these dual voltageswere not more than 100 mV apart. It was showed that themaximum speed-up (with VDDL = 0.4 V and VDDH =0.45 V) was ∼45%, which was equal to what is obtained bypowering up all cells to the VDDH.

Above studies demonstrated that near-threshold voltagesare necessary for higher speed demands. Keeping this factin mind, this section continues with articles that have triedto increase performance more by parallelism and pipeliningwithin sub/near-threshold region.

2.2.1. Parallelising. One good example of parallelism hasbeen illustrated in JPEG cores in [10]. With sub/near thresh-old techniques explained in Logic Design Section 2.1.1, itbecame best suitable for low-energy and medium-frequencyapplications, such as mobile image processing.

A comprehensive study of parallelism can be found in[22] which studies all the main factors influencing the energyof a system such as size of L1 cache and cluster, number ofclusters and VDD and Vth selection within a cluster. Firstly,memory tends to operate at speeds faster than the core atsubthreshold region, and therefore the idea of using morethan one cluster that share one memory was proposed. It wasshown that the energy optimal point is 2 cores per clusterwith 2 clusters. This point brought about a 53% increasein energy efficiency compared to traditional multiprocessordesigns. For targets above 150 MHz, the optimal numberof clusters increased from 2 to 3. Interestingly, a designwith increased number of clusters, and therefore total cores,required less energy than a design with a scaled voltage of thesmaller number of cores and with same constrains.

2.2.2. Pipelining. Pipelining in subthreshold region leads toleaky circuits, as discussed before, and as a result, if still asubthreshold pipeline is necessary, it has to be very simple.


Table 3: Comparison of pipelining strategies.

CriteriaReferences

[27] [28] [29] [30] [31]

TechniqueInstructionisolation

DVFS and criticalpath isolationunder temperaturevariations

Variable clock intimes of processvariations

Soft edge flip-flop

Flow-through latchbetween stages andselection of differ-ent voltages

Technology 45 nm BPTM 70 nm 90 nm PTM 65 nm PTM 32 nm

Circuit

32-bit in-order 5-stage dual-pipelineprocessor withIA32

in-ordersuperscalarpipeline withthe Alpha ISA

32-bitmicroprocessor

34-bit pipelinedadder

6 stages pipelinedFPU

Frequency 1.25 GHz 1.5–3 GHz ∼0.1–1 GHz 2–2.5 GHz

Improves BIPS/Wby 47% (actual fre-quency notreported)

Area and/orfrequency impact

28% performancereduction due to ins-truction isolation

∼4.5% area over-head /3.4–11% fre-quency overhead

2.6% areaoverhead/13%–50%performance impro-vement

5–20%performanceimprovement

40% performanceimprovement

Energy/Temperatureimpact

13% power reduc-tion

Reduces tempera-ture by 6.6–9%

3% energy overhead19% power saving(4.9 mW)

Not reported

Min voltage740 mV for ADD680 mV for XORand AND

700 mVScaling from 1.2 V to1 V

Scaling from1.2 V to 1.05 V(5–20%VDD

reduction)

Scaling from 1.4 Vto 0.95 V

Pros DVS enabledTemperaturevariations tolerant,DVFS enabled

Low energy andarea overhead

Rather large powerreduction

Rather largeperformanceimprovement

ConsPerformancereduction

PV variations notdiscussed

Not supporting verylow voltages

Not supportingvery low voltages,PVT variations notdiscussed

Not supportingvery low voltages

For example in [32] considering subthreshold operation dif-ficulties like PVT variations, it was concluded that variationsare distributed over the length of a path which makes shallowpipelines with high-FO4 delay per stage more advantageous.Hence, in [11] a 2 stage pipeline implementation was selectedfor the processor.

Because of above study and as review of different litera-ture shows, discussion about low-power pipelining is morelogical in near-threshold than subthreshold era and the restof this subsection focuses on near-threshold region.

Generally, there are three main sources of energy con-sumption in pipeline: instructions, circuits (including dat-apath, registers, and control), and synchronisation plan. Asit will be explained in detail, each instruction has its ownspecific energy usage. And depending on synchronisationstrategy running between stages, active energy differs. WhileSection 2.1.1 covered data path and control circuits, somespecific concerns are discussed in this subsection. Moreover,as some techniques useful for near-threshold pipelining(such as how to cope with PVT variations in pipeline) werelocated in low power super-threshold researches, inevitablythese studies have also been included (see Table 3).

Starting from instruction, the first discussion will beabout isolation. It has been reported in [27] that as supplyvoltage reduces, ADD instruction operates correctly until0.74 V, while logical instructions (XOR and AND) tolerateVDD scaling down to 0.68 V. Therefore it was proposed thatisolating ADD operation lets the ALU operate at 0.68 V byproviding 2-cycles for ADD operation and 1-cycle for otherinstructions, resulting in more power savings. For ADD, theALU saved another 23% power because halving the frequencyat the reduced VDD also decreased power consumption at thecost of performance degradation.

Authors in [28] have considered both instructions anddatapath. Any possible delay failure in specific instructionssuch as ADD (under process variation and voltage scaling)was prevented by adaptively extending the clock period totwo-cycles while all standard operations were single cycle.Execution datapath was changed so that whenever a failurein operations became probable, those operations could beexecuted in two cycles. The prediction was done by utilisinga small predecoding logic. In addition, if the temperatureexceeded a threshold value, a lower supply voltage (VDDL)was applied to the execution unit. Once the temperature fell


below the threshold, nominal supply (VDDH) was reapplied.It is also interesting that during execution, only EX stagereceived VDDL while all other pipeline stages received VDDH.

In synchronisation, it is often attempted to modify theclock so that the slack time in datapath is used for compen-sation of variations or voltage scaling. For example in [29]by considering instruction, datapath and clocking, authorsassociated a variable delay with each pipeline stage, and atable of delays were adjusted to meet the delay of each specificinstruction. Whenever the delays of all stages were elapsed,a new clock was created and therefore, some clocks wereshortened and the overall speed was increased. This variabledelay unit was located close to the corresponding datapathto be subject to the similar PVT conditions. A delay selectorreads the inputs of the pipeline to choose appropriate delayvalue from operation selection table.

In [30], with focusing on synchronisation plan, a new softedge flip-flop (SEFF) was proposed to postpone the clockof the master latch to produce a window along which bothmaster and slave latches were active. This window, whichis called the transparency window, allowed timing slacks topass between adjacent pipeline stages. The delayed clock wascreated by employing an inverter chain and sizing them inorder to maintain the desired delay. Available slacks at stageswere passed to the previous stages, providing previous stageswith surplus of borrowed time. Since positive slacks wereavailable in all stages of the pipeline, as a result of this timeborrowing, the clock could be increased or circuit voltagecould be decreased to reduce the power consumption.

In [31], a design was presented with a flow-through latchbetween two stages so that clocking of that latch added anextra half cycle to the pipeline. This half cycle provided extratime borrowing to absorb delays due to process variation inthe previous stages. Gating the latch and switching betweenthe modes with and without the extra latency allow forpostfabrication tuning. A voltage interpolation was also usedto deliberately select different effective voltages needed foreach stage to run at a single nominal frequency. Therefore, ifpipeline ran slowly due to process variation, there were twoways to obtain the nominal operating frequency. One optionwas connecting more stages to VDDH so that the effectivevoltage increased. Another option as discussed before wasextending two stages with a latch in between to a single stageto provide additional time for execution while decreasingenergy by switching more stages to VDDL.

Considering the effect of clock in power consumption,as another synchronising plan, it should be pointed out thatasynchronous pipelines are playing a vital role in recentdesigns. Although they are beyond the scope of this review,taking the idea of eliminating the clock in synchronisedworld, one can find [33] with Moebius pipeline proposed.In this pipeline, a stage sent a COMPLETE signal to theprevious stage when the computation was done and at thesame time held the result until the COMPLETE signal fromthe next stage came. This way in addition of saving clockpower, the available slack in the path was utilised veryefficiently and moreover variations were dealt with in a betterway.

This subsection is concluded with a survey in Pipelining[34]. This survey states that the single-issue in-order archi-tecture, as also the case for above studies, is appropriate forvery low-energy design points, while the quad-issue out-of-order is only suitable at very high-performance applications[34]. It was also discovered that the dual-issue in-order andout-of-order processors were efficient for many differentkind of design performances.

3. Discussion

In Section 2.1.1, the major problems of stacking, a techniquewhich is used for decreasing leakage, were addressed byupsizing [5] and BB [7]. BB was also utilised by [9, 10, 12]for dealing with variations. In [12] also BB was preferred overDVS for lower frequencies. DVS was also inferior to DFS asreported by [11]. Moreover, L sizing was proved in [14] to bemore power/performance efficient than W sizing but unlikeBB which was employed at whole chip level, L+W sizing wasonly useful at block level. Finally using older technologies forsubthreshold design was encouraged by [4, 8] which resultsin a huge energy saving.

In SRAM Design Section 2.1.2, again stacking was usedby [4] for leakage reduction and effects of upsizing and gatingwere studied for decreasing leakage.

Different read/write assists methods were discussed likein [16] reconfigurable write assist, supported UDVS fromsuper- to subthreshold voltages. For increasing read stability,new read-buffer techniques were used in [16, 17, 19]. Readproblem was addressed by a novel single-ended cell designin [18] and the SA with common problems of density andvariability were also eliminated.

Weak writability was made up for in [15] by a new writeassist technique and multiple-bit soft error in subthresholdvoltages was considered. In [9], ST based design removed theread/write assist necessity.

Power/performance optimum cache sizes and hierarchi-cal SRAM designs were discussed in [22, 23], respectively.Finally the benefit of old technologies together with near-threshold voltage for SRAM design was again emphasised in[24].

Moving to performance degradation Section 2.2, authorsin [25] suggested near-threshold voltages for better perfor-mance results while benefiting from its low power advan-tages. Avoiding costly level shifters, in [26] near-thresholdvoltage gained the same speed-up as super-threshold volt-ages. Seeking for more performance, authors in [10] usedparallel cores with sub/near-threshold voltages. Looking forpower/performance optimum number of cores, in [22] 2cores per cluster with 2 clusters for targets below 150 MHzwere recommended.

In processors world, however, pipelining is crucial butin [32] it was pointed out that subthreshold design limitspipelines to 2 stages when variations are considered. There-fore, near-threshold design was again highlighted.

Some techniques for low-power pipelining, useful fornear-threshold voltages, then were necessary. In [27] morepower-consuming instructions were isolated which helpedto save more energy. The same idea was used in [28] which


prevented the being executed instructions from failure intimes of variations.

Exploiting time slacks in stages was the most importanttechnique for handling variations in pipelines. In [29],for example, different delays due to differences betweeninstructions was utilised and as it will be seen, many kinds ofFFs have been designed to benefit from time slacks. In [31]also time borrowing was done using a latch inserted inside astage which also helped in postfabrication tuning.

Finally in [34] it was acknowledged that the single-issue in-order architecture is appropriate for very low-powerdesign goals.

This suggests that complicated instructions and architec-tures are not appropriate for low-power pipelines as they leadto a leaky and error-prone structure.

It can be concluded from Table 1 that power consump-tion can be reduced by using Body Biasing for compensatingthe variations and mismatch between Vth of pullup and pull-down network. In SRAM designs using reconfigurability andemploying different read/write assists to isolate nonaccessedcells are important factors for both speed and power inaccord to Table 2. Table 3 also showed that, for optimisingpower and speed, using synchronisation strategies is asimportant as instruction isolation.

This review also presents future directions in next sectionbut discussion about time borrowing is necessary beforeproceeding (readers are referred to [25, 35] for a completeunderstanding of error detection techniques in pipelines).First of all it should be noted that, under process variations,the SEFF delay should be changed. It means a techniqueshould evaluate variation and apply different postsiliconSEFF delays so that variations are compensated. A systemwhich can calculate variations should be designed andintegrated. Razor [36] is such a technique that has alreadybeen used. However, Razor method might pick up the wrongfrequency. For example, if an AND is followed by an ADD,as ADD is more prone to variations and tends to cause error,Razor detects this error and increases clock period. However,the subsequent instruction, which is an AND, does not needthis frequency reduction.

One way to find out if an FF has caught true data,as Razor does, is comparing the data with a delayed clockdata. Another way, however, is calculating if an incomingdata has violated the setup and hold times of FF and, basedon that, latching an erroneous data, as done in [37]. Thisidea is actually similar to Razor II [38] and has the sameproblem as Razor. Moreover, Razor also needs a minimumshort path delay because when a clock is triggered, shadowlatch at Razor will be waiting for a late coming signal, bymeans of a delayed clock, but at same time the short pathresults may change the shadow latch data, before critical pathof previous clock discloses its data. Furthermore, there is aprobability that metastability propagates through the errordetection logic and causes metastability of the restore signalitself, which has been addressed in next versions by addingmore circuitry like [39]. In [35] (which is an advanced formof [37]) a new FF is proposed that can handle both shortand critical path errors and moreover the FF can recovercritical path errors, like Razor, and also can predict short path

errors. But this technique incurs a large area and is suitablefor super-threshold voltages and it still has the same problemas discussed before.

Another problem of these in situ monitors is theiractivity, area and energy overhead. Authors in [40] use thehigh clock phase as the error-detection window for the shortpath problem, where minimum delay paths must not arrivebefore the falling clock edge. Latch transparency feature wasalso taken advantage of and by above assumption, the extramaster latch of FF was eliminated and energy was reducedand metastability was tackled using transparency.

Using instruction isolation and due to instruction spe-cific delays, however, the rate of violation resulting fromdifferent instructions delays will be cancelled and just thoseviolations caused by temperature will emerge. Authors in[27] present a comprehensive research by putting all theseidea together along with using error correction (the details oferror correction scheme was not published however) for itspipeline and LUT for keeping the delay of different instruc-tions. The next section will present the future directions innear-threshold and subthreshold design techniques.

4. Future Directions

The requirement of different delays by different instructionsmeans that a transparency window is needed whose sizecan be changed by different instructions. Employing SEFFsfor this purpose is a unique technique that to our bestknowledge has never been used so far. By designing this newFF, a transition detector can detect long path delays duringtransparency window and therefore setting an error signal fortuning the size of window. Moreover, different instructionsalso lead to different delays being applied which as a resultdecrease the rate of errors.

Like the approach in [27], an instruction delay can bepredicted, with a Look-Up Table (LUT), and be applied toSEFF and if timing is violated because of error detection,LUT entry should be updated with an increased delay.This LUT can be implemented in a ROM as it keeps datapermanently after once filled. In another technique, if justprocess variations are of concern, error detection can beeliminated by just postsilicon evaluations and this way errordetection circuitry can be clock gated or totally discarded byan offchip error detection scheme.

Another opportunity of performance improvement canbe created by employing instruction isolation using an extratransparent FF (TFF) in EX stage of pipeline, so that longdelay instructions can use two stages and short delays useone stage (See Figure 1) and even more stages are applicable.Depending on situation, these TFFs can be transparent orfunctional. This way it is not necessary to stall the pipelinefor energy consuming instructions to be completed by twocycles (or more). Also, a short instruction can be completedquickly, and depending on other instructions on pipeline,they can go through the transparent FFs without clocking(which again saves energy). Having said that, the EX stagedesign should be changed so that long instructions are splitto two (or more) parts in order to implement each part in


Ex1 Ex2Dec

LUT

Clk

Control

Err.Err.

Trans.

Clk Gen

Update

Inst. C1 C2 C3 C4 C5ADD Ex1 Ex2

WB

AND Ex1 TFF WBAND Ex1 TFF WB

WB

Inst. C1 C2 C3 C4ADD Ex

WB

ANDEx

WB

ANDEx WB

Err. Err.

Trans. = 0

Trans. = 1

Figure 1: Proposed architecture with a sample instruction flow.When Trans. = 1, pipeline is working in LP mode, otherwise thehigh-speed mode is applied.

one stage of pipeline with almost the same delay. Moreover,for taking advantage of DVS, the FFs can be one of those witherror correction and time borrowing features [40]. When thepipeline needs more speed and can handle higher voltages,the TFF becomes transparent and pipeline can work withhigher frequencies. And once pipeline needs to consume lesspower and lower frequencies can be tolerated, by activatingTFF, DVS helps the pipeline to work with the lowest voltagepossible. When the optimum voltage is applied, the errordetection scheme helps the pipeline with DFS to handlePVT variations. LUT can also be used to keep record ofappropriate delays for different instructions.

5. Conclusion

Looking at different aspects of low-power design, onecan immediately find out that, apart from emerging newdevice technologies, it is impossible to maintain such adesign without approaching to near threshold/subthresholdregions. However, these regions bring about many issues thatresearchers have been engaged in for recent years. Theseproblems include leakage increase, PVT vulnerability andperformance degradation. This paper tried to present a com-plete review of recent attempts for solving these problemsand compared them to find out which ones have been moreeffective. This work also proposes future directions based onthe outcome of the review and currently the paper authorsare involved in implementation of these proposed directions.

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