rev description date approved add codec 12/21/2010...

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SPECTRUM DIGITAL INCORPORATED

514202-0001

Thursday, March 22, 2012 1 57

B

SMART GRID EVM

TITLE PAGE

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21 22 23 24 25 26 27 28 29 30

31 32

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ENGR

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DATE

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DATE

ENGR-MGR

MFG

7

DWN

DATE8

DATE

10

SH

DATE

CHK

RLSE

APPLICATION

REV

3 5

NEXT ASSY

DATE

6

DATE

9

QA

USED ON

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15

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AAAA

R.R.P.

T.W.K.

R.R.P.

R.R.P.

C.M.D.

R.R.P.

R.R.P.

10/21/2010

16

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B A AB

10/21/2010

10/21/2010

10/21/2010

10/21/2010

10/21/2010

10/21/2010

I2C ADDRESS MAP

SCHEMATIC CONTENTSSHEET01 - TITLE PAGESHEET02 - OMAP-L138 McASPSHEET03 - OMAP-L138 SATA INTERFACESHEET04 - OMAP-L138 SERIAL I/OSHEET05 - OMAP-L138 VIDEO PORT OUTSHEET06 - OMAP-L138 VIDEO PORT INSHEET07 - OMAP-L138 USB 2.0 PORTSHEET08 - OMAP-L138 USB 1.0 PORTSHEET09 - OMAP-L138 EMIF ASHEET10 - OMAP-L138 DDR2 EMIFSHEET11 - OMAP-L138 JTAG/CLOCKSSHEET12 - OMAP-L138 POWER PINSSHEET13 - OMAP-L138 I/O POWER PINSSHEET14 - OMAP-L138 GROUND PINSSHEET15 - DDR2 MEMORYSHEET16 - SPI BUFFERS ISHEET17 - SPI BUFFERS IISHEET18 - SPI FLASHSHEET19 - I2C EEPROMSHEET20 - NANDSHEET21 - MDIO MUXSHEET22 - MII ETHERNET PHYSHEET23 - ETHERNET CONNECTORSHEET24 - USB-2-ETHERNETSHEET25 - MCASP MUXINGSHEET26 - AUDIO CODECSHEET27 - EXTERNAL UARTSSHEET28 - RS232 CONNECTORSHEET29 - GPS RS232

Initial schematic for layout

DESCRIPTIONREV APPROVEDDATE

10/21/2010 RRPA

BASE( HEX) BASE BINARY I2C ADDRESS TABLE SHEET

I2C EEPROM0X50 101 0000W

TPS65070 PMIC100 1000W 0X48

TLV320AIC3106001 1000W

TCA6416 - U34 - User Switches

0X18

0X21 010 0001W

POWER MEASUREMENT - NOT ON OMAP-L138 CPU BUS

INA219 - 5V INPUT100 0000W

100 0001W

100 0010W

100 0011W

100 0100W

100 0101W

100 0110W

INA219 - PMIC 3V3

INA219 - PMIC I/O VOLTAGE ( 1V8/3V3 )

INA219 - PMIC 1V2

INA219 - PMIC 1V2 LDO

INA219 - PMIC 1V8 LDO

INA219 - RTC 1V2 LDO EXTERNAL

A A A A A A

33 34 35 36 37 38

REVISION STATUS OF SHEETS

A A A A A A

43 44 45 46 47 4841 42

A AREV

SH

51

AREV

SH

39

49

40

50

A A

A A

SCHEMATIC CONTENTS CONT'DSHEET25 - MMC/SD CONNECTORSHEET31 - BIT MAPPED LCD INTERFACE SHEET32 - USB CONNECTORSSHEET33 - USER LEDS/SWITCHESSHEET34 - BIT RESETS AND I/OSHEET35 - BOOT SWITCHESSHEET36 - JTAG EMULATION CONNECTORSSHEET37 - EMIF EXPANSION CONNECTORSHEET38 - VPIF EXPANSION CONNECTORSHEET39 - CC INTERFACE ISHEET40 - CC INTERFACE IISHEET41 - CANSHEET42 - ZERO CROSSING DETECTORSHEET43 - ADC FOR PLCSHEET44 - PLC INTERFACESHEET45 - PLC MODULES 1SHEET46 - PLC MODULES 2SHEET47 - ISOLATION POWER SUPPLIESSHEET48 - CODEC ISOLATIONSHEET49 - TLV320AIC34SHEET50 - TLV320AIC34 CHANNEL 2SHEET51 - ANALOG VOLTAGE FRONT ENDSHEET52 - ANALOG CURRENT FRONT ENDSHEET53 - POWER ROUTERSHEET54 - RTC POWERSHEET55 - TPS65070 PMICSHEET56 - POWER

ADD CODEC 12/21/2010 RRPB

MULTIPLE CHANGES 8/21/2011 RRPC

COMPLIANCE CHANGES 3/02/2012 RRPD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AXR0/ECAP0_APWM0/GP8[7]/MII_TXD[0]/CLKS0AXR1/DRX0/GP1[9]/MII_TXD[1]

AXR4/FSR0/GP1[12]/MII_COL

AXR7/EPWM1TZ[0]/GP1[15]

AXR11/FSX1/GP0[3]

AXR2/DR0/GP1[10]/MII_TXD[2]

CPU_AXR[5]

CPU_ACLKX

AXR3/FSX0/GP1[11]/MII_TXD[3]

AFSX/GP0[12]

CPU_AXR[0]

CPU_AXR[4]

AHCLKX/USB_REFCLKIN/UART1_CTS/GP0[10]CPU_AHCLKX

AXR12/FSR1/GP0[4]

ACLKX/GP0[14]

AXR5/CLKX0/GP1[13]/MII_TXCLKAXR6/CLKR0/GP1[14]/MII_TXEN

AXR1/DX0/GP1[9]/MII_TXD[1] [22]AXR2/DR0/GP1[10]/MII_TXD[2] [22]

AXR6/CLKR0/GP1[14]/MII_TXEN [22]AXR5/CLKX0/GP1[13]/MII_TXCLK [22]AXR4/FSR0/GP1[12]/MII_COL [22]

AXR3/FSX0/GP1[11]/MII_TXD[3] [22]

AXR0/ECAP0_APWM0/GP8[7]/MII_TXD[0]/CLKS0 [22]

AXR12/FSR1/GP0[4] [25]AXR11/FSX1/GP0[3] [25]AFSX/GP0[12] [25]ACLKX/GP0[14] [25]

AHCLKX/USB_REFCLKIN/UART1_CTS/GP0[10] [25]

PLC_PWM2 [45]

PLC_PWM1 [45]

AXR13/CLKX1/GP0[5] [25]AXR14/CLKR1/GP0[6] [25]

L138_BIT_I2C_SDA_IN [48]

L138_BIT_I2C_SDA_EN [48]

PLC_AFEP16 [45,46]PLC_AFEP14 [45,46]

L138_BIT_I2C_SCL [48]L138_BIT_I2C_SDA_OUT [48]

Size:

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A


514202-0001


B

SMART GRID EVM

McASP/MII Ethernet MAC

TO MII ETHERNET

POWER GROUP A

OMAP-L138

U22-1

ACLKR/GP0[15] A1

ACLKX/GP0[14] B1

AFSR/GP0[13] C2

AFSX/GP0[12] B2

AHCLKR/UART1_RTSn/GP0[11] A2

AHCLKX/USB_REFCLKIN/UART1_CTSn/GP0[10] A3

AXR10/DR1/GP0[2] D4

AXR11/FSX1/GP0[3] C5AXR12/FSR1/GP0[4] C4

AXR13/CLKX1/GP0[5] B3AXR14/CLKR1/GP0[6] B4

AXR15/EPWM0TZ[0]/ECAP2_APWM2/GP0[7] A4

AXR7/EPWM1TZ[0]/GP1[15] D2

AXR8/CLKS1/ECAP1/APWM1/GP0[0] E4AXR9/DX1/GP0[1] C3

AXR0/ECAP0_APWM0/GP8[7]/MII_TXD[0]/CLKS0 F3AXR1/DX0/GP1[9]/MII_TXD[1] E1

AXR2/DR0/GP1[10]/MII_TXD[2] E2AXR3/FSX0/GP1[11]/MII_TXD[3] E3

AXR4/FSR0/GP1[12]/MII_COL D1AXR5/CLKX0/GP1[13]/MII_TXCLK D3AXR6/CLKR0/GP1[14]/MII_TXEN C1

R361 22

R365 22

R359 22

R362 22R364 22

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4

4

3

3

2

2

1

1

D D

C C

B B

A A

SATA_RXP

SATA_RXN

SATA_TXNCON_SATA_RXPCON_SATA_RXN

SATA_TXP CON_SATA_TXPCON_SATA_TXN

SATA_REFP

SATA_CLKP

SATA_CLKN

SATA_REFN

VCC_1V2_LDO

VCC_1V8_LDO

3V3_EVM

3V3_EVM

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A


514202-0001


B

SMART GRID EVM

SATA INTERFACE

DIFFERENTIAL PAIR 100 OHM DIFFERENTIALIMPEDANCESHORT AND STRAIGHT AS POSSIBLE,MINIMUM NUMBER OF VIAS

Pin # Function 1 Ground 2 A+ (Transmit) 3 A- (Transmit) 4 Ground 5 B- (Receive) 6 B+ (Receive) 7 Ground - coding notch A 7-pin Serial ATA data cable

DIFFERENTIAL PAIR 100 OHM DIFFERENTIALIMPEDANCESHORT AND STRAIGHT AS POSSIBLE,MINIMUM NUMBER OF VIAS

C930.01uF

C2650.1uF

R38710K

C95

1.0uF

E6NFM21PC474R1C3D

13

2

C911uF

C277

0.01uF

R161NO-POP

C901uF

C274.1uF

C1000.1uF

U32

CCLD-033-50-100.00

E/D1

NC 2GND3

VoD+ 4

VoD- 5

VCC 6

E7NFM21PC474R1C3D

13

2 C1040.001uF

L15Ferrite Chip

C1030.001uF C83 .1uF

C273.1uF

C89

0.1uF

C275.1uF

OMAP-L138

U22-15

NC.M3 M3

SATA_REFCLKN N1

SATA_REFCLKP N2

SATA_REGN3 SATA_RXN L2

SATA_RXP L1

SATA_TXN J2

SATA_TXP J1

SATA_VDD.2N4

SATA_VDD.4P2

SATA_VDD.1M2

SATA_VDDRP3

SATA_VSS.1H1

SATA_VSS.3K1

SATA_VSS.5L3SATA_VSS.6M1

SATA_VSS.2H2

SATA_VSS.4K2

SATA_VDD.3P1C920.01uF

C272.1uF

J10

SATA HEADER 7

11223344556677

MH1 8

MH9 9

C271

560pF

C1010.1uF

C84 .1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RSVD/RTC_ALARM]/UART2_CTSn/GP0[8]/DEEPSLEEPn

T_CPU_SPI1_CLK/GP2[13]

CPU_SPI1_SOMI/GP2[11]CPU_SPI1_SOMI/GP2[11]

CPU_SPI1_ENAn/GP2[12]

CPU_SPI1_SIMO/GP2[10]CPU_SPI1_SIMO/GP2[10]CPU_SPI1_CLK/GP2[13]

SPI0_ENAn/WPWM0B/MII_RXDVCPU_SPI0_CLK/EPWM0A/GP1[8[/MII_RXCLK

SPI0_SIMO/EPWMSYNCO/GP8[5]/MII_CRSSPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER

SPI0_CLK/EPWM0A/GP1[8[/MII_RXCLK

SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3]

SPI0_SCS[2]/UART0_RTSn/GP8[1]/MII_RXD[0]/SATA_CP_DET

SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2]SPI0_SCS[3]/UART0_CTSn/GP9[2]/MII_RXD[1]/SATA_MP_SWITCH

SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12

CPU_SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12CPU_SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12

SPI1_SCS[3]/UART1_RXD/SATA_LED/GP1[1]SPI1_SCS[2]/UART1_TXD/SATA_CP_POD/GP1[0]

SPI1_SCS[4]/UART2_TXD/I2C1_SDA/GP1[2]SPI1_SCS[5]/UART2_RXD/I2C1_SCL/GP1[3]

I2C0_SDAI2C0_SCL

AMUTE/UART2_RTSn/GP0[9]

CPU_SPI1_ENAn/GP2[12] [16]CPU_SPI1_CLK/GP2[13] [16,17]CPU_SPI1_SIMO/GP2[10] [16,17]CPU_SPI1_SOMI/GP2[11] [16,17]

SPI0_ENAn/EPWM0B/MII_RXDV [22,37]SPI0_CLK/EPWM0A/GP1[8]/MII_RXCLK [22,37]SPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER [22,37]SPI0_SIMO/EPWMSYNCO/GP8[5]/MII_CRS [22,37]

SPI0_SCS[2]/UART0_RTSn/GP8[1]/MII_RXD[0]/SATA_CP_DET [22,37]SPI0_SCS[3]/UART0_CTSn/GP9[2]/MII_RXD[1]/SATA_MP_SWITCH [22,37]SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2] [22,37]SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3] [22,37]

SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12 [21,38]SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 [21,38]

RSVD/RTC_ALARM]/UART2_CTSn/GP0[8]/DEEPSLEEPn [28]

CPU_SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12 [16]CPU_SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12 [17]

SPI1_SCS[2]/UART1_TXD/SATA_CP_POD/GP1[0] [46]SPI1_SCS[3]/UART1_RXD/SATA_LED/GP1[1] [46]

I2C0_SDA [19,26,33,34,37,38,46,55]

SPI1_SCS[5]/UART2_RXD/I2C1_SCL/GP1[3] [28]SPI1_SCS[4]/UART2_TXD/I2C1_SDA/GP1[2] [28]

I2C0_SCL [19,26,33,34,37,38,46,55]

AMUTE/UART2_RTSn/GP0[9] [28]

Size:

Date:

DWG NORevision:

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Title:

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A


514202-0001


B

SMART GRID EVM

AM1808 SERIAL I/O

TO MII ETHERNET

SPI FLASH AND CC MODULE

LINUX CONSOLE

UART1

I2C INTERFACE

POWER GROUP A

OMAP-L138

U22-6

RSVD/RTC_ALARM/UART2_CTSn/GP0[8]/DEEPSLEEPn F4

SPI0_ENAn/EPWM0B/MII_RXDV C17

SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12 D17SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 E16

SPI0_SCS[2]/UART0_RTSn/GP8[1]/MII_RXD[0]/SATA_CP_DET D16SPI0_SCS[3]/UART0_CTSn/GP8[2]/MII_RXD[1]/SATA_MP_SWITCH E17

SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2] D18SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3] C19

SPI1_ENAn/GP2[12] H16

SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12 E19SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12 F18

SPI1_SCS[2]/UART1_TXD/SATA_CP_POD/GP1[0] F19SPI1_SCS[3]/UART1_RXD/SATA_LED/GP1[1] E18

SPI1_SCS[4]/UART2_TXD/I2C1_SDA/GP1[2] F16SPI1_SCS[5]/UART2_RXD/I2C1_SCL/GP1[3] F17

SPI1_SCS[6]/I2C0_SDA/TM64P3_OUT12/GP1[4] G18SPI1_SCS[7]/I2C0_SCL/TM64P2_OUT12/GP1[5] G16

SPI0_CLK/EPWM0A/GP1[8]/MII_RXCLK D19

SPI0_SIMO/EPWMSYNC0/GP8[5]/MII_CRS C18SPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER C16

SPI1_CLK/GP2[13] G19SPI1_SIMO/GP2[10] G17SPI1_SOMI/GP2[11] H17

AMUTE/UART2_RTSn/GP0[9] D5

R325 22

R324 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LCD_AC_ENB_CSn/GP6[0]

UART_INTA

BOOTMODE[5][35]BOOTMODE[6][35]BOOTMODE[7][35]

BOOTMODE[2][35]

BOOTMODE[0][35]

BOOTMODE[4][35]BOOTMODE[3][35]

BOOTMODE[1][35]

VP_DOUT[15]/LCD_D[15]/UPP_XD[7]/GP7[7][31,38]VP_DOUT[14]/LCD_D[14]/UPP_XD[6]/GP7[6][31,38]VP_DOUT[13]/LCD_D[13]/UPP_XD[5]/GP7[5][31,38]VP_DOUT[12]/LCD_D[12]/UPP_XD[4]/GP7[4][31,38]VP_DOUT[11]/LCD_D[11]/UPP_XD[3]/GP7[3][31,38]VP_DOUT[10]/LCD_D[10]/UPP_XD[2]/GP7[2][31,38]

VP_DOUT[9]/LCD_D[9]/UPP_XD[1]/GP7[1][31,38]VP_DOUT[8]/LCD_D[8]/UPP_XD[0]/GP7[0][31,38]

VP_DOUT[7]/LCD_D[7]/UPP_XD[15]/GP7[15][31,38]VP_DOUT[6]/LCD_D[6]/UPP_XD[14]/GP7[14][31,38]VP_DOUT[5]/LCD_D[5]/UPP_XD[13]/GP7[13][31,38]VP_DOUT[4]/LCD_D[4]/UPP_XD[12]/GP7[12][31,38]VP_DOUT[3]/LCD_D[3]/UPP_XD[11]/GP7[11][31,38]VP_DOUT[2]/LCD_D[2]/UPP_XD[10]/GP7[10][31,38]VP_DOUT[1]/LCD_D[1]/UPP_XD[9]/GP7[9][31,38]VP_DOUT[0]/LCD_D[0]/UPP_XD[8]/GP7[8][31,38]

UPP_CHB_WAIT/GP8[12][38]

VP_CLKO3/GP6[1][38]

MMCSD1_DAT[7]/LCD_PCLK/GP8[11][31,38]MMCSD1_DAT[6]/LCD_MCLK/GP8[10][38]MMCSD1_DAT[5]/LCD_HSYNC/GP8[9][31,38]MMCSD1_DAT[4]/LCD_VSYNC/GP8[8][31,38]

VP_CLKIN2/MMCSD1_DAT[3]/GP6[4][38]VP_CLKO2/MMCSD1_DAT[2]/GP6[3][38]

VP_CLKIN3/MMCSD1_DAT[1]/GP6[2][38]MMCSD1_DAT[0]/UPP_CHB_CLK/GP8[15][38]

MMCSD1_CLK/UPP_CHB_START/GP8[14][38]MMCSD1_CMD/UPP_CHB_ENABLE/GP8[13][38]

LCD_AC_ENB_CSn/GP6[0][31,38]

UART_INTA[27]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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D


514202-0001

Wednesday, May 30, 2012 5 57

B

SMART GRID EVM

Video Port

POWER GROUP C

OMAP-L138

U22-5

LCD_AC_ENB_CSn/GP6[0]R5

VP_DOUT[0]/LCD_D[0]/UPP_XD8/GPIO7[8]W1 VP_DOUT[1]/LCD_D[1]/UPP_XD[9]/GP7[9]W2

VP_DOUT[10]/LCD_D[10]/UPP_XD[2]/GP7[2]/BOOT[2]T2 VP_DOUT[11]/LCD_D[11]/UPP_XD[3]/GP7[3]/BOOT[3]T3 VP_DOUT[12]/LCD_D[12]/UPP_XD[4]/GP7[4]/BOOT[4]R1 VP_DOUT[13]/LCD_D[13]/UPP_XD[5]/GP7[5]/BOOT[5]R2 VP_DOUT[14]/LCD_D[14]/UPP_XD[6]/GP7[6]/BOOT[6]R3 VP_DOUT[15]/LCD_D[15]/UPP_XD[7]/GP7[7]/BOOT[7]P4

VP_DOUT[2]/LCD_D[2]/UPP_XD[10]/GP7[10]W3 VP_DOUT[3]/LCD_D[3]/UPP_XD[11]/GP7[11]V1 VP_DOUT[4]/LCD_D[4]/UPP_XD[12]/GP7[12]V2 VP_DOUT[5]/LCD_D[5]/UPP_XD[13]/GP7[13]V3 VP_DOUT[6]/LCD_D[6]/UPP_XD[14]/GP7[14]U1 VP_DOUT[7]/LCD_D[7]/UPP_XD[15]/GP7[15]U2

VP_DOUT[8]/LCD_D[8]/UPP_XD[0]/GP7[0]/BOOT[0]U3 VP_DOUT[9]/LCD_D[9]/UPP_XD[1]/GP7[1]/BOOT[1]T1

MMCSD1_DAT[4]/LCD_VSYNC/GP8[8]G4 MMCSD1_DAT[5]/LCD_HSYNC/GP8[9]H4 MMCSD1_DAT[6]/LCD_MCLK/GP8[10]F2 MMCSD1_DAT[7]/LCD_PCLK/GP8[11]F1

VP_CLKOUT3/GP6[1]K4

VP_CLKIN3/MMCSD1_DAT[1]/GP6[2]J3 VP_CLKOUT2/MMCSD1_DAT[2]/GP6[3]K3 VP_CLKIN2/MMCSD1_DAT[3]/GP6[4]H3

UPP_CHB_WAIT/GP8[12]G3

MMCSD1_CMD/UPP_CHB_ENABLE/GP8[13]J4 MMCSD1_CLK/UPP_CHB_START/GP8[14]G2

MMCSD1_DAT[0]/UPP_CHB_CLK/GP8[15]G1

R371 22

R372 22

R376 22

R358 22

R356 22

R374 22

R379 22

RN13 RPACK8-1012345678 9

10111213141516

R375 22

R373 22

R370 NO-POP

R378 22

R512 0

R377 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VP_DIN[7]/UHPI_HD[15]/UPP_CHA_D[15]/RMII_TXD[1]VP_DIN[6]/UHPI_HD[14]/UPP_CHA_D[14]/RMII_TXD[0]

VP_DIN[3]/UHPI_HD[11]/UPP_CHA_D[11]/RMII_RXD[0]VP_DIN[2]/UHPI_HD[10]/UPP_CHA_D[10]/RMII_RXERVP_DIN[1]/UHPI_HD[9]/UPP_CHA_D[9]/RMII_MHZ_50_CLKVP_DIN[0]/UHPI_HD[8]/UPP_CHA_D[8]/RMII_CRS_DV

VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_CHA_D[7]VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_CHA_D[6]VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_CHA_D[5]VP_DIN[12]/UHPI_HD[4]/UPP_CHA_D[4]VP_DIN[11]/UHPI_HD[3]/UPP_CHA_D[3]

VP_DIN[8]/UHPI_HD[0]/UPP_CHA_D[0]/GP6[5]

VP_CLKIN1/UHPI_HDS1n/GP6[6]

VP_CLKIN0/UHPI_HCSn/GP6[7]/UPP_2XTXCLK

UHPI_HCNTL0/UPP_CHA_CLK/GP6[11]UHPI_HCNTL1/UPP_CHA_START/GP6[10]UHPI_HRWn/UPP_CHA_WAIT/GP6[8]UHPI_HHWIL/UPP_CHA_ENABLE/GP6[9]

UART_INTD

UHPI_HINTn/GP6[12]UHPI_HRDY/GP6[13]

RESETOUTn

VP_DIN[9]/UHPI_HD[1]/UPP_CHA_D[1]VP_DIN[10]/UHPI_HD[2]/UPP_CHA_D[2]

VP_DIN[5]/UHPI_HD[13]/UPP_CHA_D[13]/RMII_TXENVP_DIN[4]/UHPI_HD[12]/UPP_CHA_D[12]/RMII_RXD[1]

UART_INTC

UART_INTB

3V3_VIO

VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_CHA_D[5][38,43]VP_DIN[12]/UHPI_HD[4]/UPP_CHA_D[4][38,43]VP_DIN[11]/UHPI_HD[3]/UPP_CHA_D[3][38,43]VP_DIN[10]/UHPI_HD[2]/UPP_CHA_D[2][38,43]

VP_DIN[9]/UHPI_HD[1]/UPP_CHA_D[1][38,43]VP_DIN[8]/UHPI_HD[0]/UPP_CHA_D[0]/GP6[5][38,43]

VP_CLKIN0/UHPI_HCSn/GP6[7]/UPP_2XTXCLK[38]

VP_CLKIN1/UHPI_HDS1n/GP6[6][38]

VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_CHA_D[6][38,43]VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_CHA_D[7][38,43]

VP_DIN[7]/UHPI_HD[15]/UPP_CHA_D[15]/RMII_TXD[1][38]VP_DIN[6]/UHPI_HD[14]/UPP_CHA_D[14]/RMII_TXD[0][38]

VP_DIN[5]/UHPI_HD[13]/UPP_CHA_D[13]/RMII_TXEN[38]

VP_DIN[0]/UHPI_HD[8]/UPP_CHA_D[8]/RMII_CRS_DV[38,43]VP_DIN[1]/UHPI_HD[9]/UPP_CHA_D[9]/RMII_MHZ_50_CLK[38,43]

VP_DIN[2]/UHPI_HD[10]/UPP_CHA_D[10]/RMII_RXER[38]VP_DIN[3]/UHPI_HD[11]/UPP_CHA_D[11]/RMII_RXD[0][38]VP_DIN[4]/UHPI_HD[12]/UPP_CHA_D[12]/RMII_RXD[1][38]

UHPI_HCNTL0/UPP_CHA_CLK/GP6[11][38,43]UHPI_HCNTL1/UPP_CHA_START/GP6[10][38]

UHPI_HRWn/UPP_CHA_WAIT/GP6[8][38]UHPI_HHWIL/UPP_CHA_ENABLE/GP6[9][38]

RESETOUTn[22,24,26,37,38]

UHPI_HINTn/GP6[12][33,38]UHPI_HRDY/GP6[13][32,38]

UART_INTB[27]

UART_INTC[27]

UART_INTD[27]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

D


514202-0001

Wednesday, May 30, 2012 6 57

B

SMART GRID EVM

Video Port Input

R315 0

R31610K

R314 NO-POP

R229 0

R283 0

POWER GROUP COMAP-L138

U22-4

VP_DIN[0]/UHPI_HD[8]/UPP_CHA_D[8]/RMII_CRS_DVW19 VP_DIN[1]/UHPI_HD[9]/UPP_CHA_D[9]/RMII_MHZ_50_CLKW18

VP_DIN[10]/UHPI_HD[2]/UPP_CHA_D[2]R19 VP_DIN[11]/UHPI_HD[3]/UPP_CHA_D[3]R18 VP_DIN[12]/UHPI_HD[4]/UPP_CHA_D[4]T16 VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_CHA_D[5]U19 VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_CHA_D[6]V19 VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_CHA_D[7]V18

VP_DIN[2]/UHPI_HD[10]/UPP_CHA_D[10]/RMII_RXERW17 VP_DIN[3]/UHPI_HD[11]/UPP_CHA_D[11]/RMII_RXD[0]V17 VP_DIN[4]/UHPI_HD[12]/UPP_CHA_D[12]/RMII_RXD[1]W16 VP_DIN[5]/UHPI_HD[13]/UPP_CHA_D[13]/RMII_TXENR14 VP_DIN[6]/UHPI_HD[14]/UPP_CHA_D[14]/RMII_TXD[0]V16 VP_DIN[7]/UHPI_HD[15]/UPP_CHA_D[15]/RMII_TXD[1]U18

VP_DIN[8]/UHPI_HD[0]/UPP_CHA_D[0]/GP6[5]P17 VP_DIN[9]/UHPI_HD[1]/UPP_CHA_D[1]R15

VP_CLKIN1/UHPI_HDS1n/GP6[6]V15

VP_CLKIN0/UHPI_HCSn/GP6[7]/UPP_2xTXCLKW14

UHPI_HCNTL1/UPP_CHA_START/GP6[10]W15 UHPI_HCNTL0/UPP_CHA_CLK/GP6[11]U17

CLKOUT/UHPI_HDS2n/GP6[14]T18

RESETOUTn/UHPI_HASn/GP6[15]T17

UHPI_HRWn/UPP_CHA_WAIT/GP6[8]T15UHPI_HHWIL/UPP_CHA_ENABLE/GP6[9]U16

UHPI_HINTn/GP6[12]R16UHPI_HRDYn/GP6[13]R17

R69 NO-POP

R68 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB0_DRV_VBUS

USB0_DM

USB0_ID

USB0_DP

FB_USB0_VBUS

VCC_1V8_LDO

3V3_EVM

USB0_DM [32]

USB0_DP [32]

USB0_ID [32]

USB0_DRV_VBUS [32]

FB_USB0_VBUS [32]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

USB 2.0 INTERFACE

Differential Pair90 ohm differential pairs

C178.22uF

C182NO-POP

C410.1uF

E5NFM21PC474R1C3D

13

2

C380.1uF

C470.01uF

C370.001uF

C500.01uF

C340.001uF

C551uF

C521uF

PWRGROUP B

PWRGROUP B

OMAP-L138

U22-10

USB0_DM M18

USB0_DP M19

USB0_DRVVBUS K18

USB0_ID P16

USB0_VBUS N19

USB0_VDDA12N17

USB0_VDDA33N18

NC.N16N16

USB0_VDDA18N14

NC.M14M14

E2NFM21PC474R1C3D

13

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB1_DPUSB1_DM

CPU_USB1_DPCPU_USB1_DM

VCC_1V8_LDO

3V3_EVM

USB1_DM [32]USB1_DP [32]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

USB 1.0 HOST INTERFACE

Differential Route 90 ohms

OMAP-L138

U22-9

USB1_DM P18USB1_DP P19

USB1_VDD18P14

USB1_VDD33P15

E4NFM21PC474R1C3D

13

2

C390.1uF

C480.01uF

C490.01uF

C400.1uF

C531uF

C350.001uF

R6615K

C360.001uF

C541uF

R318 24.9 1%

E3NFM21PC474R1C3D

13

2

R6715K

R317 24.9 1%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EMA_D[0]/GP4[8]EMA_D[1]/GP4[9]EMA_D[2]/GP4[10]EMA_D[3]/GP4[11]EMA_D[4]/GP4[12]EMA_D[5]/GP4[13]EMA_D[6]/GP4[14]EMA_D[7]/GP4[15]

EMA_WAIT[0]/GP3[8]

EMA_WAIT[1]/GP2[1]


3V3_VIO

3V3_VIO

3V3_VIO

SD0_CLK [30,37]SD0_CMD [30,37]SD0_DATA0 [30,37]SD0_DATA1 [30,37]SD0_DATA2 [30,37]SD0_DATA3 [30,37]

EMA_A[1]/GP5[1] [20,27,37]EMA_A[2]/GP5[2] [20,27,37]

EMA_BA[1]/GP2[9] [27,37]EMA_BA[0]/GP2[8] [27,31,37]

EMA_OEn/GP3[10] [20,27,37]

EMA_WEn/GP3[11] [20,27,37]

EMA_RNW/GP3[9] [37]

EMA_WAIT[0]/GP3[8][20,37]

EMA_D[6]/GP4[14][20,27,37]EMA_D[5]/GP4[13][20,27,37]EMA_D[4]/GP4[12][20,27,37]EMA_D[3]/GP4[11][20,27,37]EMA_D[2]/GP4[10][20,27,37]

EMA_D[1]/GP4[9][20,27,37]EMA_D[0]/GP4[8][20,27,37]

EMA_D[7]/GP4[15][20,27,37]

EMA_CLK/GP2[7] [37]

USB1_PWR_EN [32]

EMA_CS[0]/GP2[0] [37]

EMA_CS[2]/GP3[15] [37]

EMA_CS[3]/GP3[14] [20,37]

EMA_CS[4]/GP3[13] [20,37]

EMA_CS[5]/GP3[12] [27,37]

SD_WP [30,37]SD_INS [30,37]

TOUCH_INT [55]

EMA_A[0]/GP5[0] [27,37]

EMA_D[14]/GP3[6][37]EMA_D[13]/GP3[5][37]EMA_D[12]/GP3[4][37]EMA_D[11]/GP3[3][37]EMA_D[10]/GP3[2][37]

EMA_D[9]/GP3[1][37]EMA_D[8]/GP3[0][37]

EMA_D[15]/GP3[7][37]EMA_A[15]/MMCSD0_DAT[6]/GP5[15] [33,37]EMA_A[14]/MMCSD0_DAT[7]/GP5[14] [33,37]EMA_A[13]/GP5[13] [33,37]

EMA_A[12] GP5[12] [37]EMA_A[11]/GP5[11] [37]

EMA_A[10]/GP5[10] [37]EMA_A[9]/GP5[9] [37]EMA_A[8]/GP5[8] [37]

EMA_A[3]/GP5[3] [37]EMA_A[4]/GP5[4] [37]EMA_A[5]/GP5[5] [37]EMA_A[6]/GP5[6] [37,41]EMA_A[7]/GP5[7] [37,41]

EMA_WAIT[1]/GP2[1][37]

CPU_CAN_INTERRUPT [41]

ZERO_PLC [42,46]

CPU_SPI1_CS_CANn [17]

GP5[12] [32]

GP5[11] [32]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 9 57

B

SMART GRID EVM

EMIFA Interface

R32710K

R32910K

R33610K

R346 22

R337 22

R354 0

R345 0

R353 22

R33510K

R184 0

R34110K

R186 0

R34710K

POWER GROUP B

OMAP-L138

U22-2

EMA_A[0]/GP5[0] C14EMA_A[1]/GP5[1] D15

EMA_A[10]/GPIO5[10] C12EMA_A[11]/GP5[11] B12EMA_A[12]/GP5[12] D13EMA_A[13]/GP5[13] D11EMA_A[14]/MMCSD0_DAT[7]/GP5[14] A12EMA_A[15]/MMCSD0_DAT[6]/GP5[15] C11

EMA_A[16]/MMCSD0_DAT[5]/GP4[0] E12EMA_A[17]/MMCSD0_DAT[4]/GP4[1] B11EMA_A[18]/MMCSD0_DAT[3]/GP4[2] E11EMA_A[19]/MMCSD0_DAT[2]/GP4[3] C10

EMA_A[2]/GP5[2] B14

EMA_A[20]/MMCSD0_DAT[1]/GP4[4] A11EMA_A[21]/MMCSD0_DAT[0]/GP4[5] B10EMA_A[22]/MMCSD0_CMD/GP4[6] A10EMA_A[23]/MMCSD0_CLK/GP4[7] E9

EMA_A[3]/GP5[3] D14EMA_A[4]/GP5[4] A14EMA_A[5]/GP5[5] C13EMA_A[6]/GP5[6] E13EMA_A[7]/GP5[7] B13

EMA_A[8]/GP5[8] A13EMA_A[9]/GP5[9] D12

EMA_BA[0]/GP2[8] C15EMA_BA[1]/GP2[9] A15

EMA_CLK/GP2[7] B7

EMA_D[0]/GP4[8]C9 EMA_D[1]/GP4[9]A8

EMA_D[10]/GP3[2]A7 EMA_D[11]/GP3[3]D6 EMA_D[12]/GP3[4]A6 EMA_D[13]/GP3[5]B6 EMA_D[14]/GP3[6]C7 EMA_D[15]/GP3[7]E6

EMA_D[2]/GP4[10]B8 EMA_D[3]/GP4[11]E8 EMA_D[4]/GP4[12]B5 EMA_D[5]/GP4[13]E7 EMA_D[6]/GP4[14]C6 EMA_D[7]/GP4[15]D7

EMA_D[8]/GP3[0]E10 EMA_D[9]/GP3[1]D9

EMA_A_RWn/GP3[9] D10

EMA_SDCKE/GP2[6] D8

EMA_WAIT[0]/GP3[8]B18

EMA_WAIT[1]/GP2[1]B19

EMA_CASn/GP2[4] A9

EMA_CS[0]n/GP2[0] A18

EMA_CS[2]n/GP3[15] B17

EMA_CS[3]n/GP3[14] A17

EMA_CS[4]n/GP3[13] F9

EMA_CS[5]n/GP3[12] B16

EMA_OEn/GP3[10] B15

EMA_RASn/GP2[5] A16

EMA_WEn/GP3[11] B9

EMA_WE_DQM[0]n/GP2[3] C8

EMA_WE_DQM[1]n/GP2[2] A5

R32810K

R33410K

R33810K

R340 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_DQS[0]

DDR_DQS[1]

DDR_DQM[0]

DDR_DQM[1]

DDR_DQGATE0

DDR_DQGATE1

T_DDR_DQGATE0

DDR_D[13]

T_DDR_DQM[0]

T_DDR_DQM[1]

DDR_D[10]

DDR_D[15]

DDR_D[11]

DDR_D[9]

DDR_D[14]

DDR_D[12]

DDR_D[8]

DDR_D[2]

DDR_D[0]

DDR_D[5]

DDR_D[7]

DDR_D[3]

DDR_D[1]

DDR_D[4]

DDR_D[6]

DDR_A[4]DDR_A[3]DDR_A[2]DDR_A[1]DDR_A[0]

DDR_BA[1]

DDR_A[5]

DDR_WEn

DDR_CKE

DDR_CSn

DDR_CASn

DDR_RASn

T_DDR_CASn

T_DDR_RASn

DDR_CLKP

DDR_CLKN

T_DDR_CLKP

T_DDR_CLKN

T_DDR_CSn

T_DDR_WEn

T_DDR_CKE

DDR_BA[2]

DDR_A[13]

T_DDR_BA[0]T_DDR_BA[1]

T_DDR_A[1]T_DDR_A[2]T_DDR_A[3]T_DDR_A[4]

T_DDR_A[5]T_DDR_A[6]T_DDR_A[7]T_DDR_A[8]T_DDR_A[9]T_DDR_A[10]T_DDR_A[11]T_DDR_A[12]



DDR_A[5]DDR_A[6]DDR_A[7]

DDR_BA[1]DDR_BA[2]

DDR_BA[0]

DDR_A[13] T_DDR_A[13]

DDR_ZP

DDR_VREF


DDR_A[6]

DDR_BA[0]

DDR_A[7]

T_DDR_BA[2]T_DDR_A[0]

DDR_D[13][15]DDR_D[14][15]DDR_D[15][15]

DDR_D[0][15]DDR_D[1][15]DDR_D[2][15]DDR_D[3][15]DDR_D[4][15]DDR_D[5][15]DDR_D[6][15]DDR_D[7][15]

DDR_D[8][15]DDR_D[9][15]

DDR_D[10][15]DDR_D[11][15]DDR_D[12][15]

DDR_DQS[0][15]

DDR_DQS[1][15]

T_DDR_DQM[0][15]

T_DDR_DQM[1][15]

T_DDR_DQGATE0[15]

DDR_DQGATE1[15]

T_DDR_WEn [15]

T_DDR_CKE [15]

T_DDR_CLKN [15]

T_DDR_CLKP [15]

T_DDR_CSn [15]

T_DDR_RASn [15]

T_DDR_CASn [15]

T_DDR_BA[0] [15]T_DDR_BA[1] [15]

T_DDR_A[0] [15]T_DDR_A[1] [15]T_DDR_A[2] [15]T_DDR_A[3] [15]T_DDR_A[4] [15]

T_DDR_A[5] [15]T_DDR_A[6] [15]T_DDR_A[7] [15]T_DDR_A[8] [15]T_DDR_A[9] [15]T_DDR_A[10] [15]T_DDR_A[11] [15]T_DDR_A[12] [15]

T_DDR_BA[2] [15]

T_DDR_A[13] [15]

DDR_VREF [15]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

AM1808 DDR2 INTERFACE

DIFF PAIR

R10422

R137 22R385 10

R129 22

R10322

R33949.9 1%

R133 22

R139 22

R163 22

OMAP-L138

U22-3

DDR_A[0] U7DDR_A[1] T7

EMB_A[10] W4DDR_A[11] T4DDR_A[12] V4DDR_A[13] T5

DDR_A[2] W6DDR_A[3] V6DDR_A[4] U5DDR_A[5] V5DDR_A[6] W5DDR_A[7] U6

DDR_A[8] U4DDR_A[9] T6

DDR_BA[0] V8DDR_BA[1] T9DDR_BA[2] U8

DDR_CKE V7

DDR_CLKN W7

DDR_CLKP W8

DDR_D[0]U15 DDR_D[1]U14

DDR_D[10]T10 DDR_D[11]T12 DDR_D[12]U10 DDR_D[13]V10 DDR_D[14]U11 DDR_D[15]W10

DDR_D[2]V14 DDR_D[3]U13 DDR_D[4]V13 DDR_D[5]V12 DDR_D[6]W12 DDR_D[7]W11

DDR_D[8]T13 DDR_D[9]T11

DDR_DQS[0]T14

DDR_DQS[1]V11

DDR_ZP U12

DDR_DQGATE0R11

DDR_DQGATE1R12 DDR_VREF R6

DDR_CASn U9

DDR_CSn V9DDR_DQM[0]W13

DDR_DQM[1]R10DDR_RASn W9

DDR_WEn T8

C2270.1UF

R121 10

R124 10

R126 22

RN12RPACK8-22

123456789

10111213141516

RN11RPACK8-22

123456789

10111213141516

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TRSTn

TMS

TDI

TDO

RTCK/GP8[0]

JTAG_TCK

EMU0EMU1

3V3_VIO

3V3_VIO

3V3_VIO

3V3_EVM

TDI[36]

TMS[36]

TRSTn[36]

TCK[36]

TDO[36]

RTCK[36]

EMU0[36]EMU1[36]

MSTR_nRST_3.3_1.8[27,33,34,36,55,56]

NMIn[38]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 11 57

B

SMART GRID EVM

JTAG/CLOCKS

R532 165

C3318 pF

R32310K

R32110K

R320 22

R533100

PWRGROUP B

OMAP-L138

U22-8

EMU0J16

EMU1K16

RESETnK14

TRSTnL17

OSCIN L19

OSCOUT K19

VSS_RTC H18

OSCVSS L18

RTC_XI J19

RTC_XO H19RTCK/GP8[0]K17

TCKJ15

TDIM16

TDOJ18

TMSL16

NMInJ17

C378.1uFR319

NO-POP

C379NO-POP

L38FERRITE BEAD

12

C3218 pF

C27

22pF

Y232.768KHz

14

23

R6510K

U66

24Mhz

VCC4

OUT3 GND 2

EN 1

R52100

R32210K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_1V2_LDO

VCC_1V2

1V2_RTC

VCC_1V8_LDO VCC_1V8_LDO

VCC_1V2

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

C


514202-0001


B

SMART GRID EVM

AM1808 POWER PINS

C1940.1uFc402-25

C2200.1uFc402-25

+ C8033uF

OMAP-L138

U22-12

CVDD.1E15

CVDD.4G13

CVDD.2G7CVDD.3G8

CVDD.7H10CVDD.8H11CVDD.9H12

CVDD.10 H13

CVDD.5H6CVDD.6H7

CVDD.12 J12CVDD.11 J6

CVDD.14 K12CVDD.13 K6

CVDD.15 L12CVDD.16 M8CVDD.17 M9CVDD.18 N8

C2210.1uF

c402-25

L3

BLMG1P500SPT

+ C4433uFC255

0.1uFc402-25

C230.01uF

C2030.1uF

c402-25

+ C4633uF

C1830.1uFc402-25

C1930.1uFc402-25

OMAP-L138

U22-14

DDR_DVDD18.3N10

DDR_DVDD18.1N6DDR_DVDD18.2N9 DDR_DVDD18.7 P10

DDR_DVDD18.4P7DDR_DVDD18.5P8

DDR_DVDD18.6 P9

DDR_DVDD18.8 R7DDR_DVDD18.9 R8

DDR_DVDD18.10 R9

E1NFM21PC474R1C3D

13

2

C2220.1uFc402-25

C2560.1uFc402-25

C2180.1uF

c402-25

C260.1uF

C2020.1uFc402-25

OMAP-L138

U22-16

PLL0_VSSA12M17

PLL1_VDDA12N15

PLL1_VSSA12M15

RTC_CVDD L14PLL0_VDDA12L15

C2130.1uFc402-25

+C6633uFC251

0.1uFc402-25

C2140.1uFc402-25

C2520.1uFc402-25

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_VIO_C

CPU_VIO_A

CPU_VIO_B3V3_VIO

3V3_VIO

3V3_VIO

VCC_1V8_LDO

VCC_1V2_LDO

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

AM1808 I/O POWER PINS

C2060.1uFc402-25

C2160.1uFc402-25

C2010.1uFc402-25

C2540.1uFc402-25

R63 0

C2050.1uFc402-25

C2090.1uFc402-25

C2000.1uFc402-25

C2340.1uFc402-25

C2570.1uFc402-25

TP2TEST POINT

1

C2370.1uF

c402-25

C1980.1uFc402-25

C1970.1uFc402-25

OMAP-L138

U22-7

DVDD3318_A.4F15

DVDD3318_A.1F5

DVDD3318_A.5G14DVDD3318_A.6G15

DVDD3318_A.2G5DVDD3318_A.3H5

DVDD3318_C.1J5

DVDD3318_B.1 E14

DVDD3318_B.5 F10DVDD3318_B.6 F11DVDD3318_B.7 F12DVDD3318_B.8 F13

DVDD3318_B.2 F6DVDD3318_B.3 F7DVDD3318_B.4 F8

DVDD3318_B.9 G9DVDD3318_B.10 J14DVDD3318_B.11 K15

DVDD3318_C.2K13

DVDD3318_C.4L13DVDD3318_C.5M13DVDD3318_C.6N13

DVDD3318_C.9P12

DVDD3318_C.7P5DVDD3318_C.8P6

DVDD3318_C.10R4

DVDD3318_C.3L4

C1950.1uFc402-25

+ C4533uF

+ C18133uF

C2330.1uFc402-25

C2040.1uFc402-25

C2110.1uFc402-25

+ C8233uF

C2530.1uFc402-25

C1900.1uFc402-25

R313 0

C2500.1uFc402-25

OMAP-L138

U22-13

DVDD18.1F14

DVDD18.3G10DVDD18.4G11DVDD18.5G12

DVDD18.2G6

DVDD18.6J13DVDD18.7K5DVDD18.8L6DVDD18.9P13DVDD18.10R13

RVDD.2 H14RVDD.1 E5

RVDD.3 N7

RSV2(VPP) T19

USB_CVDD M12

+ C5933uF C196

0.1uFc402-25

C2310.1uFc402-25

R326 0

C2120.1uFc402-25

C2250.1uFc402-25

C1910.1uFc402-25

C1920.1uFc402-25

C2490.1uFc402-25

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

AM1808 GROUND PINS

OMAP-L138

U22-11

VSS.1A19

VSS.10K7VSS.11K8VSS.12K9VSS.13K10VSS.14K11VSS.15L5

VSS.16 L7VSS.17 L8VSS.18 L9VSS.2H8

VSS.19 L10VSS.20 L11VSS.21 M4VSS.22 M5VSS.23 M6VSS.24 M7VSS.25 M10VSS.26 M11VSS.27 N5

VSS.3H9

VSS.28 N11VSS.29 N12VSS.30 P11

VSS.4H15VSS.5J7VSS.6J8VSS.7J9VSS.8J10VSS.9J11

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

T_DDR_DQS[0]DDR_DQS[0]

DDR_DQS[1]

DDR_D[0]DDR_D[7]

DDR_D[2]DDR_D[5]

T_DDR_D[10]

T_DDR_D[8]T_DDR_D[9]

T_DDR_D[0]T_DDR_D[1]T_DDR_D[2]T_DDR_D[3]

T_DDR_D[11]



T_DDR_DQS[1]

DDR_D[13]DDR_D[10]

DDR_D[15]

DDR_D[9]DDR_D[14]

DDR_D[8]

DDR_D[1]DDR_D[6]

DDR_DQGATE1

T_DDR_DQM[0]T_DDR_DQM[1]

DDR_ODT

DDR_VREF

DDR_D[11]DDR_D[12]

T_DDR_DQGATE0

T_DDR_CLKP

T_DDR_WEn

T_DDR_CLKN

T_DDR_CASnT_DDR_RASn

T_DDR_CSn

T_DDR_CKE

T_DDR_BA[0]T_DDR_BA[1]

T_DDR_A[2]T_DDR_A[3]



T_DDR_BA[2]

T_DDR_A[13]


T_DDR_A[4]

T_DDR_A[5]


T_DDR_A[12]

DDR_D[4]DDR_D[3]


T_DDR_D[9]

T_DDR_D[0]

T_DDR_D[1]

T_DDR_D[2]

T_DDR_D[3]


T_DDR_D[13]

T_DDR_D[14]

T_DDR_D[15]

T_DDR_D[4]

T_DDR_D[5]

T_DDR_D[6]

T_DDR_D[7]

VCC_1V8_LDO

VCC_1V8_LDO

VCC_1V8_LDO

T_DDR_DQGATE0[10]

DDR_VREF [10]

DDR_D[13] [10]

DDR_D[14] [10]

DDR_D[15] [10]

DDR_D[0] [10]

DDR_D[1] [10]

DDR_D[2] [10]

DDR_D[3] [10]DDR_D[4] [10]

DDR_D[5] [10]

DDR_D[6] [10]

DDR_D[7] [10]

DDR_D[8] [10]

DDR_D[9] [10]

DDR_D[10] [10]

DDR_D[11] [10]DDR_D[12] [10]

DDR_DQS[0][10]

DDR_DQS[1][10]

T_DDR_DQM[0][10]T_DDR_DQM[1][10]

T_DDR_WEn[10]T_DDR_CKE[10]

T_DDR_CLKN[10]T_DDR_CLKP[10]

T_DDR_CSn[10]

T_DDR_RASn[10]T_DDR_CASn[10]

T_DDR_BA[0][10]T_DDR_BA[1][10]

T_DDR_A[0][10]T_DDR_A[1][10]T_DDR_A[2][10]T_DDR_A[3][10]T_DDR_A[4][10]

T_DDR_BA[2][10]

T_DDR_A[5][10]T_DDR_A[6][10]T_DDR_A[7][10]T_DDR_A[8][10]T_DDR_A[9][10]

T_DDR_A[10][10]T_DDR_A[11][10]T_DDR_A[12][10]T_DDR_A[13][10]

DDR_DQGATE1[10]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

DDR2 - EMIF B

R3671K 1%

C2410.1UF

C2470.1UF

C246560PF

R3660

C219560PF R369

1K 1%

R105 22

C2630.1UF

C2600.1UF

R3860

+C26910UF

R368NO-POP

C226560PF

R106 22

RN7 RPACK4-22

12345

678

U29

MT47H64M16HR-3:G

NC10A1 NC9A2 NC8A8 NC7A9

VDD.4 D1

NC5D2

VSS.4 D3

VSSQ.3 D7UDQS#/NUD8

VDDQ.7 D9

DQ14 E1

VSSQ.5 E2

UDME3

UDQSE7

VSSQ.8 E8

DQ15 E9

VDDQ.8 F1

DQ9 F2

VDDQ.1 F3VDDQ.2 F7

DQ8 F8

VDDQ.9 F9

DQ12 G1

VSSQ.10 G2

DQ11 G3DQ10 G7

VSSQ.1 G8

DQ13 G9

VDD.2 H1

NC11H2

VSS.3 H3

VSSQ.9 H7

LDQS#/NUH8

VDDQ.10 H9

DQ6 J1

VSSQ.4 J2

LDMJ3

LDQSJ7

VSSQ.2 J8

DQ7 J9

VDDQ.3 K1

DQ1 K2

VDDQ.4 K3VDDQ.5 K7

DQ0 K8

VDDQ.6 K9

DQ4 L1

VSSQ.7 L2

DQ3 L3DQ2 L7

VSSQ.6 L8

DQ5 L9

VDDL M1

VREF M2

VSS.5 M3

VSSDL M7

CKM8

VDD.1 M9

CKEN2 WE#N3 RAS#N7

CK#N8

ODTN9

BA2P1

BA0P2 BA1P3

CAS#P7 CS#P8

A10R2

A1R3 A2R7

A0R8

VDD.3 R9

VSS.2 T1

A3T2

A5T3 A6T7

A4T8

A7U2

A9U3

A11U7

A8U8

VSS.1 U9

VDD.5 V1

A12V2

RFU.1V3RFU.2V7

NC/A13V8

NC4AA1 NC3AA2 NC2AA8 NC1AA9RN10 RPACK4-22

12345

678

RN8 RPACK4-2212345

678

C238560PF

RN9 RPACK4-22

12345

678

C2300.1UF

C2320.1UF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_SPI1_SIMO/GP2[10]

CPU_SPI1_CLK/GP2[13]

SPIROM_SPI1_SIMO/GP2[10]

SPIROM_SPI1_CLK/GP2[13]

CPU_SPI1_SOMI/GP2[11]

SPIROM_MDM_ENABLEn

3V3_EVM

3V3_EVM

3V3_EVM

3V3_EVM

3V3_EVM

CPU_SPI1_CLK/GP2[13][4,17]

CPU_SPI1_SIMO/GP2[10][4,17]

SPIROM_SPI1_SIMO/GP2[10] [18]

SPIROM_SPI1_CLK/GP2[13] [18]

MDM_SPI1_SIMO/GP2[10] [45,46]

MDM_SPI1_CLK/GP2[13] [45,46]

CPU_SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12[4] SPIROM_SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12 [18]

MDM_SPI1_ENAn/GP2[12] [45,46]CPU_SPI1_ENAn/GP2[12][4]

CPU_SPI1_SOMI/GP2[11][4,17]

MDM_SPI1_SOMI/GP2[11] [45,46]

SPIROM_SPI1_SOMI/GP2[11] [18]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

C


514202-0001

Monday, May 21, 2012 16 57

B

SMART GRID EVM

SPI BUFFERS I

U62CSN74LVTH125PW

89

10

U65

SN74LVC1G08DCKRG4

1

24

53

R493 0

C3770.1uF

U62DSN74LVTH125PW

1112

13

R494 0

R51910K

R508 0

R523 0

R509 0

R495 0

R52410K

U62ASN74LVTH125PW

32

1 714

U59SN74LVC1G125

3

4

5

2

1

R525 0

U62BSN74LVTH125PW

65

4

C3740.1uF

C369.1uF R526 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A ACPU_SPI1_SOMI/GP2[11]

CPU_SPI1_SIMO/GP2[10]

CPU_SPI1_CLK/GP2[13]

SPI1_CS_CANn

CPU_SPI1_SOMI/GP2[11]

SPI1_CS_CANn

3V3_EVM

3V3_EVM

3V3_EVM

3V3_EVM

3V3_EVM

CAN_SPI1_SOMI/GP2[11] [41]

CC_SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12 [39]

LCD_SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12 [31]

CC_SPI1_CLK/GP2[13] [39,40]

CPU_SPI1_SIMO/GP2[10][4,16] CC_SPI1_SIMO/GP2[10] [39,40]

CAN_SPI1_SIMO/GP2[10] [41]

CPU_SPI1_CLK/GP2[13][4,16]

CAN_SPI1_CLK/GP2[13] [41]

CC_SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12 [39]

CC_SPI1_SOMI/GP2[11] [39]

CPU_SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12[4]

CC2_SPI1_SOMI [40]

CPU_SPI1_SOMI/GP2[11][4,16]

CPU_SPI1_CS_CANn[9] SPI1_CS_CANn [41]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

C


514202-0001

Monday, May 21, 2012 17 57

B

SMART GRID EVM

SPI BUFFERS II

R530 0

R496 0

R531 0

R513 0

R514 0

U63ASN74LV125APWR

32

1 714

C371

.1uF

R52710K

C372

.1uF

U63CSN74LV125APWR

89

10

R52810K

R498 0

U63BSN74LV125APWR

65

4

R529 0

R499 0

U63DSN74LV125APWR

1112

13

U61SN74LVC1G125

3

4

5

2

1

U58SN74LVC1G125

3

4

5

2

1

C3750.1uF

R501 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SPI_WP

SPI_HOLD





SPIROM_SPI1_SOMI/GP2[11]

SPIROM_SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12

3V3_EVM

3V3_EVM

3V3_EVM

3V3_EVM

LCD_SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12 [31]

SPIROM_SPI1_SIMO/GP2[10][16]

SPIROM_SPI1_CLK/GP2[13][16]

SPIROM_SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12[16]

SPIROM_SPI1_SOMI/GP2[11][16]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

B


514202-0001

Monday, May 21, 2012 18 57

B

SMART GRID EVM

SPI FLASH/I2C EEPROM

R28210K

R27010K

U1

M25P64-VMF6TP

CS7

DIO 15

GND 10

VCC2

HOLD1

WP 9DO8

SCLK 16

NC.33

NC.44

NC.55

NC.66 NC.11 11

NC.12 12

NC.13 13

NC.14 14C162

0.1uF

R497 0

R28410K

R26910K

R26810K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

I2C0_SDAI2C0_SCL

3V3_VIO

3V3_VIO

5V_IN

I2C0_SCL[4,26,33,34,37,38,46,55]I2C0_SDA[4,26,33,34,37,38,46,55]

PMI2C_SDA [53]PMI2C_SCL [53]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

B


514202-0001


B

SMART GRID EVM

I2C EEPROM

R278NO-POP

J7

HEADER 4

1234

R2900

R279NO-POP

C141.1uF

R289NO-POP

R280NO-POP

U2

24WC256

A0 1VCC8

VSS 4NC 3SCL6SDA5

A1 2WP7

R2910

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NAND_RY/BYn

EMA_OEn/GP3[10]EMA_CS[3]/GP3[14]EMA_CS[4]/GP3[13]

EMA_WEn/GP3[11]

EMA_D[0]/GP4[8]EMA_D[1]/GP4[9]

EMA_D[2]/GP4[10]EMA_D[3]/GP4[11]

EMA_D[4]/GP4[12]EMA_D[5]/GP4[13]EMA_D[6]/GP4[14]EMA_D[7]/GP4[15]

EMA_WAIT[0]/GP3[8]

EMA_A[1]/GP5[1]EMA_A[2]/GP5[2]

3V3_EVM

3V3_EVM

3V3_EVM

3V3_EVM

3V3_EVM

EMA_D[6]/GP4[14] [9,27,37]EMA_D[5]/GP4[13] [9,27,37]EMA_D[4]/GP4[12] [9,27,37]

EMA_D[3]/GP4[11] [9,27,37]EMA_D[2]/GP4[10] [9,27,37]EMA_D[1]/GP4[9] [9,27,37]EMA_D[0]/GP4[8] [9,27,37]

EMA_D[7]/GP4[15] [9,27,37]

EMA_WAIT[0]/GP3[8][9,37]

EMA_A[1]/GP5[1][9,27,37]EMA_A[2]/GP5[2][9,27,37]

EMA_OEn/GP3[10][9,27,37]EMA_CS[3]/GP3[14][9,37]EMA_CS[4]/GP3[13][9,37]

EMA_WEn/GP3[11][9,27,37]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 20 57

B

SMART GRID EVM

NAND FLASH

nand boot loader uses chip select 3

C2920.1uF

R22010K

U41

socket

I/O7 44I/O6 43I/O5 42I/O4 41

VCC.112

I/O3 32I/O2 31I/O1 30I/O0 29

VSS.2 36

RE8CE9

VCC.2 37DNU/VSS 38

CLE16ALE17WE18WP19

NC.11NC.22NC.33NC.44NC.55

NC.1111

VSS.113

R/B2n6R/Bn7

CE210

NC.1414NC.1515

NC.2020NC.2121NC.2222NC.2323NC.2424 DNU.25 25DNU.26 26NC.27 27NC.28 28

NC.33 33NC.34 34NC.35 35

NC.39 39NC.40 40

NC.45 45NC.46 46NC.47 47DNU.48 48

MH

1M

H1

MH

2M

H2

R2234.7k5%

C2910.1uF

R21710K

R224 0

C2931uF

R2154.7k5%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SEL_MDIO_TIMER

3V3_VIO

3V3_VIO

SEL_MDIO_TIMER[33]

SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12[4,38]

SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12[4,38]

MDIO_D [22]

MDIO_CLK [22]

TM64P0_OUT12 [39]

TM64P1_OUT12 [40]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

C


514202-0001

Monday, May 21, 2012 21 57

B

SMART GRID EVM

MDIO MUX

R51010K

R511NO-POP

C376.1uF

U64

SN74CBTLV3257PW

1A4

4B1 14

2A73B1 11

3A9

4A12 4B2 13

S 1

1B1 2

OE 15

3B2 10

1B2 32B1 52B2 6

VCC16

GND8

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MII_TXP1

MII_TXM1

MII_LINK_LED

MII_SPEED_LED

MDIO_D

MII_RXM1

MII_RXP1

MDIO_CLK

3V3_VIO

ENET_VDDA

3V3_VIO

ENET_VDDA

3V3_EVM3V3_VIOENET_VDDIOENET_VDDCRVCC_1V2

MII_RXP1 [23]

MII_RXM1 [23]

RESETOUTn[6,24,26,37,38]

MII_TXP1 [23]

MII_TXM1 [23]

MII_SPEED_LED [23]

MII_LINK_LED [23]

AXR1/DX0/GP1[9]/MII_TXD[1][2]AXR2/DR0/GP1[10]/MII_TXD[2][2]

AXR6/CLKR0/GP1[14]/MII_TXEN[2]

AXR5/CLKX0/GP1[13]/MII_TXCLK[2]

AXR4/FSR0/GP1[12]/MII_COL[2]

AXR3/FSX0/GP1[11]/MII_TXD[3][2]

AXR0/ECAP0_APWM0/GP8[7]/MII_TXD[0]/CLKS0[2]

SPI0_ENAn/EPWM0B/MII_RXDV[4,37]SPI0_CLK/EPWM0A/GP1[8]/MII_RXCLK[4,37]

SPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER[4,37]

SPI0_SIMO/EPWMSYNCO/GP8[5]/MII_CRS[4,37]

SPI0_SCS[2]/UART0_RTSn/GP8[1]/MII_RXD[0]/SATA_CP_DET[4,37]SPI0_SCS[3]/UART0_CTSn/GP9[2]/MII_RXD[1]/SATA_MP_SWITCH[4,37]

SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2][4,37]SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3][4,37]

MDIO_D[21]

MDIO_CLK[21]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

B


514202-0001

Monday, May 21, 2012 22 57

B

SMART GRID EVM

ETHERNET PHY

Differential Pair

Internal Regulator Disable

Do NOT populate when using PHYInternal Regulator

R36NO-POP

R72 0

R3122K

R89 12.1K

R3092K

C187

0.1uF

R372K

R3062K

C186

0.1uF

Y525.0000MHz

31

2

4

C6233pF

R83 1K

R49 49.9

R45 49.9

R33049.9

R382K

R304NO-POP

R500NO-POP

TP3ENET_INT

L30

BLM21PG221SN1D

1 2

R48 49.9

R64 49.9

R44 49.9

L31

BLM21PG221SN1D

12

R305NO-POP

R33349.9

R43NO-POP

C56

10uF

C30

10uF

C180

0.1uF

R42NO-POP

R46 49.9

R33149.9

R47 49.9

R88 49.9

C61

10uF

R3112.2K

R61NO-POP

R33249.9

U19

LAN8710A-EZK

TX_CLK20

TXD022 TXD123 TXD224 TXD325

TX_EN21

INT/TX_ER/TXD418

COL/CRS_DV/MODE215CRS14

RX_CLK/PHYAD17

RXD0/MODE011 RXD1/MODE110 RXD2/RMIISEL9 RXD3/PHYAD28

RX_DV26

RX_ER/RXD4/PHYAD013

MDC17

MDIO16

TX+ 29

TX- 28

RX+ 31

RX- 30

LED2/INTSELn 2

LED1/REGOFF 3

XTAL2 4

XTAL1/CLKIN 5

RBIAS 32RESETn19

GN

D1

33V

DD

IO12

VD

DC

R6

VD

D2A

1V

DD

1A27

C188

0.1uF

L29

BLM21PG221SN1D

12

R3082K

R51NO-POP

R3072K

C6033pF

C189

0.1uF

R60NO-POP

R54 49.9

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3V3_EVM3V3_EVM3V3_EVM 3V3_EVM

MII_LINK_LED[22]

MII_TXM1[22]

MII_SPEED_LED[22]

MII_RXM1[22]

MII_RXP1[22]

MII_TXP1[22]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

B


514202-0001


B

SMART GRID EVM

ETHERNET MII CONNECTOR

Differential Pair 100 ohm

Differential Pair 100 ohm

R259330

R264NO-POP

C1380.1uF

R266NO-POP

R263NO-POP

R26710

C1390.1uF

R26210

R265NO-POP

Green LED

Yellow LED

J6

J0011D01BNL

TX+1

TX-2 TXCT4

RX+3

RX-6 RXCT5

NC7CHS_GND38 CHS_GND1 13

CHS_GND2 14

A_GRN9

C_GRN10

A_YLW12

C_YLW11

R261330

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DM_9621DP_9621

BGRES

LNK_LEDSPD_LED

LNK_LED

SPD_LED

EECSEECKEEDIO

RREF

USB_LED

DM9621_RX+

DM9621_TX+DM9621_TX-

DM9621_RX-

3V3_EVM

3V3_EVM

GNDA_9621

GNDA_9621

3V3_EVM

3V3_EVM 3V3A_9621

3V3PLL_9621

3V3A_9621 3V3PLL_9621

GNDA_9621GNDA_9621

3V3_EVM

3V3_EVM

GNDA_9621

3V3_EVM

3V3_EVM

GNDA_9621GNDA_9621

GNDA_9621

GNDA_9621

1V8A_9621_RX

1V8A_9621_TX

3V3_EVM 3V3_EVM

GNDA_9621

3V3_EVM

1V8_VOUT_9621

GNDA_9621

3V3_EVM

1V8A_9621_TX

GNDA_9621

1V8A_9621_RX

RESETOUTn[6,22,26,37,38]

DP_9621[32]DM_9621[32]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

B


514202-0001

Monday, May 21, 2012 24 57

B

SMART GRID EVM

ETHERNET MII CONNECTOR

100 OHM

100 OHM

90 OHM

PROGRAMMED

R4616.98K 1%

R475NO-POP

TP389621_WOL

R46047K

R477NO-POP

R46649.9

R43547K

C34010uFc603-35x45

R4710

R481NO-POP

C33210uFc603-35x45

R476NO-POP

C3280.1uFc402-25

C33010uFc603-35x45

R46749.9

C34710uF

c603-35x45

C3410.1uFc402-25

R42947K

R46849.9

C3270.1uFc402-25

C33410uFc603-35x45

C3380.1uF

c402-25

C3370.1uFc402-25

R136 2.2K

R46949.9

FB5

Ferrite

R47410K

C3350.1uFc402-25

C3390.1uF

c402-25

D25 Green

C3440.1uF

c402-25

U55

93C46_56_66

CS1SK2DIN3DOUT4

VCC 8NC1 7NC2 6GND 5

R46312K 1%

R421NO-POP

U54

DM9621NP

BGGND 1BGRES 2

RXVDDOUT 3RX+ 4RX- 5

RXGND 6TXGND 7

TX+ 8TX- 9

TXVDDOUT 10TXE 11

TXD1 12

TXD

013

RX

D1

14R

XD

015

GN

D.1

16R

XD

V17

MD

C18

MD

IO19

EE

DIO

20E

EC

K21

EE

CS

22C

LK50

M23

VC

C3.

124

SMI_D25 SMI_CK26 USB_LED27 SPD_LED28 LNK_LED29 TEST130 TEST231 VBUS_IN32 WOL33 RSTB34 X1_12M35 X2_12M36

VC

C3A

37G

ND

.238

RR

EF

39D

M40

DP

41V

CC

33_P

LL42

GN

D_P

LL43

VC

CO

UT

44V

CC

3.2

45X

246

X1

47G

ND

.348

PW

RP

AD

49

R464 330

C3310.1uFc402-25

R4700

R436NO-POP

C34510uF

c603-35x45

FB4

Ferrite

Green LED

Yellow LED

J18

J0011D01BNL

TX+1

TX-2 TXCT4

RX+3

RX-6 RXCT5

NC7CHS_GND38 CHS_GND1 13

CHS_GND2 14

A_GRN9

C_GRN10

A_YLW12

C_YLW11

FB6

Ferrite

C34210uFc603-35x45

R47810K

C33610uFc603-35x45

R47910K

R42247K

R472330

C3330.1uF

c402-25

C3430.1uFc402-25

R480NO-POP

R42747K

R473330

C325 15pF

C348 15pF

R43047K

R465 0

C326 15pF

R462NO-POP

C32910uF

c603-35x45

C349 15pF

R42847K

FB3

Ferrite

Y712MHz

C3460.1uF

c402-25

Y825.0000MHz

31

2

4

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AIC_BCLK

AIC_DOUT

AIC_WCLK

AIC_DIN

AIC_MCLK

3V3_EVM

3V3_EVM

AXR12/FSR1/GP0[4][2]

AXR11/FSX1/GP0[3][2]

AFSX/GP0[12][2]

ACLKX/GP0[14][2]

AUDIO_EXP_SEL[35]

AIC34_AXR11 [48]

AIC34_AXR12 [48]

AIC34_ACLKX [48]

AIC34_AFSX [48]

AIC34_AHCLKX [48]

AIC_BCLK [26]

AIC_WCLK [26]

AIC_DIN [26]

AIC_DOUT [26]

AXR13/CLKX1/GP0[5][2]

AXR14/CLKR1/GP0[6][2]

AHCLKX/USB_REFCLKIN/UART1_CTS/GP0[10][2] AIC_MCLK [26]

AIC34_AXR13 [48]

AIC34_AXR14 [48]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

McASP Muxing

U16SN74CBTLV16212

S01

GN

D.1

8V

CC

17

1A121A232A142A253A163A27 3B2 48

GN

D.4

49

3B1 502B2 512B1 521B2 531B1 54

S255 S156

4A194A2105A1115A2126A1136A2147A1157A2168A118

GN

D.2

19

8A2209A1219A22210A12310A22411A12511A22612A12712A228 12B2 2912B1 3011B2 3111B1 3210B2 3310B1 349B2 359B1 368B2 37

GN

D.3

38

8B1 397B2 407B1 416B2 426B1 435B2 445B1 454B2 464B1 47

C570.1uF

R31010K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AIC_WCLK

AIC_MCLK

AIC_DOUTAIC_DIN

AIC_BCLK

XTAL_24.576

3V3_VIO

VCC_1V8_LDO

3V3_EVM

3V3_EVM

I2C0_SCL[4,19,33,34,37,38,46,55]

RESETOUTn[6,22,24,37,38]

I2C0_SDA[4,19,33,34,37,38,46,55]

AIC_MCLK[25]AIC_BCLK[25]

AIC_WCLK[25]AIC_DIN[25]

AIC_DOUT[25]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

AUDIO CODEC

R220K

C50.47uF

R302.2K

C30.47uF

C15.1uF

Y1

24.576MHz

OE1

GND2 OUT 3

VDD 4

C84.7uF

C20.47uF

R15 22

C9.1uF

R17 22

R520K

R310K

TP33.

C184.7uF

C104.7uF

R110K

R24 22

C144.7uF

R9 22

TP32.

C19

.1uFU12

TLV320AIC3106IRGZ

GPIO135

DV

DD

36

MCLK37BCLK38WCLK39DIN40DOUT41

DV

SS

.242

SELECT43

IOV

DD

44

MFP0 / SPI_CSn / GPI / I2C_A045 MFP1 / SPI_SCK / GPI / I2C_A146 MFP2 / SPI_MISO / GPIO47 MFP3 / SPI_MOSI / GPI48

SCL / GPIO1 SDA / GPIO2

LINE1LP / MIC1LP3

LINE1LM / MIC1LM4

LINE1RP / MIC1RP5

LINE1RM / MIC1RM6

LINE2LP / MIC2LP7

LINE2LM / MIC2LM8

LINE2RP / MIC2RP9

LINE2RM / MIC2RM10

MIC3L11

MICDET12

MICBIAS13

MIC3R14

AV

SS

_AD

C15

DR

VD

D.1

16D

RV

DD

.217

HPLOUT 18

HPLCOM 19

DR

VS

S.2

20D

RV

SS

.121

HPRCOM 22

HPROUT 23

DR

VD

D.3

24

AV

DD

_DA

C25

AV

SS

_DA

C26

MONO_LOP 27

MONO_LOM 28

LEFT_LOP 29

LEFT_LOM 30

RIGHT_LOP 31

RIGHT_LOM 32

RESET33

GPIO234

DV

SS

.149

C7

.1uF

C110.1uF

C10.47uF

R292.2K

R16 22

J4 Line Out

3

421

56

J3Line In

3

421

5 6

C12.1uF

R10 22

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


UART_A_CTS

UART_A_RX

UART_A_DSR

UART_A_RIUART_A_DCDUART_A_RTS

UART_A_TX

UART_A_DTR

CC_UART_RXINCC_UART_TXOUT

PLC_RXBPLC_TXB

CC2_UART_RXINCC2_UART_TXOUT

UART_INTn

3V3_EVM

3V3_EVM

3V3_EVM

3V3_EVM

3V3_EVM

EMA_D[6]/GP4[14][9,20,37]EMA_D[5]/GP4[13][9,20,37]EMA_D[4]/GP4[12][9,20,37]EMA_D[3]/GP4[11][9,20,37]EMA_D[2]/GP4[10][9,20,37]EMA_D[1]/GP4[9][9,20,37]EMA_D[0]/GP4[8][9,20,37]

EMA_D[7]/GP4[15][9,20,37]

UART_A_DSR [29]

UART_A_RI [29]

UART_A_RX [29]

UART_A_DCD [29]

UART_A_CTS [29]UART_A_TX [29]

UART_A_RTS [29]

UART_A_DTR [29]

CC_UART_RXIN [39]CC_UART_TXOUT [39]

EMA_OEn/GP3[10][9,20,37]

EMA_WEn/GP3[11][9,20,37]

EMA_BA[1]/GP2[9][9,37]EMA_BA[0]/GP2[8][9,31,37]

EMA_A[0]/GP5[0][9,37]

EMA_CS[5]/GP3[12][9,37]

EMA_A[1]/GP5[1][9,20,37]EMA_A[2]/GP5[2][9,20,37]

MSTR_nRST_3.3_1.8[11,33,34,36,55,56]

PLC_RXB [46]PLC_TXB [46]

CC2_UART_RXIN [40]CC2_UART_TXOUT [40]

UART_INTA[5]UART_INTB[6]UART_INTC[6]UART_INTD[6]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

D


514202-0001

Monday, May 21, 2012 27 57

B

SMART GRID EVM

External UARTS

U37

16 MHz

VCC4

OUT3 GND 2

EN 1

U42SN74LVC1G04DCKR3

4

5

21

R222 22

C2890.1uF

U43

TL16C554AIPNR

NC

.11

DCDDn 2RIDn 3

RXD 4

VC

C.1

5

INTn6

D07D18D29

NC

.10

10

D311D412D513D614D715

GN

D.1

16

RXA 17

RIAn 18DCDAn 19

NC

.20

20N

C.2

121

DSRAn 22

CTSAn 23DTRAn 24

VC

C.2

25

RTSAn 26

INTA27

CSAn28

TXA 29

NC

.30

30

IOWn31

TXB 32

CSBn33

INTB34

RTSBn 35

GN

D.2

36

DTRBn 37CTSBn 38

DSRBn 39

NC

.40

40N

C.4

141

DCDBn 42RIBN 43

RXB 44

VC

C.3

45

A246 A147 A048

NC

.49

49

XTAL1 50

XTAL2 51

NC

.52

52

RESET53

RXRDYn54 TXRDYn55

GN

D.3

56

RXC 57

RICn 58DCDCn 59

NC

.60

60N

C.6

161

DSRCn 62

CTSCn 63DTRCn 64

VC

C.4

65

RTSCn 66

INTC67

CSCn68 TXC 69

IORn70

NC

.71

71

TXD 72

CSDn73

INTD74

RTSDn 75

GN

D.4

76

DTRDn 77CTSDn 78

DSRDn 79

NC

.80

80

U45

SN74LVC138ARGYR

A1 B2 C3

G2A4

G2B5

G16

Y7 7

GND.1 8

Y6 9Y5 10Y4 11Y3 12Y2 13Y1 14Y0 15

VCC 16

GND.2 17

C2970.1uF

C3010.1uF

R22710k

C2900.1uF

C283.001uF

C2940.1uF

C2840.1uF

C2950.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RSA_RXD

RSA_CTS

RSA_RTSRSA_TXD

RSA_RXD

RSA_CTS

RSA_RTS

RSA_TXD

3V3_VIO

3V3_EVM3V3_VIO

3V3_VIO

AMUTE/UART2_RTSn/GP0[9][4]

SPI1_SCS[5]/UART2_RXD/I2C1_SCL/GP1[3][4]

SPI1_SCS[4]/UART2_TXD/I2C1_SDA/GP1[2][4]

RSVD/RTC_ALARM]/UART2_CTSn/GP0[8]/DEEPSLEEPn[4]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

LINUX CONSOLE RS232 CONNECTOR

R2710

R2772.2K

C1500.1uF

C1490.1uF

C1570.1uF

C158 0.1uF

C163 0.1uF

U3TRS3386ECPWR

C1+1

V+ 2C1-3

C2+4

C2-5

V- 6

DIN17

DIN28

DIN39

ROUT210

ROUT111

VL 12

RIN2 13

RIN1 14

DOUT3 15

DOUT2 16

DOUT1 17

GND 18

VCC 19

PWRDOWN20

P1

DB-9-MALE

594837261

11

10

R2722.2K

R273NO-POP

C1590.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

S_A_DCDS_A_DSRS_A_RXDS_A_CTSS_A_RI

S_A_RTSS_A_TXDS_A_DTR

S_A_DCDS_A_DSRS_A_RXDS_A_RTS

S_A_CTSS_A_TXD

S_A_DTRS_A_RI

3V3_EVM

3V3_EVM

UART_A_TX[27]UART_A_RTS[27]

UART_A_DTR[27]

UART_A_DCD[27]UART_A_DSR[27]

UART_A_RX[27]UART_A_CTS[27]

UART_A_RI[27]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

GPS RS232 CONNECTOR

U6 MAX3243

T1IN14T2IN13T3IN12

R5OUT15 R4OUT16

INVALID21

R2OUTB20R1OUT19R2OUT18R3OUT17

C1+28

C1-24

V+27

VC

C26

GN

D25

V- 3

C2- 2

C2+ 1

R1IN 4R2IN 5R3IN 6

FORCEON 23FORCEOFF 22

T1OUT 9T2OUT 10T3OUT 11

R4IN 7R5IN 8

+ C156

10uF

P2

DB-9 MALE

594837261

11

10

R287

10

C1601uF C151

1uF

R28610K

C1521uF

C1610.1uF

C1671uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3V3_VIO3V3_VIO

SD_WP[9,37]

SD0_CMD[9,37]

SD0_CLK[9,37]

SD0_DATA3[9,37]

SD0_DATA0[9,37]

SD_INS[9,37]

SD0_DATA2[9,37]SD0_DATA1[9,37]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

SD/MMC CONNECTOR

These signals have internal pullups enabled by default.

C14222uF

R30051K

C1530.1uF

R30351K

R26051K

R29551K

R29651K

R30251K

R30151K

R29451K

J17

MMC/SD_CARD

DAT31 CMD2 VSS13 VDD4 CLK5 VSS26 DAT07 DAT18 DAT29

WPWPCOM CO

CARD_DETECTCD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

R_LCD_R3

R_LCD_B2

R_LCD_R4

R_LCD_G4

R_LCD_B5

R_LCD_B1

R_LCD_B4

R_LCD_BACKLIGHT_PWR

R_LCD_DCLK

R_LCD_PWM0

R_LCD_MDISP

R_LCD_PANEL_PWR

R_LCD_HSYNC

R_LCD_G2

R_LCD_G0

R_LCD_B3

R_LCD_R5

R_LCD_G5

R_LCD_R2

R_LCD_G3

R_LCD_G1

R_LCD_VSYNC

R_LCD_R1

R_LCD_B2

R_LCD_G2

R_LCD_DCLK

R_LCD_R1

R_LCD_B5

R_LCD_PWM0

R_LCD_BACKLIGHT_PWR

R_LCD_R5R_LCD_R4

R_LCD_R5

R_LCD_PANEL_PWR

R_LCD_MDISP

R_LCD_B1

R_LCD_G5

R_LCD_R2

R_LCD_G0

R_LCD_HSYNC

R_LCD_G4

R_LCD_B3

R_LCD_R3

R_LCD_VSYNCR_LCD_B5

R_LCD_G3

R_LCD_B4

R_LCD_G1

M_LCD_G5

M_LCD_G1M_LCD_G0

M_LCD_B5

M_LCD_B2

M_LCD_G2

M_LCD_B4

M_LCD_R2

M_LCD_B1

M_LCD_G4M_LCD_G3

M_LCD_B3

M_LCD_R5

M_LCD_R1

M_LCD_R3M_LCD_R4

M_LCD_BACKLIGHT_PWR

M_LCD_MDISP

M_LCD_PANEL_PWR

M_LCD_HSYNC

M_LCD_PWM0

M_LCD_VSYNCM_LCD_DCLK

3V3_EVM

3V3_EVM5V_IN

3V3_EVM

3V3_VIO

3V3_VIO

3V3_VIO

LCD_SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12[17]

LCD_SPI1_SCS[0]/EPWM1B/GP2[14]/TM64P3_IN12[18]


LCD_EXP_EN[35]

LCD_EXP_EN[35]

EMA_BA[0]/GP2[8][9,27,37]

VP_DOUT[15]/LCD_D[15]/UPP_XD[7]/GP7[7][5,38]VP_DOUT[14]/LCD_D[14]/UPP_XD[6]/GP7[6][5,38]VP_DOUT[13]/LCD_D[13]/UPP_XD[5]/GP7[5][5,38]VP_DOUT[12]/LCD_D[12]/UPP_XD[4]/GP7[4][5,38]VP_DOUT[11]/LCD_D[11]/UPP_XD[3]/GP7[3][5,38]

VP_DOUT[10]/LCD_D[10]/UPP_XD[2]/GP7[2][5,38]VP_DOUT[9]/LCD_D[9]/UPP_XD[1]/GP7[1][5,38]VP_DOUT[8]/LCD_D[8]/UPP_XD[0]/GP7[0][5,38]

VP_DOUT[7]/LCD_D[7]/UPP_XD[15]/GP7[15][5,38]VP_DOUT[6]/LCD_D[6]/UPP_XD[14]/GP7[14][5,38]VP_DOUT[5]/LCD_D[5]/UPP_XD[13]/GP7[13][5,38]

VP_DOUT[4]/LCD_D[4]/UPP_XD[12]/GP7[12][5,38]VP_DOUT[3]/LCD_D[3]/UPP_XD[11]/GP7[11][5,38]VP_DOUT[2]/LCD_D[2]/UPP_XD[10]/GP7[10][5,38]VP_DOUT[1]/LCD_D[1]/UPP_XD[9]/GP7[9][5,38]VP_DOUT[0]/LCD_D[0]/UPP_XD[8]/GP7[8][5,38]

MMCSD1_DAT[7]/LCD_PCLK/GP8[11][5,38]

MMCSD1_DAT[5]/LCD_HSYNC/GP8[9][5,38]MMCSD1_DAT[4]/LCD_VSYNC/GP8[8][5,38]

TSX1_RIGHT[55]

TSX2_LEFT[55]TSY1_TOP[55]

TSY2_BOTTOM[55]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 31 57

B

SMART GRID EVM

BIT MAPPED LCD TOUCH INTERFACE

H = A->B

H = A->B

LCD_B0_B

LCD_R0_B

RGB5

65 to

RGB

666

C1451000pF

R276 NO-POP

RN2RPACK4-22

1234 5

678

U4

SN74AVC16T245DGG

1DIR1

1B0 21B1 3

GND.5 4

1B2 51B3 6

VCCB.2 7

1B4 81B5 9

GND.6 10

1B6 111B7 12

2B0 132B1 14

GND.7 15

2B2 162B3 17

VCCB.1 18

2B4 192B5 20

GND.8 21

2B6 222B7 23

2DIR24

2OE25

2A7262A627

GND.128

2A5292A430

VCCA.131

2A3322A233

GND.234

2A1352A036

1A7371A638

GND.339

1A5401A441

VCCA.242

1A3431A244

GND.445

1A1461A047

1OE48

C1470.1uF

RN6 RPACK4-22

1234 5

678

R50210K

J1

HEADER 30X2

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

C1640.1uF

RN1RPACK4-22

1234 5

678

R50310K

C1460.1uF

C1441000pF

R275NO-POP

R504 NO-POP

C1481000pF

RN5 RPACK4-22

1234 5

678

R505NO-POP

R27410K

C1430.1uF

U5

SN74AVC16T245DGG

1DIR1

1B0 21B1 3

GND.5 4

1B2 51B3 6

VCCB.2 7

1B4 81B5 9

GND.6 10

1B6 111B7 12

2B0 132B1 14

GND.7 15

2B2 162B3 17

VCCB.1 18

2B4 192B5 20

GND.8 21

2B6 222B7 23

2DIR24

2OE25

2A7262A627

GND.128

2A5292A430

VCCA.131

2A3322A233

GND.234

2A1352A036

1A7371A638

GND.339

1A5401A441

VCCA.242

1A3431A244

GND.445

1A1461A047

1OE48

R28810K

R506NO-POP

C1681000pF

R507 NO-POP

RN4RPACK4-22

1234 5

678

C27022uF

RN3RPACK4-22

1234 5

678

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

usb1_vbus

USB0_DMUSB0_DP

MUX0_USB0_DPMUX0_USB0_DM

EVM_5V EVM_5V

3V3_EVM

EVM_5V

USB0_VBUS

3V3_VIO

EVM_5V

EVM_5V

3V3_EVM

3V3_EVM

3V3_EVM

USB1_PWR_EN[9]

UHPI_HRDY/GP6[13] [6,38]

USB0_ID[7]

USB0_DRV_VBUS[7]

USB1_DM[8]USB1_DP[8]

FB_USB0_VBUS[7]

USB0_DM[7]USB0_DP[7]

DP_9621 [24]DM_9621 [24]

GP5[12][9]

GP5[11][9]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 32 57

B

SMART GRID EVM

USB INTERFACE CONNECTORS

For OTG modeor device modepull ID line high

For host only,pull ID line low

FULL SIZE B CONNECTOR

MICRO A-B CONNECTOR

FULL SIZE A CONNECTOR

90 ohm differential pairs

90 ohm differential pairs90 ohm differential pairs

90 ohm differential pairs

J5A

USB-micro/A/B connector

VBUS1AB

D-2AB

D+3AB

GND5AB

SH

IELD

55

ID4AB

SH

IELD

66

SH

IELD

77

SH

IELD

88

MH

19

MH

210

C3500.1uF

R293 0

C1400.1uF

J2

USB-A connector

VBUS1D-2D+3GND4

S25

S16

R28110K

C1540.1uF

R29710K

C4150uF

U51

TPD2E001DRLRG4

Vcc1

IO13 GND 4

IO2 5NC2 2

U56

TS3USB221A

1D+ 11D- 22D+ 32D- 4

GN

D5

OEn6 D-7 D+8 S9 VC

C10

R285NO-POP

J5B


ATTACH1B

D-2BD+3B

GND4B

SHIELD1 1

SHIELD2 2

U52

TPS2042BDGN

GND.11

IN2

EN13 EN24

OC2 5

OUT2 6OUT1 7

OC1 8GND.29

R29910K

R17410K

J5C


VBUS-A1A

D-2AD+3A

GND4A

SHIELD3 3

SHIELD4 4

U49

TPD2E001DRLRG4

Vcc1

IO13 GND 4

IO2 5NC2 2

R292 0

R175NO-POP

Q3BSS138G

DS

Q2BSS138G

DS

C1654.7uF

R17810K

R344

10K

C1660.1uF

C6150uF

R183NO-POP

R8

10K

R29810K

R350 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

User_LED_1

User_SW_4

User_SW_2

User_LED_2

User_SW_1

User_SW_3

User_SW_2

User_SW_4User_SW_3

User_SW_1

L138_LED1

L138_LED2

L138_LED3

3V3_EVM

3V3_VIO

3V3_VIO

3V3_EVM

3V3_EVM

3V3_EVM

3V3_VIO

3V3_EVM

3V3_EVM3V3_EVM 3V3_EVM

3V3_EVM

3V3_EVM

USER_PB_1 [56]

I2C0_SDA[4,19,26,34,37,38,46,55]

I2C0_SCL[4,19,26,34,37,38,46,55]

SW_RST [56]

UHPI_HINTn/GP6[12][6,38]

EMA_A[15]/MMCSD0_DAT[6]/GP5[15][9,37]

EMA_A[14]/MMCSD0_DAT[7]/GP5[14][9,37]

EMA_A[13]/GP5[13][9,37]

MSTR_nRST_3.3_1.811,27,34,36,55,56]

SEL_MDIO_TIMER [21]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 33 57

B

SMART GRID EVM

USER SWITCH & LEDS

USER DIP SWITCHES

IO EXPANDER

TP20

R207 0

TP18

R21810K

R415 330

R4091K

DS2LED GRN

U23D

SN74LV125APWR

1112

13

R2130

C114

0.1uF

C1150.1uF

R417

10K

R416 330

R168220

R21010K

1234

ON

S5

DIP_SWITCH_3

1234 5

678

DS1LED GRN

U23A

SN74LV125APWR

32

1 714

U23C

SN74LV125APWR

89

10

DS3LED GRN

TP14

TP16

U40

TCA6416PW

ADDR 21

GND12

INT1

P00 4P01 5P02 6P03 7P04 8P05 9P06 10P07 11

P10 13P11 14P12 15P13 16P14 17P15 18P16 19P17 20

RESET3

SCL22

SDA23

VCCI2 VCCP 24

R419

10K

R212NO-POP

D18

Green

R4101K

R4111K

R420

10K

TP17

R414 330

R4121K

R169220

TP19

D16

Green

R204 NO-POP

C2100.1uF

D17

Green

U23B

SN74LV125APWR

65

4

TP15

R2034.7k

R167220

R418

10K

TP21

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3V3_VIO

3V3_EVM

3V3_EVM

3V3_VIO

I2C0_SDA[4,19,26,33,37,38,46,55]

I2C0_SCL[4,19,26,33,37,38,46,55]

CC_VREGEN [39]CC_GPIO1 [39]CC_GPIO2 [39]CC_GPIO3 [39]

PLC_RESET [46]

PLC_EN [46]

CPU_CAN_RESETn [41]

RESET_CCn [39,40]

CODEC_RESET [48]

PLC_TXDRVEn [45]

ADC_ENn [43]PLC_AFEP18 [45]

CC_GPIO14 [40]

CC_VREGEN2 [40]CC_GPIO12 [40]CC_GPIO13 [40]

MSTR_nRST_3.3_1.8[11,27,33,36,55,56]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 34 57

B

SMART GRID EVM

BIT RESET AND IO

R185NO-POP

C2760.1uF

R518 NO-POP

C2790.1uF

U34

TCA6416PW

ADDR 21

GND12

INT1

P00 4P01 5P02 6P03 7P04 8P05 9P06 10P07 11

P10 13P11 14P12 15P13 16P14 17P15 18P16 19P17 20

RESET3

SCL22

SDA23

VCCI2 VCCP 24

R18710K

R1900

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AUDIO_EXP_SEL

3V3_EVM3V3_VIO

3V3_VIO

3V3_VIO

3V3_VIO

3V3_VIO

LCD_EXP_EN [31]

AUDIO_EXP_SEL [25]

BOOTMODE[5][5]

BOOTMODE[6][5]

BOOTMODE[7][5]

BOOTMODE[2][5]

BOOTMODE[0][5]

BOOTMODE[4][5]

BOOTMODE[3][5]

BOOTMODE[1][5]ADC_ON [43]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

BOOT SWITCH

BOOT MODE

PROBE GND CONNECTOR

Distribute 2 pin headersaround outside edges of the board

BOOT[4] BOOT[3] BOOT[1] BOOT[0]MODE

NOR EMIFA

NAND-8 EMIFA

SPI1 FLASHDEFAULT

UART2

EMU DEBUG

OFF

OFF

OFF

ON

ON OFF OFF ON

S2:8 S2:5S2:6S2:7

ON ON ON

ON

ON OFF OFF

OFF OFF

OFF OFF OFF

R453NO-POP

R194NO-POP

R2011K

J14

HEADER2

12

R4541K

R393NO-POP

R4551K

R3901K

J13

HEADER2

12

R196NO-POP

R4001K

R456NO-POP

R394NO-POP

R3911K

R457NO-POP

R3881K

R193NO-POP

R3924.7K

R4584.7K

1234

ON

5678

S2MINI_DIP_SW8

123456789 10 11 12 16151413

R3971K

R4594.7K

R398NO-POP

J8

HEADER2

12

R3891K

R195NO-POP

R452NO-POP

R399NO-POP

R3954.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TDI

EMU0

TMS

TRSTn

RTCKTDO

RTCKJTAG_TCKTMS

TDO

JTAG_TCKEMU1

TRSTn

RTCK

TDO

TDI

TRSTn

TMS

TDI

3V3_VIO

3V3_VIO3V3_VIO

3V3_VIO

TCK [11]

TRSTn [11]

TMS [11]

TDI [11]

RTCK [11]

TDO [11]

MSTR_nRST_3.3_1.8 [11,27,33,34,55,56]

EMU1 [11]

EMU0 [11]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

JTAG CONNECTORS

ARM JTAG

TI 14 PIN JTAG

U47

SN74LVC1G125DCKR

OE1

A2

GND 3

VCC 5

Y 4

J12

header 7x2

2468

101214

135791113

C303

0.1uF

R403 0

R40210K

R244 22

C131

0.1uF

J11

HEADER 10X2

135791113151719

2468

101214161820

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3V3_VIO

5V_IN 5V_IN

EMA_D[11]/GP3[3] [9]

EMA_CS[0]/GP2[0][9]

EMA_A[2]/GP5[2] [9,20,27]

EMA_A[10]/GP5[10] [9]

EMA_A[4]/GP5[4] [9]

EMA_CS[5]/GP3[12][9,27]

EMA_D[3]/GP4[11] [9,20,27]

EMA_CS[4]/GP3[13][9,20]EMA_CS[3]/GP3[14][9,20]

EMA_D[13]/GP3[5] [9]

EMA_A[6]/GP5[6] [9,41]

EMA_D[5]/GP4[13] [9,20,27]

EMA_D[15]/GP3[7] [9]

I2C0_SCL [4,19,26,33,34,38,46,55]

EMA_RNW/GP3[9] [9]

I2C0_SDA [4,19,26,33,34,38,46,55]

EMA_A[14]/MMCSD0_DAT[7]/GP5[14] [9,33]

EMA_D[1]/GP4[9] [9,20,27]

EMA_CLK/GP2[7] [9]

EMA_A[12] GP5[12] [9]

EMA_CS[2]/GP3[15][9]

EMA_D[7]/GP4[15] [9,20,27]

EMA_A[0]/GP5[0] [9,27]

EMA_D[9]/GP3[1] [9]

EMA_A[8]/GP5[8] [9]

RESETOUTn[6,22,24,26,38]

EMA_D[2]/GP4[10][9,20,27]EMA_D[4]/GP4[12][9,20,27]

EMA_A[3]/GP5[3][9]

EMA_WEn/GP3[11] [9,20,27]

EMA_BA[0]/GP2[8] [9,27,31]EMA_D[0]/GP4[8][9,20,27]

EMA_D[10]/GP3[2][9]

EMA_A[11]/GP5[11][9]

EMA_A[1]/GP5[1][9,20,27]

EMA_D[6]/GP4[14][9,20,27]

EMA_A[13]/GP5[13][9,33]

EMA_A[5]/GP5[5][9]

EMA_OEn/GP3[10] [9,20,27]

EMA_WAIT[0]/GP3[8] [9,20]

EMA_A[15]/MMCSD0_DAT[6]/GP5[15][9,33]

EMA_BA[1]/GP2[9] [9,27]

EMA_D[14]/GP3[6][9]

EMA_WAIT[1]/GP2[1] [9]

EMA_D[8]/GP3[0][9]

EMA_A[9]/GP5[9][9]

EMA_D[12]/GP3[4][9]

EMA_A[7]/GP5[7][9,41]

SPI0_CLK/EPWM0A/GP1[8]/MII_RXCLK[4,22]SPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER[4,22]SPI0_SIMO/EPWMSYNCO/GP8[5]/MII_CRS[4,22]

SPI0_ENAn/EPWM0B/MII_RXDV[4,22]SPI0_SCS[2]/UART0_RTSn/GP8[1]/MII_RXD[0]/SATA_CP_DET[4,22]

SPI0_SCS[3]/UART0_CTSn/GP9[2]/MII_RXD[1]/SATA_MP_SWITCH[4,22]SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2][4,22]

SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3][4,22]

SD0_DATA2[9,30]SD0_DATA0[9,30]

SD0_CLK[9,30]

SD_WP[9,30] SD_INS [9,30]SD0_DATA3 [9,30]SD0_DATA1 [9,30]SD0_CMD [9,30]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

EMIF EXPANSION CONNECTOR

40

4142

80 79

39

J15

100 pins

2468

101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698

100

13579111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799

R3961K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

5V_IN5V_IN

3V3_VIO

VP_DIN[12]/UHPI_HD[4]/UPP_CHA_D[4] [6,43]VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_CHA_D[6] [6,43]

VP_DIN[0]/UHPI_HD[8]/UPP_CHA_D[8]/RMII_CRS_DV [6,43]

VP_DIN[8]/UHPI_HD[0]/UPP_CHA_D[0]/GP6[5] [6,43]

VP_DIN[4]/UHPI_HD[12]/UPP_CHA_D[12]/RMII_RXD[1] [6]

VP_DIN[10]/UHPI_HD[2]/UPP_CHA_D[2] [6,43]

VP_DIN[2]/UHPI_HD[10]/UPP_CHA_D[10]/RMII_RXER [6]

VP_DIN[6]/UHPI_HD[14]/UPP_CHA_D[14]/RMII_TXD[0] [6]

VP_CLKIN3/MMCSD1_DAT[1]/GP6[2] [5]

VP_CLKO2/MMCSD1_DAT[2]/GP6[3] [5]

VP_CLKO3/GP6[1] [5]


VP_DOUT[15]/LCD_D[15]/UPP_XD[7]/GP7[7][5,31]


VP_DOUT[9]/LCD_D[9]/UPP_XD[1]/GP7[1][5,31]


VP_DOUT[4]/LCD_D[4]/UPP_XD[12]/GP7[12] [5,31]





VP_DOUT[10]/LCD_D[10]/UPP_XD[2]/GP7[2] [5,31]VP_DOUT[12]/LCD_D[12]/UPP_XD[4]/GP7[4] [5,31]


I2C0_SDA [4,19,26,33,34,37,46,55]I2C0_SCL [4,19,26,33,34,37,46,55]

RESETOUTn[6,22,24,26,37]

VP_DIN[5]/UHPI_HD[13]/UPP_CHA_D[13]/RMII_TXEN[6]

MMCSD1_DAT[5]/LCD_HSYNC/GP8[9][5,31]MMCSD1_DAT[7]/LCD_PCLK/GP8[11][5,31]

VP_DIN[7]/UHPI_HD[15]/UPP_CHA_D[15]/RMII_TXD[1][6]

MMCSD1_DAT[6]/LCD_MCLK/GP8[10][5]

MMCSD1_DAT[0]/UPP_CHB_CLK/GP8[15][5]

MMCSD1_CMD/UPP_CHB_ENABLE/GP8[13][5]

VP_DIN[3]/UHPI_HD[11]/UPP_CHA_D[11]/RMII_RXD[0][6]

MMCSD1_CLK/UPP_CHB_START/GP8[14][5]


VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_CHA_D[7][6,43]

MMCSD1_DAT[4]/LCD_VSYNC/GP8[8][5,31]

VP_DIN[1]/UHPI_HD[9]/UPP_CHA_D[9]/RMII_MHZ_50_CLK[6,43]

VP_DIN[9]/UHPI_HD[1]/UPP_CHA_D[1][6,43]VP_DIN[11]/UHPI_HD[3]/UPP_CHA_D[3][6,43]

VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_CHA_D[5][6,43]

VP_CLKIN0/UHPI_HCSn/GP6[7]/UPP_2xTXCLK[6]

VP_CLKIN1/UHPI_HDS1n/GP6[6][6]

VP_CLKIN2/MMCSD1_DAT[3]/GP6[4][5]

SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 [4,21]

UHPI_HCNTL1/UPP_CHA_START/GP6[10] [6]UHPI_HCNTL0/UPP_CHA_CLK/GP6[11] [6,43]UHPI_HHWIL/UPP_CHA_ENABLE/GP6[9] [6]UHPI_HRWn/UPP_CHA_WAIT/GP6[8] [6]UHPI_HRDY/GP6[13] [6,32]UHPI_HINTn/GP6[12] [6,33]UPP_CHB_WAIT/GP8[12] [5]

SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12 [4,21]NMIn[11]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

LCD/VPIF EXPANSION CONNECTOR

40 39

42 41

R4131K

J16

100 pins

2468

101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698

100

13579111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RESET_CC2530CC_P0.5

RESET_CCnCC_P0.7CC_P0.6CC_P1.1CC_P0.0

CC_P0.1RESET_CCnCC_P0.2CC_P0.3

CC_P0.4

CC_P2.0

CC_P1.3

CC_P1.4

CC_P2.1CC_P2.2

CC_P1.5

CC_P1.7CC_P1.6

CC_SPI1_SOMI/GP2[11]CC_SPI1_SIMO/GP2[10]CC_SPI1_CLK/GP2[13]

CC_SPI_CSAn

CC_P1.0

TM64P0_OUT12

CC_SPI_CSAn

CC_SPI_CSBn

3V3_EVM

3V3_EVM

3V3_EVM

RESET_CCn[34,40]CC_UART_TXOUT[27]CC_UART_RXIN[27]

CC_SPI1_SIMO/GP2[10] [17,40]CC_SPI1_CLK/GP2[13] [17,40]

CC_SPI1_SOMI/GP2[11] [17]

CC_GPIO2[34]

CC_VREGEN[34]

CC_GPIO3 [34]

CC_GPIO1 [34]

CC_SPI1_SCS[1]/EPWM1A/GP2[15]/TM64P2_IN12[17]CC_SPI_CSBn [40]

TM64P0_OUT12 [21]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

D


514202-0001

Monday, May 21, 2012 39 57

B

SMART GRID EVM

ZIGBEE INTERFACE

NOTE: DIMENSIONS AND LOCATIONS OF THESE CONNECTORS MUST MEET SPECIFICATION FOR INTERFACE MODULESREFERENCE CC2530-EVM-UG

1 1

P0.2 - CC MODULE UART RX

P0.3 - CC MODULE UART TX

P1.4 - CC MODULE SS

P1.5 - CC MODULE C

P1.6 - CC MODULE MO

P1.7 - CC MODULE MI

P1 P2ON CC MODULES

P21 P20 ON SMART GRID BOARD

R53 0

R21110K

P20

HEADER 10X2

13579

1113151719

2468101214161820

R249 0R77 0

R232 0

R22510K

R231 0

C1320.1UF

R238 0

TP31TP-20RD10TP30TP-20RD10

JP14

CON3

12

3

TP26TP-20RD10

R242 0

TP39TP-20RD10

R248 0

P21

HEADER 10X2

13579

1113151719

2468101214161820

R100 0

R233 0

R23 NO-POP

TP25TP-20RD10

TP28TP-20RD10

R33 NO-POP

R243 0

R245 0

R240 0

R250 0

+C13310UF

TP24TP-20RD10

R239 0R235 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CC2_P0.5CC_P2.0

RESET2_CC2530RESET_CCn

CC_SPI1_CLK/GP2[13]CC_SPI_CSBn

CC2_P1.3CC2_P1.0

CC2_P1.4CC2_P1.5

CC2_P2.1CC2_P2.2

CC2_P1.6CC2_P1.7

CC2_P0.7CC2_P0.6CC2_P1.1CC2_P0.0

CC2_P0.1RESET_CCn

CC2_SPI1_SOMICC_SPI1_SIMO/GP2[10]

CC2_P0.2CC2_P0.3

CC2_P0.4

TM64P1_OUT12

3V3_EVM

CC_GPIO13 [34]CC_GPIO12[34]

CC_GPIO14 [34]

RESET_CCn[34,39]CC2_UART_TXOUT[27]CC2_UART_RXIN[27]

CC_SPI1_SIMO/GP2[10] [17,39]CC_SPI1_CLK/GP2[13] [17,39]

CC2_SPI1_SOMI [17]

CC_SPI_CSBn [39]

CC_VREGEN2[34]

TM64P1_OUT12 [21]

Size:

Date:

DWG NORevision:

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D


514202-0001

Monday, May 21, 2012 40 57

B

SMART GRID EVM

XXX INTERFACE

1 1

P1 P2ON CC MODULES

P25 P24ON SMART GRID BOARD

NOTE: DIMENSIONS AND LOCATIONS OF THESE CONNECTORS MUST MEET SPECIFICATION FOR INTERFACE MODULESREFERENCE

P0.2 - CC MODULE UART RX

P0.3 - CC MODULE UART TX

P1.4 - CC MODULE SS

P1.5 - CC MODULE C

P1.6 - CC MODULE MO

P1.7 - CC MODULE MI

C3670.1UF

R234 0

+C36810UF

P25

HEADER 10X2

13579

1113151719

2468101214161820

R154 NO-POP

TP43TP-20RD10

TP27TP-20RD10

R159 NO-POP

R483 0

R490 0TP41TP-20RD10

R484 0

TP44TP-20RD10

R485 0

TP29TP-20RD10

R491 0

P24

HEADER 10X2_0

13579

1113151719

2468101214161820

R151 0

TP42TP-20RD10

R492 0R486 0

R257 0

R487 0

R482 0

R131 0

R488 0

TP40TP-20RD10

R489 0 R120 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CANHA

CANLA

3V3_EVM

GND_ISO_CAN

3V3_EVM

CAN_SPI1_CLK/GP2[13][17]

CAN_SPI1_SOMI/GP2[11][17]

CPU_CAN_RESETn[34]SPI1_CS_CANn[17]

CAN_SPI1_SIMO/GP2[10][17]

CPU_CAN_INTERRUPT[9]

EMA_A[6]/GP5[6][9,37]

EMA_A[7]/GP5[7][9,37]

Size:

Date:

DWG NORevision:

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Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

CAN INTERFACE

2

CAN-TERM

R14 0

R11 NO-POP

R13 NO-POP

U7

SN65HVD235

VCC 3

CANH 7

CANL 6

GND 2

AB5

TXD1

RXD4

RS8

U13

MCP2515-I/SO

TXCAN 1RXCAN 2

CLKOUT/SOF 3TX0RTSn 4TX1RTSn 5TX2RTSn 6

OSC2 7OSC1 8

VSS 9

VDD18RESETn17CSn16SO15SI14SCK13INTn12RX0BFn11RX1BFn10

JP1

HEADER 2

12

C1700.1uF

R4120 SIZE 1206

Y320MHz

GND

U50

SM712.TCT

1 2

3

C24 33pF

C175.1uF

R12 0

C25 33pF

P3DB9F

594837261

1011

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LINE_N

LINE_AC

ZERO_PLC

3V3_EVM

3V3_EVM

LINE_AC[44]

ZERO_PLC [9,46]

LINE_N [44]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

ZERO CROSSING DETECTOR

R247 100K

R2561.5K 5 %

C3090.1uF

R258 270

U48

SN74LVC1G57DCKR

IN0(A)3

IN1(B)1

GN

D2

Y 4VD

D5

IN2(AB)6

R255240K

R252 0

D22DL4148-TP

C3080.1uF

D21BZV55 C136

.33uF

R251 100K

ISO1FOD817BSD

21 4

3

R241 100K Q1BC817-40LT1G

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ADC_ON

3V3_ADS901

ADC_D0

ADC_D9

ADC_D4ADC_D5

ADC_D1

ADC_D6

ADC_D2ADC_D3

ADC_D7ADC_D8

ADC_CLK

ADC_ON

3V3_EVM 3V3_EVM

3V3_EVM

3V3_EVM

ADC_GND

ADC_GND

ADC_GND

ADC_GND

ADC_GND ADC_GND

ADC_GND

VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_CHA_D[5][6,38]VP_DIN[12]/UHPI_HD[4]/UPP_CHA_D[4][6,38]VP_DIN[11]/UHPI_HD[3]/UPP_CHA_D[3][6,38]VP_DIN[10]/UHPI_HD[2]/UPP_CHA_D[2][6,38]

VP_DIN[9]/UHPI_HD[1]/UPP_CHA_D[1][6,38]VP_DIN[8]/UHPI_HD[0]/UPP_CHA_D[0]/GP6[5][6,38]

VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_CHA_D[6][6,38]VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_CHA_D[7][6,38]

VP_DIN[0]/UHPI_HD[8]/UPP_CHA_D[8]/RMII_CRS_DV[6,38]

UHPI_HCNTL0/UPP_CHA_CLK/GP6[11][6,38]

ADC_ENn[34]

VP_DIN[1]/UHPI_HD[9]/UPP_CHA_D[9]/RMII_MHZ_50_CLK[6,38]

ADC_ON[35]

PLC_ADCIN [45]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

ADC FOR PLC INTERFACE

R4014.7k5%

R4044.7k5%

FB1 Ferrite

U46

SN74LVC1G125DCKR

OE 1

A 2

GND3

VCC5

Y4

RN154.7K

1 2 3 45678 C121

0.1uF

C2980.1uF

R246 22

C3070.1uF

C1250.01uF

C1231uF

C3020.1uF

C1240.1uF

FB2

Ferrite

Y6

10MHZ

OE1

GND2 OUT 3

VDD 4

C1270.1uF

R4054.7k5%

U44

ADS901E

+Vs.3 1LVdd 2

D0(LSB)3 D14 D25 D36 D47 D58 D69 D710 D811 D9(MSB)12

GND.413 GND.314

CLK15

OE16

PWRdn17

+Vs.2 18

GND.219 GND.120

LpBy21

REFT 22

NC23

REFB 24

LnBy25

CM 26

IN 27

+Vs.1 28

C3060.1uF

C296 0.1uF

RN144.7K

1 2 3 45678

R230 4.7k 5%

RN164.7K

1 2 3 45678

C2990.1uF

C3000.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LINE_N

LINE_AC

LINE_N_F

LINE_A

LINE_A_CON

LINE_N_F

LINE_A

LINE_N_F

LINE_A

PL_TXRX

GND_AC_PWR

GND_AC_PWR

GND_AC_PWR

GND_AC_PWR

GND_AC_PWR GND_AC_PWR

LINE_N [42]

LINE_AC [42]

PL_TXRX [45,46]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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D


514202-0001

Monday, May 21, 2012 44 57

B

SMART GRID EVM

PLC INTERFACE

SD PART# 103531-0001R

T2

NO-POP(TRANS_DA2303AL)

8

7

5

6

4

32

1

L23 NO-POP(FIT44-2)

JP11HDR_2_P1_INCH

12

P17

1714968

123

TP36

Test Point_0

C129

0.47uF_440V_(BFC233810474)

C870.01uF 250V

D1SM6T10CA

TP37

Test Point_0

L22 NO-POP(FIT44-2)

JP7HDR_2_P1_INCH

12

JP9HDR_2_P1_INCH

12

L26 DR1040-150-R

R1714.7

R2281MR226

NO-POP

T1

VITEC_TRANS_70PR7282

1

2

5

4

10

97

6

JP6HDR_2_P1_INCH

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PL_TXRX

PLC_ADCIN

PLC_AFEP16

PLC_AFEP14

PLC_AFEP18

PLC_TXDRVEn

PLC_AFEP17

PLC_AFEP15

PLC_3V3

PLC_5V0

PLC_VPLC

GND_AC_PWR

PLC_5V0EVM_5V

PLC_PWM2[2]

PLC_PWM1[2]

PL_TXRX [44,46]

PLC_TXDRVEn [34]

PLC_ADCIN [43]

PLC_AFEP18 [34]

PLC_AFEP16 [2,46]

PLC_AFEP14 [2,46]

MDM_SPI1_ENAn/GP2[12][16,46]

MDM_SPI1_SIMO/GP2[10][16,46]

MDM_SPI1_CLK/GP2[13][16,46]

MDM_SPI1_SOMI/GP2[11][16,46]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

PLC MODULE

R594.7K

R814.7K

R116 0

R56 0

R122 0

R128 0

R107 0

MODULE1

PLC_AFE

11

22

33

44

55

66

77

88

99

1010

1111

1212 13 13

14 14

15 15

16 16

17 17

18 18

19 19

20 20

21 21

22 22

23 23

24 24

R1174.7K

R114 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PL_TXRXL1

ADC_B0

PLC_GPIO4

I2C0_SDA I2C0_SCL

PLC_RXBPLC_TXB

PLC_3V3PLC_VPLC

EVM_15V PLC_VPLC

PLC_3V33V3_EVM

GND_AC_PWR

PLC_3V3PLC_3V3

MDM_SPI1_SIMO/GP2[10][16,45]MDM_SPI1_CLK/GP2[13][16,45]

MDM_SPI1_SOMI/GP2[11] [16,45]PLC_RESET[34]

PLC_EN[34]SPI1_SCS[2]/UART1_TXD/SATA_CP_POD/GP1[0][4] SPI1_SCS[3]/UART1_RXD/SATA_LED/GP1[1] [4]

PL_TXRX [44,45]

ZERO_PLC [9,42]

I2C0_SCL [4,19,26,33,34,37,38,55]I2C0_SDA[4,19,26,33,34,37,38,55]

MDM_SPI1_ENAn/GP2[12] [16,45]

PLC_TXB[27] PLC_RXB [27]

PLC_AFEP16 [2,45]

PLC_AFEP14[2,45]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 46 57

B

SMART GRID EVM

PLC MODULE 2

R113NO-POP

R910

R73 NO-POP R74 NO-POPR80 NO-POP

R102 0

R970

Z51

R58 NO-POP

R94 NO-POP

R109 0

Z61

R41 0

R57 NO-POP

R70 NO-POP

R90 NO-POP

R98NO-POP

R108 0R101 0

R78 0

R79 NO-POP

R95 NO-POP

P7

SFH31-NPPB-D17-SP-BK

1 23 45 67 89

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 34

10

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TLV34_VREFVREF_2.048V VREF_1V65

AVCC

5V_ISO

5V_IN

GND_ISO

3V3_ISO5V_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISOGND_ISO

GND_ISO

1V8_ISO5V_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISOGND_ISO

GND_ISO

5V_ISO

5V_ISO

GND_ISO

GND_ISOGND_ISO

GND_ISO

GND_ISOGND_ISO

3V3_ISOAVCC

AC_AGNDGND_ISO

GND_ISO GND_ISO

TLV34_VREF [51,52]

AVCC [52]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

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D


514202-0001

Monday, May 21, 2012 47 57

B

SMART GRID EVM

ISOLATION POWER

VOUT = 0.8 * ( 1+(RTOP/RBOTTOM) )

3.3 = 0.8 * ( 1+(RTOP/RBOTTOM ))

4.125 = ( 1+(RTOP/RBOTTOM ))

3.125 RBOTTOM = RTOP

VOUT = 0.8 * ( 1+(RTOP/RBOTTOM) )

1.8 = 0.8 * ( 1+(RTOP/RBOTTOM ))

2.25 = ( 1+(RTOP/RBOTTOM ))

1.25 RBOTTOM = RTOP

R2094.99K 1%

U17R05P05S

VIN

-2

VIN

+1

VO

UT-

5

VO

UT+

7

U38TPS74701

IN11 VOUT2 10

BIAS4 PG 3

EN5 GND 6

IN22

SS7 FB 8

VOUT1 9

PP

111

R716.24 1%

C2862.2uF

R40 4.99K

R501K

R554.99K 1%C179

0.001uF

C2880.001uF

C1842.2uF

C5110uF

C291uF

R21 0

R25 0

U18TPS74701

IN11 VOUT2 10

BIAS4 PG 3

EN5 GND 6

IN22

SS7 FB 8

VOUT1 9

PP

111

C1855.6pF

TP35

TP

C1770.1uF

U15LM4040A20IDBZT

21

3

R22NO-POP

C13 NO-POP

R20215.8K 1% C285

5.6pF

R214 0

TP34

TP

-

+ U14OPA356AIDDBV

3

41

52

R390 C22

.1uF

C11210uF

R3520K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ISO_I2C_SDA_ENABLE

BIT_I2C_SDA_IN

BIT_I2C_SCL

BIT_I2C_SDA_OUT

BIT_I2C_SDA_EN

ISO_I2C_SDA_IN

GND_ISO

3V3_ISO

GND_ISO

3V3_EVM

GND_ISO

3V3_ISO

GND_ISO

3V3_EVM

3V3_ISO

GND_ISO

3V3_ISO

GND_ISO

3V3_EVM

3V3_EVM

GND_ISO

3V3_ISO

GND_ISO

3V3_EVM

3V3_ISO

GND_ISO

3V3_EVM

3V3_ISO

GND_ISO

GND_ISO

3V3_ISO

ISO_AIC34_AXR11 [50]


ISO_AIC34_ACLKX [49,50]

ISO_AIC34_AFSX [49,50]

ISO_AIC34_AHCLKX [49,50]



ISO_RSTn_AIC34 [49,50]

ISO_I2C_SCL [49,50]

AIC34_AXR11[25]

AIC34_AXR12[25]

AIC34_ACLKX[25]

AIC34_AFSX[25]

AIC34_AHCLKX[25]

AIC34_AXR13[25]

AIC34_AXR14[25]

ISO_I2C_SDA_OUT [49,50]

CODEC_RESET[34]

L138_BIT_I2C_SDA_OUT[2]

L138_BIT_I2C_SDA_IN[2]

L138_BIT_I2C_SDA_EN[2]

L138_BIT_I2C_SCL[2]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

B


514202-0001


B

SMART GRID EVM

GALVANIC ISOLATION

R850

C2070.1uF

R1560

R99 0

R157NO-POP

R152 NO-POP

U27

ISO7240CFDW

VCC1 1

GND1.1 2

INA 3

INB 4

INC 5

IND 6

ENABLE 7

GND1.2 8GND2.29

CTRL10

OCTD11

OUTC12

OUTB13

OUTA14

GND2.115

VCC216

R84NO-POP

R153 0

R96 0

C2670.1uF

U33

ISO7240CFDW

VCC1 1

GND1.1 2

INA 3

INB 4

INC 5

IND 6

ENABLE 7

GND1.2 8GND2.29

CTRL10

OCTD11

OUTC12

OUTB13

OUTA14

GND2.115

VCC216

R130 0

R1970

R198NO-POP

R87 NO-POPR930

R86 0

C2080.1uFU21

ISO7240CFDW

VCC11

GND1.12

INA3

INB4

INC5

IND6

ENABLE7

GND1.28 GND2.2 9

CTRL 10

OCTD 11

OUTC 12

OUTB 13

OUTA 14

GND2.1 15

VCC2 16

C2680.1uF

R191 NO-POPR192 0

C199.1uF

C2280.1uF

U20SN74LVC1G1253

4

5

2

1

R92 0

R4512.2K

C2290.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AIC34_DVDD

AIC34_AVDD

AIC34_AVDD

AIC34_IOVDD

AIC34_DRVDD

3V3_ISO

3V3_ISO

3V3_ISO

3V3_ISO

3V3_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISO GND_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISO GND_ISO

1V8_ISO

GND_ISO

GND_ISO

GND_ISO

ISO_I2C_SCL[48,50]ISO_I2C_SDA_OUT[48,50]

ISO_AIC34_AXR12[48]

ISO_AIC34_ACLKX[48,50]

ISO_AIC34_AFSX[48,50]

ISO_AIC34_AHCLKX[48,50]

ISO_AIC34_AXR14[48]

ISO_RSTn_AIC34[48,50]

V1+[51]V1-[51]

I1+[52]I1-[52]

CODEC_CLK2[50]

V2+[51]V2-[51]

I2+[52]I2-[52]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

B


514202-0001


B

SMART GRID EVM

TLV320AIC34 CODEDR141NO-POP

R1340

R148 0

R181 0

R1420

R179 10K

L12

FERRITE CHIP

R165 0

C990.1uF

R127 0

C960.1uF

C105

.1uF

R176 0R437 22

R138 0

U31

TLV320AIC34IZAS

LINE2LP_AH10LINE2LM_AG10

LINE1LP_AK9LINE1LM_AL10

LINE1RP_AK10LINE1RM_AJ10

LINE2RP_AF10LINE2RM_AE10

MIC3L_AD10MIC3R_AA10

MIC3L_BD11MIC3R_BA11

LINE2LP_BH11LINE2LM_BG11

LINE1LP_BK8LINE1LM_BL11

LINE1RP_BK11LINE1RM_BJ11

LINE2RP_BF11LINE2RM_BE11

SC

LL9

SD

AL6

RE

SE

TAn

G2

RE

SE

TBn

G1

MICBIAS_AB10

MICBIAS_BB11

MICDET_AC10

MICDET_BC11

MC

LK_A

K2

MC

LK_B

L1

IOV

DD

.1H

7IO

VD

D.2

K7

HPRCOM_B A6

HPRCOM_A B6

AD

DR

_AL7

AD

DR

_BL8

AV

DD

_DA

CB

3

AV

SS

_AD

CD

8

AV

SS

_DA

C.1

D4

AV

SS

_DA

C.2

E4

AV

SS

_DA

C.3

F4A

VS

S_D

AC

.4G

4

BC

LK_A

K3

BC

LK_B

L2

DIN

_AK

5

DIN

_BL4

DO

UT_

AK

6

DO

UT_

BL5

WC

LK_A

K4

WC

LK_B

L3

DR

VD

D.1

B4

DR

VD

D.2

A4

DR

VD

D.3

B9

DR

VD

D.4

A9

DR

VS

S.1

D5

DR

VS

S.2

D6

DR

VS

S.3

D7

DV

DD

K1

DV

SS

.1E

8D

VS

S.2

F8D

VS

S.3

G8

DV

SS

.4H

4D

VS

S.5

H5

DV

SS

.6H

6D

VS

S.7

H8

HPLCOM_B A7

GPIO1_A J2

GPIO1_B J1

GPIO2_A H2

GPIO2_B H1

HPROUT_A B5

HPLCOM_A B7

HPROUT_B A5

HPLOUT_A B8

HPLOUT_B A8

LEFT_LOM_A D2

LEFT_LOM_B D1

LEFT_LOP_A C2

LEFT_LOP_B C1

MONO_LOM_A A2

MONO_LOM_B B1

MONO_LOP_A A3

MONO_LOP_B A1

RIGHT_LOM_A F2

RIGHT_LOM_B F1

RIGHT_LOP_A E2

RIGHT_LOP_B E1

R145 0

U24

24 MHz

OFFn 1

GND 2

VCC4

CLK3

R144 10K

L33

FERRITE CHIP

C2454.7uF

C1074.7uF

R180 0

C79

.1uF

C240

.1uF

R166 0

C2784.7uF

C280

.1uF

C774.7uF

R150 0

C700.1uF

L10

FERRITE CHIP

R147 22

C980.1uF

R125 0

C102

.1uF

R135NO-POP

R182 0

R146 0

C970.1uF

C94

.1uF

R162 0

C258

.1uF

L32

FERRITE CHIP

R143 0

L17

FERRITE CHIP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AIC34_DVDD_B

AIC34_AVDD_B

AIC34_AVDD_B

AIC34_IOVDD_B

AIC34_DRVDD_B

3V3_ISO

3V3_ISO

3V3_ISO

3V3_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISO

GND_ISO GND_ISO

GND_ISO

GND_ISO

GND_ISO GND_ISO

1V8_ISO

GND_ISO

GND_ISO

GND_ISO ISO_I2C_SCL[48,49]ISO_I2C_SDA_OUT[48,49]

ISO_AIC34_AXR11[48]

ISO_AIC34_ACLKX[48,49]

ISO_AIC34_AFSX[48,49]

ISO_AIC34_AHCLKX[48,49]

ISO_AIC34_AXR13[48]

ISO_RSTn_AIC34[48,49]

IN4-[52]

V4+[51]V4-[51]

IN+[52]

CODEC_CLK2 [49]

I3+[52]I3-[52]

V3+[51]V3-[51]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

B


514202-0001


B

SMART GRID EVM

TLV320AIC34 CODED

L36

FERRITE CHIP

R442NO-POP

R440 0R443 10K

C311

.1uF

R438 0

R445 10K

C3144.7uF

C316

.1uF

R432 0

C319

.1uF

R423 0

C315

.1uF

R431 0

R426 0

L37

FERRITE CHIP

C3124.7uF

C3240.1uF

R450 NO-POP

U53

TLV320AIC34IZAS

LINE2LP_AH10LINE2LM_AG10

LINE1LP_AK9LINE1LM_AL10

LINE1RP_AK10LINE1RM_AJ10

LINE2RP_AF10LINE2RM_AE10

MIC3L_AD10MIC3R_AA10

MIC3L_BD11MIC3R_BA11

LINE2LP_BH11LINE2LM_BG11

LINE1LP_BK8LINE1LM_BL11

LINE1RP_BK11LINE1RM_BJ11

LINE2RP_BF11LINE2RM_BE11

SC

LL9

SD

AL6

RE

SE

TAn

G2

RE

SE

TBn

G1

MICBIAS_AB10

MICBIAS_BB11

MICDET_AC10

MICDET_BC11

MC

LK_A

K2

MC

LK_B

L1

IOV

DD

.1H

7IO

VD

D.2

K7

HPRCOM_B A6

HPRCOM_A B6

AD

DR

_AL7

AD

DR

_BL8

AV

DD

_DA

CB

3

AV

SS

_AD

CD

8

AV

SS

_DA

C.1

D4

AV

SS

_DA

C.2

E4

AV

SS

_DA

C.3

F4A

VS

S_D

AC

.4G

4

BC

LK_A

K3

BC

LK_B

L2

DIN

_AK

5

DIN

_BL4

DO

UT_

AK

6

DO

UT_

BL5

WC

LK_A

K4

WC

LK_B

L3

DR

VD

D.1

B4

DR

VD

D.2

A4

DR

VD

D.3

B9

DR

VD

D.4

A9

DR

VS

S.1

D5

DR

VS

S.2

D6

DR

VS

S.3

D7

DV

DD

K1

DV

SS

.1E

8D

VS

S.2

F8D

VS

S.3

G8

DV

SS

.4H

4D

VS

S.5

H5

DV

SS

.6H

6D

VS

S.7

H8

HPLCOM_B A7

GPIO1_A J2

GPIO1_B J1

GPIO2_A H2

GPIO2_B H1

HPROUT_A B5

HPLCOM_A B7

HPROUT_B A5

HPLOUT_A B8

HPLOUT_B A8

LEFT_LOM_A D2

LEFT_LOM_B D1

LEFT_LOP_A C2

LEFT_LOP_B C1

MONO_LOM_A A2

MONO_LOM_B B1

MONO_LOP_A A3

MONO_LOP_B A1

RIGHT_LOM_A F2

RIGHT_LOM_B F1

RIGHT_LOP_A E2

RIGHT_LOP_B E1

C318

.1uF

R4410

L34

FERRITE CHIP

R439 0

R424 0

C3230.1uF

R4490

C317

.1uF

C313

.1uF

C3210.1uF

R434 0

R448NO-POP

C3104.7uF

R446 0

C3220.1uF

R447 0

R444 0

L35

FERRITE CHIP

R433 0

C3204.7uF

R425 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TLV34_VREF

TLV34_VREF

TLV34_VREF

TLV34_VREF

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

V1+ [49]

V1- [49]

V2+ [49]

V2- [49]

V3+ [50]

V3- [50]

V4+ [50]

V4- [50]

TLV34_VREF[47,52]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 51 57

B

SMART GRID EVM

DDR2 - EMIF B

RV1S20K275

12

C1747pF 50V

R172 330K 1%

L4

EXCML20A390U1 2

JP3HDR3_0P1INCH

123

C352 0.47uF

R1101.5K 5 %

L14

EXCML20A390U1 2

C210.015uF

R119 330K 1%R118 330K 1%

R177 330K 1%

C353 0.47uF

P9

17067141

L9

EXCML20A390U1 2

JP4HDR3_0P1INCH

123

R173 330K 1%

C6447pF 50V

R281.5K 5 %

C4247pF 50V

C6547pF 50V

C354 0.47uF

P6

17067141

R32 330K 1%

P5

17067141

R76 330K 1%

C355 0.47uF

RV4S20K275

12

C1647pF 50V

C580.015uF

P11

17067141

R82 330K 1%

C7647pF 50V

R31 330K 1%

P10

17067141

L6

EXCML20A390U1 2

R621.5K 5 %

C356 0.47uF

R123 330K 1%

P12

17067141

R34 330K 1%

C880.015uF

L2

EXCML20A390U1 2

C357 0.47uF

RV2S20K275

12

R1581.5K 5 %

C7547pF 50V

L13

EXCML20A390U1 2

JP5HDR3_0P1INCH

123

L5

EXCML20A390U1 2

RV3S20K275

12

L1

EXCML20A390U1 2

C358 0.47uF

C4347pF 50V

C680.015uF

R75 330K 1%

P8

17067141

P4

17067141

C351 0.47uF

JP2HDR3_0P1INCH

123

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TLV34_VREF

TLV34_VREF

TLV34_VREF

TLV34_VREF

AVCC

AVCC

AVCC

AVCC

AVCC

AVCC

AVCC

AVCC

AVCC

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGNDAC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AC_AGND

AVCC

TLV34_VREF[47,51]

I1+ [49]

I1- [49]

I2+ [49]

I2- [49]

I3+ [50]

I3- [50]

IN+ [50]

IN4- [50]

AVCC [47]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 52 57

B

SMART GRID EVM

DDR2 - EMIF B

D8DL4148-TP

L21

BLM21BD121SN1D

C365 0.47uF

P13

17067141

JP10HDR3_0P1INCH

123

D12DL4148-TP R236

NO-POP

P23

17067141

D5DL4148-TP

C12247pF 50V

C366 0.47uF

TVS3SMAJ5.0CA

12

C363 0.47uF

L24

BLM21BD121SN1D

P22

17067141

D4DL4148-TP

C11747pF 50V

D6DL4148-TP

TVS1SMAJ5.0CA

12

D3DL4148-TP

L25

BLM21BD121SN1D

R199NO-POP

P19

17067141C359 0.47uF

C13047pF 50V

R221NO-POP

R200NO-POP

D10DL4148-TP

JP8HDR3_0P1INCH

123

D13DL4148-TP

TVS2SMAJ5.0CA

12

C1180.015uF

C360 0.47uF

C13447pF 50V

C11347pF 50V

D7DL4148-TP

C10647pF 50V

R254NO-POP

C13747pF 50V

C361 0.47uF

L19

BLM21BD121SN1D

D15DL4148-TP

C1350.015uF

D9DL4148-TP

C12647pF 50V

D14DL4148-TP

C1280.015uF

C362 0.47uF

P15

17067141

L27

BLM21BD121SN1D

L20

BLM21BD121SN1D

D11DL4148-TP

D20DL4148-TP

D19DL4148-TP TVS4

SMAJ5.0CA

12

R253NO-POP

P14

17067141

D2DL4148-TP

P18

17067141

JP13HDR3_0P1INCH

123

JP12HDR3_0P1INCH

123

L16

BLM21BD121SN1D

R237NO-POP

C364 0.47uF

P16

17067141

L28

BLM21BD121SN1D

C1080.015uF

R219NO-POP

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PMI2C_SCL

PMI2C_SDA

PMI2C_SCLPMI2C_SDA

PMI2C_SCLPMI2C_SDA

PMI2C_SCLPMI2C_SDA

PMI2C_SCLPMI2C_SDA

PMI2C_SCLPMI2C_SDA

PMI2C_SCLPMI2C_SDA

PMI2C_SCLPMI2C_SDA

3V3_EVM5V_IN EVM_5V

5V_IN VCC_5V_PM

VCC_5V_PM

5V_IN VCC_PM_I2C

VCC_PM_I2C

VCC_5V_PM

3V3_OUT

VCC_5V_PM

3V3_VIO

VCC_5V_PM

VCC_1V2

VCC_5V_PM

VCC_1V2_OUT

VCC_IO_3V3_1V8_OUT

VCC_1V2_LDO

VCC_5V_PM

VCC_1V2_LDO_OUT VCC_1V8_LDO

VCC_5V_PM

VCC_1V8_LDO_DOUT

VCC_5V_PM VCC_5V_PM

1V2_RTC

VCC_5V_PM

1V2_RTC_OUT

VCC_5V_PM

PMI2C_SCL[19]

PMI2C_SDA[19]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

B


514202-0001


B

SMART GRID EVM

POWER ROUTER

I2C ADDRESS 1000000b I2C ADDRESS 1000001b I2C ADDRESS 1000010b

I2C ADDRESS 1000011b I2C ADDRESS 1000100b I2C ADDRESS 1000101b

I2C ADDRESS 1000110b

R180.02

U8INA219IDCN VIN

+1

VIN

-2

GN

D3

VS

4

SC

L5

SD

A6

A0

7A

18

R201

U35INA219IDCN V

IN+

1

VIN

-2

GN

D3

VS

4

SC

L5

SD

A6

A0

7A

18

C224

0.1uF

R1490.02

U10INA219IDCN V

IN+

1

VIN

-2

GN

D3

VS

4

SC

L5

SD

A6

A0

7A

18

R383 0

R1890.02

C282

0.1uF

C262

0.1uF

R1880.02

U9INA219IDCN V

IN+

1

VIN

-2

GN

D3

VS

4

SC

L5

SD

A6

A0

7A

18

C174

0.1uF

R1150.02

U30INA219IDCN V

IN+

1

VIN

-2

GN

D3

VS

4

SC

L5

SD

A6

A0

7A

18

R3824.7K

U26INA219IDCN V

IN+

1

VIN

-2

GN

D3

VS

4

SC

L5

SD

A6

A0

7A

18

R384 0

U36INA219IDCN V

IN+

1

VIN

-2

GN

D3

VS

4

SC

L5

SD

A6

A0

7A

18

C172

0.1uF

R190.02

C173

0.1uF

R3814.7K

C281

0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1V2_RTC_OUT

VIN_RTC

VIN_LDOEVM_5V

VIN_RTC

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

RTC POWER,ETC

Vout = ((RTOP+RBOTTOM)/RBOTTOM) *1.193

R70

R6NO-POP

R272K 1%

U11 TPS79901-ADJ

EN3

VOUT 5

FB 4

VIN1

GN

D2 C20

2.2uF

C171

1uF

R26221K 1%

TP1TP

C1765.6pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCC_IO_3V3_1V8_OUT

3V3_OUT

VCC_1V2_OUT

VCC_1V2_LDO_OUT

VCC_1V8_LDO_OUT

TPS65070_VSYS TPS65070_VSYS TPS65070_VSYS

TPS65070_VSYS

TPS65070_VSYS

TPS65070_VSYS

EVM_5V

TPS65070_VSYS

VCC_1V8_LDO_OUTVCC_1V8_LDO_DOUT

VCC_1V8_LDO_OUT

TPS65070_VSYS

VIN_LDO

I2C0_SDA[4,19,26,33,34,37,38,46]

TSX1_RIGHT[31]TSX2_LEFT[31]TSY1_TOP[31]

TSY2_BOTTOM[31]

MSTR_nRST_3.3_1.8[11,27,33,34,36,56]

TOUCH_INT[9]

I2C0_SCL[4,19,26,33,34,37,38,46]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001


B

SMART GRID EVM

3.3 VOLT, 1.8 VOLT, CORE POWER

R1114.7K

C2230.1uF

C2480.1uF

R35210K

TP7TP

R357 0TP5TP

R360 0

C2360.1uF

C86 2.2uF

L11 2.2uH

C711uF

R35110K

+ C7222uF

C2420.1uF

C2350.1uF

C2440.1uF

R155 150K

TP4Test Point_0

+ C782.2uF

R380NO-POP

C2641uF

R1640

TP9Test Point_0

R34810K

R363 0

U28

TPS65070

DEFDCDC3 17

L3 31

VINDCDC3 32

VINDCDC1/2 21

L1 20

AVDD6 1

VDCDC1 19

PB_INn25 PGOOD26VLDO2 2

VINLDO1/2 3

VLDO1 4

EN_DCDC316 EN_DCDC215 EN_DCDC114

SYS.1 8

RESETn39 INTn40 SDAT27 SCLK28

DEFDCDC2 18

VDCDC2 23

PGND.330

L2 22

ISINK1(AD_IN6) 34

POWER_ON13

L4 37

AGND.142PGND(PWR_PAD)49

AC10

USB12

BAT.26BAT.15

TS11

ISET9

TSX1(AD_IN1)43TSX2(AD_IN2)44TSY1(AD_IN3)45TSY2(AD_IN4)46

INT_LDO48

PB_OUT24

ISET135

ISET236

BYPASS41

THRESHOLD47

SYS.2 7

VDCDC3 29

FB_WLED 38

ISINK2(AD_IN7) 33

+ C742.2uF

+ C6322uF

C2150.1uF

L8 2.2uH

R140 909

+ C6722uF

C691uF

C2661uF

+ C26110uF

R1121K

R170301K

U25

TPS3805H33DCK

SNS5

GND2

VDD 4

RSTn 3

NC.1 1

TP6Test Point_0

L7 2.2uH

+ C7310uF

R1320.025

R342NO-POP

+ C24310uF

+ C21710uF

R355 0

R34947K

D23MBRA340T3

+ C8122uF

D24MBRA340T3

R160 150K

R343NO-POP

+ C8510uF

TP8TP

+ C2592.2uF

C2390.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

5V_CONN

5V_IN5V_CONN

EVM_15V

5V_IN

SW_RST[33]

USER_PB_1 [33]

MSTR_nRST_3.3_1.8 [11,27,33,34,36,55]

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

A


514202-0001

Monday, May 21, 2012 56 57

B

SMART GRID EVM

POWER

5V POWER INPUT

SOFTWARERESET

Mounting holes 0.250 pad 0.125 drill

R408 0

Z31

S1SWITCH

31 2

S4

SPST

13

24

C287 0.1uF

U39

TPS61093DSK

GND 1

VIN2

CP23

CP14

EN5

SS6

FB 7

OUT 8

SW 9

VO 10

PW

R_P

AD

11

C15522uF

R520 0

J9

RASM712

SLEEVESHUNTCENTER

C1110.01uF

Q4BSS138G

DS

R521 0

C169150uF

C1161uF

R205294K

S3

SPST

13

24

R20610.2K

R40610K

L18 10uH

C109100uF

Z11

R208200K

C119 0.1uF

C11010uF

R21610K

R5220

Z21

R407

1K

C12010uF

C3050.1uF

C3040.1uF

Z41

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Size:

Date:

DWG NORevision:

Sheet o f

Title:

Page Contents:

D


514202-0001

Tuesday, June 05, 2012 57 57

B

SMART GRID EVM

REVISION HISTORY

REVISION A

INITIAL RELEASE

REVISION B

ADDED SECOND CODEC CHANNEL

REVISION C

ADDED USB TO ETHERNET CIRCUIT

REVISION D

COMPLIANCE CHANGES

ASSEMBLY

PRINTED CIRCUIT BOARD/SCHEMATIC REVISION A

ASSEMBLY

PRINTED CIRCUIT BOARD/SCHEMATIC

REVISION B

ASSEMBLY

PRINTED CIRCUIT BOARD/SCHEMATIC REVISION C

REVISION C

ASSEMBLY


REVISION D

COMPLIANCE CHANGES,2.1mm power jack, oscillator instead ofcrystal on processor, tweak location of display connector

REVISION EASSEMBLY


rev description date approved add codec 12/21/2010...

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