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H T T P : / / S A N T A N U . D E S E . I I S C . A C . I N P H O N E 0 8 0 - 2 2 9 3 3 0 9 0 • E - M A I L S A N T A N U @ I I S C . A C . I N

S A N T A N U M A H A P A T R A Designation : Professor Department : Electronic Systems Engineering (formerly CEDT) Date of Birth : 19th December 1976 Specialization : Nanoelectronic Device Modeling

EDUCATIONDegree University Year DisciplineB.E. Jadavpur

University,Calcutta

1999 Electronics andTelecommunicationEngineering

M.Tech. Indian Institute ofTechnology, Kanpur

2001 Electrical Engineering (Spl: Microelectronics)

PhD Ecole PolytechniqueFederale deLausanne (EPFL),Switzerland

2005 Electrical Engineering

DETAILS OF SERVICE AT THE INSTITUTE16-08-05 to 28-09-10 : Assistant Professor29-09-10 to 18-12-15 : Associate Professor19-12-15 to present : Professor

AWARDS AND RECOGNITIONA. Faculty:

1. Senior Member IEEE2. Editorial Board Member for SADHANA3. Ramanna Fellowship (now SERB-STAR) in 2012.4. Out-of-the-term promotion to Professor, 2015, IISc Bangalore5. Out-of-the-term promotion to Associate Professor, 2010, IISc

Bangalore

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6. Associateship of Indian Academy of Science 2009.7. IBM Faculty Award 2007.8. Microsoft Research India Outstanding Young Faculty Award

2007.9. S. K. Chatterjee research grant award 2006 (IISc Electrical

Science Division)

B. Students:

Dr. A. Sengupta (Post Doc)

DST Nano S&T Post-Doc fellowship DST Faculty Inspire Fellowship

Dr. P. Ghosh (Post Doc) Kothari Post-Doc fellowshipDr. S. Bhattacharya (Post Doc)

DST Faculty Inspire Fellowship

Dr. Dipankar Saha (PhD)

Falling Walls Lab India Finalist

Dr. Anuja Chanana Sarukkai Jagannathan award 2016 from IISc

Dr. N. Sharan (PhD) Best paper award IEEE CONECCT 2015

CEFIPRA fellowship 2013 for attending ESONN workshop

Sarukkai Jagannathan award 2014 from IISc

Dr. R. Verma (PhD) TechnoInventor 2014 award from India Electronics and Semiconductor Association (IESA)

Assistant Professor IIIT-ADr. J. Srivatsava (PhD) Tag Corporation medal for best thesis

Post-Doc fellowship from UC Berkeley (BSIM group)

Dr. P. K. Thakur (PhD) Post-Doc fellowship from UC Berkeley (BSIM group)

Dr. S. S. Dan (PhD) Tag Corporation medal for best thesis Post-Doc fellowship from EPFL

Dr. R. K. Ghosh (PhD) Tag Corporation medal for best thesis DST Faculty Inspire Fellowship Post-

Doc fellowship from Penn-State Univ. DST Faculty Inspire Fellowship

Madhuchhanda Brahma (PhD)

Raman-Charpak Fellowship by CEFIPRA

Nature Research Travel grantA. Abraham (M.E. Micro)

Alumni medal for best project

S. Sarkar (M.E. Micro) Best project award under SMDP-II, DeitY

A. Sahoo (M.Sc. Engg.) Tag Corporation medal for best thesisB. Ray (M.Sc. Engg.) TechnoInventor award from Indian

Semiconductor Association for best thesis

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N. Patel (M.Sc. Engg.) TechnoInventor award from Indian Semiconductor Association for best thesis

Chethan Kumar (M.E. Micro)

Best paper award IEEE CONECCT 2015

RESEARCH AND SCIENTIFIC INVESTIGATIONHIGLIGHTS

Founded ‘Nanoscale Device Research Laboratory’ at ESE in May 2006

Present thrust areas of research are: Multi-scale modeling of nanoelectronic devices and energy storage in nanomaterials.

Activities are well supported by the competitive grant schemes of different funding agencies (DST, CEFIPRA, CSIR and ISRO)

GUIDANCE OF RESEARCH STUDENTSCompleted

11 PhD, 7 MSc (Engg.)

In Progress

5 PhD See Annexure I for details

PUBLICATIONS & PATENTSBook: 1Journal Papers: 83h-index : 22i10 index : 47Total Citations: 1720 (Google Scholar)Patent Applications: 1 See Annexure II for details

MAJOR PROJECT GRANTS

Title Cost Duration

Agency Role

1. Computational screening of 2D materials for applications in integrated circuits

6 lakh

Feb 2020 to Feb 2023

SERB-MATRICS

PI

2. 2D Material Informatics for lithium ion storage 95

lakh

July 2019 to July 2022

Technology Mission Division Energy & Water (DST)

PI

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3. Electronic synapses based on two dimensional materials for neuromorphic computing

47.8 lakh

Feb 2019 to Feb 2022

BRICS Cooperation

Indian PI

4. Quantum Transport Equation based next Generation Compact Models

13 lakh

May 2018 to April 2021

CSIR PI

5. First principles based exploration of atomically thin layered material for next generation Li ion battery

15.7 lakh

April 2017 to March 2020

ISRO STC PI

6. Understanding electron and phonon transport in hetero atomic layer transistors

24.5 lakh

Dec 2015 to Dec 2018

DST PI

7. Performance evaluation of (MOS)2FET through novel device simulator development

29 lakh

Dec 2012 Nov 2015

DST PI

8. Professional Compact Models for Next Generation Multiple-Gate MOS Transistors

35 lakh

March 2012 to Feb 2015

DST Ramanna Fellowship

PI

9. Compact modeling of asymmetric double gate nano scale transistors

23.26

lakhs

Aug 2010 to Jul 2013

IFCPAR PI

10.

Ab Initio Analytical Study of the Effect of Strain on Silicon Nanoelectronics

14 lakh

s

April 10 to March 13

ISRO STC PI

11.

Computationally Efficient Analytical Solution of Non-Linear Poisson’s Equations for Compact Modeling of Nano-Scale Multi-Gate Transistors

25.4 lakh

s

Feb ‘09 to Feb ‘12

DST PI

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12.

Single Electronics: Towards Hybrid CMOS-SET circuit design

13.17

lakhs

Nov ‘07 to Oct ‘10

CSIR PI

13.

Compact modeling and simulation of silicon nano wire transistors

8.5 lakh

s

May ‘06 to May ‘09

DST Fast track PI

14.

Compact modeling of Carbon Nanotube transistors and their interconnects

21.3 lakh

s

Jan ’09 to Jan ‘12

DST Fast track Co-PI

DST: Department of Science and TechnologyCSIR: Council for Scientific and Industrial ResearchCEFIPRA/IFCPAR: Indo French Centre for the Promotion of Advanced Research

NOTEWORTHY RESEARCH ACCOMPLISHMENTS

Single Electron Transistors: In his doctoral thesis (2001 to 2005), he worked on Single Electron Transistor (SET) and its hybridization with CMOS. He developed the ‘MIB’ compact model for SET and a CAD framework for SET-MOSFET co-circuit-simulation. His work resulted in seven journal and several conference (including two IEDM, one DAC and one ISSCC) papers. His second IEDM paper was also reported in Wall Street Journal Dec 2003. The book “Hybrid CMOS Single Electron Transistor Device and Circuit Design” (from Artech house) based on his thesis was sold over 400 copies around the world and used as textbook in nanoelectronics courses in several universities. He continued his research in this area after joining IISc and for the demonstrated the effect of energy quantization on hybrid MOS-SET circuits.

Compact Modeling of multi-gate MOSFETs: At IISc, he has developed ‘indDG’- a new compact model for silicon double-gate (DG) MOSFET, which is applicable for both common double gate (CDG) and independent double gate (IDG) configuration. In the process of model development his team introduced several novel techniques e.g., single-implicit equation-based Poisson solution (IEEE T-ED 57, 632-636), surface-potentials-relationship based charge linearization (IEEE T-ED 59, 1002-1007) etc. The algorithm developed for the solution of surface-potential-equation (IEEE T-ED. 58, 1663), was later used in industry-standard BSIM-IMG model. His team has recently formulated quantum-drift-diffusion based compact model for III-V channel based MOSFET, which could have a profound impact on semiconductor industry for upcoming technology nodes. Novel techniques have been proposed to obtain an analytical solution of the coupled Schrodinger-Poisson system [IEEE Trans. Elec. Dev. 64, 1519

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(2018)]. New charge linearization scheme has been introduced to capture local thermal equilibrium of the sub-band carriers [IEEE Trans. Elec. Dev. 65, 888 (2017)] . Models have been implemented in professional circuit simulator [WCM 2018] and good convergence behaviour is observed for benchmark circuit simulations.

Thermoelectric of Carbon-Nanomaterials: Prof. Mahapatra has made significant contribution in understanding electrothermal and thermoelectric properties in carbon nano-materials (nanotube and graphene) through physics based analytical modeling. A theory (IEEE T-ED 60, 2064-2070) is proposed to obtain ZT (thermoelectric figure of merit) in the order of 0.5 at room temperature from a single layer graphene sheet by novel phonon mean-free-path engineering technique. Several such “isotopically modified” n and p type graphene sheets could be placed in an array to obtain desired output voltage. This theory demonstrates the immense potential of metallic graphene for waste-heat-recovery/energy-harvesting applications. It opens up a new area of research: ‘in-chip thermoelectric generator for next-generation green ICs’, which so far remains unexplored due to the limitations of existing thermoelectric materials. Based on this novel concept an Indian patent is applied in August 2013 (3625/CHE/2013).

Multi-scale modeling of 2D Materials based transistors: His team has made substantial contribution in modeling of carrier transport in 2D material-based field effect transistors. He employs first principles based techniques to assess the impact of new nanomaterial on conventional and tunneling MOS transistor performance [Scientific reports 8 (1), 5993, IEEE Trans. Elec. Dev. 65, 1198 (2018), IEEE J. Elec. Dev. Soc. 1, 175 (2013), IEEE Trans. Elec. Dev. 60, 2782 (2013)]. Atomistic model developed by his team delineates charge transmission at the interfaces of 2D materials, [Appl. Phys. Lett. 108, 253106 (2016), npj 2D Mat. Appl. 1, 17 (2017)] which is hard to probe by experiments. Recently his team has proposed multiscale modeling technique for all-2D MISFET, which starts from the atomic granularity of the material and ends up in SPICE [npj 2D Materials and Applications 2 (1), 28]. They demonstrated how an atomic level phenomenon (e.g. band-gap opening in graphene) could be translated into a circuit performance metric (e.g. frequency of a ring oscillator). Such first-principles-based models enable systematic performance evaluation of emerging materials at device and circuit level at early phase of advanced technology node development.

Energy Storage in 2D Materials: Recently he has ventured in energy science. Rhenium disulfide is a promising lithium ion battery material, but its distorted structure makes computational modelling challenging. His team has developed novel atomistic modeling methodology which uses hardware-accelerator-assisted high-throughput DFT based structure searching to model the reversible

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lithiation of ReS2 including metal–sulphur bond cleavage [Nature Communications Chemistry 1 (1), 81].

INDUSTRIAL INTERACTIONS Honorary technical advisor of Tech Next Lab (P) Ltd. Collaborated with Silvaco Inc. for implementation of compact

models in circuit simulator. Visiting position of Cypress Semiconductor (India) device

reliability group. Collaboration with Intel (USA) for compact modeling activities.

Joint papers in Solid State Electronics and VLSI Design 2010 conference.

Supervised M.E. Microelectronics project jointly with Texas Instruments, India

TEACHING

Course No. Course titleNo. of Credit

s

Average No. of

students

No. of times taught

E3 225 Art of Compact Modeling

3:0 20 12

E3 268 Advance CMOS and beyond CMOS

3:0 5 3

WORKSHOP ORGANISED

Indo-French workshop on “Emerging Trends in Electron Device Modeling” during 30th March to 1st April 2015

Workshop on “Art of Compact Modeling” at IIT Gandhinagar during 12-21 May 2014 under its Knowledge Network program.

Workshop on Compact Modeling during 22-23 Aug 2014 at IISc Bangalore under Indian Nanotechnology Users’ Program (INUP)

ANNEXURE I : LIST OF RESEARCH STUDENTS/ASSOCIATESPRESENT STUDENTS

Position

Name Duration Research Topic

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PhD Biswapriyo Das

Since August 2015

Multi-scale modeling of 2D material interface

PhD Arnab Kabriraj

Since August 2016

Energy storage

PhD Vaishnavi Vishnubhotla

Since August 2018

Device Modeling

PhD Mayank Kumar

Since January 2020

Energy storage

PhD Sirsha Guha Since January 2020

Device modeling

MTech (Res)

Tripti Jain Since August 2020

Learning based device model

PAST STUDENTS/ASSOCIATES

Name Duration/ Graduation Date

Research Title Current Status

Dr. Pujarini Ghosh

Post Doc (June 2013 to Aug 2014)

Graphene Thermoelectric

Faculty, Macquarie University, Sydney

Amretasish Sengupta

Post-Doc (April 2012-March 2014)

2D Material based MOSFET

DST Inspire Faculty at IIEST, Shibpur (formerly BESU)

Arkaprava Bhattacharya

Post-Doc (Feb-March 2013)

Compact Modeling Assistant Professor SASTRA University

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Sitangshu Bhattacharya

Post-Doc (2008-2013)

Carrier and heat transport in carbon nanomaterials

Assistant Professor at IIIT Allahabad

Madhuchhanda Brahma

(Jointly with Prof. S. Sambandan)

PhD (June 2019)

Multiscale modeling of quantum transport in 2D material based MOS transistors

Ananda Shankar Chakraborty

PhD (March 2019)

Quantum-Drift-Diffusion Formalism Based Compact Model For Low Effective Mass Channel MOSFET

Institute Research Associate

Dipankar Saha

PhD (October 2017)

Atomistic study of carrier transmission in hetero-phase MoS2 structures

Institute Post Doc IITB

Anuja Chanana

PhD (March 2016)

First principles study of 2D material metal contact

Post Doc JNCASR

Neha Sharan

PhD (December 2014)

Compact modeling of short channel common double gate MOSFET adapted to gate-oxide thickness asymmetry

R&D Engineer, IMEC Belgium

Rekha Verma

PhD (December 2013)

Investigation of electrothermal and thermoelectric properties of Carbon nanomaterials

Assistant Professor at IIIT Allahabad

Radhamajari Samanta

(Jointly with Prof. S. Raha)

PhD (December 2013)

Timing-driven routing in VLSI physical design under uncertainty

AMD Bangalore

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Ram Krishna Ghosh

PhD (August 2013)

Exploration of real and complex dispersion relationship of nanomaterials for next generation transistor applications

Inspire Faculty JNU Delhi

Pankaj Thakur

PhD (June 2013)

Poisson's Solution and Large-Signal Modeling for Independent Double Gate MOSFET

Assistant professor at IIT-Ropar

Post Doc: UC Berkeley

Jandhyala Srivatsava

PhD (March 2013)

Compact Modeling of Independent/Asymmetric Double Gate MOSFETs

Assistant professor at IIIT Hyd

Post Doc: UC Berkeley

Surya Shankar Dan

PhD

(Aug 2009)

Impact of energy quantization on Single Electron Transistor devices and circuits

Assistant professor at IIT Kgp

Post Doc: EPFL

Chethan Kumar

MSc. Engg.

(Jan 2018)

First Principles Based Mobility Estimation of Graphene

Intel India

A. Rex M.Sc. Engg. (2011)

Thermal conductivity modeling for metallic single walled carbon nanotube

Pursuing PhD at IAP-IISc

Avinash Sahoo

M.Sc. Engg. (2009)

Inversion charge modeling of multiple gate FinFET.

----

Rakesh P M.Sc. Engg. (2009)

Analytical modeling of Quantum threshold voltage for short channel Multigate Silicon Nanowire transistors

Pursuing PhD at University of Minnesota

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Biswajit Ray M.Sc. Engg. (2008)

Impact of Body Center Potential on the Electrostatics of Undoped Body Multi Gate Transistors: A Modeling Perspective

San Disk USA

PhD: Purdue University

Ramesha A M.Sc. Engg. (2008)

Sub-threshold Slope Modeling & Gate Alignment Issues in Tunnel Field Effect Transistor

DRDO

Nayan Patel M.Sc. Engg. (2007)

Performance Enhancement of the Tunnel Field Effect Transistor for Future Low Stand-by Power Applications

Cypress Semiconductor

ANNEXURE II: PUBLICATIONS AND PATENT APPLICATIONSPATENT APPLICATIONS

1. R. Verma, S. Bhattacharya and S. Mahapatra, " A graphene based thermoelectric generator", Applied for Indian patent, 3625/CHE/2013, August 2013.

2. S. Mahapatra and N. Patel, "An n-type tunnel FET device with strained SiGe layer at source", Applied for Indian patent, 02057/CHE/2007, September 2007

BOOK AND BOOK CHAPTER

1. “Hybrid CMOS Single Electron Transistor Device and Circuit Design”, Santanu Mahapatra and Adrian M. Ionescu, Artech House Publication ISBN 1-59693-069-1, 2006.

2. Chapter in “Emerging Nanoelectronics: Life With and After CMOS” Edited by Adrian M. Ionescu and Kaustav Banerjee, Editors, Kluwer Academic Publishers, ISBN: 1-4020-75332, 2004.

JOURNAL PUBLICATIONS

1. Biswapriyo Das, Diptiman Sen and Santanu Mahapatra, “Tuneable quantum spin Hall states in confined 1T’ transition metal dichalcogenides”, Scientific Reports, Nature Publishing group, 10, 6670, 2020.

2. Arnab Kabiraj, Mayank Kumar  and Santanu Mahapatra, “High-throughput discovery of high Curie point two-dimensional

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ferromagnetic materials”, npj Computational Materials,  Nature Publishing group, 6, 35, 2020

3. Arnab Kabiraj and Santanu Mahapatra, “Intercalation driven reversible switching of 2D magnetism”, Journal of Physical Chemistry C, Vol. 124, No. 1146-1157, 2020.

4. Madhuchhanda Brahma, Arnab Kabiraj, Marc Bescond and Santanu Mahapatra, “Phonon limited anisotropic quantum transport in phosphorene field effect transistors”  Journal of Applied Physics, Vol. 126, No. 114502, 2019. [Editor’s Pick]

5. Sahil Garg, Bipan Kaushal, Sanjeev Kumar, S.R Kasjoo, Santanu Mahapatra and Arun K. Singh, “Extraction of trench capacitance and reverse recovery time of InGaAs self-switching diode”  IEEE Transactions on Nanotechnology, Vo. 18, pp. 925, 2019.

6. Arnab Kabiraj and Santanu Mahapatra, “High-throughput first-principles-calculations based estimation of lithium ion storage in monolayer rhenium disulfide”  Communications Chemistry,  Nature publishing group, 2018. [Nature collection: Nobel Prize in Chemistry 2019]

7. Biswapriyo Das and Santanu Mahapatra, “An Atom-to-Circuit modeling approach to all-2D Metal-Insulator Semiconductor Field-Effect Transistors” npj 2D Materials and Applications, Nature publishing group,Vol.2, No.28, 2018.

8. Madhuchhanda Brahma, Arnab Kabiraj, Dipankar Saha and Santanu Mahapatra, “Scalability assessment of Group-IV mono-chalcogenide based tunnel FET”  Scientific Reports,  Nature publishing group, 2018.

9. Ananda Sankar Chakraborty and Santanu Mahapatra, “Compact Model for Low Effective Mass Channel Common Double-Gate MOSFET,”  IEEE Transactions on Electron Devices, Vol. 65, No.3, pp. 888-894, 2018.

10. Madhuchhanda Brahma, Marc Bescond, Demetrio Logoteta, Ram Krishna Ghosh and Santanu Mahapatra, “ Germanane MOSFET for sub-Deca Nanometer High Performance Technology Nodes” IEEE Transactions on Electron Devices, Vol. 65, No.3, pp. 1198-1204,  2018.

11. Arup Paul , Manabendra Kuiri , Dipankar Saha, Biswanath Chakraborty , Santanu Mahapatra, A.K. Sood and Anindya Das, “Photo-tunable Transfer Characteristics in MoTe2-MoS2 Vertical Hetero-structure”   NPJ 2D Materials and Applications, Vol.1,  2017.

12. Dipankar Saha and Santanu Mahapatra, “Anisotropic transport in 1T’ monolayer MoS2 and its metal interfaces” RSC Physical Chemistry Chemical Physics, Vol. 19, pp. 10453, 2017.

13. Dipankar Saha and Santanu Mahapatra, “Asymmetric Junctions in Metallic-Semiconducting-Metallic Heterophase MoS2,”  IEEE Transactions on Electron Devices, Vol. 64, No. 5, pp. 2457-2460, 2017.

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14. Ananda Sankar Chakraborty and Santanu Mahapatra, “Surface Potential Equation for Low Effective Mass Channel Common Double-Gate MOSFET,”  IEEE Transactions on Electron Devices, Vol.64, No.4, pp. 1519-1527, 2017.

15. Adam Makosiej, Navneet Gupta, Naga Vakul, Andrei Vladimirescu, Sorin Cotofana, Santanu Mahapatra, Amara Amara, and Costin Anghel, “Ultra-Low Leakage SRAM Design with sub-32nm Tunnel FETs for Low Standby Power Applications,” IET Micro & Nano Letters, Vol. 11, Issue 12, pp. 828-831, 2016.

16. Dipankar Saha and Santanu Mahapatra “Atomistic modeling of the metallic-to-semiconducting phase boundaries in monolayer MoS2,” Applied Physics Letters, Vol 108, pp. 253106, 2016.

17. Dipankar Saha and Santanu Mahapatra, “Theoretical insights on the electro-thermal transport properties of monolayer MoS2 with line defects,” Journal of Applied Physics, Vol. 119, pp. 134304, 2016.

18. Anuja Chanana and Santanu Mahapatra, “Density Functional Theory based Study of Chlorine Doped WS2 -metal Interface,” Applied Physics Letters , Vol. 108, pp. 103107, 2016.

19. Dipankar Saha and Santanu Mahapatra, “Analytical Insight into the Lattice Thermal Conductivity and Heat Capacity of Monolayer MoS2,” Physica E, Vol. 83, pp. 455–460, 2016.

20. Anuja Chanana and Santanu Mahapatra, “Prospects of Zero Schottky Barrier Height in a Graphene Inserted MoS2-Metal Interface,” Journal of Applied Physics , Vol. 119, pp. 014303, 2016.

21. Neha Sharan and Santanu Mahapatra, "Compact Noise Modeling for Common Double Gate MOSFET Adapted to Gate Oxide Thickness Asymmetry," appearing in IET Circuits, Devices & Systems, 2015.

22. Anuja Chanana and Santanu Mahapatra, "Theoretical Insights to Niobium Doped Monolayer MoS2-Gold Contact," IEEE Transactions on Electron Devices, Vol. 62, No. 7, pp. 2346-2351, 2015.

23. Amretashis Sengupta, Anuja Chananna and Santanu Mahapatra, “Phonon scattering limited performance of monolayer MoS2 and WSe2 n-MOSFET”, AIP Advances Vol.2, Issue 5, pp. 027101, 2015.

24. Amretashis Sengupta, Dipankar Saha and Santanu Mahapatra, “Effect of line defects on the electrical transport properties of monolayer MoS2 sheet,” IEEE Transactions on Nanotechnology, Vol. 14, No. 1, pp. 51, 2015.

25. Anuja Chanana and Santanu Mahapatra, "First Principle Study of Metal Contact to Monolayer Black Phosphorous," Journal of Applied Physics Vol.116, pp. 204302, 2014.

26. Sitangshu Bhattacharya, Dipankar Saha, Aveek Bid, and Santanu Mahapatra, "A Continuous Electrical Conductivity Model for Monolayer Graphene from Near Intrinsic to Far Extrinsic Region," IEEE Transactions on Electron Devices, Vol. 61, No. 11, pp. 3646, 2014.

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27. Dipankar Saha, Amretashis Sengupta, Sitangshu Bhattacharya and Santanu Mahapatra, "Impact of Stone-Wales and lattice vacancy defects on the electro-thermal transport of the free standing structure of metallic ZGNR", Journal of Computational Electronics (Springer), Vol. 13, No. 4, pp. 862, 2014.

28. Neha Sharan and Santanu Mahapatra, “A Short Channel Common Double Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry”, IEEE Transactions on Electron Devices, Vol. 61, No.8, pp. 2732, 2014.

29. Ramkrishna Ghosh, Madhuchhanda Brahma and Santanu Mahapatra, “Germanane: a ‘Low Effective Mass’- ‘High Bandgap’ 2-D Channel Material for Future FETs”, IEEE Transactions on Electron Devices, Vol. 61, No.7, pp. 2309, 2014.

30. Anuja Chananna, Amretashis Sengupta and Santanu Mahapatra, “Performance Analysis of Boron Nitride Embedded Armchair Graphene Nanoribbon MOSFET with Stone-Wales Defects", Journal of Applied Physics, Vol. 115, pp. 034501, 2014.

31. Neha Sharan and Santanu Mahapatra, "Continuity Equation Based Nonquasi-static Charge Model for Independent Double Gate MOSFET”, Journal of Computational Electronics (Springer), Vol. 13, No. 2, pp. 353, 2014.

32. Ramkrishna Ghosh and Santanu Mahapatra, "Monolayer Transition Metal Dichalcogenide Channel Based Tunnel Transistor", IEEE Journal of the Electron Devices Society, Vol. 1, No. 10, pp. 175, 2013.

33. Amretashis Sengupta and Santanu Mahapatra, "Negative differential resistance and effect of defects and deformations in MoS2 armchair nanoribbon MOSFET”, Journal of Applied Physics, Vol. 114, pp. 194513, 2013.

34. Rekha Verma, Sitangshu Bhattacharya and Santanu Mahapatra, "Solution of Time Dependent Joule Heat Equation for a Graphene Sheet under Thomson Effect", IEEE Transactions on Electron Devices, Vol. 60, No. 10, pp. 3548, 2013.

35. Ramkrishna Ghosh and Santanu Mahapatra, “Proposal for Graphene-Boron Nitride Heterobilayer Based Tunnel FET", IEEE Transactions on Nanotechnology, Vol. 12, No. 5, pp. 665, 2013.

36. Amretashis Sengupta, Ram Krishna Ghosh, Santanu Mahapatra, "Performance Analysis of Strained Monolayer MoS2 MOSFET," IEEE Transactions on Electron Devices, Vol. 60, No. 9, pp. 2782, 2013.

37. Rekha Verma, Sitangshu Bhattacharya and Santanu Mahapatra, "Modeling of Temperature and Field Dependent Electron Mobility in a Single Layer Graphene Sheet", IEEE Transactions on Electron Devices, Vol.60, No. 8, pp. 2695, 2013.

38. Neha Sharan and Santanu Mahapatra, "Non-Quasi-Static Charge Model for Common Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry", IEEE Transactions on Electron Devices, Vol.

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60, No.7, pp. 2419, 2013.39. Amrethashis Sengupta and Santanu Mahapatra, "Performance limits

of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors, " Journal of Applied Physics, Vol. 113, Issue 20, pp. 194502, 2013.

40. Rekha Verma, Sitangshu Bhattacharya and Santanu Mahapatra, "Thermoelectric Performance of a Single Layer Graphene Sheet for Energy Harvesting", IEEE Transactions on Electron Devices, Vol. 60, No.6, pp. 2064, 2013.

41. Ramkrishna Ghosh, Sitangshu Bhattacharya and Santanu Mahapatra,"k.p based closed form energy band gap and transport electron effective mass model for [100] and [110] relaxed and strained Silicon nanowire", Solid State Electronics, Vol. 80, pp. 124, 2013.

42. Rekha Verma, Sitangshu Bhattacharya and Santanu Mahapatra, "A physics based flexural phonon dependent thermal conductivity model for single layer graphene", IOP Semiconductor Science and Technology, Vol. 28, pp. 015009, 2013.

43. Ramkrishna Ghosh and Santanu Mahapatra, "Direct Band-to-band tunneling in reverse biased MoS2 nanoribbon p-n junctions", IEEE Transactions on Electron Devices, Vol. 60, No.1, pp. 274, 2013.

44. Rekha Verma, Sitangshu Bhattacharya and Santanu Mahapatra, "Physics-Based Solution for Electrical Resistance of Graphene under Self-Heating Effect", IEEE Transactions on Electron Devices, Vol. 60, No.1, pp. 502, 2013.

45. Aby Abraham, Pankaj Thakur and Santanu Mahapatra, "Bipolar Poisson Solution for Independent Double-Gate MOSFET", IEEE Transactions on Electron Devices, Vol. 60, No.1, pp. 498, 2013.

46. Srivatsava Jandhyala and Santanu Mahapatra, "Inclusion of the Body Doping in the Compact Models for Fully-Depleted Common Double Gate MOSFET Adapted to Gate-oxide Thickness Asymmetry", IET Electronics Letters, Vol. 48, No. 13, pp. 794, 2012.

47. Rekha Verma, Sitangshu Bhattacharya and Santanu Mahapatra, "Theoretical Estimation of Electro-migration in Metallic Carbon Nanotubes Considering Self-Heating-Effect", IEEE Transactions on Electron Devices, Vol. 59, No. 9, pp. 2476, 2012.

48. Srivatsava Jandhyala, Aby Abraham, Costin Anghel and Santanu Mahapatra, "Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET", IEEE Transactions on Electron Devices Vol. 59, No. 7, pp. 1974, 2012.

49. Ramkrishna Ghosh, Sitangshu Bhattacharya and Santanu Mahapatra," Physics based band gap model for relaxed and strained [100] silicon nanowires", IEEE Transactions on Electron Devices, Vol. 59, No. 6, pp. 1765, 2012.

50. Srivatsava Jandhyala, Rutwick Kashyap, Costin Anghel and Santanu Mahapatra, "A Simple Charge Model for Symmetric Double-Gate

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MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry", IEEE Transactions on Electron Devices, Vol. 59, No. 4, pp. 1002, 2012.

51. Aby Abraham, Srivatsava Jandhyala and Santanu Mahapatra, "Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFET", IEEE Transactions on Electron Devices, Vol. 59, No.4, pp. 1199, 2012.

52. Sitangshu Bhattacharya and Santanu Mahapatra,"Quantum Capacitance in Bilayer Graphene Nanoribbon", Physica E, Vol. 44, Issues 7–8, pp. 1127, 2012.

53. Rekha Verma, Sitangshu Bhattacharya and Santanu Mahapatra, "Analytical Solution of Joule Heating Equation for Metallic Single Walled Carbon Nanotube Interconnects", IEEE Transactions on Electron Devices, Vol. 58, No. 11, pp. 3991, 2011.

54. Srivatsava Jandhyala and Santanu Mahapatra, "An efficient robust algorithm for the surface potential calculation of Independent DG MOSFET", IEEE Transactions on Electron Devices, Vol. 58, No. 6, pp. 1663, 2011.

55. Sitangshu Bhattacharya, Amalraj Rex and Santanu Mahapatra "Physics Based Thermal Conductivity Model for Metallic Single Walled Carbon Nanotube Interconnects", IEEE Electron Device Letters, Vol. 32, No. 2, pp. 203, 2011.

56. Pankaj Thakur and Santanu Mahapatra, "Large Signal Model For Independent DG MOSFET", IEEE Transactions on Electron Devices, Vol. 58, No. 1, pp. 46, 2011.

57. Rakesh Kumar P and Santanu Mahapatra, “Analytical Modeling of Quantum Threshold Voltage for Triple Gate MOSFET”, Solid State Electronics, Vol. 54, 1586, 2010.

58. Sudipta Sarkar, Ananda Shankar Roy and Santanu Mahapatra, "Unified Large and Small Signal Non Quasi-Static Model for Long Channel Symmetric DG MOSFET", Solid State Electronics, Vol. 54, pp. 1421, 2010.

59. Sitangshu Bhattacharya and Santanu Mahapatra, “Negative Differential Conductance and Effective Electron Mass in Highly Asymmetric Ballistic Bilayer Graphene Nanoribbon” Physics Letters A, Vol. 374, pp. 2850, 2010.

60. Sitangshu Bhattacharya and Santanu Mahapatra, “Simplified Theory of Carrier Back-Scattering in Semiconducting Carbon Nanotubes: a Kane's Model Approach”, Journal of Applied Physics, Vol.107, Issue 9, pp. 094314, 2010. Also published in Virtual Journal of Nanoscale Science & Technology, Vol. 21, Issue 10, 2010.

61. Surya Shankar Dan and Santanu Mahapatra, "Impact of Energy Quantisation in SET Island on Hybrid Complementary Metal Oxide Semiconductor– Single Electron Transistor Integrated Circuits", IET Circuits Devices Systems, Vol. 4, Issue 5, pp. 449, 2010.

62. Sivakumar Bondada, Soumyendu Raha and Santanu Mahapatra, “An

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efficient reduction algorithm for computation of interconnect delay variability for statistical timing analysis in clock tree planning”, Sadhana - Academy Proceedings in Engineering Science Vol. 35, Part 4, pp. 407, 2010.

63. Sitangshu Bhattacharya and Santanu Mahapatra, "Analytical Study of Low Field Diffusive Transport in Highly Asymmetric Bilayer Graphene Nanoribbon", Vol. 10, No. 3, pp. 409, IEEE Transactions on Nanotechnology, 2010.

64. Avinash Sahoo, Pankaj Kumar Thakur, and Santanu Mahapatra, "A Computationally Efficient Generalized Poisson Solution For Independent Double Gate Transistors", IEEE Transactions on Electron Devices, Vol. 57, no.3, pp. 632, 2010.

65. Rakesh Kumar P and Santanu Mahapatra, "Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire Transistor", Vol. 10, No. 1, pp. 121, IEEE Transactions on Nanotechnology, 2010.

66. Surya Shankar Dan and Santanu Mahapatra, "Analysis of Energy Quantization Effects on Single Electron Transistor Circuits", in IEEE Transactions on Nanotechnology, Vol.9, No.1, pp. 38, 2010.

67. Surya Shankar Dan and Santanu Mahapatra, "Impact of Energy Quantization Effects on the Performance of Current-Biased SET Circuits", IEEE Transactions on Electron Devices, Vol 56, No 8, pp.1562, 2009.

68. Surya Shankar Dan and Santanu Mahapatra, "Modeling and Analysis of Energy Quantization Effects on Single Electron Inverter Performance", Physica E: Low-dimensional Systems and Nanostructures, Vol. 41, Issue 8, pp. 1410, 2009.

69. Sitangshu Bhattacharya and Santanu Mahapatra, "Influence of Band Non- Parabolicity on Few Ballistic Properties of III-V Quantum Wire Field Effect Transistors Under Strong Inversion", Journal of Computational and Theoretical Nanoscience, Vol.6, No.7, pp. 1605, 2009.

70. Biswajit Ray and Santanu Mahapatra, "Modeling of Channel Potential and Subthreshold Slop of Symmetric Double Gate Transistor", IEEE Transactions on Electron Devices, Vol. 56, No. 2, pp. 260, 2009.

71. Ratul Kumar Baruah and Santanu Mahapatra, "Justifying threshold voltage definition for undoped body transistors through “crossover point” concept", Physica B: Condensed Matter, Volume 404, Issues 8-11, pp. 1029, 2009.

72. Sitangshu Bhattacharya, Surya Shankar Dan and Santanu Mahapatra, "Influence of band non-parabolicity on the quantized gate capacitance in delta-doped MODFED of III-V and related materials," Journal of Applied Physics, Vol. 104, No. 7, pp. 074304, 2008.

73. Biswajit Ray and Santanu Mahapatra, "Modeling and analysis of body potential of cylindrical Gate-All-Around nanowire transistor", IEEE

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Transactions on Electron Devices, Vol. 55, No. 9, pp. 2409, 2008.74. Nayan B Patel, Ramesha A and Santanu Mahapatra, "Drive Current

Boosting of n-type Tunnel FET with Strained SiGe layer at Source", Microelectronics Journal, Vol 39, Issue 12, PP. 1671, 2008.

75. Chaitanya Sathe, Surya Shankar Dan, and Santanu Mahapatra, "Assessment of SET logic Robustness through Noise Margin Modeling", IEEE Transactions on Electron Devices, Vol. 55, No. 3, pp. 909, 2008.

76. Serge Ecoffey, Didier Bouvet, Santanu Mahapatra, Gilles Reimbold, and Adrian Mihai Ionescu, "Electrical Conduction in 10nm-thin Polysilicon Wires from 4K to 400K and their Operation for Hybrid Memory", Japanese Journal of Applied Physics Part 1, Vol. 45, No. 6, 2006.

77. Santanu Mahapatra and Adrian Mihai Ionescu, “Realization of multiple value logic and memory by hybrid SETMOS architecture”, IEEE Transactions in Nanotechnology, Vol. 4, No. 6, pp. 705, 2005.

78. Serge Ecoffey, Vincent Pott, Santanu Mahapatra, Didier Bouvet, Pierre Fazan, Adrian Mihai Ionescu, “A Hybrid CMOS-SET co-fabrication Platform Using Nanograin Polysilicon Wires”, Microelectronic Engineering, Vol 78-79, pp.239, 2005.

79. Santanu Mahapatra , Vaivabh Vaish, Christoph Wasshuber, Kaustav Banerjee and Adrian Mihai Ionescu, “Analytical Modelling of Single Electron Transistor (SET) for Hybrid CMOS-SET Analog IC Design”, IEEE Transactions on Electron Device, Vol. 51, No. 11, pp. 1772, 2004.

80. Santanu Mahapatra and Adrian Mihai Ionescu, “A Novel Elementary Single Electron Transistor Negative Differential Resistance Device”, Japanese Journal of Applied Physics, Part 1, Vol. 43, No. 2, pp. 538, 2004.

81. Adrian Mihai Ionescu, Santanu Mahapatra, and Vincent Pott, “Hybrid SETMOS Architecture with Coulomb Blockade Oscillations and High Current Drive”, IEEE Electron Device Letters, Vol.25, No.6, pp. 411, 2004.

82. Santanu Mahapatra , Adrian Mihai Ionescu, and Kaustav Banerjee, “A Quasi-Analytical SET Model for Few Electron Circuit Simulation”, IEEE Electron Device Letters, Vol.23, No.6, pp. 366, 2002.

83. Santanu Mahapatra , Adrian Mihai Ionescu, Kaustav Banerjee and Michel Declercq, “A SET Based Quantizer Circuit for Digital Communications”, IEE Electronics Letters, Vol. 38, No. 10, pp. 443, 2002.

CONFERNCE PUBLICATIONS

1.Madhuchhanda Brahma, Arnab Kabiraj and Santanu Mahapatra, ‘Insights on anisotropic dissipative quantum transport in n-type Phosphorene MOSFET’, IEEE International Conference on VLSI Design

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2019, Delhi, India.

2.Ananda Sankar Chakraborty, Srivatsava Jandhalya and Santanu Mahapatra, ‘Analytical Surface Potential Solution for Low Effective Mass Channel Common Double Gate MOSFET’, Workshop of Compact Modeling, TechConnect Briefs, Volume: 4, Pages: 224 – 227, 2018.

3.Richa Chakravarty, Dipankar Saha and Santanu Mahapatra, “New Asymmetric Atomistic Model for the Analysis of Phase-engineered MoS2-Gold Top Contact”, IEEE International Conference on VLSI Design 2018, Pune, India

4.Anuja Chanana and Santanu Mahapatra, “Analysis of Vacancy Defects in Hybrid Graphene-Boron Nitride Armchair Nanoribbon Based n-MOSFET at Ballistic Limit", appearing in IWCE 2015, Purdue, USA.

5.Chethan Kumar M, Neha Sharan, and Santanu Mahapatra, “indDG: A New Compact Model for Common Double Gate MOSFET adapted to Gate Oxide Thickness Asymmetry”, IEEE CONECCT 2015, Bangalore, India.

6.Dipankar Saha, Sitangshu Bhattacharya and Santanu Mahapatra, “Modeling of sheet-concentration and temperature-dependent resistivity of a suspended monolayer graphene”, ICEE 2014, Bangalore India

7.Neha Sharan and Santanu Mahapatra, “NQS modeling of Independent DG MOSFET by re- laxation time approximation approach”, Workshop on Compact Modeling, Washington- DC, June 16-18, 2014.

8.Neha Sharan and Santanu Mahapatra, "Small signal Non Quasi-static model for Common Double Gate MOSFET adapted to gate oxide thickness asymmetry”, IEEE International Conference on VLSI Design 2014, India.

9.Rekha Verma, Sitangshu Bhattacharya and Santanu Mahapatra, "Electro-thermal Aspects in Carbon Based Interconnects", TechConnect World, Summit and Showcase 2013, Nanotech Conference and Expo 2013, Washington DC, USA.

10. Pankaj Kumar Thakur and Santanu Mahapatra, "Modeling and Analysis of MOS Capacitor Controlled by Independent Double Gates", Workshop on Compact Modeling, Nanotech Conference and Expo 2012, California, USA.

11. Rekha Verma and Santanu Mahapatra, "Electro-thermal modeling in Metallic Single Walled Carbon Nanotube Interconnects", MOS-AK/GSA India 2012, International Workshop on Device Modeling for Microsystems, 2012 India.

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12. Sudipta Sarkar, Ananda Shankar Roy and Santanu Mahapatra, "A Non Quasi-Static Small Signal Model for Long Channel Symmetric DG MOSFET", IEEE International Conference on VLSI Design 2010 , India.

13. Sitangshu Bhattacharya and Santanu Mahapatra, "Does Nanotubes and Nanowires Exhibit Negative Capacitances?", International Workshop on Physics for Semiconductor Devices (IWPSD) 2009 , India.

14. Surya Shankar Dan and Santanu Mahapatra, "Impact of Energy Quantization in SET island on Hybrid CMOS-SET Integrated Circuits", International Workshop on Physics for Semiconductor Devices (IWPSD) 2009 , India.

15. Surya Sankar Dan and Santanu Mahapatra, "Analysis of the energy quantization effects on SET inverter performance using noise margin modeling and monte carlo simulation", IEEE International Conference on VLSI Design 2009, India.

16. Ratul Baruah and Santanu Mahapatra, “Concept of ‘crossover point’ and its application on threshold voltage definition for undoped-body transistors”, IEEE International Conference On VLSI Design 2009, India.

17. Santanu Mahapatra , Ramesha A and Nayan Patel, “Tunnel FET: Nano-Scale Switch For Low Standby Power Applications”, International Conference on Nano and Microelectronics (ICONAME) 2008, Puducherry, India

18. Biswajit Ray and Santanu Mahapatra, "A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor", IEEE International Conference on VLSI Design 2008, Hyderabad, India

19. Biswajit Ray and Santanu Mahapatra, "Analytical Potential Model for Omega Gate Cylindrical Nanowire Transistor", International Conference on Nano and Microelectronics 2008, Puducherry, India

20. Nayan B Patel and Santanu Mahapatra, “Performance Enhancement of the Tunnel Field Effect Transistor using SiGe Source, International Workshop on Physics for Semi-conductor Devices 2007, Mumbai, India

21. Biswajit Ray, Shubhakar, and Santanu Mahapatra, “Necessity for quatum simulation for future technology nodes, International Workshop on Physics for Semi-conductor Devices 2007, Mumbai, India

22. Shubhakar, Biswajit Ray and Santanu Mahapatra, "Challenges Posed to the State of the Art Device Simulators in Nanoscale Regime", VLSI Design And Test Symposium 2007, Kolkata, India

23. Shubhakar and Santanu Mahapatra, "Effects of material properties

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and device parameters on the performance of Silicon nanowire FET", ANM-2007, International conference, IIT Bombay, India

24. Ashish Pal, Saptarshi Das, Biswajit Ray and Santanu Mahapatra, "A New Spice Simulator for Single Electron Transistor Based Integrated Circuits", VLSI Design And Test Symposium 2007, Kolkata, India

25. Nayan B. Patel and Santanu Mahapatra, "A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications", VLSI Design And Test Symposium 2007, Kolkata, India

26. Chaitanya Sathe and Santanu Mahapatra, "Modeling and Analysis of Noise Margin in SET Logic", International Conference on VLSI Design 2007, Bangalore, India

27. Nayan B. Patel and Santanu Mahapatra, "Tunnel FET - A Novel Device with Sub-Threshold Swing less than 60 mV/decade for Future Low Stand-by Power Applications", National Conference on VLSI and Communication Engineering, 2007, Kottayam, India

28. Serge Ecoffey, Vincent Pott, Didier Bouvet, Marco Mazza, Santanu Mahapatra, Alexandre Schmid, Yusuf Leblebici, Michel J. Declercq, Adrian M. Ionescu, “Nano-Wires for Room Temperature Operated Hybrid CMOS-NANO Integrated Circuits”, International Solid State Circuits Conference (ISSCC), Vol. 1, pp. 260-263, 2005.

29. Adrian Mihai Ionescu, Vincent Pott, Serge Ecoffey, Santanu Mahapatra, Kirsten Moselund, Paolo Dainesi, Kathy Buchheit, Marco Mazza, “Emerging nanoelectronics: multi-functional nanowire”, Proc. of CAS 2004, vol. 1, pp. 3-8, October, Romania.

30. Serge Ecoffey, Vincent Pott, Santanu Mahapatra, Didier Bouvet, Pierre Fazan, Adrian Mihai Ionescu, “A Hybrid CMOS-SET co-fabrication Platform Using Nanograin Polysilicon Wires”, Micro and Engineering (MNE) 2004, September, Rotterdam, Nederland.

31. Santanu Mahapatra and Adrian Mihai Ionescu, "A novel single electron SRAM architecture", Proc. of IEEE NANO 2004, August, Munich, Germany.

32. Santanu Mahapatra , Vincent Pott, Serge Ecoffey, Alexandre Schmid, Christoph Wasshuber, Kaustav Banerjee, Yusuf Leblebici, Michel Declercq, Joseph Tringe, Adrian Mihai Ionescu, “SETMOS: A Novel True Hybrid SET-CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog ICs”, IEEE International Electron Device Meeting (IEDM) 2003, December, pp. 703-706, Washington DC, USA.

33. Santanu Mahapatra , Kaustav Banerjee, Florent Pegeon, Adrian

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Mihai Ionescu, “A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits”, International Conference on Computer Aided Design (ICCAD) 2003, pp. 497-502, November, San Jose, USA.

34. Santanu Mahapatra , Vincent Pott, and Adrian Mihai Ionescu, “Few Electron Negative Differential Resistance (NDR) Devices”, International Semiconductor Conference (CAS) 2003, Vol.1, pp. 51-54, September, Sinaia, Romania.

35. Santanu Mahapatra , Vincent Pott, Adrian Mihai Ionescu, “SETMOS-A High Current Coulomb Blockade Oscillation Device”, European Solid-State Device Research Conference (ESSDERC) 2003, pp. 183-186, September, Estoril, Portugal.

36. Santanu Mahapatra , Adrian Ionescu, Kaustav Banerjee and Michel Declercq, “Modelling and analysis of power dissipation in Single Electron logic”, IEEE International Electron Device Meeting (IEDM) 2002, pp. 323-326, December, San Francisco, USA.

37. Santanu Mahapatra , Adrian Ionescu and Kaustav Banerjee, “Quasi-analytical modelling of drain current and conductances of single electron transistors with mib”, 32nd European Solid-State Device Research Conference (ESSDERC) 2002, pp. 391-394, September, Florence, Italy.

38. Adrian Ionescu, Michel Declercq, Santanu Mahapatra, Kaustav Banerjee, and Jaques Gautier, “Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits”, 39th Design Automation Conference (DAC) 2002, pp. 88-93, June, New Orleans, Louisiana, USA.

39. Adrian Ionescu, Michel Declercq, Santanu Mahapatra and Kaustav Banerjee, “Teaching microelectronics in the silicon ICs showstopper zone: a course on ‘Ultimate devices and circuits: towards quantum electronics’”, 4th European workshop on Microelectronics Education (EWME) 2002, May, Spain.

37. Santanu Mahapatra , Adrian Ionescu, Kaustav Banerjee and Michel Declercq, “A SET quantizer circuit aiming at digital communication system”, ISCAS 2002.

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