profdoc.um.ac.irprofdoc.um.ac.ir/articles/a/1033148.pdfsimulation results in the 0.18 um cmos...

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Analog Integrated Circuits and SignalProcessingAn International Journal ISSN 0925-1030Volume 74Number 2 Analog Integr Circ Sig Process (2013)74:317-330DOI 10.1007/s10470-012-9984-7

A new non-uniform adaptive-samplingsuccessive approximation ADC forbiomedical sparse signals

Maryam Zaare, Hassan Sepehrian &Mohammad Maymandi-Nejad

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A new non-uniform adaptive-sampling successive approximationADC for biomedical sparse signals

Maryam Zaare • Hassan Sepehrian •

Mohammad Maymandi-Nejad

Received: 6 July 2012 / Revised: 22 September 2012 / Accepted: 16 November 2012 / Published online: 7 December 2012

� Springer Science+Business Media New York 2012

Abstract This paper presents a new sampling technique

and a successive approximation analog to digital converter

(SA-ADC) which samples sparse signals in a non-uniform

adaptive way. The proposed sampling technique has the

capability to be incorporated in the structure of the

SA-ADC. The proposed SA-ADC changes the rate of

sampling in accordance with the rate of changes of the

signal. In this way, the data volume is reduced considerably

without losing the important information in the signal.

Simulation results in the 0.18 um CMOS technology shows

a power saving of up to 90.5 % and a compression ratio of

7.5 compared to the conventional sampling technique of

ECG signals.

Keywords Successive approximation ADC � Low power �Non-uniform sampling � Signal specific sampling �Biomedical signal � Electrocardiogram

1 Introduction

Bio-potential signals convey valuable information for

diagnostic purposes. In many cases it is desirable to have a

record of such signals for a relatively long period of time.

For example, in order to diagnose heart arrhythmias,

electrocardiography (ECG) recording is widely used. Since

heart arrhythmia may happen unexpectedly, long term

recording of the ECG signal is necessary for accurate

diagnosis. In these cases the ECG (or any other bio-

potential signal) recording device should be portable. This

requires the electronic recording device to consume very

little power and to have a relatively large memory to

sample and save the signal for several days (or even

weeks). Reducing the number of samples in the recording

device is critical in the reduction of the memory size as

well as the power consumption.

Figure 1 illustrates a sample of an ECG signal. The

main features of the ECG signal are shown by the P, Q, R,

S, and T letters. As can be seen in this figure the waveform

can be divided into regions of slow and fast transitions

(corresponding to ‘low activity’ and ‘high activity’ regions

in Fig. 1). The region around the QRS complex has the

fastest transitions. In other regions the signal variations are

moderate or slow. The required sampling rate depends on

the harmonics of the QRS complex and the application. For

example, the analysis of heart rate variations (HRV)

requires high resolution of time for the detection of the R

points. This demands a high sampling rate (250 Samples/s)

[1]. Sampling the whole signal with this high rate increases

the volume of data. In this case, many consecutive samples

in the slow transition regions are almost the same and do

not convey much information. If we can change the rate of

sampling in accordance with the rate of signal variations,

the data volume can be reduced considerably without los-

ing the important information in the ECG signal.

In order to reduce the volume of sampled data in a

monitoring device, the bio-signal is typically sampled and

converted to digital by an analog to digital converter

(ADC) at the Nyquist rate or more. The sampled data is

then compressed using compression technique to reduce

the size of the memory needed to save the data [2–6]. In

M. Zaare (&) � H. Sepehrian � M. Maymandi-Nejad

Integrated Systems Lab., Department of Electrical Engineering,

Ferdowsi University of Mashhad, Mashhad, Iran

e-mail: [email protected]

H. Sepehrian


M. Maymandi-Nejad


123

Analog Integr Circ Sig Process (2013) 74:317–330

DOI 10.1007/s10470-012-9984-7

Author's personal copy

this method, although the size of data is reduced, the power

consumption of the circuit prior to digitization is not

decreased. If the reduction of the sampling rate happens

during digitization, it can lead to lower power consumption

in the analog part of the circuit. Hence, the technique that is

used to reduce the number of samples should be compatible

with the architecture of the ADC. In bio-implantable

devices in which the sampled signal is to be transmitted out

of the body, reducing the sampling rate is also desirable

since it leads to lower transmitter power.

The successive approximation analog to digital con-

verter (SA-ADC) is a good candidate for low to moderate

sampling rates and can be designed to be very low power

[7–12]. In this paper we propose a new SA-ADC which

implements a non-uniform adaptive-sampling technique.

Using this SA-ADC the data volume can be reduced for

sparse bio-signals like ECG while the power consumption

is also decreased. In Sect. 2 of this paper a few of the state-

of-the-art techniques to reduce data volume for bio-signals

are reviewed. In Sect. 3, the proposed non-uniform adap-

tive-sampling algorithm is discussed and the MATLAB

simulation results are presented. The proposed SA-ADC is

presented in Sect. 4 and simulation results are provided.

We finally conclude the paper in Sect. 5.

2 Bio-potential signal sampling techniques

Since bio-potential signals are sparse in time-domain,

sampling with a fixed frequency is not suitable. Hence,

adaptive-sampling is used in bio-potential recording sys-

tems [1, 13, 14] in which the sampling frequency changes

with the rate of signal variations.

In [1] a sampling technique for ECG signal is presented

in which the sampling rate is controlled by an activity

detector block (ACTDET). The analog to digital conver-

sion is done by an 11-bit SA-ADC. The rate of signal

variations is detected by a switched capacitor (SC) differ-

entiator. The output of the differentiator is compared with a

threshold to choose the sampling frequency which can be

either 64 Hz (fL = 64 Hz) or 1,024 Hz (fH = 1024 Hz). fHis suitable for sampling the R signal of the ECG while fL is

suitable for other slow varying parts. The threshold voltage

(Vth) is made adaptive to let the circuit follow the variations

of the ECG signal.

Using this technique the data volume is decreased by a

factor of 7.3 compared to the case where the sampling is

done by a constant frequency of 1,024 Hz [1]. Although the

ratio of the total number of data without any compression

to the number of compressed data is a relatively good, the

implementation of this technique requires more complex

digital circuitry and several relatively power hungry analog

blocks; like opamp, filter, SC differentiator and compara-

tors. Hence, this technique would not be very power-effi-

cient. Moreover, using a differentiator increases the noise

sensitivity of the circuit. Also, in the calculation of the

compression ratio, the extra data that should be saved as an

indication of the exact time of sampling (typically known

as the time stamps or time flags) are not considered. Hence,

the effective compression ratio is lower.

In [13] a non-uniform sampling technique is presented

in which two different sampling frequencies are used. In

this method the maximum and minimum points of the

signal are detected and the sampling frequency is increased

around these points. Circuit level simulations have shown

that this technique can reduce the average sampling fre-

quency and the volume of data by 50 and 35 %, respec-

tively. For the implementation of this system two

differentiators are used. Using differentiator increases the

noise susceptibility of the system.

Another sub-Nyquist sampling technique is the asyn-

chronous sampling and has been known since 1950 [15]. In

the asynchronous technique instead of sampling the signal

at fixed instants, the signal is sampled whenever it crosses a

threshold voltage. This way the sampling rate matches the

rate of change of the signal.

In the adaptive asynchronous sampling, the threshold is

changed according to the slope of the signal which may

lead to loss of some of the features of the signal. In Ref-

erence [14] a modified adaptive asynchronous sampling is

used. In this technique each peak and valley of the signal is

saved and used to calculate the high and low threshold

voltages for the next period. When the signal rises (falls)

and crosses the high (low) threshold the system starts

sampling with the highest rate. This method is able to

detect the QRS complex of the ECG and the sampled data

Fig. 1 ECG waveform with

inherent time-domain sparsity

318 Analog Integr Circ Sig Process (2013) 74:317–330

123


cannot be used to recover the whole ECG signal. This is

due to the fact that the sampling times are not saved.

Moreover, the proposed algorithm is not optimum for

detecting local extrema, e.g. the P and T waves of the ECG.

A relatively new method for sampling sparse signals

with under-Nyquist rate is compressive sampling (CS). The

CS allows full recovery of the original signal. It has been

recently considered for EEG and ECG compression

[16–20]. In [16] digital CS is proposed in which com-

pression is done after digitization with an ADC. The ulti-

mate goal in CS is to bring CS algorithm down to the

analog part of the system before the ADC. However, there

is still a long way to reach this goal. Moreover, compres-

sion techniques based on CS require a complex digital

post-processing. In fact the main reason for using CS is to

reduce the work load and complexity of the coder at the

expense of more complex decoder.

There are other sampling techniques that can theoreti-

cally decrease the volume of data but they require a

complex function to be implemented [21]. These kinds of

techniques are not desirable from a circuit point of view.

Based on the above discussions, it is clear that the best

way for sampling a sparse signal with minimum data vol-

ume and power consumption is to sample the signal with a

sub-Nyquist rate such that it can be accommodated in the

sampler circuit (before or during the ADC). The under-

sampling should be done in an adaptive way (and not

stochastically) so that the signal can be recovered without

much difficulty.

3 The proposed non-uniform adaptive-sampling

technique

3.1 Basic operation

In this section we present the proposed non-uniform

adaptive-sampling technique. In this method, sampling is

done based on the activity of the signal. The system has

two clock signals CLKH and CLKL with frequencies fH (the

high sampling frequency) and fL (the low sampling fre-

quency), respectively. The relationship between these

frequencies will become clear later. For the sake of illus-

tration, Fig. 2 shows a typical ECG signal sampled with

this technique. As can be seen the ECG signal is composed

of regions with slow and fast variations. This figure shows

the two clocks used in the sampling system. The signal is

monitored at a rate determined by CLKH to detect the rate

of change of the signal. During the fast transition regions

the signal is sampled by fH and during the slow transition

regions the signal is sampled by fL. The CLKsample in Fig. 2

is the overall clock which represents the sampling instants.

Clearly, the sampling rate is changing based on the rate of

variation of the ECG.

An important issue in the proposed technique is how to

detect the fast and slow transition regions. This is shown in

the flow chart of Fig. 3 which illustrates the procedure of

the proposed sampling technique. Let TH and TL be the

period of CLKH and CLKL, respectively. We also define

m as the ratio of TL to TH (m = TL/TH) and VDAC(PS) as the

value of the last sampled signal (i.e. the last digital code

converted to analog by a digital-to-analog converter). The

sampling algorithm starts by initializing the value of

VDAC(PS). The input signal at time nTH (Vi(n 9 TH)) is

compared with VDAC(PS). If the absolute value of the dif-

ference is not larger than a threshold value (Vth), then the

signal variation has not been fast enough and the signal is

not sampled. However, if the time interval between n 9 TH

and the last sampling instant is equal to TL (the condition

satisfied by Mod(n, m) = 0) the signal should be sampled.

If the absolute value of the above difference is larger than

Vth then the signal variations has been fast enough and the

signal is sampled. The value of the VDAC(PS) is also updated

for the next sampling. Note that the signal is being moni-

tored by fH, however, it is not necessarily sampled with this

frequency. In fact the sampling is done at a rate whose

average is more than fL and less than fH. To obtain the best

results in terms of the lowest distortion in the recovered

signal and not losing important information of the signal,

the three parameters fL, fH, and Vth should be chosen

carefully. fH is typically chosen large enough so that the

highest frequency harmonic present in the signal can be

sampled properly (at least the Nyquist rate of the signal).

This can be obtained from the short time fourier transform

Fig. 2 A cycle of ECG signal

sampled with the proposed

technique

Analog Integr Circ Sig Process (2013) 74:317–330 319

123


(STFT) [22]. fL is chosen based on the frequency contents

of the P and T waves of the ECG [1]. We have obtained the

best value for Vth based on system level simulations using

MATLAB, as will be explained later.

The above algorithm can be implemented by an

SA-ADC and a digital control circuit. Compared to other

signal specific sampling techniques [1], [13], the proposed

method does not require power hungry analog block and

differentiators and leads to a considerable power saving

besides a reduction in the data volume.

3.2 MATLAB simulation results

In order to show the effectiveness of the proposed sampling

technique, we have used the ECG signals from the MIT-BIH

Arrhythmia database [23]. To compare the performance of the

proposed technique with the other state of the art methods we Ta

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Table 1 Classification of signal quality versus PRD

PRD Reconstructed signal quality

0 * 2 % ‘‘Very good’’ quality

2 * 9 % ‘‘Very good’’ or ‘‘good’’ quality

C9 % Not possible to determine the quality group


123


use two popular criteria, i.e. compression ratio (CR) and per-

centage root-mean-square difference (PRD). CR is the ratio of

the total number of data without any compression to the

number of compressed data. PRD is defined as the following:

PRD ¼ kX �~Xk2

kXk2

� 100 ð1Þ

where X is the original signal vector and ~X is the recon-

structed signal. To calculate the PRD, the signal is regen-

erated from the sampled data using linear interpolation.

Table 1 shows the classification of the signal quality in

terms of the PRD [24].

We have run simulations on all 48 records of the MIT-

BIH database and for each parameter a minimum, maxi-

mum, and average (over all records) value is obtained for

PRD and CR. Table 2 shows the simulation results. In

these simulations the total number of samples is 1080. The

high and low clock frequencies (fH and fL) are 1,080 and

67.5 Hz, respectively. The value of 1,080 for fH is high

enough for diagnosis purposes. The low clock frequency of

67.5 is 1/16 of fH = 1,080. This ratio between fL and fHleads to a simpler circuit for implementing the sampling

technique. We consider a 10-bit ADC with a reference

voltage of 1 V for digitization of the signal. As mentioned

above the value of Vth is very important in the proper

Fig. 6 Record number 101 (a), 116 (b), and 231 (c) of the MIT-BIH

database and the sampling times using the proposed signal specific

sampling technique

Fig. 5 CR and PRD versus Dx

Fig. 4 The average PRD versus the average CR


123


operation of the proposed method. Here we use the term Dx

as the equivalent digital value for Vth. Increasing Dx leads

to more data volume reduction and a larger CR. It also

reduces the power consumption.

The recovery of the original signal from the sampled

data requires the exact time of the samplings if a non-

uniform sampling is used. The method of saving these time

flags is important in reducing the volume of data. The

Fig. 7 Three records of MIT-

BIH shown in Fig. 7 and the

reconstructed signals


123


technique that we have used for saving the time flags along

with the data is as follow: Since, the ratio of fH to fL is 16

we can assign a 4-bit digit for representing the sampling

time with respect to the previous sampled data. In this

technique each sample is saved by 14 bits (10 bits for the

data and 4 bits for the time flag). The 4-bit time flag shows

the distance of a sample from the previous one, in terms of

the number of CLKH pulses. The compression ratio that

includes the impact of these extra bits is represented in

Table 2 by CR and can be found by the equation below.

CR ¼ Ntotal �M

NProposed � ðMþ 4Þ ð2Þ

where M is the number of bits for each sample (M = 10),

Ntotal and NProposed are the total number of samples withoutFig. 8 Conventional SA-ADC

Fig. 9 The proposed structure


123


any compression and the number of samples with the

proposed non-uniform sampling technique, respectively.

According to Table 2, for a Dx of ±60LSB (1LSB =

0.98 mV) the maximum and average PRD are 7.2 and

5.2 % respectively. Although the average value of PRD is

less than 9 (good range in Table 1) for Dx up to ±80LSB, we

have to make sure the signal quality is good for all the

records. Therefore, we choose Dx = ±60LSB to consider

the worst case. For this value of Dx the total number of

samples is reduced from 1,080 to 108 which corresponds to

an average CR of 7.2 and an average PRD of 5.2 %. Fig. 4

illustrates the average PRD versus the average CR and Fig. 5

shows CR and PRD in terms of Dx. According to these

figures and Table 1, there is a limit on CR and Dx if the

signal quality is to be maintained within a specific range.

Figure 6 shows three ECG records from the MIT-BIH

database and their samples using the proposed technique. In

these figures Dx is chosen equal to ±60LSB. As can be seen,

when the signal variation is fast the sampling rate has increased

while for slow varying intervals the sampling rate is low. In

Fig. 7 the original signals (record numbers 101, 116, and 231)

and the recovered signals are shown simultaneously. Clearly,

the recovered signal faithfully represents the original one.

4 The proposed non-uniform adaptive-sampling

SA-ADC

The technique presented above has the ability to be

incorporated in an SA-ADC easily. The SA-ADC is

Fig. 10 Clock signal and decision times

Fig. 11 Control logic block and its signals


123


suitable for slow to moderate sampling rates and low power

applications. Hence, it is a good choice for bio-medical

applications [11, 12]. Moreover, in an SA-ADC before a

sampling starts the analog value of the previous sample is

saved on the capacitors of its DAC. This is what we need in

the proposed technique. Also, the addition and subtraction

of the Vth can be accomplished in the digital control block

of the SA-ADC using a digital adder.

Figure 8 shows the schematic diagram of a conventional

N-bit SA-ADC consisting of a sample and hold (S/H), a

comparator, a successive approximation register (SAR) and

a capacitive digital-to-analog converter (DAC). In the

Table 3 The truth table of the SERF adder [25]

A B Cin SUM Cout

0 0 0 0 0

0 0 1 Vdd-Vth 0

0 1 0 1 Vtp

0 1 1 0 1

1 0 0 1 \Vtp

1 0 1 Vth 1

1 1 0 0 [Vdd-Vth

1 1 1 [Vdd-Vth 1

Fig. 12 Proposed SERF adder

Fig. 13 Block diagram of

10-bit adder


123


sampling phase, the analog input signal is sampled and

held on capacitor Cs. At the same time the SAR is reset and

all DAC capacitors are discharged. In the next N clock

phases, the SA-ADC uses the binary search algorithm to

find the digital code corresponding to the analog voltage

stored on Cs [10]. At the end of a conversion, the analog

value of the N-bit digital number is stored on the DAC

capacitors.

4.1 Proposed structure

The structure of the proposed SA-ADC is shown in Fig. 9.

Compared to a conventional SA-ADC, this structure has a

multiplexer, an N-bit adder, and a control logic block. All

these blocks are implemented using digital circuit. Hence,

they are not power hungry. The proposed ADC requires

two more clock cycles for each conversion. These extra

cycles are used to check whether the absolute value of the

input signal variation is larger than Vth or not. The opera-

tion of the proposed architecture is as follows. First, Vi is

sampled on the sampling capacitor Cs (Vi(nTH) or Vi(n), in

short). Next, Vi(n) is compared with the voltage stored on

the DAC capacitors, which is due to the last conversion

(VDAC(PS)). Depending on the value of Vi(n) two different

directions may be taken the ADC.

– If Vi(n) [ VDAC(PS), the comparator output is zero. The

output of the comparator is latched in the control circuit

and is applied to the carry input of the adder. Therefore,

Dx (the digital number representing Vth) is added to the

last sampled digital code (available at the output of

the multiplexer). In the next clock cycle, Vi(n) is

compared with the new value stored in the DAC, i.e.

Table 4 Transistor sizes of SERF adder

X1 X2 X3 X4 X5–X8 M1 M2 M3 M4 M5 M6–M9

WL (lm) 1.5/0.18 0.5/0.18 1.5/0.18 0.5/0.18 0.5/0.18 0.5/0.18 1.5/0.18 0.5/0.18 1.5/0.15 2.5/0.18 0.5/0.18

Fig. 14 The schematic of the

comparator

Fig. 15 The schematic of the bootstrap switch

Table 6 Transistor sizes and capacitor values of bootstrap switch

WL (lm) of M1–M3, M5, M7,

M9–M13

WL (lm) of M4, M8 C1–C2 C3

1/0.18 3/0.18 10fF 500fF

Table 5 Transistor sizes of comparator

P0–P6 N0–N2 N3, N6 N4, N5 M1, M3 M2, M4

WL (lm) 0.5/0.18 0.5/0.18 1/0.18 0.5/0.18 6.1/0.18 1.8/0.18


123


VDAC(PS) ? Vth. If Vi(n) \ VDAC(PS) ? Vth then the sig-

nal variation has not been large enough and the ADC

does not convert the signal into digital. In this case the

control circuit subtracts Vth from the DAC voltage using

2’s complement of Dx. Otherwise, the input signal (Vi(n))

is converted to digital and, as a result, Vi(n) is stored in the

DAC capacitors for the next sampling.

– If Vi(n) \ VDAC(PS), the comparator output is one. The

output of the comparator is latched in the control circuit

and is applied to the carry input of the adder. In this case

Dx is subtracted from VDAC(PS) to generate VDAC(PS)-

Vth. In the next clock cycle, Vi(n) is compared with the

new value stored in the DAC. If Vi(n) [ VDAC(PS)-Vth

then the signal variation has not been large enough and

the ADC does not convert the signal into digital.

Otherwise, the input signal (Vi(n)) is converted to digital

and the value of the DAC voltage is updated.

As mentioned above, the proposed architecture requires

two more clock cycles. This is illustrated in Fig. 10. These

extra cycles are used to implement the above mentioned

decisions. As shown in this figure, in the first half-cycle the

input voltage is sampled. In the second half-cycle the

sampled voltage is compared with VDAC(PS) and the result

of the comparison is latched in a DFF to be used as the

carry input of the adder. In the third half-cycle the adder

adds ±Vth to the value of the DAC voltage. In the last

(fourth) half-cycle the comparator compares the sampled

input signal with VDAC(PS) ± Vth. If the sampled signal is to

be converted to digital the DAC is reset and the next N

clock cycles are used for conversion (assuming N-bit

converter). Otherwise, the voltage of the DAC is restored

to its previous value and the comparator turns off for the

rest of the N clock cycles.

All the above functions are implemented by the control

logic block. The schematic of the control block and the

timing diagram of the control signals are shown in Fig. 11.

The control signals Clk1, add_select, CLKcomp, res1,

Comp_ctrl should be generated using appropriate digital

gates (not shown in Fig. 11 for conciseness). When the

Fig. 16 Waveforms of a Sampling Clock, Clksample, b DAC output voltage, VDAC, c supply current of the comparator, d DAC current taken from

Vref and e supply current of the adder


123


Comp_ctrl signal is 1, the comparator is on for the com-

parisons needed at the beginning of each monitoring cycle.

The signal CLKsample indicates the times that the compar-

ator should be on for a conversion by applying the supply

voltage to the comparator (Comp_enable). The output of

the comparator is latched in a DFF by CLKcomp. The carry

input (Cin) of the adder and a signal called Conv_En is

generated from the output of the DFF. Cin goes to the

adder and Conv_En indicates whether the ADC should

convert the signal or not by generating the CLKsample

control signal. The Select signal is used for the control

signal of the multiplexer (Fig. 9). The Reset signal is

generated for resetting the DAC, if necessary.

4.2 ADC circuit and simulation results

The proposed non-uniform adaptive-sampling SA-ADC is

implemented in the 0.18 lm CMOS technology for

10-bits of resolution. The supply voltage is 1 V. For the

digital adder the sense energy recovery full adder (SERF)

reported in [25] is a suitable candidate due to its low

power consumption. However, the main problem of this

adder is that for some combination of inputs (Table 3) the

outputs can not reach GND or Vdd owing to the fact that

the outputs are generated by pass transistors. This can

lead to extra power dissipation in the succeeding stages.

To solve this problem we have modified the adder as

shown in Fig. 12. In the modified structure, pass transis-

tors are replaced by transmission gates and XOR function

is implemented besides the XNOR function. The modified

SERF full adder cell is used to make a 10-bit adder as

shown in Fig. 13. Table 4 shows the size of all the SERF

adder transistors.

The schematic of the comparator is illustrated in Fig. 14

[7]. The inputs of this comparator are applied to both

PMOS and NMOS transistors. Hence, the input range is rail

to rail. The transistor sizes of the comparator are shown in

Table 5. The SA-ADC needs a switch to sample the input

signal. In order to avoid limiting the input signal swing, we

Table 7 Simulation results of the proposed SA-ADC

Proposed adaptive-

sampling off

Proposed

adaptive-sampling

on

Average sampling rate 1,000 Hz 95 Hz

Data Size 10 bit 14 bit

Data Rate 10,000 bit/S 1,330 bit/S

Average power over one

ECG period

570 nW 54 nW

Total memory required

for 3-day recording

324 Mbyte 43.1 Mbyte

Power saving 90.5 %

Area 90,832 lm2 Area overhead: 6.5 %

Table 8 Performance comparison with other designs

Parameter [1] [20] This work

Technology 0.5 lm 90 nm 180 nm

Supply voltage 2 V 0.6 V 1 V

Power

consumption

5.2 lW

(including the

SPI power)

1.9 lW 0.58 lW

Power saving NA NA 90.5 %

Area Conventional

SA-ADC:

723,600 lm2

90,000 lm2 Conventional

SA-ADC:

84,957 lm2

ACTDET:

918000 lm2Extra logic:

5,875 lm2

Sampling rate Between 64 and

10,24 Hz

\20 kHz 95 Hz

CR 7 10 7.5

PRD NA 10 dBa 2.67 %

Simulation/

Measurement

Measurement Measurement Simulation

a This is SNDR and is defined as the reference signal energy divided

by the error energy between the reconstructed signal and the reference

Fig. 17 Record number 231 of the MIT-BIH database. Sampling

times (a), original and recovered signals (b)


123


have used a bootstrap switch. The schematic of the boot-

strap switch is shown in Fig. 15 [26]. Table 6 illustrates

transistor sizes and capacitor values of bootstrap switch.

Figure 16 illustrates sampling clock, output voltage of

the DAC, the supply current of the comparator and the

adder, as well as the current taken from Vref. The Clksample

signal shows the periods in which the sampling is done.

Whenever Clksample is high a conversion has happened and

when it is low, the input is not converted to digital. During

the periods that Clksample is low, the input has been less

than ±60LSB. The current waveforms in this figure show

the times that each block is not active. When a block is

active a current is taken from the supply or Vref.

In order to check the performance of the SA-ADC an

ECG signal from the MIT-BIH data base (record 231) is

applied to the ADC. Fig. 17 depicts the original and the

recovered signals. Simulation results of the SA-ADC are

shown in Table 7. As can be seen, the average sampling

rate is reduced to 95 Hz. The average power consumption

of the proposed ADC is lowered by 90.5 % and the number

of bits of the required memory is reduced by 86.7 %.

Simulated specifications of the proposed SA-ADC are

compared with the state-of-the-art implementations in

Table 8. The proposed architecture exhibits considerable

power saving, while the area overhead is 6.5 %. The power

consumption reported in Table 8 is the total power of the

circuit for converting of one sample.

5 Conclusions

A new non-uniform signal specific sub-Nyquist sampling

technique for sparse signals has been proposed. The pre-

sented algorithm monitors the signal with a high frequency

and adaptively adjusts the sampling rate based on the

activity of the signal. Hence, the average sampling rate is

reduced, resulting in considerable power saving and

smaller memory size requirement. Circuit level simulations

of the proposed technique show a compression ratio of 7.5

for the ECG signal and a power saving of 90.5 %. Total

memory required for 3-day recording in conventional and

proposed system is 324 and 43.1 Mbyte, respectively.

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Maryam Zaare was born in

Mashhad, Iran, in 1983. She

received the B.S. and M.S. degrees

in electrical engineering, in 2006

and 2008, respectively, from

Ferdowsi University of Mashhad,

Mashhad, Iran, where she is cur-

rently working toward the Ph.D.

degree. Her research interests

include design of analog and

mixed-signal integrated circuits

and systems, data converters, and

biomedical circuits and systems.

Hassan Sepehrian was born in

Mazandaran, Iran, in 1984. He

received the B.S. from Shahed

University of Tehran, Iran, in

2008 and M.S. degrees from

Ferdowsi University of Mash-

had, Mashhad, Iran, in 2010,

both in electronics engineering.

He is currently working in NRP

Company in Tehran, Iran. His

research interests include design

of analog and mixed-signal

integrated circuits and systems,

data converters, and biomedical

circuits and systems.

Mohammad Maymandi-Nejadreceived the B.Sc. degree from

Ferdowsi University of Mash-

had, Mashhad, Iran, in 1990 and

the M.Sc. degree from Khajeh

Nassir Tossi University of

Technology, Tehran, Iran, in

1993, and the Ph.D. degree from

the University of Waterloo,

Waterloo, ON, Canada, in 2005,

all in electronics engineering.

From 1994 to 2001, he was a

Lecturer in the Department of

Electrical Engineering, Fer-

dowsi University of Mashhad,

where he was engaged in teaching and research and also conducted

several industrial projects in the field of automation and computer

interfacing. He is currently an Assistant Professor in the same

department. His current research interests include low-voltage, low-

power analog ICs and their applications in biomedical circuits and

systems. Dr. Maymandi-Nejad received the Strategic Microelectron-

ics Council of Information Technology Academia Collaboration

(ITAC) Industrial Collaboration Award in 2005 for his work on a

wireless bioimplantable device for monitoring blood pressure of

transgenic mice.


123


http://www.physionet.org/physiobank/database/mitdb/

http://www.physionet.org/physiobank/database/mitdb/

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