research article the design of low noise amplifiers in

Research ArticleThe Design of Low Noise Amplifiers in Deep Submicron CMOSProcesses A Convex Optimization Approach

David H K Hoe1 and Xiaoyu Jin2

1Department of Engineering Loyola University Maryland Baltimore MD 21210 USA2Department of Electrical Engineering University of Texas at Tyler Tyler TX 75799 USA

Correspondence should be addressed to David H K Hoe dhhoeloyolaedu

Received 17 June 2015 Revised 21 August 2015 Accepted 30 August 2015

Academic Editor Roc Berenguer

Copyright copy 2015 D H K Hoe and X Jin This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

With continued process scaling CMOS has become a viable technology for the design of high-performance low noise amplifiers(LNAs) in the radio frequency (RF) regime This paper describes the design of RF LNAs using a geometric programming (GP)optimization method An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noiseobserved in the MOSFETs An extensive survey of analytical models and experimental results reported in the literature is carriedout to quantify the issue of excessive thermal noise for short-channel MOSFETs Short channel effects such as channel-lengthmodulation and velocity saturation effects are also accounted for in our optimization processThe GP approach is able to efficientlycalculate the globally optimum solution The approximations required to setup the equations and constraints to allow convexoptimization are detailed The method is applied to the design of inductive source degenerated common source amplifiers at the90 nm and 180 nm technology nodesThe optimization results are validated through comparison with numerical simulations usingAgilentrsquos Advanced Design Systems (ADS) software

1 Introduction

The low-noise amplifier (LNA) is the critical component inthe analog front-end of a radio frequency (RF) receiver TheLNA is responsible for providing sufficient amplification ofweak input signals while minimizing the amount of addedelectronic noise and distortion As a result the characteristicsof the LNA set the upper limit on the performance ofthe overall communication system The optimization of theLNA is a complex task involving tradeoffs that must bemade among several competing parameters including noisefigure linearity and impedance matching [1] While bipolartechnologies have traditionally dominated RF designs dueto their superior switching frequency and gain they arenot particularly suited for low power design and are notdirectly compatible with scaled digital CMOS processesIn the late 1990s the transit frequency of CMOS devicesreached the 40GHz range which enabled the design andimplementation of RF CMOS circuits that could processsignals on the order of 4GHz [2] A combination of improved

processing technology suitable MOS circuit architecturesand amenable wireless standards have helped push CMOStechnology to the forefront for RF circuit implementations[3ndash5] Implementing high quality RF analog circuits onscaled digital processes is a desired goal for a couple ofreasons First a primemotivation is the increased integrationdensities and resulting lower costs Second it allows therealization of a complete RF transceiver on a systems-on-a-chip (SoC) implementation which would further improvedesign flexibility and system optimization [6] An SoC designwith digital analog and RF components will pave the wayfor radio systems that are largely software-controlled digitaldevices [3] While the digital components dominate in asoftware-defined radio (SDR) architecture the analog front-end including the LNA will remain the critical componentthat determines the overall system performance

In the rapidly growing consumer demand for portablewireless devices with long battery life obtaining sufficientreceiver sensitivity while minimizing power dissipation is amajor design objective As process scaling continues to shrink

Hindawi Publishing CorporationVLSI DesignVolume 2015 Article ID 312639 16 pageshttpdxdoiorg1011552015312639

2 VLSI Design

the dimensions of the CMOS transistors RF circuits willbenefit from the improved switching frequencies Howeverthe main issue will be the reduction in performance dueto increased thermal noise from MOSFETs implemented inscaled digital CMOS processes and lower gain and signalswing headroom as voltage supplies are inevitably decreasedWith reduction in the analog voltage supplies an increase inpower dissipation is required in order to maintain constantperformance [7]Hence innovations in circuit topologies andoptimizationmethodswill be required tomaintain low powerand high performance as device scaling continues deep intothe nanometer-scale dimensions

A common design methodology is to determine theminimum noise that can be obtained given constraints onimpedance matching and power dissipation Using classicaltwo-port noise theory the optimum impedance that must bepresented at the source of the LNA in order to achieve theminimumnoise figure (NF) can be calculatedAn appropriatematching network is inserted between the source and theLNA to help achieve this goal as illustrated in Figure 1 Itis well known that maximum power transfer between thesource and the amplifier input occurs when the complexconjugate of 1198851015840in matches the source impedance 119885119904 [1]Common-source (CS) amplifiers have been the most popularCMOS LNA circuit topologies due to their good low-noiseperformance and high gains However when using a CSamplifier the input impedance119885in presented by theMOSFETmakes it difficult to optimally match with the externalimpedance 119885119904 which is generally resistive in nature [8]Hence tradeoffs in terms of noise performance and gainmustbe made with this architecture

The basic amplifier architecture illustrated in Figure 2allows the noise figure to beminimized while achieving inputmatching under power constrained conditions The additionof inductive source degeneration and an input impedancematching inductive component denoted by 119871 119904 and 119871119892respectively allows improved impedance matching to beobtained over a narrow band of interest The addition of thecapacitance 119862119890 gives the added design flexibility of meetinga given power dissipation and input matching specificationwhile maintaining a very low noise performance [9] Thecascode device1198722 provides isolation with the load

Efficient and accurate optimization techniques for imple-menting analog integrated circuits are a critical facet of aCAD-based design flow This is essential when the goal is tominimize the time-to-market for a product and thus haveworking designs on first silicon [10] While the noise analysisof a linear two-port network provides some insight into howto optimize the noise figure (NF) of an amplifier [11] this clas-sical approach does not provide any guidance on the sizingof the devices Various approaches that incorporate suitableFET device characteristics and noise models into the designprocess have been developed [12ndash14] In order to accountfor second order effects in devices as scaling occurs twogeneral optimization strategies can be used simulation-basedand equation-based methods A simulation-based approachallows more general topologies and circuit parameter varia-tions to be exploredHowever there are a couple of drawbacksto this approach First as metaheuristic algorithms such as

LNA

Matchingnetwork

Load

Z998400in

s(t)

Zin

minus

+

Zs

Figure 1 Generalized block diagram of the low noise amplifier asthe key front-end component

RF input source

RF output to next stage

VDD

VDD

LoutCout

Ce

Rout

M2

M1Lg

Ls

Rs

Vs

Figure 2 Schematic of a CMOS cascode low noise amplifier withinductive source degeneration

genetic algorithms and other evolutionary techniques areoften used this approach is very computationally intensiveThis is due to the large number of iterations that requiredetailed circuit simulations to be executed [15ndash18] Secondthere is no guarantee that a globally optimum solution isfound On the other hand equation-based methods attemptto formulate a solution for amore restricted set of parametersand usually for a predetermined circuit topology Geometricprogramming methods are able to find a globally optimumsolution very efficiently for a well-formulated problem [19]The trade-off in this case is that certain approximationsmust be made to ensure that the device equations are in aform suitable for numerical optimization However once thesystem is set-up a globally optimum design can quickly befound

In this paper the focus is on the optimization of a specifictopology the CS CMOS LNA when short-channel effectssuch as excess thermal noise must be taken into consider-ation As such we will make use of convex optimization aform of geometric programming Geometric programming(GP) has been previously employed to optimize a variety ofintegrated circuit designs including both analog and digitalcircuits [20ndash25] For a comprehensive overview and list ofGP applications see [19] The approach in this paper is tooptimize the NF of the CS LNA subject to various constraints

VLSI Design 3

such as input circuit quality factor power consumption andinput impedance matching similar to [12] The optimizationprocedure will allow the globally optimum selection ofdevice parameters Geometric programming has been usedto optimize the design of RF CMOS low-noise amplifiers atthe 035 120583m technology node [26] using the design proposedin [9] While the work by [26] results in globally optimumsolutions with an extremely small computational cost it doesnot take into account MOSFET submicron device character-istics and the issue with excess noise in the nanoscale regimeis not addressed

The main contribution of this study is the incorporationof importantMOSFET short-channel effects including excessnoise into a GP framework to enable the optimization ofLNAs designed in deep submicron processes [27] An exten-sive review and evaluation of the various approaches usedto model the excess noise in nanoscale devices is given Inaddition the approximations required to convert the relevantdevice equations into a form required by the GP algorithmswhile minimizing the amount of accuracy lost in the noiseand current-voltage model equations are detailedThis paperis outlined as follows The second section provides the back-ground theory on modeling MOSFET noise including thevarious models used to explain the sources of excess thermalnoise in MOSFETs with nanoscale dimensions The thirdsection describes the optimization method for designing theRF LNA using geometric programming The fourth sectionpresents the results from applying geometric programmingto obtain the globally optimal solution for RF LNA designs in90 nmand 180 nmprocessesThe generated optimal solutionsare compared with results from Agilentrsquos Advanced DesignSystems (ADS) software Finally the implication of geometricprogramming for short-channel CMOS designs is discussedand future work in this area is described

2 Noise in Deep Submicron CMOS Processes

While MOSFETs in aggressively scaled CMOS processeshave sufficiently high transit frequencies (119891119879) for RF circuitapplications issues with increased noise levels may preventlow noise operation This section discusses the issues withexcess noise that have been experimentally observed Areview of basic noise theory is first undertaken followedby a discussion of the relevant observations in the literatureregarding the issue of excess MOSFET noise This sectionconcludes with a summary of the key parameters used tomodel this excess thermal noise in deep submicron processes

21 Basic MOSFET Noise Theory An expression for thepower spectral density due to the thermal noise in aMOSFETis derived in this subsection The relationship between thechannel current and the local channel conductivity of theMOSFET is considered first The drain current of a MOSFETcan be expressed by the following relationship

119868119889 = 119892 (119881 (119909)) sdot 119889119881 (119909)119889119909 (1)

where 119881(119909) is the channel potential at position 119909 in thedevicersquos channel as shown in Figure 3 119889119881(119909) is the dc voltage

ChannelOxideGate

Source Drain

Vd

Id

Vg

Vs

x

L

Vb

V(x)

Figure 3 Cross-section of an 119899-channel MOSFET transistor

difference in the electron quasi-Fermi level in the inversionlayer and the hole quasi-Fermi level in the substrate atposition 119909 and 119892(119881(119909)) is the local channel conductivity

For a simple long-channel MOSFET using the gradualchannel approximation the following relationships can bewritten [8]

119892 (119881 (119909)) = 120583119862ox119882(119881od minus 119881 (119909)) 119881od = 119881gs minus 119881th (2)

where 119881gs is the gate-to-source voltage 119881th is the thresholdvoltage 119881od is the gate overdrive voltage 119882 is the width ofthe MOSFET 120583 is the carrier mobility and 119862ox is the oxidecapacitance per unit area

Assuming a differential segment Δ119909 of the channel asmall noise voltage contribution V(119909) across the segment Δ119909is observed which is added to the dc voltage 119881(119909) Thisvoltage can cause noise in the drain current which leadsto a change in the dc current through the MOSFET In thefollowing analysis a couple of assumptions are made Firstnoise sources of the different channel segments are local andnot correlated Second the charge carriers are in thermalequilibrium The boundary conditions of the small voltagecontribution V(119909) are V(119909)|119909=0119871 = 0 [8] The power spectraldensity 119878119894119889 for the thermal noise of a long-channel MOSFETis then expressed by the Klaassen-Prins equation [28]

119878119894119889 = 41198961198791198712119868119889 int

119881ds

01198922 (119881) sdot 119889119881 (3)

where 119868119889 is the drain current of the device The impact ofhot electron effects can be modeled by replacing the latticetemperature with carrier temperature 119879119890(119909) [8]

119878119894119889 = 41198961198791198712119868119889 int

119881ds

0

119879119890 (119909)119879 1198922 (119881) sdot 119889119881 (4)

For noise analysis it is often convenient to treat theMOSFETas a resistive element

119878119894119889 = 41198961198791205741198921198890 (5)

The parameter 120574 is known as the white noise gamma factorgiven the relationship between the thermal noise powerspectral density and the output conductance at different biasconditions [27]

120574 = 11198920119868119889119871 int

119881ds

0

119879119890 (119909)119879 1198922 (119881) sdot 119889119881 (6)

4 VLSI Design

In (6) 1198920 is the channel conductance per unit length at thesource and 1198921198890 is the channel conductance at zero drainbias The value of 120574 is unity for zero drain bias in long-channel devices and decreases toward 23 in saturation Theexpression in (6) is commonly used to express the thermalnoise in long-channel MOSFETs In practice the white noisegamma parameter continues to be used as a common metricto allow experimental or theoretical results to be comparedfrom different research groups when describing the degreeof excess channel thermal noise in short-channel transistors[29]

The variation of the channel charge due to thermal noiseis capacitively coupled to the gate terminal resulting in anoisy gate current Just as the white noise gamma parameterprovides a convenient way to express the power spectraldensity of the thermal noise the introduction of a betaparameter allows the induced gate noise to be expressed ina similar manner [8]

119878119894119892 = 4119896119879120573119892119892 (7)

The parameter 120573 is basically independent of the substrateconductivity and its value is 43 in the saturation region forlong-channel MOSFETs The conductance 119892119892 is given by

119892119892 = 12059621198622gs51198921198890 (8)

where119862gs is the intrinsic gate capacitance of the transistor Inthe circuit model representation illustrated in Figure 4 theconductance 119892119892 is connected between the gate and sourceshunted by the gate noise current 119894119899119892 From (8) it can beobserved that the conductance 119892119892 increases with frequencyindicating that the induced gate noise can dominate at radiofrequencies The conductance 119892119892 is also proportional to thesquare of 119862gs so a small value of 119862gs will favor a lowerinduced gate noise

Since the induced gate noise is correlated with the drainthermal noise the correlation coefficient is defined as [8]

119888 = 119894119899119892 sdot 119894lowast119899119889radic1198942119899119892 sdot 1198942119899119889

(9)

where 119894119899119892 sdot 119894lowast119899119889 is the spectrum of the cross-correlation ofthe drain thermal noise and the induced gate noise Thecomplex correlation coefficient 119888 is theoretically 0395119895 forlong-channel MOSFETs as noted in Appendix C [8]

The finite resistance of the gate material also contributesto this noisy gate current and can become the dominantsource of gate thermal noise in short-channelMOSFETs [30]Two factors tend to minimize this source of gate noise Firstmodern CMOS processes use silicided gate material whichhelps reduce the resistance in the gate Second for wideMOSFETs a multifinger layout can be used whereby severaldevices (ie ldquofingersrdquo) are connected in parallel giving thegate resistance as [31]

119877119892 = 119877sh12 sdot 1198992119891

119882119871 (10)

Cgsgggs

+

minus

ngi

Figure 4 Circuit model for the gate noise [1 8]

where 119877sh is the sheet resistance of the gate material 119899119891 is thenumber of fingers and the factor of 12 is due to the distributednature of the gate resistance when it is contacted on bothends [12 32] As devices scale to submicron dimensionsthe interface resistance between the silicide and polysiliconlayers becomes an important component of 119877119892 which is notsignificantly impacted by layout optimizations [33]

22 Modeling Thermal Noise in Short-Channel DevicesExcess thermal noise for scaled devices must be taken intoaccount when designing LNAs operating at RF frequenciesIn this subsection we review recent methods used to modelthis noise This provides the background on the currentunderstanding of the excess thermal noise issue in deepsubmicron devices While this issue is still a matter ofopen debate among researchers [34 35] the development ofmodels will provide the reader with the context to understandthe comparisons in the following subsection as well as therationale for the use of an empirical fit to the data for ouroptimization method Here the emphasis is on extending theclassical theory of thermal noise to submicron devices byincluding short-channel effects such as velocity saturationchannel-length modulation and hot carriers The Klaassen-Prins equation for the noise power spectral density in (3)can be modified to include channel-length modulation andvelocity saturation effects as follows

119878119894119889 = 41198961198791198712elec119868119889 int

119881ds

01198922119888 (119881) sdot 119889119881 (11)

where 119871elec is the electrical channel length of the MOSFETreplacing the effective channel length 119871eff in the long-channel expression [29 30 35]The parameter119871elec is definedas 119871elec = 119871eff minus Δ119871 where Δ119871 is the length of thevelocity saturated region The parameter 119892119888 is the revisedconductivity taking velocity saturation into considerationThe noise contribution of the pinch-off region is assumedto be negligible as experimental evidence indicates that thechannel thermal noise is practically independent of the drain-to-source voltage beyond the saturation voltage [30]

The approach by Han et al [36 37] is to considerthe effects of velocity saturation and carrier heating Whilethe carrier mobility is considered independent of the biasconditions and is usually modeled as a constant in long-channel MOSFETs it is degraded in short-channel devicesdue to the high lateral electric field from drain to source [38]and is thus dependent on the bias conditionsThe impedancefield method [39] was used to recalculate the thermal noise

VLSI Design 5

for short-channelMOSFETsThe drain current of aMOSFETwith the effect of mobility degradation is then given by [37]

119868119889 = 1198920 (119881) (119889119881119889119909)1 + (119889119881119889119909) 119864119862 (12)

where the local channel conductance1198920(119881) = 120583eff119882119862ox(119881odminus120572119881) The parameter 119864119862 = 2Vsat120583eff is the critical field atwhich velocity saturation occurs Vsat is the saturation velocityof carriers 120583eff is the effective mobility and 120572 is a coefficientdescribing the bulk-charge effectThebulk-charge effect is thevariation of threshold voltage caused by nonuniform channeldepletion and the dependence of the threshold voltage onthe channel potential The impact of the carriers in thevelocity saturation region on the drain thermal noise currentis ignored in this analysis Applying a similar procedure as[30] the channel noise of theMOSFET takes the form of [37]

119878119894119889 = 41198961198791198712elec119868119889 (1 + 119881ds (119871elec119864119862))2

sdot int119881ds0

11989220 (119881) (1 + 119864119864119862) sdot 119889119881

(13)

where the electrical channel length of the MOSFET is 119871elec =119871eff minus Δ119871 In order to obtain a compact analytical equation aclosed-form expression is given by [37]

119878119894119889 asymp 41198961198791198921198890 1 minus 119906 + 11990623

1 minus 1199062 (14)

where 1198921198890 is the drain conductance at 119881ds = 0V 119906 =120572119881ds119881od The coefficient of the bulk-charge effect 120572 has atypical value of 12 [40]

Based on [36] the longitudinal electric field (119864) along thechannel was examined by Deen et al [31] The longitudinalelectric field (119864) is now expressed as a function of the position119909 along the channel instead of simply being constant

119864 (119909) = 119864119862119881119889[(2119881od minus 119881119889)2 minus 4120572119864119862119881119889119909]12

(15)

where 119881119889 = 119868119889(119882119862oxVsat) and 119881od is the gate overdrivevoltage given in (2) The revised total channel charge can beobtained by integrating the drain current from 0 to 119871elec withthe expression of 119864(119909) in (15) The total drain current noisepower spectral density is then obtained

119878119894119889 = 411989611987941198812od + 1198812119889 + 119881od11988111988931198812od (119881od minus 119881119889) 120572119868119889 (16)

An analytical thermal noise model following [41] was devel-oped by Jeon et al [42] which includes short-channel effectssuch as channel-length modulation velocity saturation andhot carrier effects The ac conductance 119892ac is a small signalconductance with the consideration of velocity saturationIt expresses the current noise source spectrum of a smallsegment of the channel length Δ119909

Δ1198942119899 = 4119896119879119888119892acΔ119891 (17)

where 119879119888 is the carrier effective temperatureThe carrier tem-perature has shown a dependency on the electric field when ahigh electric field is present in short-channel MOSFETs Therelation of 119879119888 and the electric field is given as

1198791198881198790 = (1 + 119864119864119888)119899 (18)

where 1198790 is the lattice temperature When 119899 = 0 the carrieris in thermal equilibrium without any carrier heating effectwhile the heating effect is considered for 119899 = 1 or 119899 = 2[8] Experimentalmeasurementswith devices having channellengths of 130 nm indicate that the carrier heating effect with119899 = 2 gives the most accurate results [42]

23 Results and Comparisons of Modeling Noise in Short-Channel Devices While the expressions for the power spec-tral density in (11) and (13) include short-channel effectsthey are not compatible with the form required by geometricprogramming A simpler noise formula which captures theessence of the noise issues at the deep submicron technologynodes is required As previously noted the channel thermalnoise can be conveniently expressed using the white noisegamma expression given in (6) Since this expression isa simple closed-form equation it has been widely usedfor noise analysis by circuit designers For long-channelMOSFETs the theoretical values of 120574 are well known It isequal to unity at zero drain bias and 23 in the saturationregion

The analysis and experimentalmeasurements by Scholtenet al [30] have shown that the channel thermal noise constant120574 and the gate current noise parameter 120573 are independent ofthe operating frequencies up to moderately high frequencies(around 10GHz) and they are not very sensitive to biasconditions for high bias voltages However both parametersare expected to increase as channel lengths scale down inthe submicron range The values of 120574 are expected to belarger than their theoretical long-channel values due to excesschannel thermal noise discussed previously for short-channelMOSFETs Due to induced gate noise related to channelnoise and the increased significance of the resistivity of thegate material at short-channel lengths the parameter 120573 willexperience a similar increase in value

Based on themeasurements of Jeon et al [43] the channelthermal noise power spectral density can still be expressed byuse of the white noise parameter 120574when short-channel effectsaccount for

120574 = 119892ds1198921198890 (1 +119864119864119862) (19)

where 119892ds is the conductance of the channel and 119864 is theaverage longitudinal electric field which is equal to 119881ds119871elecThe parameter 119864119862 is the critical electric field which is equalto 2Vsat120583eff Based on the model of (19) 120574 is a function of thedrain bias for different channel lengths

For nanoscale devices with feature sizes below 100 nmit is still debated whether short-channel effects as discussedabove are adequate for describing the effects of short-channel noise [44] Some researchers have suggested that

6 VLSI Design

Deen et al 2006Scholten et al 2003Jeon et al 2010

1E minus 22

1E minus 23

1E minus 24

1E minus 250 01

Gate length (120583m)02 03 04

S i119889

(A2 H

z)

Figure 5 Thermal noise comparison of different analytical noisemodels

shot noise is better able to describe the noisy behavior forFETs below 40 nm [34 45 46] As this study focuses onLNA design optimization down to the 90 nm node it will beassumed that excess thermal noise can be adequately handledthrough modification of the white noise gamma parameter120574 Experimental results from a number of researchers appearto support this approach [31 34 43] A comparison betweenthe expression for the channel thermal noise in (16) [31]with the thermal noise calculation using the two 120574 modelsfrom [30 43] have been made As shown in Figure 5 withthe numerical data in Table 1 their results are comparablewith a similar trend regarding different channel lengths SinceScholten et al [30] and Jeon et al [43] have completed arelatively in-depth study of the noise parameters and thereis relatively good agreement of their work with the analyticalmodel of Deen et al [31] the noise calculations in this workare carried out based upon the results of [30 43]

3 Optimization Methods

The optimization of the CMOS LNA design in terms ofminimizing its noise figure as the main cost function isconsidered in this section The maximum allowed powerdissipation is used as the main design constraint as this is achief concern for modern systems especially those intendedfor mobile electronic systems The influence of other designconstraints such as the quality factor of the input circuitand the input impedance matching requirement is takeninto account during the optimization process The noiseanalysis of the LNA and the parameters used to model thenoise characteristics of submicron MOSFETs are consideredfirst Then the device equations needed to model the drain

Ce

Lg

Ls

s

g d

RsCgs gs

+

minus

Zin

nR119904ng

nRout

nout

ndgmgsi i

i

i

i

Figure 6 Small signal circuit for noise analysis

Table 1 Thermal noise comparison of different analytical noisemodels

Gate lengthPower spectral density of channel thermal

noise (A2Hz)

Deen et al [31] Scholten et al[30] Jeon et al [43]

90 nm 907 times 10minus24 104 times 10minus23 107 times 10minus23



current 119868ds as well as the transconductance 119892119898 and theoutput conductance 1198921198890 are described Finally the overallmethod used to optimize the LNA design within a geometricprogramming framework is detailed

31 Noise Analysis of the LNA This subsection describes howthe noise figure of the LNAgiven in Figure 2 can be calculatedby small signal analysis Also the design parameters used todescribe the noise characteristics of short-channel MOSFETsare given The thermal noise is the major concern at RFintermediate frequencies for MOSFETs Four noise sourceshave been considered in this study the thermal noise ofthe source resistance (119894119899119877119904) the channel thermal noise (119894119899119889)the gate noise (119894119899119892) and the thermal noise of the outputresistance (119894119899119877out) These are depicted in Figure 6 The noisecontributions due to the gate resistance are factored intothe elevated value for the parameter 120573 as discussed below[30] Neglecting the effect of the gate-to-drain capacitance119862gd on the noise calculations introduces a small error butallows closed-form equations to be derived This error isminimized through the use of a cascode topology where1198722mitigates theMiller effect of119862gd [12]The noise contributionsof the cascode device 1198722 in Figure 2 are considered tobe negligible compared to the contributions of the mainFET 1198721 Following the observations by [30] the noisecontributions of the MOSFET source and bulk resistance aretaken to be minimal and are neglected in this analysis

The contributions of these four noise sources referredto the output are denoted by 119894119899119900119877119904 119894119899119900119889 119894119899119900119892 and 119894119899119900119877out respectively Table 2 summarizes the expressions for thesenoise sources [9 47]

VLSI Design 7

Table 2 Output-referred noise equations

Noise source Expression Output-referred expression

119877119904 1198942119899119877119904 = 4119896119879 1119877119904Δ119891 119894119899119900119877119904 = 11989211989811989521205960119862tot

119894119899119877119904119894119899119889 1198942119899119889 = 41198961198791205741198921198890Δ119891 119894119899119900119889 = minus12 119894119899119889119894119899119892 1198942119899119892 = 4119896119879120573119892119892Δ119891 119894119899119900119892 = 1198921198981198951205960119862tot

1 minus 1198951198771199041205960119862tot11989521198771199041205960119862tot119894119899119892

119877out 1198942119899119877out = 4119896119879 1119877out

Δ119891 119894119899119900119877out = 119894119899119877out

The correlation between the induced gate noise and thechannel thermal noise is represented by 119894119899119900corrTherefore theLNA noise factor can be expressed as

119865 = 1198942119899119900119877119904 + 1198942119899119900119889 + 1198942119899119900119892 + 1198942119899119900corr + 1198942119899119900119877out1198942119899119900119877119904

(20)

Then the noise factor at resonance is obtained as

119865 = 1 + (14) 1205741198921198890 + 1198922119898 (119862gs119862tot)2 (1198762 + 14) 120573 (51198921198890) + 119892119898119888 (119862gs119862tot)radic(120574 sdot 120573) 20 + 1119877out

11989221198981198771199041198762 (21)

where 120574 is defined by (5) 120573 is the gate noise parameter 119888 is thecorrelation coefficient 119862gs is the intrinsic gate capacitance119862tot is the sum of119862gs and119862119890 and119876 is the quality factor of theinput circuit

Based on the studies by [30 31 43] the white noise factor120574 is assumed to be independent of the operating frequenciesup to 10GHz and to be independent of bias conditions Acomparison of the values 120574 versus FET channel length is givenin Figure 7

The measured and analytical 120574 compare favorably whenobserved at various gate lengths (eg 90 nm 180 nm and350 nm) as shown in Figure 7 As expected the white noisefactor 120574 increases when the channel length decreases Forlong-channel devices (channel lengths greater than 1 120583m) thetraditional value for 120574 is 23

Numerical values for the gate noise parameter 120573 andcorrelation coefficient 119888 are estimated from [30 43] and aresummarized along with the parameter 120574 in Table 3 Thereis a significant increase in the value of the parameter 120573 asthe channel length decreases due to the contribution fromthe gate resistance which consists of the resistance of thevias the effective resistance of the silicide and the contactresistance between the silicide and polysilicon layers [30 33]The value of 120573 is close to 43 for long-channel devices butmore than doubles in value for 180 nm devices Therefore asignificant increase is predicted for devices at the 90 nmnodeThemagnitude of the correlation coefficient is 0395 for long-channel devices [8] and it decreases due to larger 120574 and 120573when channel length reduces in size as can be inferred from(C3) in Appendix C A reasonable approximation is that thevalues for the parameters 120573 and 119888 are relatively independentof frequency and variations with bias conditions for stronginversion Scholten et al [30 48] have shown that modelingthe gate noise power spectral density 119878119894119892 with a constant valuefor 120573 using (7) gives a good fit to experimentally measuredresults for short-channel devices over a range of appliedvoltages up to 10GHz They also show that the correlationcoefficient 119888 is relatively independent of frequency and biasvoltage

In order to determine the sensitivity to 120574 and 120573 in thecalculation of the minimum noise figure the effect of varyingthese parameters was analyzed (see Appendix D for furtherdetails) When a plusmn10 variation is applied to 120574 a smallpercentage of variation (around 4) occurs to the minimumnoise figure Similarly less than 4 variation occurs on theminimum noise figure when a plusmn10 change is applied to 120573This gives confidence to the assumption that the parameters120574 and 120573 can be modeled as constants for a given technologynode without adversely affecting the optimization results

32 Device Equations for Submicron FETs This subsectionoutlines how the device models that take into account short-channel effects can be developed in a form suitable forgeometric programming As device geometries approachsubmicron dimensions and below various high field effectssuch as velocity saturation and channel length modulationmust be taken into consideration A piece-wise model of thedrain current 119868ds which includes these effects has been usedin this analysis [38]

119868ds = 120583eff119862ox (119882119871 ) sdot 119881od119881ds minus (1198982)1198812ds1 + (120583eff119881ds) (2Vsat119871)

119868119889sat = 120583eff119862ox (119882119871) (1198812od (2119898)) (1 + 120582119881ds)1 + 120583eff119881od (2119898Vsat119871)

120583eff = 12058301 + 120579119881od (22)

where119898 is the body effect factor Vsat is velocity saturation120583effis effective mobility in m2V 1205830 is normal field mobility and120579 is normal field mobility degradation factor in Vminus1 In (21)the transconductance 119892119898 and the output conductance 1198921198890 arethe two main technology-dependent parameters Analyticalsolutions are obtained for 119892119898 and 1198921198890 by taking the derivativeof the closed-form analytical drain current solutions for

8 VLSI Design

10 100 1000

Deen et al 2006

Scholten et al 2003Jeon et al 2010

Gate length (nm)

00

05

10

15

20

Whi

te n

oise

fact

or120574

Figure 7 White noise factor 120574 versus gate length

Table 3 Noise parameters for the noise analyses for 90 nm and180 nm CMOS processes

Parameters 90 nm design 180 nm designWhite noise factor (120574) 12 105Gate noise parameter (120573) 75 38Correlation coefficient (119888) 02 02

short-channel CMOS transistors (see Appendix A) yieldingthe following equations

119892119898= 119862ox1205830119882Vsat sdot (1 + 120582119881ds) (4119898Vsat119871119881od + (2119898Vsat119871120579 + 1205830) 1198812od)

(2119898Vsat119871 + (2119898Vsat119871120579 + 1205830) 119881od)2

119892119889 = 120583eff119862ox (119882119871) [119881od minus 119898119881ds minus (1198982) (120583eff (2Vsat119871))1198812ds](1 + (120583eff119881ds) (2Vsat119871))2

(23)

Then the channel conductance at zero bias condition is

1198921198890 = 120583eff119862ox (119882119871 )119881od (24)

The final expressions for 119892119898 and 1198921198890 will need to be placedin a form suitable for geometric programming as describedbelow

33 Geometric Programming Optimization of the LNA Ageometric program solves an optimization problemwhere theobjective function is in the formof a posynomial function andthe constraints are expressed as posynomial inequalities andmonomial equalities All design parameters are nonnegativevariables A monomial function has the following form [19]

119892 (119909) = 11988811990911988611 11990911988622 11990911988633 sdot sdot sdot 119909119886119899119899 (25)

where 119888 is a positive constant (119888 gt 0)11990911199092 and119909119899 are realpositive variables and 1198861 1198862 and 119886119899 are constants knownas the exponents of the monomial Any positive constant is amonomial Monomials are closed under multiplication anddivision A posynomial function is a sum of one or moremonomial functions as shown in the following equation

119891 (119909) = 119870sum119896=1

11988811989611990911988611198961 11990911988621198962 11990911988631198963 sdot sdot sdot 119909119886119899119896119899 (26)

where 119888119896 gt 0 Note that posynomial functions are also closedunder addition and multiplication A standard form for ageometric programming can be defined as an optimizationproblem with the following form

Minimize an objective function 1198910(119909)subject to constraints

119891119894 (119909) le 1 119894 = 1 119898119892119894 (119909) = 1 119894 = 1 119901 (27)

where 119909 = (1199091 119909119899) is a vector with components 1199091198941198910(119909) is an objective function with the form of a posynomialfunction 1198911(119909) 1198912(119909) 119891119898(119909) are posynomial functions1198921(119909) 1198922(119909) 119892119901(119909) are monomial functions and 119909119894 arethe optimization variables (119909119894 are always greater than zero)[19]

The objective function for this optimization problemis to minimize the noise figure NF which is already ina posynomial form Most of the design constraints areeither in a posynomial form or monomial form The mainchallenge is to translate the analytical expressions for thedevice transconductance (119892119898) and output conductance (1198921198890)in (23) into a form suitable for geometric programmingFollowing the work of [19] a curve-fitting approach is usedto obtain monomial expressions for 119892119898 and 1198921198890

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(28)

The details on the curve fitting and the resulting fittingparameters are given in Appendix B

Process-dependent parameters for 90 nm and 180 nmtechnology nodes were derived from the SPICE model filesprovided by a predictive technology model (PTM) [49 50]Furthermore the vertical field mobility degradation factor 120579the channel-length modulation parameter 120582 and the bodyeffect coefficient 119898 were extracted from the device charac-terizations provided by running SPICE simulations using thePTM models The relevant parameters are summarized inTable 4

In addition to the noise figure the major design con-straints for LNAs include the quality factor input impedancematching and power consumption Due to the resonantbehavior of the circuit the quality factor of the input circuitat the resonant frequency 1205960 is given by

119876 = 1119877tot1205960119862tot

= 121198771199041205960119862tot

(29)

VLSI Design 9

Table 4 Technology parameters for 90 nm and 180 nm CMOSprocesses

Parameters 90 nm 180 nmElectron mobility 1205830 00179m2V 00288m2VElectron velocity saturation Vsat 110 times 105ms 918 times 105msOxide capacitance per unit area119862ox

0014 Fm2 000857 Fm2

Body effect coefficient119898 121 118Vertical field mobilitydegradation factor 120579 03 Vminus1 02 Vminus1

Channel-length modulationparameter 120582 04Vminus1 03 Vminus1

To maximize the power transfer the input impedance of theLNA is required to match the source input impedance whichis assumed to be 50Ω The impedance matching constraintscan be expressed as

1205960 = 1radic119871 tot sdot 119862tot

119877119904 = 119892119898119862tot

119871 119904 = 50 ohms(30)

where 119871 tot is the sum of 119871119892 and 119871 119904The optimization problem using geometric programming

can then be expressed as followsMinimize an objective functionNoise factor119865 in (20)subject to design constraints

119871 = 119871 feature size1 120583m le 119882 le 100 120583m119862gs

119862totle 1

32

119862gs

119862ox119882119871 = 1119892119898119871 119904119862tot

= 50Ω119868ds sdot 119881DD le 119875119863max

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(31)

For the 90 nm process 119871 feature size = 90 nm 119881DD = 2V andthe maximum power dissipation 119875119863max is set at 1mW Forthe 180 nm process and 119871 feature size = 180 nm 119881DD = 3Vand 119875119863max = 15mW The current 119868ds is the drain-to-sourcecurrent through device1198721 in this design

4 Results and Discussion

The optimal design of the CMOS LNA has been computedusing CVX a package for specifying and solving geometric

Table 5 Optimal design results for low-noise amplifier when inputcircuit quality factor119876 = 4 and output circuit quality factor119876out = 5Parameters 90 nm 180 nmOutput conductance (1198921198890) 00082 S 00063 STransconductance (119892119898) 00069 S 00052 SGate width (119882) 22172 120583m 27006 120583mGate length (119871) 90 nm 180 nm119875 factor (119875 = 119862gs119862tot) 01128 01681Gate intrinsic capacitance (119862gs) 18696 fF 2787 fFAdditional capacitance (119862119890) 0147 pF 013792 pFSource inductor (119871 119904) 12063 nH 15828 nHGate inductor (119871119892) 2532 nH 24943 nHDrain current (119868ds) 05mA 05mAMinimum noise figure (119865min) 06076 dB 08229 dB

programming problems [51]The average execution time wasabout 145 seconds on a 323GHz PC with 4GBmemoryTheresulting optimal design parameters are shown in Table 5

The results from the optimal design using geometricprogramming have been compared with results from Agi-lentrsquos Advanced Design System (ADS) software a numericalsimulation tool used for RF design The input FET 1198721was biased at 05mA and the power supply was set to2V with the values of 119871119892 119871 119904 and 119862119890 determined by theconstraints used in the GP optimization The output parallelRLC values are calculated by the output circuit quality factorwhich is given as 5 in this study For the 90 nm designADS simulations indicate that the minimum noise figureis 02799 dB for a gate width of 27 120583m while the optimalwidth from the optimization of geometric programming is22172 120583m with a minimum noise figure of 06076 dB Forthe 180 nm design a minimum noise figure of 07708 dBwas obtained for a gate width of 20120583m while the optimalwidth from the optimization of geometric programming is27006120583m with a minimum noise figure of 08229 dB Asshown in Figure 8 the minimum noise figures from theADS simulations are smaller than theminimumnoise figuresfrom the GP results These discrepancies likely are causedby the lack of implementation of the excess thermal noisein the BSIM3 MOSFET models The 90 nm design displaysrelatively larger differences than the 180 nm design which isnot unexpected as excess noise is more significant in shorterchannel devices The optimal widths for minimizing the NFfrom the GP optimization and ADS simulations are not anexact match but the overall trends are fairly close Thisindicates that geometric programming which can rapidlyfind an optimal point can be used to guide the design ofshort-channel CMOSLNAsA gooddesignmethodologywillthen use detailed circuit simulations to fine tune the designand verify its performance As current simulation modelsdo not adequately account for excess thermal noise someadditional analysis based on experimentally determined FETnoise characteristicswill be required by the designer to ensurethat the optimal design is found

10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

gure

(dB)

180nm ADS180nm GP

90nm ADS90nm GP

Figure 8 Variations of noise figure with different gate width and119876 = 4

It should be noted that the inductor value of 25 nH for 119871119892would not be economical in terms of area when implementedas an on-chip planar spiral inductor A prudent design choicewould be to implement part of the inductance on the chipand the rest through the bond wire alternatively one coulduse the bond wire plus an external inductor on the printedcircuit board [1] Also advances in materials and fabricationtechnologies have made it possible to embed high qualityinductors on the order of 20 nH to 30 nH in a packagesubstrate that are suitable for RF applications [52 53]

Tradeoff analyses were performed to examine the influ-ence of the quality factor and drain current on the design ofshort-channel CMOS LNAs As the optimization results forLNAsdesigned in 90 nmand 180 nmprocesses are similar thetrade-off analysis for the 90 nm case is presented in this paperAn inverse relationship is observed between the quality factorand the minimum noise figure as seen in Figure 9(a) Whenthe input quality factor increases from 2 to 8 the minimumnoise figure decreases from 1 dB to 039 dBThe quality factornot only affects the minimal noise figure but also influencesthe optimal width of the LNAsWhen the quality factor variesfrom 2 to 8 the optimal width changes almost 10 times from75 120583m to 67 120583m as seen in Figure 9(b) This considerablechange in the optimal width indicates the importance of thequality factor in determining the optimal width of1198721

The drain current appears to have great influence onthe noise figure when the drain current is at a relativelysmall scale (ie less than 05mA) However there is notmuch variation in the noise figure when the drain currentincreases from 1mA to 5mA as shown in Figure 10 Such anobservation is true at different levels of channel width Thissuggests that for this 90 nmprocess the best balance betweenpower dissipation area and noise figure exists when the LNAis biased with 05 to 10mA of current When the channelwidth is set to 20120583m the optimal range for the input circuitquality factor is from 4 to 6 This observation is consistentwith the results reported in [9]

(a)

(b)

3 4 5 6 72 8Quality factor

00

02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

02

04

06

08

10

Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5

Figure 9 (a) Variation of minimal noise figure with differentinput quality factors 119876 and (b) variation of the optimal width withdifferent quality factors

0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA

Figure 10 Effect of drain current and channel width on the noisefigure (90 nm)

Variations in the frequency of operation also have asignificant influence on the noise figure (Figures 11 and 12)In many applications an RF LNA will be optimized for aparticular narrowband of operation for example at 24GHzTherefore the influence of operational frequency on the noisefigure will be limited and there is a clear choice for theoptimum device width for minimizing the noise figure

In sum our results show that the use of geometricprogramming allows the global optimal design optimizationof an LNA to be obtained with great efficiency This studyhas focused on the common LNA configuration that usessource inductive degeneration Short-channel effects havebeen taken into account when modeling the electronic noisein theMOSFETs as well as in the device characteristicsWhilesome approximations must be made to put the equations inthe proper form required by a GP framework the results areguaranteed to return a globally optimum solution Varioustrade-off analyses can be efficiently run as well under givenconstraints such as power dissipation and input qualityfactor For example the input circuit quality factor has agreat influence on not only the minimum noise figure butalso the optimal width Our results in general align wellwith other results in the literature In the particular caseof the 90 nm technology node used in this study one can

VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)

Figure 11 Effect of channel width on the noise figure at differentfrequencies

0 20 40 60 80 100 120

0051152253354455Frequncy (GHz) Width (120583m)

012345

Noi

se fi

gure

(dB)

Figure 12 Effect of operational frequency and channel width on thenoise figure

quickly determine the ldquosweet spotrdquo in the design The trade-off analyses in this case indicate that the best designs in termsof power and noise figure for the LNA design occur when thedrain current is in the range of 05mA to 1mA with an inputcircuit quality factor around 5

5 Summary and Future Directions

This paper has examined the use of geometric programmingfor obtaining the globally optimum design of RF CMOSLNAs implemented with short-channel devices The maincontribution of this work has been the development of aframework for noise modeling of short-channel devices byincluding short-channel effects including velocity saturationand channel-length modulation This noise model forms thebasis of the objective function for geometric programming tominimize the noise figure of CMOS LNAs In addition thenoise figure is minimized subject to the design constraintsof input circuit quality factor power consumption and inputimpedance matching Specific results from the optimizationprocedure are applied at the 90 nm and 180 nm technologynodes to determine the optimal channel width and noisefigure for RF CMOS LNAs Trade-off analysis indicates someimportant relationships among the design parameters such asthe inverse relationship between noise figure and input circuit

quality factor The relationship between the noise figure andchannel width at a given power dissipation and the inputcircuit quality factor are consistent with simulations fromAgilentrsquos ADS software The overall design trends are alsoconsistentwith other studies reported in the literatureHencethis study has validated the use of geometric programmingas an efficient method to guide the optimal design of CMOSLNAs targeted for implementation at nanoscale technologynodes

Future work will focus on the enhancement of noisemodeling for short-channel CMOS LNAs For example thenoise contributions from the gate inductor (119871119892) and thesource inductor (119871 119904) due to their finite quality factor causedby parasitic effects should be included in the analysis Asdevices continue to scale to deep submicron nodes thedoping concentration in the substrate will increase Thisaffects how the device characteristics are modelled such asthe relationship between carrier mobility and diffusivity Inaddition quantum effects should be includedwhenmodelingthe noise in the channel current [31] It is expected that moresophisticated equivalent circuit models will be required tomodel the physical effects of nanoscale devices The effect ofthe substrate as a source of noise and the back-gate transcon-ductance in the small signal model should be consideredThethinning of the gate oxide at aggressively scaled technologiesmay make gate leakage effects an important considerationOther sources of noise such as shot noise should also betaken into consideration below the 40 nm node The existingnoise optimization framework using GP can be modifiedto include these effects In addition the application of GPoptimization for other topologies such as the shunt-seriesfeedback amplifier will be considered in future work Finallywith the trend towards biasing analog circuits in the weakto moderate inversion regions to reduce power dissipationit would be interesting to explore GP methods as outlined inthis paper to optimize these circuits

Appendices

A Expressions for MOSFET OutputConductance and Transconductance

In this appendix analytical expressions for the output con-ductance and transconductance are discussed for both long-channel devices and short-channel devices

A1 Derivations of 1198921198890 and 119892119898 for Long-Channel DevicesFor long-channel devices the well-known expressions of thedrain current in both the triode region and saturation regionare given as

119868119889triode = 1205830119862ox119882119871 (119881od sdot 119881ds minus 1

21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design

where 119881od = 119881gs minus 119881th By definition the output conductance119892119889 is

119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)

Therefore the output conductance at zero bias (ie 119881ds = 0)can be expressed by

1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 1205830119862ox119882119871 119881od = radic2119882119871 1205830119862ox119868119889sat (A3)

The transconductance of a long-channel device in saturationis given as

119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 1205830119862ox119882119871 sdot 119881od = radic2119882119871 1205830119862ox119868119889sat (A4)

For long-channel devices it is obvious that the outputconductance at zero bias 1198921198890 has the same form as thetransconductance in saturation in terms of 119881od or 119868119889satA2 Derivations of 1198921198890 and 119892119898 for Short-Channel DevicesThe drain current for short-channel devices is expresseddifferently than for the long-channel devices By taking someimportant short-channel effects into account such as velocitysaturation and channel-lengthmodulation the expressions of

the analytical drain current model in both the triode regionand saturation region are given by [38]

119868119889triode= 120583eff119862ox (119882119871 ) sdot (119881gs minus 119881th)119881ds minus (1198982)119881

2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat

= 120583eff119862ox (119882119871 ) (119881gs minus 119881th)2 (2119898)1 + 120583eff (119881gs minus 119881th) (2119898Vsat119871)

sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)

After applying the quotient rule the output conductance 119892119889can be expressed as

119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 120583eff119862ox (119882119871 ) (119881od minus 119898119881ds) sdot (1 + 120583eff119881ds (2Vsat119871)) minus (119881od119881ds minus (1198982)119881

2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2

= 120583eff119862ox (119882119871) [119881od minus 119898119881ds minus (1198982) (120583eff (2Vsat119871))1198812ds](1 + 120583eff119881ds (2Vsat119871))2

(A10)

Therefore the output conductance at zero bias (119881ds = 0) canbe expressed by

1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)

By substituting the effective mobility equation into thesaturation drain current formula the equation of 119868119889sat forshort-channel devices can be rewritten as

119868119889sat= 120583eff119862ox (119882119871 ) (119881gs minus 119881th)2 (2119898)

1 + 120583eff (119881gs minus 119881th) (2119898Vsat119871)sdot (1 + 120582119881ds)

(A12)

Using (A6) and (A12) the transconductance of a short-channel device in saturation is given as

119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840

= 119862ox1205830119882Vsat sdot (1 + 120582119881ds)sdot 4119898Vsat119871119881od + (2119898Vsat119871120579 + 1205830) 1198812od(2119898Vsat119871 + (2119898Vsat119871120579 + 1205830) 119881od)2

(A13)

VLSI Design 13

B Monomial Expressions for 119892119898 and 1198921198890This appendix describes how a curve-fitting approach is usedto determinemonomial expressions for the transconductance(119892119898) and output conductance (1198921198890) from the analyticalexpressions derived in Appendix A Monomial expressionsof transconductance (119892119898) and output conductance (1198921198890) aregiven by

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)

The geometry ranges specified for the devices for the mono-mial curve-fitting are given in Table 6(a) Additionally thebias conditions are chosen to ensure the transistors operatein the saturation regions for example 119881ds ge 119881od as shown inTable 6(a) The fitting parameters that were determined fromthe above process are listed in Table 6(b) for both the 90 nmand 180 nm CMOS processes used in this study

The accuracy of the curve fitting has been examined bycomparing the estimated transconductance (119892119898) and outputconductance (1198921198890) from the monomial expressions withcalculated values from the analytical solutions

The curve fitting results for the 90 nm process are shownin Figures 13 and 14 The coefficient of determination (1198772value) for the transconductance curve fitting is 09999indicating that the regression fits extremely well with thedata compared with the analytical solutions in (23) Themaximum relative error from curving fitting is about 256(Figure 13(a)) Furthermore 982 of the curve fitting datahas a relative error less than 10 (Figure 13(b))

The coefficient of determination for the output conduc-tance is 10 suggesting that the curve fitting is close to perfectThe accuracy of curve fitting is shown in Figure 14(a) witha maximum relative error of 097 Moreover among thiscurve fitting data 9999 of the points have a relative errorof less than 096 (Figure 14(b))

The curve fitting results are shown in Figures 15 and 16for the 180 nm process The coefficients of determination (1198772value) for these two curve fittings are very close to 1 andmorethan 97 of curve fitting data have a relative error less than10 for both cases

C Expression for the Correlation Coefficient

This appendix describes the calculation of correlation coeffi-cient 119888 following [8] Since the induced gate noise is correlatedwith the drain thermal noise the correlation coefficient isdefined as


(C1)

where 119894119899119892 sdot 119894lowast119899119889 is the spectrum of the cross-correlation of thedrain thermal noise and the induced gate noise 1198942119899119889 is thespectrum of the drain thermal noise and 1198942119899119892 is the spectrum

Table 6 (a) Ranges of devices geometry and bias conditions forcalculation of 119892119898 and 1198921198890 for 90 nm and 180 nm CMOS processes(b) Fitting parameters of monomial expressions of 119892119898 and 1198921198890 for90 nm and 180 nm CMOS processes

(a)

Parameters 90 nm 180 nm

Gate length 119871 009 120583m le 119871 le 045 120583m 018120583m le 119871 le 09 120583mGate width119882 1 120583m le 119882 le 100120583m 1 120583m le 119882 le 100120583mOverdrivevoltage 119881od

01 V le 119881od le 04V 01 V le 119881od le 05 V

Drain to sourcevoltage 119881ds

05 V le 119881ds le 10 V 06V le 119881ds le 12 V

(b)

Parameters 90 nm 180 nm1198600 00423 004631198601 minus04578 minus044891198602 05275 053111198603 04725 046891198610 00091 000961198611 minus05637 minus055951198612 05305 051941198613 04695 04806

of the induced gate noise In a long-channel device they aregiven as [8]

119894119899119892 sdot 119894lowast119899119889 = 4119896119879 sdot 19119895120596 (119862ox119882119871) sdot Δ1198911198942119899119889 = 4119896119879120574long1198921198890Δ1198911198942119899119892 = 4119896119879120573long119892119892Δ119891

(C2)

where 119892119892 is given by (8) and 119862gs = (23)119862ox119882119871 Bysubstitution of (C2) into (C1) the correlation coefficient 119888for long-channel can be calculated as

119888 = 16radic(15) 120573long sdot 120574long 119895 (C3)

Substituting 120573long and 120574long with their corresponding long-channel values of 43 and 23 yields 119888 = radic532119895 = 0395119895D Sensitivity of the 120574 and 120573 Parameters

This appendix shows the sensitivity of the 120574 and 120573 parameterson the calculation of the minimum noise figure The effectof varying the 120574 parameter is shown in Figure 17 When aplusmn10 variation is applied to 120574 a small percentage of variation(around 4) occurs to the minimum noise figure Similarlyless than 4 variation occurs on the minimum noise figurewhen aplusmn10 change is applied to120573 as illustrated in Figure 18

14 VLSI Design

0500

10001500200025003000

Cou

nts

05 1 15 2 25 30Relative error ()

(a)

Cum

ulat

ive

31 15 2 25050Relative error ()

002040608

1

dens

ity fu

nctio

n

Y 0982X 1002

(b)

Figure 13 (a) Histogram of relative error for curve fitting of 119892119898 for 90 nm (b) Cumulative density function of relative error for curve fittingof 119892119898 for 90 nm

0500

10001500200025003000

Cou

nts


(a)


Cum

ulat

ive

X 09604Y 09999

002040608

1

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)

Y 09784X 1004

002040608

1


Cum

ulat

ive

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)


002040608

1X 1001Y 0999

Cum

ulat

ive

dens

ity fu

nctio

n

(b)


130110 115 120 125 135 1401051White noise factor

04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)

Figure 17 Variation of 120574 factor on the minimum noise figure for a nominal value of 120574 = 12

VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)

Figure 18 Variation of 120573 factor on the minimum noise figure for anominal value of 120573 = 75

This gives confidence to the assumption that the parameters120574 and 120573 can be modeled as constants for the purposes ofoptimization

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] T H Lee The Design of CMOS Radio-Frequency IntegratedCircuits Cambridge University Press Cambridge UK 2ndedition 2004

[2] MHammes CKranz andD Seippel ldquoDeep submicronCMOStechnology enables system-on-chip for wireless communica-tions ICsrdquo IEEE Communications Magazine vol 46 no 9 pp154ndash161 2008

[3] A A Abidi ldquoRF CMOS comes of agerdquo IEEE MicrowaveMagazine vol 4 no 4 pp 47ndash60 2003

[4] T H Lee ldquoFrom oxymoron to mainstream the evolution andfuture of RF CMOSrdquo in Proceedings of the IEEE InternationalWorkshop on Radio-Frequency Integration Technology (RFITrsquo07) pp 1ndash6 IEEE Singapore December 2007

[5] H S Bennett R Brederlow J C Costa et al ldquoDevice andtechnology evolution for Si-based RF integrated circuitsrdquo IEEETransactions on Electron Devices vol 52 no 7 pp 1235ndash12582005

[6] P-H BonnaudMHammes AHanke et al ldquoA Fully IntegratedSoC for GSMGPRS in 013120583m CMOSrdquo in Proceedings of theIEEE International Solid-State Circuits Conference (ISSCC rsquo06)pp 1942ndash1951 IEEE San Francisco Calif USA February 2006

[7] A-J Annema B Nauta R van Langevelde and H TuinhoutldquoAnalog circuits in ultra-deep-submicron CMOSrdquo IEEE Journalof Solid-State Circuits vol 40 no 1 pp 132ndash143 2005

[8] A van der Ziel Noise in Solid State Devices and Circuits JohnWiley amp Sons New York NY USA 1986

[9] P Andreani and H Sjoland ldquoNoise optimization of an induc-tively degenerated CMOS low noise amplifierrdquo IEEE Trans-actions on Circuits and Systems II Analog and Digital SignalProcessing vol 48 no 9 pp 835ndash841 2001

[10] R A Rutenbar G G E Gielen and J Roychowdhury ldquoHier-archical modeling optimization and synthesis for system-level

analog and RF designsrdquo Proceedings of the IEEE vol 95 no 3pp 640ndash669 2007

[11] H AHausW R AtkinsonWH Fonger et al ldquoRepresentationof noise in linear twoportsrdquo Proceedings of the IRE vol 48 no1 pp 66ndash74 1960

[12] D K Shaeffer and T H Lee ldquoA 15-V 15-GHz CMOS low noiseamplifierrdquo IEEE Journal of Solid-State Circuits vol 32 no 5 pp745ndash759 1997

[13] J-S Goo H-T Ahn D J Ladwig Z Yu T H Lee and RW Dutton ldquoA noise optimization technique for integrated low-noise amplifiersrdquo IEEE Journal of Solid-State Circuits vol 37 no8 pp 994ndash1002 2002

[14] T-K Nguyen C-H Kim G-J Ihm M-S Yang and S-G LeeldquoCMOS low-noise amplifier design optimization techniquesrdquoIEEE Transactions onMicrowaveTheory and Techniques vol 52no 5 pp 1433ndash1442 2004

[15] P Vancorenland C De Ranter M Steyaert and G GielenldquoOptimal RF design using smart evolutionary algorithmsrdquo inProceedings of the 37th Design Automation Conference (DACrsquo00) pp 7ndash10 June 2000

[16] M Chu and D J Allstot ldquoElitist nondominated sorting geneticalgorithmbasedRF IC optimizerrdquo IEEETransactions onCircuitsand Systems I Regular Papers vol 52 no 3 pp 535ndash545 2005

[17] X Xia Y LiW Ying and L Chen ldquoAutomated design approachfor analog circuit using genetic algorithmrdquo in Proceedings of the7th International Conference on Computational Science (ICCSrsquo07) Beijing ChinaMay 2007 Part IV vol 4490 ofLectureNotesin Computer Science pp 1124ndash1130 Springer 2007

[18] A Somani P P Chakrabarti and A Patra ldquoAn evolutionaryalgorithm-based approach to automated design of analog andRF circuits using adaptive normalized cost functionsrdquo IEEETransactions on Evolutionary Computation vol 11 no 3 pp336ndash353 2007

[19] S Boyd S-J Kim L Vandenberghe and A Hassibi ldquoA tutorialon geometric programmingrdquo Optimization and Engineeringvol 8 no 1 pp 67ndash127 2007

[20] M D Hershenson S P Boyd and T H Lee ldquoOptimaldesign of a CMOS op-amp via geometric programmingrdquo IEEETransactions on Computer-Aided Design of Integrated Circuitsand Systems vol 20 no 1 pp 1ndash21 2001

[21] P K Meduri and S K Dhali ldquoA methodology for automatictransistor-level sizing of CMOS opampsrdquo in Proceedings of the24th International Conference on VLSI Design (VLSI Design rsquo11)pp 100ndash105 IEEE Chennai India January 2011

[22] M D M Hershenson A Hajimiri S S Mohan S P Boydand T H Lee ldquoDesign and optimization of LC oscillatorsrdquoin Proceedings of the IEEEACM International Conference onComputer-Aided Design Digest of Technical Papers pp 65ndash69IEEE ACM San Jose Calif USA November 1999

[23] S S Mohan M D M Hershenson S P Boyd and T HLee ldquoSimple accurate expressions for planar spiral inductancesrdquoIEEE Journal of Solid-State Circuits vol 34 no 10 pp 1419ndash14201999

[24] B Swahn and S Hassoun ldquoGate sizing FinFETs vs 32nmbulk MOSFETsrdquo in Proceedings of the 43rd IEEEACM DesignAutomation Conference (DAC rsquo06) pp 528ndash531 2006

[25] K Kasamsetty M Ketkar and S S Sapatnekar ldquoA new classof convex functions for delay modeling and its application tothe transistor sizing problemrdquo IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol 19 no 7 pp779ndash788 2000

16 VLSI Design

[26] W-T Cheung and N Wong ldquoOptimized RF CMOS low noiseamplifier design via geometric programmingrdquo in Proceedingsof the International Symposium on Intelligent Signal Processingand Communications (ISPACS rsquo06) pp 423ndash426 Yonago JapanDecember 2006

[27] X Jin and D H K Hoe ldquoOptimization of short channel CMOSLNAs by geometric programmingrdquo in Proceedings of the IEEE55th International Midwest Symposium on Circuits and Systems(MWSCAS rsquo12) pp 9ndash12 IEEE Boise Idaho USA August 2012

[28] F M Klaassen and J Prins ldquoThermal noise ofMOS transistorsrdquoPhilips Research Reports vol 22 pp 505ndash514 1967

[29] A J Scholten R van Langevelde L F Tiemeijer and DB M Klaassen ldquoCompact modeling of noise in CMOSrdquo inProceedings of the IEEE Custom Integrated Circuits Conference(CICC rsquo06) pp 711ndash716 San Jose Calif USA September 2006

[30] A J Scholten L F Tiemeijer R van Langevelde R J Havens AT Zegers-van Duijnhoven and V C Venezia ldquoNoise modelingfor RFCMOS circuit simulationrdquo IEEE Transactions on ElectronDevices vol 50 no 3 pp 618ndash632 2003

[31] M J Deen C-H Chen S Asgaran G A Rezvani J Taoand Y Kiyota ldquoHigh-frequency noise of modern MOSFETscompactmodeling andmeasurement issuesrdquo IEEE Transactionson Electron Devices vol 53 no 9 pp 2062ndash2081 2006

[32] B Razavi R-H Yan and K F Lee ldquoImpact of distributedgate resistance on the performance of MOS devicesrdquo IEEETransactions on Circuits and Systems I FundamentalTheory andApplications vol 41 no 11 pp 750ndash754 1994

[33] A Litwin ldquoOverlooked interfacial silicide-polysilicon gateresistance in MOS transistorsrdquo IEEE Transactions on ElectronDevices vol 48 no 9 pp 2179ndash2181 2001

[34] V M Mahajan P R Patalay R P Jindal et al ldquoA physicalunderstanding of RF noise in bulk nMOSFETs with channellengths in the nanometer regimerdquo IEEETransactions onElectronDevices vol 59 no 1 pp 197ndash205 2012

[35] J C J Paasschens A J Scholten and R van LangeveldeldquoGeneralizations of the Klaassen-Prins equation for calculatingthe noise of semiconductor devicesrdquo IEEE Transactions onElectron Devices vol 52 no 11 pp 2463ndash2472 2005

[36] K Han J Gil S-S Song et al ldquoComplete high-frequencythermal noise modeling of short-channel MOSFETs and designof 52-GHz low noise amplifierrdquo IEEE Journal of Solid-StateCircuits vol 40 no 3 pp 726ndash734 2005

[37] K Han H Shin and K Lee ldquoAnalytical drain thermal noisecurrent model valid for deep submicron MOSFETsrdquo IEEETransactions on Electron Devices vol 51 no 2 pp 261ndash2692004

[38] Y Taur and T H Ning Fundametals of Modern VLSI DevicesCambridge University Press Cambridge UK 2nd edition2009

[39] W Shockley J A Copeland and R P James ldquoThe impedancefield method of noise calculation in active semiconductordevicesrdquo in Quantum Theory of Atoms Molecules and SolidState pp 537ndash563 Academic Press New York NY USA 1966

[40] B J Sheu D L Scharfetter P-K Ko and M-C Jeng ldquoBSIMberkeley short-channel IGFET model for MOS transistorsrdquoIEEE Journal of Solid-State Circuits vol 22 no 4 pp 558ndash5661987

[41] Y Tsividis Operation and Modeling of the MOS TransistorOxfordUniversity PressNewYorkNYUSA 2nd edition 2003

[42] J Jeon J D Lee B-G Park andH Shin ldquoAn analytical channelthermal noise model for deep-submicron MOSFETs with short

channel effectsrdquo Solid-State Electronics vol 51 no 7 pp 1034ndash1038 2007

[43] J Jeon B-G Park and H Shin ldquoInvestigation of thermalnoise factor in nanoscale MOSFETsrdquo Journal of SemiconductorTechnology and Science vol 10 no 3 pp 225ndash231 2010

[44] V M Mahajan R P Jindal H Shichijo S Martin F-C HouandD Trombley ldquoNumerical investigation of excess RF channelnoise in sub-100 nm MOSFETsrdquo in Proceedings of the 2ndInternational Workshop on Electron Devices and SemiconductorTechnology (IEDST rsquo09) pp 1ndash4 Mumbai India June 2009

[45] R Navid and R Dutton ldquoThe physical phenomena responsiblefor excess noise in short-channel MOS devicesrdquo in Proceedingsof the International Conference on Simulation of SemiconductorProcesses and Devices (SISPAD rsquo02) pp 75ndash78 Kobe Japan2002

[46] J Jeon J Lee J Kim et al ldquoThe first observation of shot noisecharacteristics in 10-nm scale MOSFETsrdquo in Proceedings of theSymposium on VLSI Technology Technical Digest pp 48ndash49Honolulu Hawaii USA June 2009

[47] X Jin Optimization of short channel RF CMOS low noiseamplifiers by geometric programming [MS thesis] University ofTexas Tyler Tex USA 2012

[48] A J Scholten L F Tiemeijer R van Langevelde et alldquoCompact modelling of noise for RF CMOS circuit designrdquo IEEProceedingsmdashCircuits Devices and Systems vol 151 no 2 pp167ndash174 2004

[49] W Zhao and Y Cao ldquoNew generation of predictive technologymodel for sub-45 nm early design explorationrdquo IEEE Transac-tions on Electron Devices vol 53 no 11 pp 2816ndash2823 2006

[50] Predictive Technology Model website httpptmasuedu[51] M Grant and S Boyd ldquoCVX Matlab software for disciplined

convex programming version 121rdquo httpcvxrcomcvx[52] S Dalmia F Ayazi M Swaminathan et al ldquoDesign of induc-

tors in organic substrates for 1ndash3GHz wireless applicationsrdquoin Proceedings of the IEEE MTT-S International MicrowaveSymposium Digest vol 3 pp 1405ndash1408 June 2002

[53] K K Samanta and I D Robertson ldquoAdvanced multilayerthick-film system-on-package technology for miniaturized andhigh performance CPWmicrowave passive componentsrdquo IEEETransactions on Components Packaging and ManufacturingTechnology vol 1 no 11 pp 1695ndash1705 2011

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014


Active and Passive Electronic Components

Control Scienceand Engineering

Journal of



RotatingMachinery


Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

Acoustics and VibrationAdvances in



Electrical and Computer Engineering

Journal of

Advances inOptoElectronics


Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of


Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014


Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation



DistributedSensor Networks


2 VLSI Design

the dimensions of the CMOS transistors RF circuits willbenefit from the improved switching frequencies Howeverthe main issue will be the reduction in performance dueto increased thermal noise from MOSFETs implemented inscaled digital CMOS processes and lower gain and signalswing headroom as voltage supplies are inevitably decreasedWith reduction in the analog voltage supplies an increase inpower dissipation is required in order to maintain constantperformance [7]Hence innovations in circuit topologies andoptimizationmethodswill be required tomaintain low powerand high performance as device scaling continues deep intothe nanometer-scale dimensions

A common design methodology is to determine theminimum noise that can be obtained given constraints onimpedance matching and power dissipation Using classicaltwo-port noise theory the optimum impedance that must bepresented at the source of the LNA in order to achieve theminimumnoise figure (NF) can be calculatedAn appropriatematching network is inserted between the source and theLNA to help achieve this goal as illustrated in Figure 1 Itis well known that maximum power transfer between thesource and the amplifier input occurs when the complexconjugate of 1198851015840in matches the source impedance 119885119904 [1]Common-source (CS) amplifiers have been the most popularCMOS LNA circuit topologies due to their good low-noiseperformance and high gains However when using a CSamplifier the input impedance119885in presented by theMOSFETmakes it difficult to optimally match with the externalimpedance 119885119904 which is generally resistive in nature [8]Hence tradeoffs in terms of noise performance and gainmustbe made with this architecture

The basic amplifier architecture illustrated in Figure 2allows the noise figure to beminimized while achieving inputmatching under power constrained conditions The additionof inductive source degeneration and an input impedancematching inductive component denoted by 119871 119904 and 119871119892respectively allows improved impedance matching to beobtained over a narrow band of interest The addition of thecapacitance 119862119890 gives the added design flexibility of meetinga given power dissipation and input matching specificationwhile maintaining a very low noise performance [9] Thecascode device1198722 provides isolation with the load

Efficient and accurate optimization techniques for imple-menting analog integrated circuits are a critical facet of aCAD-based design flow This is essential when the goal is tominimize the time-to-market for a product and thus haveworking designs on first silicon [10] While the noise analysisof a linear two-port network provides some insight into howto optimize the noise figure (NF) of an amplifier [11] this clas-sical approach does not provide any guidance on the sizingof the devices Various approaches that incorporate suitableFET device characteristics and noise models into the designprocess have been developed [12ndash14] In order to accountfor second order effects in devices as scaling occurs twogeneral optimization strategies can be used simulation-basedand equation-based methods A simulation-based approachallows more general topologies and circuit parameter varia-tions to be exploredHowever there are a couple of drawbacksto this approach First as metaheuristic algorithms such as

LNA

Matchingnetwork

Load

Z998400in

s(t)

Zin

minus

+

Zs

Figure 1 Generalized block diagram of the low noise amplifier asthe key front-end component

RF input source

RF output to next stage

VDD

VDD

LoutCout

Ce

Rout

M2

M1Lg

Ls

Rs

Vs

Figure 2 Schematic of a CMOS cascode low noise amplifier withinductive source degeneration

genetic algorithms and other evolutionary techniques areoften used this approach is very computationally intensiveThis is due to the large number of iterations that requiredetailed circuit simulations to be executed [15ndash18] Secondthere is no guarantee that a globally optimum solution isfound On the other hand equation-based methods attemptto formulate a solution for amore restricted set of parametersand usually for a predetermined circuit topology Geometricprogramming methods are able to find a globally optimumsolution very efficiently for a well-formulated problem [19]The trade-off in this case is that certain approximationsmust be made to ensure that the device equations are in aform suitable for numerical optimization However once thesystem is set-up a globally optimum design can quickly befound

In this paper the focus is on the optimization of a specifictopology the CS CMOS LNA when short-channel effectssuch as excess thermal noise must be taken into consider-ation As such we will make use of convex optimization aform of geometric programming Geometric programming(GP) has been previously employed to optimize a variety ofintegrated circuit designs including both analog and digitalcircuits [20ndash25] For a comprehensive overview and list ofGP applications see [19] The approach in this paper is tooptimize the NF of the CS LNA subject to various constraints

VLSI Design 3






119868119889 = 119892 (119881 (119909)) sdot 119889119881 (119909)119889119909 (1)


ChannelOxideGate

Source Drain

Vd

Id

Vg

Vs

x

L

Vb

V(x)







119878119894119889 = 41198961198791198712119868119889 int

119881ds

01198922 (119881) sdot 119889119881 (3)


119878119894119889 = 41198961198791198712119868119889 int

119881ds

0

119879119890 (119909)119879 1198922 (119881) sdot 119889119881 (4)


119878119894119889 = 41198961198791205741198921198890 (5)


120574 = 11198920119868119889119871 int

119881ds

0

119879119890 (119909)119879 1198922 (119881) sdot 119889119881 (6)

4 VLSI Design



119878119894119892 = 4119896119879120573119892119892 (7)


119892119892 = 12059621198622gs51198921198890 (8)




(9)



119877119892 = 119877sh12 sdot 1198992119891

119882119871 (10)

Cgsgggs

+

minus

ngi




119878119894119889 = 41198961198791198712elec119868119889 int

119881ds

01198922119888 (119881) sdot 119889119881 (11)



VLSI Design 5


119868119889 = 1198920 (119881) (119889119881119889119909)1 + (119889119881119889119909) 119864119862 (12)


119878119894119889 = 41198961198791198712elec119868119889 (1 + 119881ds (119871elec119864119862))2

sdot int119881ds0

11989220 (119881) (1 + 119864119864119862) sdot 119889119881

(13)


119878119894119889 asymp 41198961198791198921198890 1 minus 119906 + 11990623

1 minus 1199062 (14)



119864 (119909) = 119864119862119881119889[(2119881od minus 119881119889)2 minus 4120572119864119862119881119889119909]12

(15)


119878119894119889 = 411989611987941198812od + 1198812119889 + 119881od11988111988931198812od (119881od minus 119881119889) 120572119868119889 (16)


Δ1198942119899 = 4119896119879119888119892acΔ119891 (17)


1198791198881198790 = (1 + 119864119864119888)119899 (18)





120574 = 119892ds1198921198890 (1 +119864119864119862) (19)



6 VLSI Design


1E minus 22

1E minus 23

1E minus 24

1E minus 250 01

Gate length (120583m)02 03 04

S i119889

(A2 H

z)





Ce

Lg

Ls

s

g d

RsCgs gs

+

minus

Zin

nR119904ng

nRout

nout

ndgmgsi i

i

i

i




noise (A2Hz)








VLSI Design 7



119877119904 1198942119899119877119904 = 4119896119879 1119877119904Δ119891 119894119899119900119877119904 = 11989211989811989521205960119862tot

119894119899119877119904119894119899119889 1198942119899119889 = 41198961198791205741198921198890Δ119891 119894119899119900119889 = minus12 119894119899119889119894119899119892 1198942119899119892 = 4119896119879120573119892119892Δ119891 119894119899119900119892 = 1198921198981198951205960119862tot

1 minus 1198951198771199041205960119862tot11989521198771199041205960119862tot119894119899119892

119877out 1198942119899119877out = 4119896119879 1119877out

Δ119891 119894119899119900119877out = 119894119899119877out


119865 = 1198942119899119900119877119904 + 1198942119899119900119889 + 1198942119899119900119892 + 1198942119899119900corr + 1198942119899119900119877out1198942119899119900119877119904

(20)



11989221198981198771199041198762 (21)









120583eff = 12058301 + 120579119881od (22)


8 VLSI Design

10 100 1000

Deen et al 2006


Gate length (nm)

00

05

10

15

20

Whi

te n

oise

fact

or120574






(2119898Vsat119871 + (2119898Vsat119871120579 + 1205830) 119881od)2


(23)


1198921198890 = 120583eff119862ox (119882119871 )119881od (24)



119892 (119909) = 11988811990911988611 11990911988622 11990911988633 sdot sdot sdot 119909119886119899119899 (25)


119891 (119909) = 119870sum119896=1

11988811989611990911988611198961 11990911988621198962 11990911988631198963 sdot sdot sdot 119909119886119899119896119899 (26)



119891119894 (119909) le 1 119894 = 1 119898119892119894 (119909) = 1 119894 = 1 119901 (27)



119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(28)




119876 = 1119877tot1205960119862tot

= 121198771199041205960119862tot

(29)

VLSI Design 9



0014 Fm2 000857 Fm2





119877119904 = 119892119898119862tot

119871 119904 = 50 ohms(30)




119862totle 1

32

119862gs

119862ox119882119871 = 1119892119898119871 119904119862tot

= 50Ω119868ds sdot 119881DD le 119875119863max

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(31)







10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

gure

(dB)

180nm ADS180nm GP

90nm ADS90nm GP





(a)

(b)


00

02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

02

04

06

08

10

Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5


0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA




VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





14 VLSI Design

0500

10001500200025003000

Cou

nts


(a)

Cum

ulat

ive


002040608

1

dens

ity fu

nctio

n

Y 0982X 1002

(b)


0500

10001500200025003000

Cou

nts


(a)


Cum

ulat

ive

X 09604Y 09999

002040608

1

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)

Y 09784X 1004

002040608

1


Cum

ulat

ive

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)


002040608

1X 1001Y 0999

Cum

ulat

ive

dens

ity fu

nctio

n

(b)



04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 3






119868119889 = 119892 (119881 (119909)) sdot 119889119881 (119909)119889119909 (1)


ChannelOxideGate

Source Drain

Vd

Id

Vg

Vs

x

L

Vb

V(x)







119878119894119889 = 41198961198791198712119868119889 int

119881ds

01198922 (119881) sdot 119889119881 (3)


119878119894119889 = 41198961198791198712119868119889 int

119881ds

0

119879119890 (119909)119879 1198922 (119881) sdot 119889119881 (4)


119878119894119889 = 41198961198791205741198921198890 (5)


120574 = 11198920119868119889119871 int

119881ds

0

119879119890 (119909)119879 1198922 (119881) sdot 119889119881 (6)

4 VLSI Design



119878119894119892 = 4119896119879120573119892119892 (7)


119892119892 = 12059621198622gs51198921198890 (8)




(9)



119877119892 = 119877sh12 sdot 1198992119891

119882119871 (10)

Cgsgggs

+

minus

ngi




119878119894119889 = 41198961198791198712elec119868119889 int

119881ds

01198922119888 (119881) sdot 119889119881 (11)



VLSI Design 5


119868119889 = 1198920 (119881) (119889119881119889119909)1 + (119889119881119889119909) 119864119862 (12)


119878119894119889 = 41198961198791198712elec119868119889 (1 + 119881ds (119871elec119864119862))2

sdot int119881ds0

11989220 (119881) (1 + 119864119864119862) sdot 119889119881

(13)


119878119894119889 asymp 41198961198791198921198890 1 minus 119906 + 11990623

1 minus 1199062 (14)



119864 (119909) = 119864119862119881119889[(2119881od minus 119881119889)2 minus 4120572119864119862119881119889119909]12

(15)


119878119894119889 = 411989611987941198812od + 1198812119889 + 119881od11988111988931198812od (119881od minus 119881119889) 120572119868119889 (16)


Δ1198942119899 = 4119896119879119888119892acΔ119891 (17)


1198791198881198790 = (1 + 119864119864119888)119899 (18)





120574 = 119892ds1198921198890 (1 +119864119864119862) (19)



6 VLSI Design


1E minus 22

1E minus 23

1E minus 24

1E minus 250 01

Gate length (120583m)02 03 04

S i119889

(A2 H

z)





Ce

Lg

Ls

s

g d

RsCgs gs

+

minus

Zin

nR119904ng

nRout

nout

ndgmgsi i

i

i

i




noise (A2Hz)








VLSI Design 7



119877119904 1198942119899119877119904 = 4119896119879 1119877119904Δ119891 119894119899119900119877119904 = 11989211989811989521205960119862tot

119894119899119877119904119894119899119889 1198942119899119889 = 41198961198791205741198921198890Δ119891 119894119899119900119889 = minus12 119894119899119889119894119899119892 1198942119899119892 = 4119896119879120573119892119892Δ119891 119894119899119900119892 = 1198921198981198951205960119862tot

1 minus 1198951198771199041205960119862tot11989521198771199041205960119862tot119894119899119892

119877out 1198942119899119877out = 4119896119879 1119877out

Δ119891 119894119899119900119877out = 119894119899119877out


119865 = 1198942119899119900119877119904 + 1198942119899119900119889 + 1198942119899119900119892 + 1198942119899119900corr + 1198942119899119900119877out1198942119899119900119877119904

(20)



11989221198981198771199041198762 (21)









120583eff = 12058301 + 120579119881od (22)


8 VLSI Design

10 100 1000

Deen et al 2006


Gate length (nm)

00

05

10

15

20

Whi

te n

oise

fact

or120574






(2119898Vsat119871 + (2119898Vsat119871120579 + 1205830) 119881od)2


(23)


1198921198890 = 120583eff119862ox (119882119871 )119881od (24)



119892 (119909) = 11988811990911988611 11990911988622 11990911988633 sdot sdot sdot 119909119886119899119899 (25)


119891 (119909) = 119870sum119896=1

11988811989611990911988611198961 11990911988621198962 11990911988631198963 sdot sdot sdot 119909119886119899119896119899 (26)



119891119894 (119909) le 1 119894 = 1 119898119892119894 (119909) = 1 119894 = 1 119901 (27)



119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(28)




119876 = 1119877tot1205960119862tot

= 121198771199041205960119862tot

(29)

VLSI Design 9



0014 Fm2 000857 Fm2





119877119904 = 119892119898119862tot

119871 119904 = 50 ohms(30)




119862totle 1

32

119862gs

119862ox119882119871 = 1119892119898119871 119904119862tot

= 50Ω119868ds sdot 119881DD le 119875119863max

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(31)







10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

gure

(dB)

180nm ADS180nm GP

90nm ADS90nm GP





(a)

(b)


00

02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

02

04

06

08

10

Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5


0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA




VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





14 VLSI Design

0500

10001500200025003000

Cou

nts


(a)

Cum

ulat

ive


002040608

1

dens

ity fu

nctio

n

Y 0982X 1002

(b)


0500

10001500200025003000

Cou

nts


(a)


Cum

ulat

ive

X 09604Y 09999

002040608

1

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)

Y 09784X 1004

002040608

1


Cum

ulat

ive

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)


002040608

1X 1001Y 0999

Cum

ulat

ive

dens

ity fu

nctio

n

(b)



04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









4 VLSI Design



119878119894119892 = 4119896119879120573119892119892 (7)


119892119892 = 12059621198622gs51198921198890 (8)




(9)



119877119892 = 119877sh12 sdot 1198992119891

119882119871 (10)

Cgsgggs

+

minus

ngi




119878119894119889 = 41198961198791198712elec119868119889 int

119881ds

01198922119888 (119881) sdot 119889119881 (11)



VLSI Design 5


119868119889 = 1198920 (119881) (119889119881119889119909)1 + (119889119881119889119909) 119864119862 (12)


119878119894119889 = 41198961198791198712elec119868119889 (1 + 119881ds (119871elec119864119862))2

sdot int119881ds0

11989220 (119881) (1 + 119864119864119862) sdot 119889119881

(13)


119878119894119889 asymp 41198961198791198921198890 1 minus 119906 + 11990623

1 minus 1199062 (14)



119864 (119909) = 119864119862119881119889[(2119881od minus 119881119889)2 minus 4120572119864119862119881119889119909]12

(15)


119878119894119889 = 411989611987941198812od + 1198812119889 + 119881od11988111988931198812od (119881od minus 119881119889) 120572119868119889 (16)


Δ1198942119899 = 4119896119879119888119892acΔ119891 (17)


1198791198881198790 = (1 + 119864119864119888)119899 (18)





120574 = 119892ds1198921198890 (1 +119864119864119862) (19)



6 VLSI Design


1E minus 22

1E minus 23

1E minus 24

1E minus 250 01

Gate length (120583m)02 03 04

S i119889

(A2 H

z)





Ce

Lg

Ls

s

g d

RsCgs gs

+

minus

Zin

nR119904ng

nRout

nout

ndgmgsi i

i

i

i




noise (A2Hz)








VLSI Design 7



119877119904 1198942119899119877119904 = 4119896119879 1119877119904Δ119891 119894119899119900119877119904 = 11989211989811989521205960119862tot

119894119899119877119904119894119899119889 1198942119899119889 = 41198961198791205741198921198890Δ119891 119894119899119900119889 = minus12 119894119899119889119894119899119892 1198942119899119892 = 4119896119879120573119892119892Δ119891 119894119899119900119892 = 1198921198981198951205960119862tot

1 minus 1198951198771199041205960119862tot11989521198771199041205960119862tot119894119899119892

119877out 1198942119899119877out = 4119896119879 1119877out

Δ119891 119894119899119900119877out = 119894119899119877out


119865 = 1198942119899119900119877119904 + 1198942119899119900119889 + 1198942119899119900119892 + 1198942119899119900corr + 1198942119899119900119877out1198942119899119900119877119904

(20)



11989221198981198771199041198762 (21)









120583eff = 12058301 + 120579119881od (22)


8 VLSI Design

10 100 1000

Deen et al 2006


Gate length (nm)

00

05

10

15

20

Whi

te n

oise

fact

or120574






(2119898Vsat119871 + (2119898Vsat119871120579 + 1205830) 119881od)2


(23)


1198921198890 = 120583eff119862ox (119882119871 )119881od (24)



119892 (119909) = 11988811990911988611 11990911988622 11990911988633 sdot sdot sdot 119909119886119899119899 (25)


119891 (119909) = 119870sum119896=1

11988811989611990911988611198961 11990911988621198962 11990911988631198963 sdot sdot sdot 119909119886119899119896119899 (26)



119891119894 (119909) le 1 119894 = 1 119898119892119894 (119909) = 1 119894 = 1 119901 (27)



119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(28)




119876 = 1119877tot1205960119862tot

= 121198771199041205960119862tot

(29)

VLSI Design 9



0014 Fm2 000857 Fm2





119877119904 = 119892119898119862tot

119871 119904 = 50 ohms(30)




119862totle 1

32

119862gs

119862ox119882119871 = 1119892119898119871 119904119862tot

= 50Ω119868ds sdot 119881DD le 119875119863max

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(31)







10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

gure

(dB)

180nm ADS180nm GP

90nm ADS90nm GP





(a)

(b)


00

02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

02

04

06

08

10

Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5


0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA




VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





14 VLSI Design

0500

10001500200025003000

Cou

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(a)

Cum

ulat

ive


002040608

1

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ity fu

nctio

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Y 0982X 1002

(b)


0500

10001500200025003000

Cou

nts


(a)


Cum

ulat

ive

X 09604Y 09999

002040608

1

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)

Y 09784X 1004

002040608

1


Cum

ulat

ive

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)


002040608

1X 1001Y 0999

Cum

ulat

ive

dens

ity fu

nctio

n

(b)



04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 5


119868119889 = 1198920 (119881) (119889119881119889119909)1 + (119889119881119889119909) 119864119862 (12)


119878119894119889 = 41198961198791198712elec119868119889 (1 + 119881ds (119871elec119864119862))2

sdot int119881ds0

11989220 (119881) (1 + 119864119864119862) sdot 119889119881

(13)


119878119894119889 asymp 41198961198791198921198890 1 minus 119906 + 11990623

1 minus 1199062 (14)



119864 (119909) = 119864119862119881119889[(2119881od minus 119881119889)2 minus 4120572119864119862119881119889119909]12

(15)


119878119894119889 = 411989611987941198812od + 1198812119889 + 119881od11988111988931198812od (119881od minus 119881119889) 120572119868119889 (16)


Δ1198942119899 = 4119896119879119888119892acΔ119891 (17)


1198791198881198790 = (1 + 119864119864119888)119899 (18)





120574 = 119892ds1198921198890 (1 +119864119864119862) (19)



6 VLSI Design


1E minus 22

1E minus 23

1E minus 24

1E minus 250 01

Gate length (120583m)02 03 04

S i119889

(A2 H

z)





Ce

Lg

Ls

s

g d

RsCgs gs

+

minus

Zin

nR119904ng

nRout

nout

ndgmgsi i

i

i

i




noise (A2Hz)








VLSI Design 7



119877119904 1198942119899119877119904 = 4119896119879 1119877119904Δ119891 119894119899119900119877119904 = 11989211989811989521205960119862tot

119894119899119877119904119894119899119889 1198942119899119889 = 41198961198791205741198921198890Δ119891 119894119899119900119889 = minus12 119894119899119889119894119899119892 1198942119899119892 = 4119896119879120573119892119892Δ119891 119894119899119900119892 = 1198921198981198951205960119862tot

1 minus 1198951198771199041205960119862tot11989521198771199041205960119862tot119894119899119892

119877out 1198942119899119877out = 4119896119879 1119877out

Δ119891 119894119899119900119877out = 119894119899119877out


119865 = 1198942119899119900119877119904 + 1198942119899119900119889 + 1198942119899119900119892 + 1198942119899119900corr + 1198942119899119900119877out1198942119899119900119877119904

(20)



11989221198981198771199041198762 (21)









120583eff = 12058301 + 120579119881od (22)


8 VLSI Design

10 100 1000

Deen et al 2006


Gate length (nm)

00

05

10

15

20

Whi

te n

oise

fact

or120574






(2119898Vsat119871 + (2119898Vsat119871120579 + 1205830) 119881od)2


(23)


1198921198890 = 120583eff119862ox (119882119871 )119881od (24)



119892 (119909) = 11988811990911988611 11990911988622 11990911988633 sdot sdot sdot 119909119886119899119899 (25)


119891 (119909) = 119870sum119896=1

11988811989611990911988611198961 11990911988621198962 11990911988631198963 sdot sdot sdot 119909119886119899119896119899 (26)



119891119894 (119909) le 1 119894 = 1 119898119892119894 (119909) = 1 119894 = 1 119901 (27)



119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(28)




119876 = 1119877tot1205960119862tot

= 121198771199041205960119862tot

(29)

VLSI Design 9



0014 Fm2 000857 Fm2





119877119904 = 119892119898119862tot

119871 119904 = 50 ohms(30)




119862totle 1

32

119862gs

119862ox119882119871 = 1119892119898119871 119904119862tot

= 50Ω119868ds sdot 119881DD le 119875119863max

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(31)







10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

gure

(dB)

180nm ADS180nm GP

90nm ADS90nm GP





(a)

(b)


00

02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

02

04

06

08

10

Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5


0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA




VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





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VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









6 VLSI Design


1E minus 22

1E minus 23

1E minus 24

1E minus 250 01

Gate length (120583m)02 03 04

S i119889

(A2 H

z)





Ce

Lg

Ls

s

g d

RsCgs gs

+

minus

Zin

nR119904ng

nRout

nout

ndgmgsi i

i

i

i




noise (A2Hz)








VLSI Design 7



119877119904 1198942119899119877119904 = 4119896119879 1119877119904Δ119891 119894119899119900119877119904 = 11989211989811989521205960119862tot

119894119899119877119904119894119899119889 1198942119899119889 = 41198961198791205741198921198890Δ119891 119894119899119900119889 = minus12 119894119899119889119894119899119892 1198942119899119892 = 4119896119879120573119892119892Δ119891 119894119899119900119892 = 1198921198981198951205960119862tot

1 minus 1198951198771199041205960119862tot11989521198771199041205960119862tot119894119899119892

119877out 1198942119899119877out = 4119896119879 1119877out

Δ119891 119894119899119900119877out = 119894119899119877out


119865 = 1198942119899119900119877119904 + 1198942119899119900119889 + 1198942119899119900119892 + 1198942119899119900corr + 1198942119899119900119877out1198942119899119900119877119904

(20)



11989221198981198771199041198762 (21)









120583eff = 12058301 + 120579119881od (22)


8 VLSI Design

10 100 1000

Deen et al 2006


Gate length (nm)

00

05

10

15

20

Whi

te n

oise

fact

or120574






(2119898Vsat119871 + (2119898Vsat119871120579 + 1205830) 119881od)2


(23)


1198921198890 = 120583eff119862ox (119882119871 )119881od (24)



119892 (119909) = 11988811990911988611 11990911988622 11990911988633 sdot sdot sdot 119909119886119899119899 (25)


119891 (119909) = 119870sum119896=1

11988811989611990911988611198961 11990911988621198962 11990911988631198963 sdot sdot sdot 119909119886119899119896119899 (26)



119891119894 (119909) le 1 119894 = 1 119898119892119894 (119909) = 1 119894 = 1 119901 (27)



119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(28)




119876 = 1119877tot1205960119862tot

= 121198771199041205960119862tot

(29)

VLSI Design 9



0014 Fm2 000857 Fm2





119877119904 = 119892119898119862tot

119871 119904 = 50 ohms(30)




119862totle 1

32

119862gs

119862ox119882119871 = 1119892119898119871 119904119862tot

= 50Ω119868ds sdot 119881DD le 119875119863max

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(31)







10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

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(dB)

180nm ADS180nm GP

90nm ADS90nm GP





(a)

(b)


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02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

02

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06

08

10

Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5


0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA




VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





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VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 7



119877119904 1198942119899119877119904 = 4119896119879 1119877119904Δ119891 119894119899119900119877119904 = 11989211989811989521205960119862tot

119894119899119877119904119894119899119889 1198942119899119889 = 41198961198791205741198921198890Δ119891 119894119899119900119889 = minus12 119894119899119889119894119899119892 1198942119899119892 = 4119896119879120573119892119892Δ119891 119894119899119900119892 = 1198921198981198951205960119862tot

1 minus 1198951198771199041205960119862tot11989521198771199041205960119862tot119894119899119892

119877out 1198942119899119877out = 4119896119879 1119877out

Δ119891 119894119899119900119877out = 119894119899119877out


119865 = 1198942119899119900119877119904 + 1198942119899119900119889 + 1198942119899119900119892 + 1198942119899119900corr + 1198942119899119900119877out1198942119899119900119877119904

(20)



11989221198981198771199041198762 (21)









120583eff = 12058301 + 120579119881od (22)


8 VLSI Design

10 100 1000

Deen et al 2006


Gate length (nm)

00

05

10

15

20

Whi

te n

oise

fact

or120574






(2119898Vsat119871 + (2119898Vsat119871120579 + 1205830) 119881od)2


(23)


1198921198890 = 120583eff119862ox (119882119871 )119881od (24)



119892 (119909) = 11988811990911988611 11990911988622 11990911988633 sdot sdot sdot 119909119886119899119899 (25)


119891 (119909) = 119870sum119896=1

11988811989611990911988611198961 11990911988621198962 11990911988631198963 sdot sdot sdot 119909119886119899119896119899 (26)



119891119894 (119909) le 1 119894 = 1 119898119892119894 (119909) = 1 119894 = 1 119901 (27)



119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(28)




119876 = 1119877tot1205960119862tot

= 121198771199041205960119862tot

(29)

VLSI Design 9



0014 Fm2 000857 Fm2





119877119904 = 119892119898119862tot

119871 119904 = 50 ohms(30)




119862totle 1

32

119862gs

119862ox119882119871 = 1119892119898119871 119904119862tot

= 50Ω119868ds sdot 119881DD le 119875119863max

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(31)







10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

gure

(dB)

180nm ADS180nm GP

90nm ADS90nm GP





(a)

(b)


00

02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

02

04

06

08

10

Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5


0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA




VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





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VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









8 VLSI Design

10 100 1000

Deen et al 2006


Gate length (nm)

00

05

10

15

20

Whi

te n

oise

fact

or120574






(2119898Vsat119871 + (2119898Vsat119871120579 + 1205830) 119881od)2


(23)


1198921198890 = 120583eff119862ox (119882119871 )119881od (24)



119892 (119909) = 11988811990911988611 11990911988622 11990911988633 sdot sdot sdot 119909119886119899119899 (25)


119891 (119909) = 119870sum119896=1

11988811989611990911988611198961 11990911988621198962 11990911988631198963 sdot sdot sdot 119909119886119899119896119899 (26)



119891119894 (119909) le 1 119894 = 1 119898119892119894 (119909) = 1 119894 = 1 119901 (27)



119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(28)




119876 = 1119877tot1205960119862tot

= 121198771199041205960119862tot

(29)

VLSI Design 9



0014 Fm2 000857 Fm2





119877119904 = 119892119898119862tot

119871 119904 = 50 ohms(30)




119862totle 1

32

119862gs

119862ox119882119871 = 1119892119898119871 119904119862tot

= 50Ω119868ds sdot 119881DD le 119875119863max

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(31)







10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

gure

(dB)

180nm ADS180nm GP

90nm ADS90nm GP





(a)

(b)


00

02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

02

04

06

08

10

Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5


0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA




VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





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04

05

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08

Min

imum

noi

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(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 9



0014 Fm2 000857 Fm2





119877119904 = 119892119898119862tot

119871 119904 = 50 ohms(30)




119862totle 1

32

119862gs

119862ox119882119871 = 1119892119898119871 119904119862tot

= 50Ω119868ds sdot 119881DD le 119875119863max

119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(31)







10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

gure

(dB)

180nm ADS180nm GP

90nm ADS90nm GP





(a)

(b)


00

02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

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Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5


0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA




VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





14 VLSI Design

0500

10001500200025003000

Cou

nts


(a)

Cum

ulat

ive


002040608

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Y 0982X 1002

(b)


0500

10001500200025003000

Cou

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(a)


Cum

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ive

X 09604Y 09999

002040608

1

dens

ity fu

nctio

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(b)


0500

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Cou

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(a)

Y 09784X 1004

002040608

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(a)


002040608

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dens

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(b)



04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









10 VLSI Design

20 40 60 80 100 1200Width (120583m)

00

04

08

12

16

20

Noi

se fi

gure

(dB)

180nm ADS180nm GP

90nm ADS90nm GP





(a)

(b)


00

02

04

06

08

10

12

Min

imum

noi

se fi

gure

(dB)

00

02

04

06

08

10

Opt

imal

wid

th (m

)

Y 1003X 2

Y 6746

X 8

Y 7462X 2

Y 0392

X 8

times10minus4

E minus 6

E minus 5


0 20 40 60 80 100 120

01 2 3 4 5 6 7 8 9 10

0

12345

Quality factor

Noi

se fi

gure

(dB)

Width (120583m)

05mA

1mA2mA

5mA




VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





14 VLSI Design

0500

10001500200025003000

Cou

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(a)

Cum

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002040608

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Y 0982X 1002

(b)


0500

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Cou

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(a)


Cum

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X 09604Y 09999

002040608

1

dens

ity fu

nctio

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(b)


0500

10001500200025003000

Cou

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(a)

Y 09784X 1004

002040608

1


Cum

ulat

ive

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

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(a)


002040608

1X 1001Y 0999

Cum

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dens

ity fu

nctio

n

(b)



04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 11

3GHz24GHz18GHz

20 40 60 80 100 1200Width (120583m)

0

05

10

15

20

25

30

35

40

Noi

se fi

gure

(dB)


0 20 40 60 80 100 120


012345

Noi

se fi

gure

(dB)







Appendices





21198812ds) 119868119889sat = 1

21205830119862ox119882119871 1198812od

(A1)

12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





14 VLSI Design

0500

10001500200025003000

Cou

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(a)

Cum

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002040608

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Y 0982X 1002

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(a)


Cum

ulat

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X 09604Y 09999

002040608

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dens

ity fu

nctio

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(b)


0500

10001500200025003000

Cou

nts


(a)

Y 09784X 1004

002040608

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Cum

ulat

ive

dens

ity fu

nctio

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(b)


0500

10001500200025003000

Cou

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(a)


002040608

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dens

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nctio

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(b)



04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









12 VLSI Design


119892119889 = 120597119868119889triode120597119881ds10038161003816100381610038161003816100381610038161003816119881gs = 1205830119862ox

119882119871 (119881od minus 119881ds) (A2)




119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds





2ds

1 + (120583eff119881ds) (2Vsat119871) 119868119889sat


sdot (1 + 120582119881ds)

(A5)

where [38 41]

120583eff = 12058301 + 120579 (119881gs minus 119881th) (A6)

120579 = 120573120579119905ox (A7)

119898 = 1 + radic120576119904119894119902119873ch (4Ψ119861)119862ox

(A8)

Ψ119861 = (119896119879119902 ) ln(119873ch119899119894 ) (A9)



2ds) sdot (120583eff (2Vsat119871))

(1 + 120583eff119881ds (2Vsat119871))2


(A10)


1198921198890 = 1198921198891003816100381610038161003816119881ds=0 = 12058301 + 120579119881od119862ox119882119871 119881od (A11)




(A12)


119892119898 = 120597119868119889sat120597119881gs1003816100381610038161003816100381610038161003816100381610038161003816119881ds

= 119862ox1205830 (119882119871 ) 12119898 (1 + 120582119881ds)

sdot [ 1198812od(1 + 120579119881od + (12058302119898Vsat119871)119881od)]1015840


(A13)

VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





14 VLSI Design

0500

10001500200025003000

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nts


(a)

Cum

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002040608

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0500

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(a)


Cum

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X 09604Y 09999

002040608

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dens

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nctio

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(b)


0500

10001500200025003000

Cou

nts


(a)

Y 09784X 1004

002040608

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Cum

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ive

dens

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nctio

n

(b)


0500

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(a)


002040608

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dens

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nctio

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(b)



04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 13


119892119898 = 1198600119871119860111988211986021198681198603ds 1198921198890 = 1198610119871119861111988211986121198681198613ds

(B1)









(C1)



(a)






(b)




(C2)





14 VLSI Design

0500

10001500200025003000

Cou

nts


(a)

Cum

ulat

ive


002040608

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dens

ity fu

nctio

n

Y 0982X 1002

(b)


0500

10001500200025003000

Cou

nts


(a)


Cum

ulat

ive

X 09604Y 09999

002040608

1

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)

Y 09784X 1004

002040608

1


Cum

ulat

ive

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

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nts


(a)


002040608

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dens

ity fu

nctio

n

(b)



04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









14 VLSI Design

0500

10001500200025003000

Cou

nts


(a)

Cum

ulat

ive


002040608

1

dens

ity fu

nctio

n

Y 0982X 1002

(b)


0500

10001500200025003000

Cou

nts


(a)


Cum

ulat

ive

X 09604Y 09999

002040608

1

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)

Y 09784X 1004

002040608

1


Cum

ulat

ive

dens

ity fu

nctio

n

(b)


0500

10001500200025003000

Cou

nts


(a)


002040608

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ulat

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dens

ity fu

nctio

n

(b)



04

05

06

07

08

Min

imum

noi

se fi

gure

(dB)


VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 15

800700 725 750 775 825 85067565120573 factor

12

13

14

15

16

Min

imum

noi

se fi

gure

(dB)





References



























16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









16 VLSI Design
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









research article the design of low noise amplifiers in

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