research article implementation, test pattern generation, and comparative analysis...

Research ArticleImplementation Test Pattern Generation andComparative Analysis of Different Adder Circuits

Vikas K Saini Shamim Akhter and Tanuj Chauhan

Jaypee Institute of Information Technology Noida 201307 India

Correspondence should be addressed to Shamim Akhter shamimakhterjiitacin

Received 30 December 2015 Revised 14 March 2016 Accepted 6 April 2016

Academic Editor Chang-Ho Lee

Copyright copy 2016 Vikas K Saini et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

Addition usually affects the overall performance of digital systems and an arithmetic function Adders are most widely used inapplications likemultipliers DSP (ie FFT FIR and IIR) In digital adders the speed of addition is constrained by the time requiredto propagate a carry through the adder Various techniques have been proposed to design fast addersWe have derived architecturesfor carry-select adder (CSA) CommonBoolean Logic (CBL) based adders ripple carry adder (RCA) andCarry Look-AheadAdder(CLA) for 8- 16- 32- and 64-bit length In this work we have done comparative analysis of different types of adders in SynopsisDesign Compiler using different standard cell libraries at 3228 nm Also the designs are analyzed for the stuck at faults (s-a-0s-a-1) using Synopsis TetraMAX

1 Introduction

In any processing unit adders are basic building block Welook for an area and power efficient fast adders to increasesystem performance [1 2] Ripple carry adders (RCA) [3] arearea and power efficient but with drawback of being slowCarry-select adders (CSA) [2 4ndash10] are one of the fastestadders among traditional adders but they are not power andarea efficient Common Boolean Logic (CBL) [7] adders arearea-power-delay efficient adders Carry Look-Ahead Adder(CLA) [11] is among the fastest adders with area overhead

The organization of this paper is as follows Section 2deals with the analysis of adder using different topologiesSection 3 presents logic for CBL adder design Section 4 dealswith comparative analysis based on delay area and poweramong different adder architectures using Synopsis DesignCompiler The fault testing concept (s-a-0 s-a-1) for variousadders is also discussed Section 5 gives the conclusionfollowed by the references

2 Different Topologies for Adder

In this section we have discussed in brief the differentarchitectures of adder namely ripple carry adder (RCA)

Carry Look-Ahead Adder (CLA) CSA SQRT-CSA andCommon Boolean Logic (CBL) adder

21 Ripple CarryAdder (RCA) It is basic parallel adderwherea chain of adders is cascaded with carry rippled from onestage to another Block diagram for 4-bit RCA is shownin Figure 1(a) Delay is due to the rippling of carry sincethe consequent blocks of adder have to wait for the carrygenerated from the previous adder Delay of119873-bit RCA adderis

119879RCA = 119879set-up + (119873 minus 1) 119879gate + 119879sum (1)

where 119879set-up is input setup time (for generating XOR andAND of basic inputs) 119879gate is the delay of two gates that isAND gate and OR gates and 119879sum is the delay of the XORgate

A 64-bit RCA is shown in Figure 1(b)There are 16 blocksand each block is a 4-bit RCA Each block has 4 full addersexcept the first block which has 3 full adders and 1 half adderas the lowest bit of addends can be added using the half adderinstead of a full adder

Hindawi Publishing CorporationVLSI DesignVolume 2016 Article ID 1260879 8 pageshttpdxdoiorg10115520161260879

2 VLSI Design

A0 A1

A2 A3

B0 B1

B2 B3

C0

C4

C1

C1C2

C2

C3

C3

S0 S1

S2 S3

(a)

HA FA FA FA

4-bit RCA 4b

RCA

4b

RCA

4b

RCA

4b

RCA

4b

RCA

4b

RCA

4b

RCA

4b RCA

4b RCA

4b RCA

4b RCA

4b RCA

4b RCA

4b RCA

4b RCA

(b)

Figure 1 (a) Block diagram for 4-bit RCA (b) Block diagram for 64-bit RCA

22 Carry Look-Ahead Adder (CLA) CLA use the concept ofgenerating carry and propagating carry We know that

119862119894+1= 119909119894119910119894+ 119909119894119862119894+ 119910119894119862119894= 119909119894119910119894+ (119909119894+ 119910119894) 119862119894 (2)

119892119894= 119909119894119910119894is generating function which generates the carry

regardless of the value of 119862119894and 119901

119894= (119909119894+ 119910119894) is propagating

function Carry propagates if either of 119909119894or 119910119894is 1

119862119894+1= 119892119894+ 119901119894119862119894= 119892119894+ 119901119894(119892119894minus1+ 119901119894minus1119862119894minus1)

= 119892119894+ 119901119894119892119894minus1+ 119901119894119901119894minus1119862119894minus1

= 119892119894+ 119901119894119892119894minus1+ 119901119894119901119894minus1(119892119894minus2+ 119901119894minus2119862119894minus2)

= 119892119894+ 119901119894119892119894minus1+ 119901119894119901119894minus1119892119894minus2+ 119901119894119901119894minus1119901119894minus2119862119894minus2

(3)

On simplifying we have

119862119894+1= 119892119894+ 119901119894119892119894minus1+ 119901119894119901119894minus1119892119894minus2+ sdot sdot sdot

+ 119901119894119901119894minus1119901119894minus2sdot sdot sdot 1199012119901111990101198921


(4)

Expressions shown above are implemented using a two-level AND-OR circuit so that 119862

119894+1can be evaluated very

quickly Due to independent computation of carry the CLAbased adder is fast as compared to RCA but at a cost ofincreased hardware Block diagram for 4-bit CLA is shownin Figure 2(a)

Since circuit of CLAAdder for higher order bit is complexto implement directly we have realized it by cascading 4-bitCLA blocks Figure 2(b) shows 64-bit adder based on CLAblocks There are 16 blocks Each block is of 4 bits and hascircuit as shown in Figure 2(a)The carry generated from anyblock is rippled to its successor blockThis is not a pure 64-bitadder It has been implemented just for study purpose

23 Carry-Select Adder (CSA) The carry-select adder con-sists of two ripple carry adders and a set of multiplexersThe block diagram for 4-bit addition using CSA is given inFigure 3(a) For adding two 4-bit numbers using CSA werequire two 4-bit full adders and that can be ripple carryadder (RCA) or Carry Look-Ahead Adder (CLA) 1st stagecomputes the 4-bit addition using 119862in = 0 and 2nd stagecomputes the same with 119862in = 1 After the two results areavailable the correct sum and carry-out are then decidedby the multiplexer once the correct carry is known [4] Fordesigning 64-bit adder we can cascade the structure shownin Figure 3(a) It means we need 16 stages of CSA to create64-bit CSA adder The number of bits in each CSA block isuniform

Figure 3(b) shows block diagram of 64-bit CSAThere are2 blocks each having 8 blocks consisting of 4-bit RCA Allblocks other than RCA0 are in pair whose119862in is connected tologic 0 or 1 which acts as 119862in and the results of whom blockis to be considered depend upon the carry propagating fromthe previous blockwhich is controlled by theMUXwhich canbe seen after every pair of blocks (smaller) Depending uponthe carry the sum is also considered to be taken The bunchof MUX can be seen at the end of both blocks these controlthe sumThe RCA block can be of any bit not necessarily of 4bits and the number of adders in each RCA block controlsthe speed and power dissipation The more the number ofmultiplexers in the circuit the more the area and powerdissipation

A CLA-CSA can be designed in the same fashion Theonly difference will be that the RCA block will be replacedby the CLA blocks The block diagram of 64-bit CLA-CSA isshown in Figure 3(c)

24 Square-Root Carry-Select Adder (SQRT-CSA) A 16-bitCSA with variable size is created by cascading four CSA withvariable input sizeThe block diagram for the same is given in

VLSI Design 3

Carry Look-Ahead Logic

PFAS G P C

PFAS G P C

PFAS G P C

PFAS G P C

AB S

P

G

C Partial full adderA0A1A2A3 B0B1B2B3

C0C1C2C3

C4

S0S1S2S3

G0G1G2G3 P0P1P2P3

(a)

CLA

0

CLA

1

CLA

2

CLA

3

CLA

4

CLA

5

CLA

6

CLA

7

CLA

8

CLA

9

CLA

10

CLA

11

CLA

12

CLA

13

CLA

14

CLA

15

(b)

Figure 2 (a) Block diagram for 4-bit CLA (b) Block diagram for 64-bit CLA based adder

A0A1A2A3 B0B1B2B3

Cin

Cin

Cin

Cout

S0S1S2S3

(0)

(1)

FAFAFAFA

FA FA FA FA

(a)

RCA1 with Cin = 0

RCA1 with Cin = 1

MUX MUX

MU

X

RCA0

RCA2

RCA3

RCA4

RCA5

RCA6

7

RCA8

RCA9

RCA10

RCA11

RCA12

RCA13

RCA14

15

(b)

CLA0

CLA

1CL

A2

CLA

3CL

A4

CLA

5CL

A6

CLA

7CL

A8

CLA

9CL

A10

CLA

11CL

A12

CLA

13CL

A14

CLA

15

MUX

MU

X

4b CLA Cin = 0

4b CLA Cin = 1

(c)

Figure 3 (a) Block diagram for 4-bit CSA (b) Block diagram for 64-bit RCA-CSA (c) Block diagram for 64-bit CLA-CSA

Figure 4(a) We have five stages of CSA with different inputsbits to each stage We have an adder with block sizes of 2 2 34 and 5 respectively In the modified SQRT-CSA the blockof CSA with 119862in = 1 is replaced with BEC (Binary to ExcessConverter) [5]

Figure 4(b) shows the block diagram of 64-bit SQRT-CSA We have an adder with block sizes of 2 3 4 5 6 7 8 910 and 10 respectively

Another interesting adder is based on CBL It is explainedin Section 3 in detail

3 Common Boolean Logic Adders

Table 1 shows the output pattern of 1-bit full adder From thetable we conclude that if the carry propagating from previousadders is ldquo0rdquo the current sum (119878) and the carry-out bit (119862)

4 VLSI Design

Cin = 0Cin = 0Cin = 0Cin = 0

Cin = 1 Cin = 1 Cin = 1 Cin = 1

A[1511]B[1511] A[107]B[107] A[64]B[64] A[32]B[32] A[10] B[10]

SUM[1511] SUM[107] SUM[64] SUM[32] SUM[10]

1511 RCA 107 RCA 64 RCA 32 RCA


10 RCA

MUX 126 MUX 106 MUX 84 MUX 63

Cin

Cout

C10 C6 C3 C1

(a)

RCA block with Cin = 0

RCA blockwith Cin = 1

2b RCA

3b

RCA

4b

RCA

5b

RCA

6b

RCA

7b

RCA

8b

RCA

9b

RCA

10b

RCA

10b

RCA

MUX MUX

(b)

Figure 4 (a) Block diagram for 16-bit SQRT-CSA [5] (b) Block diagram for 64-bit SQRT-CSA

Table 1 Design requirement for the design of full adder

119862in A B S C0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

are the XOR and AND of the two input bits respectively Onthe other hand if the carry propagating from previous adder

is ldquo1rdquo the current sum (119878) bit is the XNOR and the carry-outbit (119862) is OR of the two input bits respectively Hence

119878 = (119860 oplus 119861)1198621015840

in + (119860 ⊙ 119861)119862in

119862 = (119860119861)1198621015840

in + (119860 + 119861)119862in(5)

The implementation of the CBL based adder is shown inFigure 5(a)

From Figure 5(a) it can be seen that MUX decidesthe final sum depending upon the carry propagating fromprevious logic cellThe carry which will propagate will decidethe final sum and the carry for the next logic cell If the carrypropagating fromprevious adder (119862

0) is ldquo0rdquo then the sum (119878

0)

will be 11987810 otherwise 119878

0would be 119878

11 Similarly if C

0is ldquo0rdquo

then carry which will propagate to next cell would be 11986210

otherwise propagating carry would be 11986211

VLSI Design 5

A1 A2 AnB1 B2 Bn

C1C0

C0SnS1 S2

0 0

000

1 1

111

middot middot middotC10C11

C20C21

Cnminus1

S10 S11 S20 S21 Sn0 Sn1

MU

X

MU

X

MUXMUX MUX

(a)

CBL0

B4B2 B3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

(b)

Figure 5 (a) Common Boolean Logic based adder (b) 64-bit Common Boolean Logic based adder

Delay of119873-bit CBL adder is

119879CBL = 119879set-up + (119873 minus 1) 119879mux + 119879sum (6)

where 119879set-up is as defined earlier 119879mux is the delay of a 2 times 1MUX and 119879sum is the delay of the XOR gate

Figure 5(b) shows the block diagram of 64-bit CommonBoolean Logic based adder There are 4 blocks having 16blocks each which means 64 blocks of Common BooleanLogic

4 Comparative Analysis ofDifferent Adder Architecture

In this section we have presented the comparison of delaypower and area of various adders using 3228 nm digitalstandard cell library using Synopsis Design Compiler

41 Design Compiler Design Compiler is developed bySynopsis Important aspects of any digital circuit like areapower delay and so forth can be calculated by DesignCompiler just providing the HDL code of the design anddigital standard cells library of the technology on which youwant to work Different standard cells libraries are providedby the Synopsis for the educational purpose The librariesare in three formats db lib and v In Design Compiler weneed db format lib format is readable format of the dbformat

42 Area-Delay Estimation of Basic Circuit Using DesignCompiler We have considered 2 input AND OR and XORgates The area delay Dynamic Power Dissipation andleakage are given in Table 2 Leakage power is considered for119881dd = 105VDC at room temperature as per the data sheetOperating frequency is 500MHz

For the understanding purpose we are analyzing a simplecircuit of full adder as shown in Figure 6 The critical pathof the full adder is highlighted in the figure It should be thedouble of the XOR gate that is 16 ns which is exactly thesame as the propagation delay as per the Design Compiler

The area of the circuit should be the area of the 2 XORgates (ie 8640896 120583m2) 2 AND gates (ie 4066308 120583m2)one OR gate (ie 2033152120583m2) and the area of the nets

Table 2 Area delay and dynamic and leakage power of SAED3228HVT digital standard cell libraries

Parameters AND OR XORArea (120583m2) 2033154 2033152 4320448Delay (ns) 01 006 008Leakage (nW) 297 393 344Dynamic (nWMHz) 3 4 2

Xi

Ci

Yi Si

Ci+1

Figure 6 Full adder

(ie 1070661 120583m2) which is equal to 15811017 120583m2 The areacalculated by Design Compiler is 15811013120583m2 which isapproximately the same

We have computed the area power or delay for thedifferent adder circuitWe have developedHDL code for eachaddermodule for different input bit length Figures 7 8 and 9show the delay for the various adders for 3228 nm technologyfor HVT (High Voltage Threshold) RVT (Regular VoltageThreshold) and LVT (Low Voltage Threshold) respectivelyfor different adder architecture for 8-bit 16-bit 32-bit and64-bit adder RVT is equivalent to standard Voltage Thresh-old Units are in nanoseconds EDK libraries for 32 and 28 nmtechnology are the same as provided by the Synopsis

Figures 10 11 and 12 show the Dynamic Power Dissi-pation for 3228 nm technology for HVT RVT and LVTrespectively Units are in microwatt Figure 13 shows siliconarea required to design hardware for various adders ofdifferent length Units are in square micrometer

Figure 14 shows leakage power dissipation for differentadder architecture for 8-bit 16-bit 32-bit and 64-bit addersUnits are in microwatt

6 VLSI Design

8 16 32 64

RCA 063 125 25 502CLA 072 144 286 572RCA-CSA 044 064 104 183SQRT-CSA 045 065 09 137CLA-CSA 046 065 105 186CSA-CBL 064 122 244 488

0

1

2

3

4

5

6

7D

elay

(ns)

(Bit)

Figure 7 Delay of various adders for HVT


005

115

225

335

4

8 16 32 64

Del

ay (n

s)

(Bit)

Figure 8 Delay of various adders for LVT


005

115

225

335

445

8 16 32 64

Del

ay (n

s)

(Bit)

Figure 9 Delay of various adders for RVT


0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)

Figure 10 Dynamic Power Dissipation of various adders for HVT


0102030405060

Pow

er (120583

W)

8 16 32 64(Bit)

Figure 11 Dynamic Power Dissipation of various adders for LVT


0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)

Figure 12 Dynamic Power Dissipation of various adders for RVT

VLSI Design 7


0

500

1000

1500

2000

2500

8 16(Bit)

32 64

Are

a(120583

m2)

Figure 13 Area of various adders


0

10

20

30

40

50

60

Leak

age p

ower

(120583W

)

8 16 32 64(Bit)

Figure 14 Leakage power of various adders

43 Required Test Patterns to Test Various Adder Circuits Inthe analysis of digital circuits testing plays a very importantrole [12] In the traditional testing we used to apply all theinput and check the output corresponding to the appliedinputs If all the results used to be fine then we used to declarethe hardware good only As the size of the digital designincreases the number of the input patterns increases Thendifferent methods were introduced to minimize the numberof the input test patterns Some of the methods like ATPGare discussed in [12] to save the time As in the environmentof such huge competition where the manufacture wants tolaunch the product as soon as possible it requires lessernumber of input test patterns The hardware which will needlesser input test patterns to test will be better as per the testingpoint of view

Similarly to find the stuck at faults we need some inputpatterns We apply those patterns to the input of the designand check the output If all the outputs corresponding to allthe inputs are correctwe can say that the hardware is free fromstuck at faults


050

100150200250300350

Num

ber o

f pat

tern

s

8 16 32 64(Bit)

Figure 15 Minimum numbers of patterns

TetraMAX is used to generate pattern using ATPG fordifferent circuits With TetraMAX designers can generatehigh-quality manufacturing test patterns without compro-mising on high performance design techniques While suchtechniques may impede other ATPG tools TetraMAX is ableto obtain coverage on the resulting complex logic Inputtest patterns using ATPG for different digital circuits aregenerated by TetraMAX and details are given in Figure 15These patterns can be used to test the circuit for various stuckat faults after manufacturing

Figure 15 shows number of input test patterns required totest various adders for 8 16 32 and 64 bits For example for 8-bit RCA we will need only 6 patterns to declare the hardwaregood while there can be total of 65536 input patters to addtwo 8-bit values

5 Conclusion

A comparative analysis of various digital adders has beenperformed in this paper The parameters of comparison weredelay area and power (dynamic and leakage) using digitalstandard cell library Test generation analysis on the adderswas also performed

With Respect to Delay For 8-bit adders RCA-CSA is approx-imately 3 faster than SQRT-CSA and CLA-CSA 42 fasterthan RCA and CSA-CBL and 60 faster than CLA

For 16-bit adders RCA-CSA is approximately 2 fasterthan SQRT-CSA and CLA-CSA 90 faster than CSA-CBLand RCA and 125 faster than CLA

For 32-bit adders SQRT-CSA is approximately 14 fasterthan RCA-CSA and CLA-CSA 170 faster than CSA-CBLand RCA and 210 faster than CLA


Adders with LVT cells are 20 and 60 slower than withRVT and HVT cells respectively

8 VLSI Design

With Respect to Power Dissipation CLA consumes powerapproximately 35 lesser than RCA 40 lesser than CSA-CBL 50 lesser than CLA-CSA and 70 lesser than SQRT-CSA and RCA-CSA

Adders with HVT cells are 15 and 2 lesser than withRVT and LVT cells respectively

With Respect to Area CLA require area approximately 15lesser than RCA 30 lesser than CSA-CBL 50 lesser thanCLA-CSA and 60 lesser than RCA-CSA and SQRT-CSA

With Respect to Leakage Power CLA have leakage powerapproximately 15 lesser than RCA 30 lesser than CSA-CBL 50 lesser than CLA-CSA and 60 lesser than RCA-CSA and SQRT-CSA

Considering the number of input test patterns requiredto test the adder CLA RCA and CSA-CBL architecture arefar better than CSA Also among non-CSA architectures CLAis the best and CSA-CBL is the worst while among CSAarchitectures CLA-CSA is better than RCA-CSA and SQRT-CSA

So depending upon the requirements we can choose theadder accordingly

Similar analysis can also be performed on other variousadders for different standard digital libraries that is 360 nmand 90 nm

Competing Interests

The authors declare that they have no competing interests

References

[1] S Akhter ldquoVHDL implementation of fast NxNmultiplier basedon vedic mathematicrdquo in Proceedings of the 18th EuropeanConference on CircuitTheory and Design (ECCTD rsquo07) pp 472ndash475 Seville Spain August 2007

[2] Y He C-H Chang and J Gu ldquoAn area efficient 64-bitsquare root carry-select adder for low power applicationsrdquo inProceedings of the IEEE International Symposium onCircuits andSystems (ISCAS rsquo05) vol 4 pp 4082ndash4085 May 2005

[3] N H E Weste D Harris and A Banerjee CMOS VLSI DesignA Circuits and Systems Perspective Pearson Education 3rdedition 2005

[4] B K Mohanty and S K Patel ldquoArea-delay-power efficientcarry-select adderrdquo IEEE Transactions on Circuits and SystemsII Express Briefs vol 61 no 6 pp 418ndash422 2014

[5] O J Bedrij ldquoCarry-select adderrdquo IRE Transactions on ElectronicComputers vol 11 no 3 pp 340ndash346 1962

[6] S Akhter S Chaturvedi and K Pardhasardi ldquoCMOS imple-mentation of efficient 16-Bit square root carry-select adderrdquoin Proceedings of the 2nd International Conference on SignalProcessing and Integrated Networks (SPIN rsquo15) pp 891ndash896Noida India February 2015

[7] B Ramkumar and H M Kittur ldquoLow-power and area-efficientcarry select adderrdquo IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems vol 20 no 2 pp 371ndash375 2012

[8] G Singh ldquoDesign of low area and low power modified 32-BIT square root carry select adderrdquo International Journal of

Engineering Research and General Science vol 2 no 4 pp 422ndash431 2014

[9] I-CWey C-C Ho Y-S Lin and C-C Peng ldquoAn area-efficientcarry select adder design by sharing the common boolean logictermrdquo in Proceedings of the International MultiConference ofEngineers and Computer Scientists (IMECS rsquo12) pp 1091ndash1094Hong Kong March 2012

[10] V Kokilavani K Preethi and P Balasubramanian ldquoFPGA-based synthesis of high-speed hybrid carry select addersrdquoAdvances in Electronics vol 2015 Article ID 713843 13 pages2015

[11] D Yagain V Krishna A and A Baliga ldquoDesign of high-speedadders for efficient digital design blocksrdquo ISRN Electronics vol2012 Article ID 253742 9 pages 2012

[12] M L Bushnell and V D Agrawal Essential of Electronic Testingfor Digital Memory and Mixed-Signal VLSI Circuits KluwerAcademic Publishers 2000

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Submit your manuscripts athttpwwwhindawicom

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Navigation and Observation



DistributedSensor Networks


2 VLSI Design

A0 A1

A2 A3

B0 B1

B2 B3

C0

C4

C1

C1C2

C2

C3

C3

S0 S1

S2 S3

(a)

HA FA FA FA

4-bit RCA 4b

RCA

4b

RCA

4b

RCA

4b

RCA

4b

RCA

4b

RCA

4b

RCA

4b RCA

4b RCA

4b RCA

4b RCA

4b RCA

4b RCA

4b RCA

4b RCA

(b)

Figure 1 (a) Block diagram for 4-bit RCA (b) Block diagram for 64-bit RCA

22 Carry Look-Ahead Adder (CLA) CLA use the concept ofgenerating carry and propagating carry We know that

119862119894+1= 119909119894119910119894+ 119909119894119862119894+ 119910119894119862119894= 119909119894119910119894+ (119909119894+ 119910119894) 119862119894 (2)

119892119894= 119909119894119910119894is generating function which generates the carry

regardless of the value of 119862119894and 119901

119894= (119909119894+ 119910119894) is propagating

function Carry propagates if either of 119909119894or 119910119894is 1

119862119894+1= 119892119894+ 119901119894119862119894= 119892119894+ 119901119894(119892119894minus1+ 119901119894minus1119862119894minus1)

= 119892119894+ 119901119894119892119894minus1+ 119901119894119901119894minus1119862119894minus1

= 119892119894+ 119901119894119892119894minus1+ 119901119894119901119894minus1(119892119894minus2+ 119901119894minus2119862119894minus2)

= 119892119894+ 119901119894119892119894minus1+ 119901119894119901119894minus1119892119894minus2+ 119901119894119901119894minus1119901119894minus2119862119894minus2

(3)

On simplifying we have

119862119894+1= 119892119894+ 119901119894119892119894minus1+ 119901119894119901119894minus1119892119894minus2+ sdot sdot sdot



(4)

Expressions shown above are implemented using a two-level AND-OR circuit so that 119862

119894+1can be evaluated very

quickly Due to independent computation of carry the CLAbased adder is fast as compared to RCA but at a cost ofincreased hardware Block diagram for 4-bit CLA is shownin Figure 2(a)

Since circuit of CLAAdder for higher order bit is complexto implement directly we have realized it by cascading 4-bitCLA blocks Figure 2(b) shows 64-bit adder based on CLAblocks There are 16 blocks Each block is of 4 bits and hascircuit as shown in Figure 2(a)The carry generated from anyblock is rippled to its successor blockThis is not a pure 64-bitadder It has been implemented just for study purpose

23 Carry-Select Adder (CSA) The carry-select adder con-sists of two ripple carry adders and a set of multiplexersThe block diagram for 4-bit addition using CSA is given inFigure 3(a) For adding two 4-bit numbers using CSA werequire two 4-bit full adders and that can be ripple carryadder (RCA) or Carry Look-Ahead Adder (CLA) 1st stagecomputes the 4-bit addition using 119862in = 0 and 2nd stagecomputes the same with 119862in = 1 After the two results areavailable the correct sum and carry-out are then decidedby the multiplexer once the correct carry is known [4] Fordesigning 64-bit adder we can cascade the structure shownin Figure 3(a) It means we need 16 stages of CSA to create64-bit CSA adder The number of bits in each CSA block isuniform

Figure 3(b) shows block diagram of 64-bit CSAThere are2 blocks each having 8 blocks consisting of 4-bit RCA Allblocks other than RCA0 are in pair whose119862in is connected tologic 0 or 1 which acts as 119862in and the results of whom blockis to be considered depend upon the carry propagating fromthe previous blockwhich is controlled by theMUXwhich canbe seen after every pair of blocks (smaller) Depending uponthe carry the sum is also considered to be taken The bunchof MUX can be seen at the end of both blocks these controlthe sumThe RCA block can be of any bit not necessarily of 4bits and the number of adders in each RCA block controlsthe speed and power dissipation The more the number ofmultiplexers in the circuit the more the area and powerdissipation

A CLA-CSA can be designed in the same fashion Theonly difference will be that the RCA block will be replacedby the CLA blocks The block diagram of 64-bit CLA-CSA isshown in Figure 3(c)

24 Square-Root Carry-Select Adder (SQRT-CSA) A 16-bitCSA with variable size is created by cascading four CSA withvariable input sizeThe block diagram for the same is given in

VLSI Design 3


PFAS G P C

PFAS G P C

PFAS G P C

PFAS G P C

AB S

P

G


C0C1C2C3

C4

S0S1S2S3

G0G1G2G3 P0P1P2P3

(a)

CLA

0

CLA

1

CLA

2

CLA

3

CLA

4

CLA

5

CLA

6

CLA

7

CLA

8

CLA

9

CLA

10

CLA

11

CLA

12

CLA

13

CLA

14

CLA

15

(b)


A0A1A2A3 B0B1B2B3

Cin

Cin

Cin

Cout

S0S1S2S3

(0)

(1)

FAFAFAFA

FA FA FA FA

(a)

RCA1 with Cin = 0

RCA1 with Cin = 1

MUX MUX

MU

X

RCA0

RCA2

RCA3

RCA4

RCA5

RCA6

7

RCA8

RCA9

RCA10

RCA11

RCA12

RCA13

RCA14

15

(b)

CLA0

CLA

1CL

A2

CLA

3CL

A4

CLA

5CL

A6

CLA

7CL

A8

CLA

9CL

A10

CLA

11CL

A12

CLA

13CL

A14

CLA

15

MUX

MU

X

4b CLA Cin = 0

4b CLA Cin = 1

(c)







4 VLSI Design


Cin = 1 Cin = 1 Cin = 1 Cin = 1

A[1511]B[1511] A[107]B[107] A[64]B[64] A[32]B[32] A[10] B[10]




10 RCA


Cin

Cout

C10 C6 C3 C1

(a)



2b RCA

3b

RCA

4b

RCA

5b

RCA

6b

RCA

7b

RCA

8b

RCA

9b

RCA

10b

RCA

10b

RCA

MUX MUX

(b)



119862in A B S C0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1



119878 = (119860 oplus 119861)1198621015840

in + (119860 ⊙ 119861)119862in

119862 = (119860119861)1198621015840

in + (119860 + 119861)119862in(5)




0)


0would be 119878

11 Similarly if C

0is ldquo0rdquo



VLSI Design 5

A1 A2 AnB1 B2 Bn

C1C0

C0SnS1 S2

0 0

000

1 1

111


C20C21

Cnminus1

S10 S11 S20 S21 Sn0 Sn1

MU

X

MU

X

MUXMUX MUX

(a)

CBL0

B4B2 B3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

(b)














Xi

Ci

Yi Si

Ci+1

Figure 6 Full adder





6 VLSI Design

8 16 32 64


0

1

2

3

4

5

6

7D

elay

(ns)

(Bit)



005

115

225

335

4

8 16 32 64

Del

ay (n

s)

(Bit)



005

115

225

335

445

8 16 32 64

Del

ay (n

s)

(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)



0102030405060

Pow

er (120583

W)

8 16 32 64(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)


VLSI Design 7


0

500

1000

1500

2000

2500

8 16(Bit)

32 64

Are

a(120583

m2)



0

10

20

30

40

50

60

Leak

age p

ower

(120583W

)

8 16 32 64(Bit)





050

100150200250300350

Num

ber o

f pat

tern

s

8 16 32 64(Bit)




5 Conclusion







8 VLSI Design








Competing Interests


References
















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 3


PFAS G P C

PFAS G P C

PFAS G P C

PFAS G P C

AB S

P

G


C0C1C2C3

C4

S0S1S2S3

G0G1G2G3 P0P1P2P3

(a)

CLA

0

CLA

1

CLA

2

CLA

3

CLA

4

CLA

5

CLA

6

CLA

7

CLA

8

CLA

9

CLA

10

CLA

11

CLA

12

CLA

13

CLA

14

CLA

15

(b)


A0A1A2A3 B0B1B2B3

Cin

Cin

Cin

Cout

S0S1S2S3

(0)

(1)

FAFAFAFA

FA FA FA FA

(a)

RCA1 with Cin = 0

RCA1 with Cin = 1

MUX MUX

MU

X

RCA0

RCA2

RCA3

RCA4

RCA5

RCA6

7

RCA8

RCA9

RCA10

RCA11

RCA12

RCA13

RCA14

15

(b)

CLA0

CLA

1CL

A2

CLA

3CL

A4

CLA

5CL

A6

CLA

7CL

A8

CLA

9CL

A10

CLA

11CL

A12

CLA

13CL

A14

CLA

15

MUX

MU

X

4b CLA Cin = 0

4b CLA Cin = 1

(c)







4 VLSI Design


Cin = 1 Cin = 1 Cin = 1 Cin = 1

A[1511]B[1511] A[107]B[107] A[64]B[64] A[32]B[32] A[10] B[10]




10 RCA


Cin

Cout

C10 C6 C3 C1

(a)



2b RCA

3b

RCA

4b

RCA

5b

RCA

6b

RCA

7b

RCA

8b

RCA

9b

RCA

10b

RCA

10b

RCA

MUX MUX

(b)



119862in A B S C0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1



119878 = (119860 oplus 119861)1198621015840

in + (119860 ⊙ 119861)119862in

119862 = (119860119861)1198621015840

in + (119860 + 119861)119862in(5)




0)


0would be 119878

11 Similarly if C

0is ldquo0rdquo



VLSI Design 5

A1 A2 AnB1 B2 Bn

C1C0

C0SnS1 S2

0 0

000

1 1

111


C20C21

Cnminus1

S10 S11 S20 S21 Sn0 Sn1

MU

X

MU

X

MUXMUX MUX

(a)

CBL0

B4B2 B3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

(b)














Xi

Ci

Yi Si

Ci+1

Figure 6 Full adder





6 VLSI Design

8 16 32 64


0

1

2

3

4

5

6

7D

elay

(ns)

(Bit)



005

115

225

335

4

8 16 32 64

Del

ay (n

s)

(Bit)



005

115

225

335

445

8 16 32 64

Del

ay (n

s)

(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)



0102030405060

Pow

er (120583

W)

8 16 32 64(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)


VLSI Design 7


0

500

1000

1500

2000

2500

8 16(Bit)

32 64

Are

a(120583

m2)



0

10

20

30

40

50

60

Leak

age p

ower

(120583W

)

8 16 32 64(Bit)





050

100150200250300350

Num

ber o

f pat

tern

s

8 16 32 64(Bit)




5 Conclusion







8 VLSI Design








Competing Interests


References
















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









4 VLSI Design


Cin = 1 Cin = 1 Cin = 1 Cin = 1

A[1511]B[1511] A[107]B[107] A[64]B[64] A[32]B[32] A[10] B[10]




10 RCA


Cin

Cout

C10 C6 C3 C1

(a)



2b RCA

3b

RCA

4b

RCA

5b

RCA

6b

RCA

7b

RCA

8b

RCA

9b

RCA

10b

RCA

10b

RCA

MUX MUX

(b)



119862in A B S C0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1



119878 = (119860 oplus 119861)1198621015840

in + (119860 ⊙ 119861)119862in

119862 = (119860119861)1198621015840

in + (119860 + 119861)119862in(5)




0)


0would be 119878

11 Similarly if C

0is ldquo0rdquo



VLSI Design 5

A1 A2 AnB1 B2 Bn

C1C0

C0SnS1 S2

0 0

000

1 1

111


C20C21

Cnminus1

S10 S11 S20 S21 Sn0 Sn1

MU

X

MU

X

MUXMUX MUX

(a)

CBL0

B4B2 B3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

(b)














Xi

Ci

Yi Si

Ci+1

Figure 6 Full adder





6 VLSI Design

8 16 32 64


0

1

2

3

4

5

6

7D

elay

(ns)

(Bit)



005

115

225

335

4

8 16 32 64

Del

ay (n

s)

(Bit)



005

115

225

335

445

8 16 32 64

Del

ay (n

s)

(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)



0102030405060

Pow

er (120583

W)

8 16 32 64(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)


VLSI Design 7


0

500

1000

1500

2000

2500

8 16(Bit)

32 64

Are

a(120583

m2)



0

10

20

30

40

50

60

Leak

age p

ower

(120583W

)

8 16 32 64(Bit)





050

100150200250300350

Num

ber o

f pat

tern

s

8 16 32 64(Bit)




5 Conclusion







8 VLSI Design








Competing Interests


References
















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 5

A1 A2 AnB1 B2 Bn

C1C0

C0SnS1 S2

0 0

000

1 1

111


C20C21

Cnminus1

S10 S11 S20 S21 Sn0 Sn1

MU

X

MU

X

MUXMUX MUX

(a)

CBL0

B4B2 B3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

(b)














Xi

Ci

Yi Si

Ci+1

Figure 6 Full adder





6 VLSI Design

8 16 32 64


0

1

2

3

4

5

6

7D

elay

(ns)

(Bit)



005

115

225

335

4

8 16 32 64

Del

ay (n

s)

(Bit)



005

115

225

335

445

8 16 32 64

Del

ay (n

s)

(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)



0102030405060

Pow

er (120583

W)

8 16 32 64(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)


VLSI Design 7


0

500

1000

1500

2000

2500

8 16(Bit)

32 64

Are

a(120583

m2)



0

10

20

30

40

50

60

Leak

age p

ower

(120583W

)

8 16 32 64(Bit)





050

100150200250300350

Num

ber o

f pat

tern

s

8 16 32 64(Bit)




5 Conclusion







8 VLSI Design








Competing Interests


References
















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









6 VLSI Design

8 16 32 64


0

1

2

3

4

5

6

7D

elay

(ns)

(Bit)



005

115

225

335

4

8 16 32 64

Del

ay (n

s)

(Bit)



005

115

225

335

445

8 16 32 64

Del

ay (n

s)

(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)



0102030405060

Pow

er (120583

W)

8 16 32 64(Bit)



0

10

20

30

40

50

60

Pow

er (120583

W)

8 16 32 64(Bit)


VLSI Design 7


0

500

1000

1500

2000

2500

8 16(Bit)

32 64

Are

a(120583

m2)



0

10

20

30

40

50

60

Leak

age p

ower

(120583W

)

8 16 32 64(Bit)





050

100150200250300350

Num

ber o

f pat

tern

s

8 16 32 64(Bit)




5 Conclusion







8 VLSI Design








Competing Interests


References
















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 7


0

500

1000

1500

2000

2500

8 16(Bit)

32 64

Are

a(120583

m2)



0

10

20

30

40

50

60

Leak

age p

ower

(120583W

)

8 16 32 64(Bit)





050

100150200250300350

Num

ber o

f pat

tern

s

8 16 32 64(Bit)




5 Conclusion







8 VLSI Design








Competing Interests


References
















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









8 VLSI Design








Competing Interests


References
















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









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