requirements for the ps/psb tfb board 1 alfred blas working group meeting - 07 december 2011...
DESCRIPTION
1.Sampling frequency Proposed improvements 3 Alfred Blas Use an ADC with a maximum sampling frequency > 125 MHz. This would allow to use the Clock used for the RF (max = 125 MHz) Allow for a clock harmonic change (no hardware implication): The clock frequency will be measured in the FPGA to detect the harmonic change When the change is detected, the loop will remain inactive during the purging of the loop Registers will be loaded with the sequence of different harmonics used within the cycle Working group meeting - 07 December 2011TRANSCRIPT
Requirements for the PS/PSB TFB board
1Alfred Blas
Working group meeting - 07 December 2011
1. Sampling frequency
2. Required Delayed Clocks
1. Sampling frequencyPSB TFB requirements (the most
demanding)
2Alfred Blas
50 MeV to 1.4 GeV PSB with Linac2 Frev [ 0.6 MHz , 1.73 MHz ] (factor 2.88)
160 MeV to 2 GeV PSB with Linac4 Frev [ 1 MHz , 1.81 MHz ] (factor 1.81)
Sampling rate for having a 20 MHz system analogue bandwidth > 60 Ms/s
Present ADC (AD6645) clock frequency range: [ 30 MHz , 105 MHz] DAC (AD9754) clock frequency range: [ DC , 125 MHz]
Present limitation for the sampling frequency : 60 MHz < fS < 105 MHz
The ratio 105/60 = 1.75 < 1.81 is marginally compatible with a use in the PSB during the Linac4 era !
< 2.88 means it is not compatible with Linac 2!
Working group meeting - 07 December 2011
1.Sampling frequencyProposed improvements
3Alfred Blas
Use an ADC with a maximum sampling frequency > 125 MHz.This would allow to use the Clock used for the RF (max = 125
MHz)
Allow for a clock harmonic change (no hardware implication):• The clock frequency will be measured in the FPGA to detect
the harmonic change• When the change is detected, the loop will remain inactive
during the purging of the loop• Registers will be loaded with the sequence of different
harmonics used within the cycle
Working group meeting - 07 December 2011
2. Required Delayed Clocks
4Alfred Blas
DPRAM
RF Clk
RF Clk + calculated
Δt
Data in
WriteAddres
s
Data out
ReadAddress
Counter
Calculated pipeline delay
Ck
2 different clock domains !
Write
Read
2 setups of this kind:• One to track the flight time change between two PUs• One
------------------------------------------------------------------------------------------PU and Kicker
FineDly
Working group meeting - 07 December 2011
2. Required Delayed Clocks
5Alfred Blas
When the required fine delay ΔT < tpd + th, the read address needs to be latched with CK (tpd = CK to data out propagation delay, th = flip-flop hold time)
When tpd + th < ΔT < TCK the read address needs to be latched with /CK (inverted CK)
Working group meeting - 07 December 2011
2. Required Delayed Clocks
6Alfred Blas
When ΔT is equal to 8.8 ns when programmed to zero as in the present case,the delayed clock handling becomes complicated.
First the offset value needs to be known and well displayed somewhereSecond, the designer needs to handle a special case when the clock period
passes through 8.8ns at113 MHz
Working group meeting - 07 December 2011
7Alfred Blas
2. Required delayed clocksADC Data synchronization
ADC conversion time: 1.4 tC 7nsFPGA flip-flop hold time = 1ns?Longer path in the FPGA from pin to F-F compared pin to clock
path :3ns?
Working group meeting - 07 December 2011
8Alfred Blas
RF Clock
ADC #2
ADC #1
ΔToffset
+ΔTvar 2
Δtoffset
ΔTADC
ΔTADC
DPRAM
DFF
Beam
Process
DPRAM
ΔToffset
+ΔTvar 1
DAC
5 clock delaysin total
maybe 6 ?
?
Working group meeting - 07 December 2011
9Alfred Blas
RF Clock
ADC #2
ADC #1
ΔToffset
+ΔTvar 2
ΔTADC
ΔTADC
DPRAM
DFF
Beam
Process
DPRAM
ΔToffset
+ΔTvar 1
DAC
Simplified version4 clock delays
in totalmaybe 5 ?
ΔTDAC?
Working group meeting - 07 December 2011
10Alfred Blas
RF Clock
ADC #2
ADC #1
DPRAM
DFF
Beam
Process
DPRAM
ΔToffset
+ΔTvar 2
DAC
Present state
Working group meeting - 07 December 2011
Cannot create a fine delay
ΔToffset
+ΔTvar 1
Possible acq. problem
3. Effect of a delay change
11Alfred Blas
DPRAM
Ck
Ck + calculated
Δt
Data in
WriteAddres
s
Data out
ReadAddress
Counter
Calculated pipeline delay
Ck
Write
Read
During an accelerating cycle the automatic delay will decrease in the following way:
Smooth decrease of the fine delay Δt down to zero -> then decrease of one pipeline stage together with an abrupt increase of the fine delay Δt of about one clock period.
Opposite behavior in a decelerating cycle.Working group meeting - 07 December 2011
3. Effect of delay change
12Alfred Blas
This delay transition (decrease of one pipeline stage) should be smooth with no glitch. The memorized clock signal in the fine delay total length has no side effect (assuming a smooth functioning of the file delay chip). Working group meeting - 07
December 2011
4. Summary
13Alfred Blas
1. The ADCs should be upgraded for a 125 MHz version (why not 16 bits)
2. The clock distribution should be implemented as described in slide 10.
3. There is no need for the sophisticated (and unfortunately not operational in all circumstances) delay switching circuit.
Working group meeting - 07 December 2011