Design of Multimedia SoC Platform with a Crossbar

On-chip Busfor Embedded Systems

Hongkyun Jung, Xianzhe Jin, Younjin Jung, Ok Kim, Byoungyup Lee,Jungbum Heo and Kwangki Ryoo

Graduate School of Information and Communication, Hanbat National University,

{hkjung, kkryoo}@hanbat.ac.kr

Reporter :LYWang 2013.10.7

We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of RISC processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows more than one master to use the bus because of multiple channels. As a result of the test program, the proposed platform has better efficiency by 26.58% than the SoC platform with shared bus on-chip bus.

Abstract

reduce design and verification time

[1]

improve SoC Network Architecture

[2]

open source soc debug interface

[7][3][4][5][6]

specification

This paper:Design of Multimedia SoC Platform with a Crossbar On-chip Busfor Embedded Systems

Related Work

Solve bottleneck of communication

Apply

What’s the problem: Communication of multiple IPs is limited by the bottleneck

on traditional shared bus.。When a master communicate with one slave , the other master can not

communicate with other slave.

Proposed method: Crossbar on-chip bus

。Multiple channel allows more than one master to use the bus.。The proposed platform will have better efficient.

Introduction

Proposed SoC platform

Let host and AC97 code communicate with each other.

16 slave interface• Select highest priority master

8 master interface• Decode address from master• Transmit request to slave interface

OpenRISC 1200• Synthesizable CPU core• IP core is implemented in VHDL• Modify cache 1 way -> 4 way

Check the sigmal between CPU and WISHBONELet Graphic image displaya computer hardware that translates data between parallel and serial

kj

Traditional shared bus

The system performance reduced when accessrequests to a shared communication resource.

Crossbar on-chip busMaster interfacecontain16 slave interface,8 master interface

Crossbar on-chip bus

Block diagram of Master Inteface

If master interface receives request from mater , it will decode the address and select the communication channel than send the request to slave interface.

Crossbar on-chip bus

Multiple channel architecture

The multiple channel architecture is formed of WISHBONE protocol. Every of the master interface consists of 16 communication channels with the 16 slave interfaces

Crossbar on-chip bus

Master select controller

When the slave interface receives a request from master. Master select controller will check the information value of master’s priority from register, and slave interface will connect to a slave according to the higher priority master.

Master select controller

• The arbiter is formed of arbiter priority 0, 1, 2 and 3. 0 shows the lowest priority value, and 3 shows the highest priority value.

• Each arbiter operates as round robin system, and has the information of the last processed master which has the corresponding priority value

• It prevents one master from occupying bus for a long time.

Table 1 shows the order of the communicationbetween the 5 masters and slave 0, when the master 0'spriority value is set to 3 and the master 1, 2, 3, 4'spriority values are set to 1 and the five masters sendrequest signals to the slave interface. ‘↓’ sign meansthere is a communication. In shared bus system, twomasters occupy the bus, but in multiple channel bus,masters communicate with slave 0 equally except forthe master 0 with the higher priority. In other words,high priority master occupies the bus continuously inprevious shared bus system, because it divided intoeight priorities, but multiple channel bus divides thepriority value to 4 steps. The masters, which have thesame priority, are granted with round robin method,and minimize one of the masters exclusive occupationon the bus, and make an efficient and balancedcommunication happen. The register file has sixteen16-bit registers, and each 16-bit register is mapped toeach of the sixteen slaves(0∼15). It offers priorityvalue of eight masters with 2 bits. The 16-bit value,which is saved to register, could be saved withdifferent values by user. Each slave sets high priorityto several masters which need to process quickly.Therefore it makes efficient communication.

• 5 masters and 1 slave• master 0's priority value is set to 3 and the master 1,

2, 3, 4's priority values are set to 1• five masters send request signals to the slave

interface

Let multiple master send request to multiple slave.

Compare shared bus with crossbar bus.

How to prove the proposal

Experimental result

Test 1： The VGA controller reads video data from the SRAM while the RISC processor is fetching the instruction

Test 2： The processor accesses to the UART when VGA controller accesses to the SRAM and the processor accesses to the FLASH memory

Experimental result

Test 1： The VGA controller reads video data from the SRAM while the RISC processor is fetching the instruction

Test 2： The processor accesses to the UART when VGA controller accesses to the SRAM and the processor accesses to the FLASH memory

Conclusion Propose multimedia SoC platform for a multiple on-chip

communication and performance improvement. The proposed SoC platform shows better efficiency by

26.58% than the SoC platform with shared on-chip bus.

My comment Learn what’s the limit of shared bus and the good

prospects of crossbar bus. This paper do not introduce crossbar bus internal

structure.

Conclusion & Comment

Backup

LRU of RISC

Round robin

Process A B C D E

到達時間 0 2 4 6 8

服務時間 (Ts) 3 6 4 5 2

quantum = 1