Reconfigurable Triple Band Low Noise AmplifierJohn Broze, Student, Binod Adhikari, Student, Mohamed Elkholy TA, Dr. Entesari ProfesorAbstract In this project, we have designed and implemented a triple band reconfigurable CMOS LNA in 0.35 CMOS technology. To operate the LNA in multi- bands switched capacitors array are used in input and output ports. The designed reconfigurable LNA targets the frequency band of 0.8-0.85GHz, 1.0-1.05GHz and 1.2-1.25GHz. In these frequency band of interest the gain was kept fairly constant at around 20dB. The LNA was optimized to operate at each frequency of interest by LC resonant circuits, capacitor array network and gain switching array. The designed topology is a single ended topology without the output buffer.Specifications and design challengesThe main objective of this project is to design a reconfigurable triple band LNA with the following specifications:Pass Band Frequency : 0.8-0.85GHz, 1.0-1.05GHz, 1.2-1.25GHzPass Band Gain: ~20dBStop Band Gain @ f0+0.2GHz : 0~5dB Noise Figure < 3dB IIP3 > 0 dBm

The major design challenges while working on this project are as follows:(i)Keeping the NF within 3dB while switching the caps/transistors to get the band switching(ii)High Q for the inductor and capacitors to get the reasonable Pass band gain (iii) Sharp attenuation in the stop band frequency to keep the stop band gain within 0~5dB(iv) High Linearity constraint of the LNA poses another challenge while designing the LNA

introductionIn modern wireless system, the receiver has to operate over wide frequency ranges to cover many standards like GSM, CDMA, GPS, Wi- Fi and so on. One of the challenging building blocks in multi-band receivers is the low-noise amplifier (LNA). Parallel, concurrent, or wide-band LNAs the commonly used approaches employed in multifunction receivers [1]. Parallel LNAs are achieved by using several LNAs for each band/standard [1]. This approach requires additional area for various LNAs in addition to switches for band selection, which increase the complexity of the receiver. Concurrent LNAs provide dual input matching at two different frequency bands [5], and wide-band LNAs provide wide-band matching [7]. Concurrent and wide-band LNAs occupy less area at the cost of higher requirement on the 1-dB compression point, and hence, higher power consumption. Thus we prefer to use reconfigurable LNA in the band of interest to minimize the area in exchange for a slight increase in NF of the LNA since the switching transistor directly adds noise at the input node of the LNA.

Thus we prefer to characterize the conventional CS LNA and then analyze it further to work for the specifications mentioned.

The Voltage gain of the conventional CS LNA is as follows:

To increase the voltage gain of the amplifier without increased power, parallel resistance of the tank must be increased. Thus we prefer to use high Q tank to increase the parallel resistance, which also helps in steep transition from pass band to stop band. Similarly the NF of the CS LNA is:

From the above NF equation we can conclude that NF of the CS LNA is inversely proportional to gm of the input transistor and the overall gain affects the NF of the CS LNA.The Linearity of the amplifier directly depends on the vdsat of the input transistor M1. Thus to have high linear gain the biasing of the M1 transistor is done such that it has high Vdsat and is biased far from the triode region.

Fig Conventional CS LNA architecture

The CS LNA with cascode transistor provides an input to output isolation and provides simultaneous input matching and low NF required as per the specifications. The output tank circuit is tuned to the required band and the input series resonant circuit is adjusted to provide sufficient matching at the desired frequency. The input matching is approximately calculated as

From the above equation we can also come up with the following equation for better understanding of the input matching.

background and previous resultsThus LNA must operate across a wide bandwidth or in different bands can incorporate band switching to incorporate all the required frequency ranges. The switch is realized using a MOS transistor.

For the band switching at the output node (which is usually at high voltage), a PMOS device may be considered. The drawback of using PMOS device is it has extra larger capacitance for the given on resistance than NMOS transistor. This capacitance lowers the tank resonance frequency when the switch is off, reducing the maximum tolerable value of output capacitor and hence limiting the size of the input transistor of the following stage. IF the output inductance is reduced to compensate for the increased parasitic capacitance due to switch , R1 of the inductor is decreased as does the gain. Thus a NMOS referred to ground is traditionally used instead of PMOS switch for band switching.

The choice of the switch is another critical design issue. For a small transistor; the on resistance is too high so that the NF cost is high and the added capacitance is less effective. A moderate device width of the transistor translates to limited Q of the added capacitance C2 thereby lowering the overall Q of the tank and eventually lowering the voltage gain. Thus it implies that the on resistance of the switch transistor must be minimized such that Rp1>> parallel resistance of the tank. But we have to keep in mind that the increased transistor size means increased capacitance during off state. Thus we can conclude that the width of S1 poses a trade-off between the tolerable value of C1 when S1 is off and the reduction of the gain when S1 is on [1].

Fig Switching strategy for the band switching

The alternative approach for band switching would be to use different tanks as per the requirement of the number of bands required and use the switching cascode transistor to switch between the tank. This is an expensive proposition since we have to use multiple inductor and capacitor for the each switching band and hardware issue becomes prominent. This scheme requires that each tank drive a copy of the following stage, e.g., a mixer. Thus, when M1 and band 1 are activated, so is mixer MX1. The principal drawback of this approach is the capacitance contributed by the additional cascode device(s) to node Y. Also, the spiral inductors have large footprints, making the layout and routing more difficult.

Fig Alternative approach for band switching transistor

M. Nozahi paper [3] presents a continuous reconfigurable LNA where continuous tuning is less sensitive to process variation. Any shift in performance can be electronically tuned using this architecture. This topology does not require higher linearity due to its narrow band nature. Thus the presented topology is used to scale the inductor value for any application and meet the input matching conditions.

Fig Tunable floating inductor and its application in input matching in CS LNA

An ideal amplifier is added to provide necessary scaling to Lg and ZA is an impedance that is used to change the gain of the amplifier. Depending on the polarity of the gain the inductor value increases of decreases. The output load is realized using two resonant circuits, each tuned at different frequency. This helps in increasing the bandwidth of the Load to cover the frequency range at the cost of lowered gain.

M. Vahidfar [4] implements a triple mode LNA enhanced by dual feedback loop for Multi- Standard receivers. Using voltage-voltage feedback and gm boosted techniques NF and input matching were set independently. The NF is optimized by adjusting the gm, the required input impedance matching is achieved by C2 capacitor adjustment. The programmable output resonator is made using switched inductor. To achieve NFmin (the minimum achievable NF for a bias condition) in each working mode, it is needed that the input transistor is sized properly in each frequency band. However if any other transistor is added in parallel with the input transistor in order to be switched in lower frequencies, the NF will be increased drastically due to added thermal noise source. Thus the size of input transistor is fixed for all frequency bands and changing the biasing condition of the transistor is done to adjust DC biasing. The penalty of not changing the transistor size in different bands may result in higher NF and more complicated biasing.

Fig Common gate amplifier configuration for LNA.

In CG LNA cannot give adequate as in CS LNA. The noise figure of the LNA is reduced by raising the gain of the amplifier in the feed-forward path. The noise figure of the common gate stage excluding the noise contribution due to the amplifier.

proposed solutionFor our project, we choose the capacitive switching method to switch between bands in a discrete fashion.

See the Appendix for the LNA schematic.

Design ConsiderationsFor the LNA design procedure, we follow the design procedure in [5] which claims to minimize the noise figure:

The input impedance of the circuit is:To match the input we will design for:

The total noise figure, including non-ideal inductors is:

Rs is the source resistance, gd0 is the drain conductance, Qs are the quality factors of the inductors, and Rp is the parallel resistor of the load LC tank.

For the linearity of the circuit, we will approximate the input IP3 to be equal to the overdrive voltage of the cascade transistors:

The transconductance is give in terms of the overall power, linearity, and drain voltage.

In order to minimize the NF, the author of defines the ratio of gate inductance to source inductance:

The noise figure is rewritten as:

By taking the first derivative in terms of the ratio of the inductances and setting the result to zero, it can be shown that for a given gm, there is a corresponding n that gives the least noise figure. It is shown below.

Design CalculationsNow that we have some insight about the circuit, we compute the actual values of our circuit as follows.

First we estimate that we will need an overdrive voltage around 300mV to meet the IIP3 requirement, and we limit the power consumption to 5mA to reduce power.

Now we can find the ratio of inductances that gives the best noise figure. We use an offchip Lg with a Q of 10.

Knowing n we calculate the value of the source inductance.

Cgs needed to tune the input impedance and for matching of real part:

For the gain we calculate the LC tank parallel resistor:

Using Rp we find the LC tank inductances and capacitances by:

For band selection we have variable Cgs capacitance, gm, and LC tank capacitance.For the LC tank:

For Cgs matching we recalculate the transconductance. From the general gain equation for source degeneration LNA we have:

To retune the input impedance to a lower frequency flow from a higher frequency fhigh see that:

In order to increase the gm for lower frequencies we add gain transistors with switches in parallel with the initial gain stage transistor.Then, recalculate the Cgs capacitance:

This Cgs will be larger than the higher frequency Cgs. To increase it we switch capacitors between the gate and source of the gain transistor.

See the Appendix for a table of comparison between our work and these strategies.

results and comparisonThe performance parameters simulated using cadence spectra are as follows:

Fig Plot of the gain of the LNA at around the desired frequency bands

The gain of the amplifier is inversely proportional to the Cgs of the input transistor. For the input matching purpose, we introduce a large gate source capacitance which kills the gain at low frequency. To equalize the gain of frequency we burn more power to increase the low frequency gm. High gain of the LNA is undesirable for the following stage of receiver chain since it adversely affects the overall linearity of the receiver architecture.

Table for the bandwidth of the LNA in the frequency of interestCenter Frequency (f0)Gain at (f0+0.2GHz)Frequency of Interest (Band)

842.6MHz(13.4, 12.6) dB0.8GHz-0.85GHz

1.026GHz(14.39, 13.95)dB1.0-1.05GHz

1.222GHz(16.79, 15.47)dB1.2-1.225GHz

The simulated data for stopband gain in the above table deviates from the specifications and should be around 5dB. High Q LC tank or notch filter can be used to limit the stop the frequency component. Q enhancement techniques are applied to limit the bandwidth of the LNA but it directly trades off with the noise figure of the LNA. Due to the increased parallel resistance due to enhanced Q, gm is lowered to keep the gain around 20dB which translates into increased noise figure. The following figure illustrates the tradeoff mentioned above.

Fig Q enhancement of the tank to limit the output bandwidth of the band

In the above figure, if the gain is not limited to 20dB the overall noise figure is 2.85dB which is well within the specifications. But the gain is in fact limited to 20dB as not to saturate the rest of the receiver architecture. This reduction in gain causes the LNA to suffers from high noise figure. This analysis was done at the mid band setting of the LNA. A similar analysis can be done for the remaining bands of interest for exact NF to BW tradeoff of every setting.

Fig NF of the LNA at different frequency of interest

The noise figure plot shows that for increased gain of the LNA NF is reduced.

Fig Input matching for the CS LNA

Input matching is achieved using a bank of capacitors to tune to the desired frequency of interest for maximum power transfer. As can be seen, the lowest band matching is not centered. To center it, additional Cgs must be added, and additional gm must be added to keep the NF below 3dB. This translates to a tradeoff between power and input matching.

Fig IIP3 plot of the LNA for the output band of 1 -1.05GHz range

The table of IIP3 of at different frequency band is as follows:Frequency RangeIIP3 values

0.8-0.85GHz3.21dB

1 -1.05GHz5.05dB

1.2 1.25GHz2.6dB

As previously mentioned IIP3 of the LNA is dependent on the Vdsat of the input transistor and for our design we have vdsat of the input transistor is 300mV which is equivalent to 3dB IIP3.ConclusionThe reconfigurable CS LNA was designed in 0.35 TSMC technology. The gain, NF and IIP3 specifications were met using a cascode common source LNA with source degeneration inductor. The input and output matching was achieved using a bank of capacitor to tune to the desired frequency at a particular operation mode. Gain switching was used to limit or boost the gain of the amplifier at different frequency bands. The switching of the transistor at the input node adds noise to the overall NF at the input and proper sizing of the switch transistor help in effectively tuning the LNA while maintaining low NF. On the output node the switch adds on resistance degrading the Q of the tank, so careful consideration should taken to maximize Q of the tank for band shaping of the LNA at the required frequencies.

REFERENCES:[1]Mohamed El-Nozahi, Edgar Sanchez-Sinencio, and Kamran Entesari, 'A CMOS Low-Noise Amplifier Wtih Reconfigurable Input Matiching Network [C] '. IEEE Tranacitons on Microwave Theory and Techniques, Vol. 57, No.5, May 2009. pp. 1054-1062.

[2] B. Razavi, 'RF Microelectronics', Prentice Hall Inc., 2nd ed .

[3] M.B. Vahidfar, and O. Shoaei, 'A Triple Mode LNA Enhanced by dual Feedback loops for Multi Standard Receivers '. Circuits and Systems, 2006. MWSCs '06 49TH IEEE International Midwest Symposium.

[4] Desheng Ma, and Fa Foster Dai, 'A 7.27 GHz Q Enhanced Low Noise Amplifier RFIC With 70 dB Image Rejection Ratio '. IEEE Microwave And Wireless Components Letters, Vol. 20, No. 8, August 2010.

[5] V. Vidojkovic, J. van der Tang, E. Hannsen, A. Leeuwenburgh, and A. van Roermund, Fully-integrated DECT/Bluetooth multi-band LNA in 0.18 m CMOS, in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2004, vol. I, pp. 565568.

[6]Enu-Pyo Hong, Dae-Joon Kim and Hyung Joun Yoo, 'A Reconfigurable CMOS Low-Noise Amplifier for wireless LAN application '. 23rd International Technical conference on circuits and systems (ITC -CSCC 2008).

1ECEN 665 Final Project Report John Broze Binod Adhikari

APPENDIX

Table of Spec ComparisonPapersPaper [1]Paper [3]Paper [4]Paper [5]This work

Technology0.13um CMOS0.18um CMOS0.13 m SiGe BiCMOS0.18um CMOS0.35um CMOS

ConfigurationCSCG(Triple Band)CSCGCS with gain switching

Supply Voltage1.2V1.8V1.7V1.2V3V

Frequencies1.9-2.4GHz1.8-2.8GHz7.27GHz2.4-5.25GHz0.8-0.85,1-1.05& 1.2-1.25GHz

Gain10-14dB>10dB22.5dB12.89-16.5dB~21dB

S11---17dB-17.5dB