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Registers and Counters
EE 200
Digital Logic Circuit Design
Dr. Abdulaziz Tabbakh
College of Computer Sciences and Engineering
King Fahd University of Petroleum and Minerals
EE 200– Digital Logic Circuit Design – KFUPM slide 2
Outline
Registers
Shift Registers
Ripple Counters
Synchronous Counters
Other Counters
EE 200– Digital Logic Circuit Design – KFUPM slide 4
Registers
Various types of registers are available
The simplest register
With each +ve Edge CLK, the input is stored
(when R=1).
The value of (I3, I2, I1, I0) immediately before the
clock edge determines the value of (A3,A2,A1,A0)
after the clock edge
The outputs can be sampled at any time to
obtain the binary information stored in the
register
The input Clear_b goes to the active‐low R
(reset) input of all four flip‐flops and is useful for
clearing the register to all 0’s asynchronously
EE 200– Digital Logic Circuit Design – KFUPM slide 5
Registers with parallel load
Registers with parallel load are a fundamental building
block in digital systems.
Synchronous digital systems have a master clock
generator that supplies a continuous train of clock
pulses.
The pulses are applied to all flip‐flops and registers in
the system.
The master clock acts like a drum that supplies a
constant beat to all parts of the system.
A separate control signal must be used to decide which
register operation will execute at each clock pulse
EE 200– Digital Logic Circuit Design – KFUPM slide 6
Registers with Parallel Load
The transfer of new information into a
register is referred to as loading or updating
the register.
We say the loading is in parallel if all the
bits are loaded simultaneously at the same
clock cycle.
To keep the content of the register
unchanged:
the inputs must be held constant
the clock must be inhibited from the circuit
Inserting gates into the clock path, to inhibit
the clock, is ill advised
EE 200– Digital Logic Circuit Design – KFUPM slide 7
Registers with Parallel Load
We use a combinational
circuit to either keep previous
value, or load a new one.
Load=0 keep previous value
Load=1 accept value from I’s
It is advisable to control the operation of the register with
the D inputs, rather than controlling the clock of the FF’s
EE 200– Digital Logic Circuit Design – KFUPM slide 8
Register with Parallel Load
EE 200– Digital Logic Circuit Design – KFUPM slide 9
Shift Registers
A shift register is a register that is capable of shifting the
binary information held in each cell to its neighboring
cell, in a selected direction
A shift register consists of a chain of flip‐flops in
cascade, with the output of one flip‐flop connected to the
input of the next flip‐flop.
All flip‐flops receive common clock pulses, which
activate the shift of data from one stage to the next
EE 200– Digital Logic Circuit Design – KFUPM slide 10
Shift Register
This shift register is unidirectional (left‐to‐right)
It does not support a left shift
The serial input determines what goes into the leftmost flip‐flop
during the shift.
The serial output is taken from the output of the rightmost
flip‐flop
To control the shift:
recirculate the output of each register cell back through a
two‐channel mux
A reset signal is required in practical designs.
EE 200– Digital Logic Circuit Design – KFUPM slide 11
Shift Register
Sometimes it is necessary to control the shift so that it occurs
only with certain pulses, but not with others.
As with the data register discussed in the previous section,
the clock’s signal can be suppressed by gating the clock
signal to prevent the register from shifting (but this approach
is not preferred as it may cause NO synchronization)
A preferred alternative in high‐speed circuits is to suppress
the clock action, rather than gating the clock signal,
By leaving the clock path unchanged, but recirculating the
output of each register cell back through a two‐channel mux
whose output is connected to the input of the cell.
When the clock action is not suppressed, the other channel of
the mux provides a datapath to the cell.
EE 200– Digital Logic Circuit Design – KFUPM slide 12
Serial Transfer
A digital system is said to operate in serial mode when data
is transferred and processed one bit at a time.
A digital system is said to operate in parallel mode when
data is transferred and processed in parallel.
A serial system will take more time to process a collection
of data, but the hardware needed is for a single bit,
while a parallel system will take only 1 clock to process a
collection of bits, but requires hardware for n-bits (i.e. n-
times more hardware/circuits).
So speed needs more hardware. (time vs. area)
Some serial transfer buses; USB cables, RS232.
Some parallel transfer buses; Parallel port, internal memory
bus.
EE 200– Digital Logic Circuit Design – KFUPM slide 13
Serial Transfer Suppose the shift
registers have four
bits each
• The 4 pulses perform identical
operations, shifting the bits of A
into B, one at a time.
• After the fourth shift, the shift
control goes to 0, and registers
A and B both have the value
1011.
Thus, the contents of A
are copied into B, so that
the contents of A remain
unchanged i.e., the
contents of A are restored
to their original value.
EE 200– Digital Logic Circuit Design – KFUPM slide 14
Serial Addition Operations in digital computers are usually done in
parallel because that is a faster mode of operation.
Serial operations are slower because a datapath
operation takes several clock cycles
but serial operations have the advantage of requiring fewer
hardware components
Serial adders adds two binary numbers starting from
their LSB.
The inputs comes from two shift registers
It adds one pair at a time through a single full‐adder (FA) circuit
The result is stored in a shift register
The carry out is stored in a D-FF and is then used as the carry
input for the next pair of significant bits
EE 200– Digital Logic Circuit Design – KFUPM slide 15
Serial Adder
The operation of the
serial adder is as follows:
Register A & B hold the
two binary numbers and
the carry FF is reset to 0
The SO of both registers
are connected to the inputs
of the FA along with the
output of the FF
S is connected to SI of
register A and C is
connected to the D of the
FF
EE 200– Digital Logic Circuit Design – KFUPM slide 16
Serial Vs. Parallel Adders
The parallel adder uses registers with a parallel load,
whereas the serial adder uses shift registers
The parallel adder needs n FA where n is the number of
bits in the inputs while the serial adder needs 1 FA and 1
FF
the parallel adder is a combinational circuit, whereas the
serial adder is a sequential circuit
EE 200– Digital Logic Circuit Design – KFUPM slide 17
Redesign Serial Adder
Let us follow a sequential circuit design approach and
use JK-FF to store the carry
Assume that the LSB bits from Reg. A and Reg. B are
called x and y.
X and y are available for every CLK since the Shift-Reg.
will provide a new x and y for each CLK.
The circuit will have
1.two inputs, x, y,
2.an output S for the sum,
3.a carry that is stored in Q.
EE 200– Digital Logic Circuit Design – KFUPM slide 18
State Table for Serial Adder
JQ = xy, KQ = x’y’=(x+y)’, S= x y Q
EE 200– Digital Logic Circuit Design – KFUPM slide 19
Serial Adder
Note that output S is a function not only of x and y, but
also of the present state of Q.
The next state of Q is a function of the present state of Q
and of the values of x and y that come out of the serial
outputs of the shift registers.
JQ = xy
KQ = x’y’=(x+y)’
S= x y Q
EE 200– Digital Logic Circuit Design – KFUPM slide 20
Universal Shift Register
If the flip‐flop outputs of a shift register are accessible, then
information entered serially by shifting can be taken out in
parallel from the outputs of the flip‐flops.
If a parallel load capability is added to a shift register, then
data entered in parallel can be taken out in serial fashion by
shifting the data stored in the register.
Some shift registers provide the necessary input and output
terminals for parallel transfer.
They may also have both shift‐right and shift‐left capabilities
EE 200– Digital Logic Circuit Design – KFUPM slide 21
Universal Shift Register
The most general shift register has the following
capabilities:
A clear control to clear the register to 0.
A clock input to synchronize the operations.
A shift‐right control to enable the shift‐right operation and the
serial input and output lines associated with the shift right.
A shift‐left control to enable the shift‐left operation and the serial
input and output lines associated with the shift left.
A parallel‐load control to enable a parallel transfer and the n
input lines associated with the parallel transfer.
n parallel output lines.
A control state that leaves the information in the register
unchanged in response to the clock.
EE 200– Digital Logic Circuit Design – KFUPM slide 22
Universal Shift Register
A register that can shift in one directions (left or right) is
called a unidirectional shift register.
A register that can shift in both directions is called a
bidirectional shift register.
A register that
1. can shift in both directions
2. has a parallel load capability
is called a Universal Shift Register.
EE 200– Digital Logic Circuit Design – KFUPM slide 23
Universal Shift Register
EE 200– Digital Logic Circuit Design – KFUPM slide 24
Universal Shift Register
Shift registers are often used to interface digital systems
situated remotely from each other
It will be expensive to use n lines to transmit n bits in
parallel for a long distance. It is more economical to use
a single line and transmit the information serially
The transmitter accepts the n‐bit data in parallel into a
shift register and then transmits the data serially.
The receiver accepts the data serially into a shift register
and then it can be taken from the outputs of the register
in parallel
the transmitter performs a parallel‐to‐serial conversion of
data and the receiver does a serial‐to‐parallel conversion
EE 200– Digital Logic Circuit Design – KFUPM slide 25
Ripple Counters
A Counter is a register that goes through a prescribed
sequence of states upon the application of input pulses
There are two types of counters:
Ripple Counters
Synchronous Counters
In a Ripple Counters, a flip‐flop output transition serves as a
trigger for other flip‐flops. In other words, the CLK input of
some or all flip‐flops are triggered by the transition that occurs
in other flip‐flop outputs.
In Synchronous Counters, a common CLK is passed to all
FF.
A counter that follows the binary number sequence is called a
binary counter (n-bit counter count from 0 to 2n-1)
EE 200– Digital Logic Circuit Design – KFUPM slide 26
Binary Ripple Counter Built with a series connection
of complementing FF
The FF are negative-edge.
What if the FF are positive-
edge triggered ?
LSB LSB
EE 200– Digital Logic Circuit Design – KFUPM slide 27
Binary Countdown Counter
A binary countdown counter is a
binary counter with a reverse count
Any bit in the sequence is
complemented if its previous least
significant bit goes from 0 to 1
The same design as the binary ripple
counter except of positive-edge FF
If negative‐edge‐triggered FF’s are
used, then CLK of each flip‐flop must
be connected to Q’ of the previous
flip‐flop
A3 A2 A1 A0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
EE 200– Digital Logic Circuit Design – KFUPM slide 28
BCD Ripple Counter
A decimal counter follows a sequence of 10 states and
returns to 0 after the count of 9
Must have at least four flip‐flops to represent each
decimal digit
A decimal counter is similar to a binary counter, except
that the state after 1001 is 0000
EE 200– Digital Logic Circuit Design – KFUPM slide 29
BCD Ripple Counter
Remember: When the CLK input goes
from 1 to 0, the flip‐flop is:
set if J = 1,
cleared if K = 1
complemented if J = K = 1
left unchanged if J = K = 0.
A3 A2 A1 A0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
EE 200– Digital Logic Circuit Design – KFUPM slide 30
BCD Ripple Counter
The operation of the counter can be
explained by a list of conditions for FF Q1
changes state after each clock pulse.
Q2 complements every time Q1 goes from 1 to
0, as long as Q8 = 0.
When Q8 = 1, Q2 remains at 0.
Q4 complements every time Q2 goes from 1 to
0.
Q8 remains at 0 as long as Q2 or Q4 is 0.
When both Q2 and Q4 become 1, Q8
complements when Q1 goes from 1 to 0. Q8 is
cleared on the next transition of Q1
This counter is called decade counter
EE 200– Digital Logic Circuit Design – KFUPM slide 31
BCD Ripple Counter
To count from 0 to 999
we need a three‐decade counter
Multiple decade counters can be constructed by connecting
BCD counters in cascade, one for each digit (decade)
A ripple counter is an asynchronous sequential circuit.
EE 200– Digital Logic Circuit Design – KFUPM slide 32
Synchronous Counters
A common clock triggers all flip‐flops simultaneously
Their design procedure follows that for Sequential
circuits.
We designed a 3-bits synchronous counter in chapter 5
000
100
010110
001111
101 011
EE 200– Digital Logic Circuit Design – KFUPM slide 33
Synchronous Binary Counter
The design of a synchronous binary counter is so simple
that there is no need to go through a sequential logic
design process
In a synchronous binary
counter, the flip‐flop in the
least significant position is
complemented with every
pulse
A flip‐flop in any other position
is complemented when all the
bits in the lower significant
positions are equal to 1.
EE 200– Digital Logic Circuit Design – KFUPM slide 34
Synchronous Counters
Synchronous binary counters have a regular pattern and can
be constructed with complementing flip‐flops and gates
The counter is enabled by Count_enable
Enable =0 all J’s & K’s = 0
The counter can be extended to any number of stages, with each stage with
each stage having an additional FF and
an AND gate
The active edge of the clock is not
essential here like the ripple counter
The synchronous counter can be triggered
with either the positive or the negative
clock edge.
EE 200– Digital Logic Circuit Design – KFUPM slide 35
Complementing Flip-Flops
The counters need to be designed with complementing
Flip-Flops
The complementing FF in a binary counter can be of
either the JK type, the T type, or the D type with XOR
gates
EE 200– Digital Logic Circuit Design – KFUPM slide 36
Down Counter
A synchronous countdown binary counter goes through
the binary states in reverse order, from 1111 down to
0000 and back to 1111
he bit in the least significant position is complemented
with each pulse.
A bit in any other position is complemented if all lower
significant bits are equal to 0.
A countdown binary counter can be constructed as up
counter, except that the inputs to the AND gates must
come from the complemented outputs
EE 200– Digital Logic Circuit Design – KFUPM slide 37
Up-Down Counter
The two counters can be combined in one circuit to form
a counter capable of counting either up or down
It has an Up and Down control Inputs
Up = 0 & Down = 0 Don’t Count
Up = 0 & Down = 1 Count Down
Up = 1 & Down = X Count Up
This set of conditions ensures that only one operation is
performed at any given time
The up input has priority
EE 200– Digital Logic Circuit Design – KFUPM slide 38
BCD Synchronous Counter
A BCD counter counts in binary‐coded decimal from 0000 to
1001 and back to 0000
Because of the return to 0 after a count of 9, a BCD counter
does not have a regular pattern, unlike a straight binary count.
To derive the circuit of a BCD synchronous counter, it is
necessary to go through a sequential circuit design
procedure.
EE 200– Digital Logic Circuit Design – KFUPM slide 39
BCD Counter – State Table
An output y, equal to 1 when the present state is 1001,
to enable the count of the next‐higher significant decade
while the same pulse switches the present decade from
1001 to 0000
EE 200– Digital Logic Circuit Design – KFUPM slide 40
BCD Counter
The unused states for minterms 10 to 15 are taken as
don’t‐care terms.
The simplified functions for T-FF are
The circuit can easily be drawn with four
T flip‐flops, five AND gates, and one OR gate.
EE 200– Digital Logic Circuit Design – KFUPM slide 41
Binary Counter with Parallel Load
Parallel load is used to start counting from a defined
state (does not always have to be ZERO).
A carry bit is set when the count reaches all 1’s
(saturate), to give indication to a following stage to start
the count.
EE 200– Digital Logic Circuit Design – KFUPM slide 42
Binary Counter with Parallel Load
EE 200– Digital Logic Circuit Design – KFUPM slide 43
Binary Counter with Parallel Load
The carry output is useful for expanding the counter to
more than four bits.
The speed of the counter is increased when the carry is
generated directly from the outputs of all four flip‐flops
rather than the method used in binary synchronous counter
A counter with a parallel load can be used to generate any
desired count sequence.
EE 200– Digital Logic Circuit Design – KFUPM slide 44
Other Counters
Counters can be designed to generate any desired
sequence of states
The sequence may follow the binary count or may be any
other arbitrary sequence
Counters are used to generate timing signals to control the
sequence of operations in a digital system.
Counters can also be constructed by means of shift
registers.
We will discuss:
Counter with Unused States
Ring Counter
Johnson Counter
EE 200– Digital Logic Circuit Design – KFUPM slide 45
Counter with Unused States A circuit with n flip‐flops has 2n binary states. Sometimes a sequential
circuit uses fewer than this maximum possible number of states
The unused states may be treated as don’t‐care conditions or may be
assigned specific next states
Once the circuit is designed and constructed, any interference during its
operation may cause the circuit to enter one of the unused states.
it is necessary to ensure that the circuit eventually goes into one of the valid states
so that it can resume normal operation.
Otherwise, the sequential circuit may circulates among unused states and can’t be
drought back to its intended sequence of state transitions.
Once the circuit is designed, it must be investigated to determine the
effect of the unused states.
The next state from an unused state can be determined from the
analysis of the circuit after it is designed.
EE 200– Digital Logic Circuit Design – KFUPM slide 46
Counter with Unused States The count sequence of the counter does not include 011 and 111
Inputs KB and KC have only 1’s and X’s in their columns, so these
inputs are always equal to 1.
The other flip‐flop input equations can be simplified by using
minterms 3 and 7 as don’t‐care conditions.
EE 200– Digital Logic Circuit Design – KFUPM slide 47
Counter with Unused States Since there are two unused states, we analyze the circuit to
determine their effect.
If the circuit happens to be in state 011 because of an error signal, the
circuit goes to state 100 after the application of a clock pulse
If the circuit happens to be in state 111 because of an error signal, the
circuit goes to state 000 after the application of a clock pulse
EE 200– Digital Logic Circuit Design – KFUPM slide 48
Counter with Unused States
If the circuit ever goes to one of the unused states
because of outside interference, the next count pulse
transfers it to one of the valid states and the circuit
continues to count correctly.
The counter is self‐correcting
In a self‐correcting counter, if the counter happens to be
in one of the unused states, it eventually reaches the
normal count sequence after one or more clock pulses.
An alternative design could use additional logic to direct
every unused state to a specific next state.
EE 200– Digital Logic Circuit Design – KFUPM slide 49
Ring Counter
A ring counter is a circular shift register with only one flip‐flop
being set at any particular time; all others are cleared
The single bit is shifted from one flip‐flop to the next to
produce the sequence of timing signals
1 0 0 0To generate 2n
timing signals, we
need either a shift
register with 2n
flip‐flops or an
n‐bit binary
counter together
with an n‐to‐2n‐line
decoder.
EE 200– Digital Logic Circuit Design – KFUPM slide 50
Johnson Counter
k‐bit ring counter circulates a single bit among the
flip‐flops to provide k distinguishable states
The number of states can be doubled if the shift register
is connected as a switch‐tail ring counter
A switch‐tail ring counter is a circular shift register with
the complemented output of the last flip‐flop connected
to the input of the first flip‐flop
EE 200– Digital Logic Circuit Design – KFUPM slide 51
Johnson Counter
A k-bit Switch-Tail configuration will generate 2k states.
To have it operate as a 2k state Ring counter, we need
2k Decoding Gates.
8 AND Gates are needed for Table below!
EE 200– Digital Logic Circuit Design – KFUPM slide 52
Johnson Counter
A Johnson counter is a k‐bit switch‐tail ring counter with 2k
decoding gates to provide outputs for 2k timing signals
The eight AND gates listed in the table, when connected to
the circuit, will complete the construction of the Johnson
counter.
Each gate is enabled during one particular state sequence
the outputs of the gates generate eight timing signals in succession
EE 200– Digital Logic Circuit Design – KFUPM slide 53
Johnson Counter
One disadvantage of Johnson counter is that if it finds
itself in an unused state, it will keep in moving from one
invalid state to another and never find its way to a valid
state.
This can be corrected by modifying the circuit to avoid
this undesirable condition
One possible correction: DC = (A + C)B
Johnson counters can be constructed for any number of
timing sequences.
The number of flip‐flops needed is one‐half the number of timing
signals.
The number of decoding gates is equal to the number of timing
signals, and only two‐input gates are needed.