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Altera PHYLite for Parallel Interfaces LoopbackReference Designs Application Note
2016.01.19
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This application note showcases loopback reference designs using the Altera PHYLite IP core.
This document is divided into three main segments:
1. A simple input/output PHYLite simulation reference design.2. A simple input/output PHYLite with dynamic reconfiguration using Arria 10 devices hardware
reference design.3. Functional description for the modules and application used in both reference designs.
Simple Input/Output PHYLite Simulation Design ExampleThis section provides architecture description and user guide for the simulation reference design.
Simulation Design Example ArchitectureThe simulation reference design is a simple design that simulates the behavior of the Altera PHYLite IPcore. This design consists of 2 main components:
• A device Under Test (DUT) module that includes two Altera PHYLite IP instances.• A traffic generator module
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.
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Figure 1: Simulation Reference Design Block Diagram
Traffic Generator (tg.sv)DUT
dut_INPUT
dut_OUTPUT
group_0_data_to_core[31:0]group_0_rdata_valid[3:0]
core_clk_out [1]
interface_locked[1]
core_clk_out[0]
interface_locked[0]group_0_data_out[3:0]
group_0_strobe_out group_0_data_from_core[31:0]group_0_oe_from_core[15:0]group_0_strobe_out_in[7:0]
group_0_strobe_out_en[3:0]
group_0_rdata_en[3:0]group_0_data_in[3:0]
group_0_strobe_in
reset_n
ref_clk
ref_clk
reset_n
locked
correct_data_counter[15:0]
phylite_top
done
pass
reset_n
Altera PHYLIte IP core
User logic
tb.v
Simulation Reference Design User GuideFollow these steps to setup and run the simulation reference design.
Requirements
The following are the requirements to run the simulation reference design:
• Quartus Prime Design Suite® versions 15.1• Simulation design example phylite_top_sim_only.par
Related Information
• AN 747 Altera PHYLite Simulation Reference Design Files• Getting Started with the Design Store
Guideline to download and install design examples from Design Store.
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Setting Up Simulation Environment
1. Follow the guidelines in Getting Started with the Design Store to download and install the referencedesign files.
2. Open the reference design .qpf file after successfully installing the design templates.3. Click on Assignments -> Settings....4. Select EDA Tools Settings -> Simulation.5. At the Settings window, choose Modelsim-Altera for Tool Name. You may choose VHDL, Verilog
HDL or System Verilog as the output netlist format.Figure 2: Simulation Settings using EDA Tools in the Quartus Prime Software
6. Open dut_INPUT.qsys file and make sure the IP has the same configuration shown below:
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Figure 3: Configuration for dut_INPUT Module
7. Make sure that the Capture strobe phase shift is set to 0 degrees to align the incoming data to strobeedge during data transfer.
8. Click Generate HDL... and select your desired simulation model format. Next, click Generate togenerate the simulation model for the dut_INPUT module. Click Close and Finish when thegeneration is complete.
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Figure 4: Generating Simulation Model
9. From the Quartus® Prime software, open dut_OUTPUT.qsys file and make sure the IP has the sameconfiguration shown below:
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Figure 5: Configuration for dut_OUTPUT Module
10.Make sure the Output strobe phase is set to 0 degrees to align outgoing data with strobe edge duringdata transfer.
11.Repeat step 9 to generate simulation model for dut_OUTPUT module.12.From the Quartus Prime software, click Processing > Start > Start Analysis & Elaboration to compile
the design.
Related InformationGetting Started with the Design StoreGuideline to download and install design examples from Design Store.
Running Simulation
1. From the Quartus Prime software, click Tools -> Run Simulation Tool -> RTL Simulation to bringup the Modelsim-Altera tool.
2. The simulation starts automatically when the Modelsim-Altera tool is launched.3. When the simulation ends, click No when the Finish Vsim window prompt appear to analyze the
simulation waveform.
ResultThe simulation result of the reference design shows the behavior of:
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• Reference clock (refclk) signal• Reset (reset_n) signal• Interface locked (locked) signal• Correct data counter (correct_data_counter) values• Transmitted and received data (group_0_data) bus• Simulation complete (done) signal
Figure 6: Design Example Simulation Flow
Simulation starts
Reference clock starts running at 200 MHz.
De-asserts reset_n signal at 70 ns.
The interface locked signal is asserted at 4805 ns to indicate PLL and the PHY circuitry are locked.
Once locked signal is asserted, data transmission begins. Correct read data values
are shown in the Transcript window.
Correct data counter starts counting at 4855 ns.
Asserts done signal to indicate simulation completed.
Simulation ends
The following shows the behavior of the signals.
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Figure 7: Reset Signal De-assertion
Figure 8: Data Transfer After Locked Signal Assertion
Figure 9: Simulation Complete with Done Signal Assertion
Simple Input/Output PHYLite with Dynamic Reconfiguration HardwareReference Design
This section provides architecture description and user guide for the hardware reference design.
Hardware Reference Design ArchitectureThe hardware reference design is an expansion of the simulation reference design. This reference designprovides the ability to perform dynamic reconfiguration to the PHYLite IP cores using Nios II softprocessor.
The hardware reference design consists of:
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• Three instances of the Altera PHYLite IP core (dut_INPUT, dut_OUTPUT and dummy).• Traffic generator module• Nios II soft processor• The In-System Sources and Probes IP core
Figure 10: Hardware Reference Design Block Diagram
DUT
dut_INPUT
dut_OUTPUT
group_0_data_to_core[31:0]group_0_rdata_valid[3:0]
core_clk_out [1]interface_locked[1]
core_clk_out[0]
interface_locked[0]
group_0_data_out[3:0]
group_0_data_from_core[31:0]
group_0_oe_from_core[15:0]
group_0_strobe_out_in[7:0]
group_0_strobe_out_en[3:0]
group_0_rdata_en[3:0]
phylite_top
Traffic Generator(tg.sv)
reset_n
Dynamic Configuration Controller(atso_dyn_cfg_ctrl)
Avalon Controller(altera_phylite_avl_ctrl)
dummy
In-system source and probes(altsource_probe)
reset_nref_clk
cfg_done
shifter
group_0_rdata_en
group_0_rdata_en
group_0_strobe_in_sepgroup_0_data_in[3:0]
avl_address[31:0]avl_byteenable[3:0]
avl_clk[1]
avl_read
avl_writedata[31:0]avl_write
avl_reset_n
pio_reset_n
avl_waitrequestavl_readdata_validavl_readdata[31:0]
reset_nref_clk
avl_clk[0]
correct_data_counter[15:0]pass
avl_reset_n
locked
done
locked
pass
group_0_strobe_out
Altera PHYLIte IP core
User logic
Hardware Design Example User Guide
System Requirements
The following are the software and hardware requirements to run the hardware reference design.
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Software Requirements
1. Quartus Prime Design Suite version 15.12. Altera Complete Design Suite versions 13.13. Hardware reference design phylite_top_1DQS_2DQ_800MHz.par file
Hardware Requirements
1. Arria 10 FPGA development kit2. Loopback FPGA mezzanine (FMC) daughter card3. USB-Blaster™ download cable
Related Information
• AN 747 Altera PHYLite with Dynamic Reconfiguration Reference Design Files• Getting Started with the Design Store
Guideline to download and install design examples from Design Store.
Setting Up the Development Kit
The following steps are to setup the Arria 10 FPGA development kit before running the reference design.
1. Make sure the Arria 10 FPGA development board switches settings are shown as below.Figure 11: Switches Settings for Arria 10 FPGA Development Kit
2. Connect the USB-Blaster cable to the Arria 10 FPGA development kit and your host machine.3. Follow the guidelines in Getting Started with the Design Store to download and install the reference
design files.4. Open the reference design .qpf file after successfully installing the design templates.
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5. In the Quartus software, open dut_INPUT.qsys and dut_OUTPUT.qsys files. Make sure the Altera PHYLiteIP core has the same configurations shown below:
Figure 12: Configuration for dut_INPUT Module
Figure 13: Configuration for dut_OUTPUT Module
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6. Click Tools -> Programmer to program the <project directory> /master_image/top.sof and <projectdirectory>/master_image/max5.pof files into the Arria 10 FPGA development board.
7. In the <project directory>/core/ folder directory, copy the clk_gui.zip folder to your local machine.8. In your local machine Quartus II software installation version 13.1 folder, go to <installation directory>\
win64\nios2eds\Nios II Command Shell.bat and execute NIOS II Command Shell.bat.9. In the command shell, specify the clk_gui folder path with the command: cd <directory to
the copied clk_gui folder>.10.Use the command java -jar clk_cont.jar to launch the clock control GUI.11.In the clock control GUI, set the target frequency as 50MHz for Si570 (X3) window. Click Set New
Frequency.Figure 14: Clock Control Setup
Related InformationGetting Started with the Design StoreGuideline to download and install design examples from Design Store.
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Generating Executable and Linking Format (.elf) Programming File
Follow the steps below to generate an executable and linking format (.elf) programming file. These stepsare necessary if you modify the phylite_dynamic_reconfiguration.c, phylite_dynamic_reconfiguration.h andhello_world.c files.
1. In the Quartus Prime software version 15.1, select Tools > Nios II Software Build Tools for Eclipse .2. Create a new workspace when the Select a workspace window prompt appears.3. A Nios II - Eclipse window appears. Select File > New > Nios II Application and BSP from
Template .4. In the SOPC Information File name parameter, browse to the location of phylite_nios.sopcinfo file in
your host machine. Click OK to select the file and Eclipse automatically loads all CPU settings.5. In the Project name parameter, specify your desired project name. This example uses
phylite_nios_1DQ2DQS_new.6. Choose Hello World as the project template.7. Click Finish to generate the project. Quartus Prime software creates a new directory named software in
the specified project location.
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Figure 15: Nios II Application and BSP from Template Settings
8. Replace the following files from <project directory>/software reference design with the files located inyour new software directory.
• hello_world.c• phylite_dynamic_reconfiguration.c• phylite_dynamic_reconfiguration.h
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9. In the Nios II - Eclipse window, press F5 to refresh the window and reload the new files into theproject.
10.Click Project > Build Project.11.Make sure the phylite_nios_1DQ2DQS_new.elf file is generated in the new <project directory>/software/
phylite_nios_1DQ2DQS_new/ directory.
Running the Hardware Reference Design
Follow the steps below to run dynamic calibration and start the data transfer for the hardware referencedesign.
1. In the Quartus Prime software installation directory in your host machine and double click on Nios IICommand Shell.bat to launch the command prompt window (command prompt A). Repeat this stepto launch the second command shell (command prompt B).Command prompt A is to display the dynamic calibration result. Command prompt B is used to runNios II commands.
2. In command prompt A, use the following command to run the Nios II terminal application for resultprintouts.nios2-terminal
3. In command prompt B, go to the project top directory.cd <project directory>
4. Run the issp.tcl script once to reset the system and clean up the instruction memory in the Nios II softprocessor.quartus_stp -t issp.tcl top.qpf 1 1
Note: Ignore the failing dynamic calibration result displayed in command prompt A. This is the resultfrom the original executable code in the Nios II memory and is not relevant to the designexample.
5. In command prompt B, download the executable (phylite_nios_1DQ2DQS_new.elf) file into the FPGAand start the dynamic calibration process with the following command:nios2-download -r -g software/phylite_nios_1DQ2DQS_new/phylite_nios_1DQ2DQS_new.elf
You may observe the passing dynamic calibration result displayed in command prompt A.6. When the Nios II instruction memory is cleaned and calibration is done, run the following command
in command prompt B to reset the system, start the random data transfer and capture internal signals.quartus_stp -t issp.tcl top.qpf 1 1 1
Note: You will see sent and received data displayed in command prompt B after running thecommand.
ResultThe hardware reference design provides:
• Dynamic calibration result• Random data transfer result
Dynamic Calibration Result
The following screen capture shows the dynamic calibration result of the hardware reference design.
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Figure 16: Dynamic Calibration Result
The screen capture includes:
• Sent and received data.• Indication of dynamic calibration has passed.• Indication that the configuration is done.• The value of the window start phase, window end phase, centered output phase and the strobe enable
window width.
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Random Data Transfer Result
The result log from the random data transfer process displays the following:
• The number of words being transferred• The sent data value• The expected data value• The received data value• The passing/failing status of the test
Figure 17: Example of Random Data Transfer Result Log
Functional Description
Device Under Test (DUT) Module
The DUT module consists of two Altera PHYLite IP instances:
• 4-bit dut_INPUT module• 4-bit dut_OUTPUT module
The function of the dut_INPUT module is to:
• Receives data aligned to strobe edge from external I/O interface.• Receives rdata_en signal from traffic generator.• Transmits data from external I/O interface to the traffic generator.
The function of dut_OUTPUT is to:
• Receives data, strobe, and output enable from the traffic generator.• Transmits edge aligned data and strobe to external I/O interface.
The DUT module in the hardware reference design also consists of a PHYLite Avalon Controller. Thefunctions of the PHYLite Avalon controller includes:
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• To perform address translation for each reconfigurable feature of the PHYLite IP.• To cache all necessary settings for each reconfigurable feature of the PHYLite IP.• To translate Nios II soft processor commands into PHYLite commands.
Traffic Generator
The traffic generator module is called tg and is located in the tg.v file.
The functionality of the traffic generator includes:
• Continuously generates data to dut_OUTPUT module through Linear Feedback Shift Register.• Asserts rdata_en signal to dut_INPUT module to read the loopback data from dut_OUTPUT module.• Compares received data against the regenerated/transmitted data.• Increments correct_data_counter for every correct data received. The correct_data_counter is a 15-bit
counter.• Asserts the done signal to indicate all data has completely received correctly.
In the hardware design example, the traffic generator sends out loopback data for comparison after NIOSII processor completes the calibration process.
NIOS II Soft Processor
The Nios II soft processor calibrates read and write operations. The Nios II interfaces with the DUTmodule through the Avalon Controller.
Dummy PHYLite
Due to the limitation of the Arria 10 development board, this module is required to enable the designexample to connect a reference clock to the DUT module data pins.
In-System Sources and Probes (altsource_probe) Module
This module is an in-system debugging IP. You can use this module to drive and capture the behavior ofthe internal signals in the design example. This module is only used in the hardware design example.
Design Example Software
The hardware design example requires hello_world.c, phylite_dynamic_reconfiguration.c and phylite_dynamic_reconfiguration.h files to run.
The hello_world.c file function is to identify the strobe enable window. The phylite_dynamic_reconfigura‐tion.c and phylite_dynamic_reconfiguration.h are the library files used by hello_world.c file. Thefind_strobe_enable_window() function in the hello_world.c performs calibration algorithm as follow:
• Read the initial output strobe phase from ODELAY CSR.• Configure and update new output strobe phase delay.• Verify the new output strobe phase delay with test data.• Sweep across a range of output strobe phase delays to identify valid strobe capture window.• Find the center output strobe phase from the valid strobe capture window.
You can configure the delay for DQS, DQ[0] and DQ[1] values to achieve better results. This referencedesign, configures only the DQS value.
Related InformationAltera PHYLite for Parallerl Interface IP Core User Guide
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Document Revision HistoryTable 1: Document Revision History
Date Version Changes
January 2016 2015.01.19 Updated reference design file links andsteps to download and install the referencedesign files.
December 2015 2015.12.11 Initial release.
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