reconfigurable computing for dsp
DESCRIPTION
Reconfigurable Computing for DSP. Kazem Cheshmi May 2010. Class presentation for the course: “ Custom Implementation of DSP Systems ” All the materials are copy rights of their respective authors as listed in references. Outline. Reconfigurable Computing[2,3] Introduction Coupling - PowerPoint PPT PresentationTRANSCRIPT
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Kazem Cheshmi
May 2010
Class presentation for the course: “Custom Implementation of DSP Systems” All the materials are copy rights of their respective authors as listed in references.
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OutlineReconfigurable Computing[2,3]
IntroductionCouplingRun-time configurations
Reconfigurable Computing for DSP[4]Motivations[2]
An example of DSP application[1]CPAC architectureSystem level integrationResults
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Implementation methods
Hard wired technology
Software programmed processor
Third method : Reconfigurable Computing[4]
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Coupling
[3]
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Run-Time ReconfigurationReconfigurable models
[3]
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Reconfigurable Computing for DSPSpecializationFlexibility
Field customizationSlow adaptationFast adaptation
Parallelism[4]
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Motivations There are two design methods:
General purposeEspecial purpose
Motivations to especial purpose:Digital signal processingWord-length optimization
Area reduction of up to 80%, power reduction up to 98%, and speedup up to 36%
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MotivationOther
MultimediaCHAMPION IGOL(hardware plug-in)SA-C(image processing)
NetworkingConvert Ponder(network policy description) to
hardwareConvert Click to efficient hardware
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CGRA Coprocessor Targeting DSP KernelsCo-porocessor
dedicated hardwareSIMDreconfigurable architectures (RAs).
CPACfunctional unit extensionSIMD acceleratorDSP kernel accelerator
G.723.1 codec (part of the H.324 standard)
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CPAC ArchitectureSingle context
Architecture PartsHost Interface
3 FIFO portsMemory
Tightly loosely
PE
[1]
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Processing Elements in CPAC
[1]
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Computational ModelModel 1
r e s u l t = (a − b) ∗ c ;Model 2
for ( j = 0; j < 100; j ++ )r e s u l t = (a [ j ] − b [ j ] ) ∗ c ;
Model 3for ( i = 0; i < 100; i ++ ) {
d i f f = 0;for ( j = i ; j < 100; j ++ )
d i f f = (a [ j ] − b [ j − i ]) ∗ c ;result [ i ] = di f f ;
}
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ConfigurationConfiguration time
Programming scenario:1. Configure vector definition registers.2. Download data vectors.3. Configure processing elements.4. Start computation.5. Synchronize by performing a blocking read
operation to the result FIFO.
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System Level IntegrationGPP is used to configure, communicate
data and scheduling tasks on co-processor
Processor InterfaceMapping Functionality
[1]
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ResultsCP-2 in inst per frame(CPI>=1)DSPs are hand-optimized
[1]
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Refrences[1] H.Svensson, “Reconfigurable Architectures for Embedded Systems,”
PHD thesis, The Department of Electrical and Information Technology Lund University, September 2008
[2] T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung,:”Reconfigurable computing: architectures and design methods”, IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, March 2005
[3] K.Compton, S.Hauck, : ‘Reconfigurable computing: a survey of systems and software’, ACM Comput. Surv., 2002, 34, (2), pp. 171–210
[4] R.Tessier ,W.Burleson, “Reconfigurable Computing for Digital Signal Processing : A Survey” , Journal of VLSI Signal Processing 28, 7–27, 2001.
[5] S.Hauck, A.DeHon, “RECONFIGURABLE COMPUTING THE THEORY AND PRACTICE OF FPGA-BASED COMPUTATION”, 2008 by Elsevier Inc.
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