realization of ip core for robot controlled trenching...

Realization of IP Core for Robot Controlled

Trenching System

C. S. Mala*, S. Ramachandran#

* Jawaharlal Nehru Technological University, Hyderabad, # SJB Institute of Technology, Bangalore

[email protected], [email protected]

ABSTRACT

An IP Core of a Robot based Trenching System has

been designed modeled on Intel‟s 8051

Microcontroller. The designed IP Core realizes all

256 instructions of 8051 and also the resources

available on a generic 8051 chip. The designed

system has both internal and external ROM and

RAM, an address generator, and a decoder.

Realization includes the timer functions, serial

communication and interrupts. A comprehensive

test bench has been developed and all instructions

and the resources on chip have been fully tested.

The code is RTL compliant and is Technology and

Platform Independent. It features a high degree of

parallelism and heavy pipelining targeted on FPGA

or ASIC. The designed system is more efficient in

terms of processing speed by over 7 to 50 times

when compared to the original Intel‟s 8051. With

this design, 8051 microcontroller would be given a

new lease of life even when it becomes obsolete

with time.

The agricultural implement IP Core design has been

primarily targeted on the Xilinx, Spartan 3 FPGA

and works at a conservative operating frequency of

50 MHz.

KEYWORDS

IP Core, Verilog, Register Transfer Logic, Robot,

Agricultural Equipment, Trencher, Automation.

1. INTRODUCTION

8051 based system has been designed using

Verilog to speed up processing and the

resources on an FPGA or an ASIC. The IP

Core developed can be used for all applications,

even for a past product, or for the ongoing

current project or for future applications. In the

present work, this IP core design is being

implemented for an agricultural application.

Yuanyuan et al. [1] have developed a Single-

Chip Speech Recognition System based on

8051 Microcontroller. However, this work

does not realize the 8051 core. The authors

have claimed ten times lower cost than a DSP

core. A. Moore, Scott [2] and Aviral Mittal [3]

have developed IP Cores for 8080 CPU (using

Verilog) and 8085 (using VHDL) respectively.

R. V. Siva Reddy, S. Ramachandran and K.

Nagabhushana Raju [4] have developed IP

Core for 8085 in Verilog conforming to RTL

guidelines and have used the Core for

Electrostatic Precipitator Processor which has

achieved significant speed of operation (over 30

folds) compared to 8085 based systems used

presently in the thermal power plants. In order

that a design may work on a chip without any

hassles, RTL conformance is inevitable [5].

N. Noguchi et al. [6] have automated

agricultural system for field applications. The

authors have developed a robot for agricultural

operation. They have used navigation sensor, an

RTK-GPS and an inertial measurement unit

(IMU) for navigation through the field.

However, this implementation is tractor

mounted and is expensive.

K. C. Jones [7] has implemented robots to weed

out farms which make their way through a field

with precision weed-destroyers onboard. The

International Journal of New Computer Architectures and their Applications (IJNCAA) 2(4): 531-549 The Society of Digital Information and Wireless Communications (SDIWC) 2012 (ISSN: 2220-9085)

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mailto:[email protected]

Robot itself weighs about 450-650 pounds and

does not completely do away with human

labour.

D. W. I. Brooke [8] claims to have improved

the performance of existing tractor mounted

agricultural system. His stress was more

towards automating for improved energy

management including waste recycling.

Zhang. X et al. [9] have developed an electronic

controlled platooning system, which will enable

an autonomous agricultural vehicle to follow a

leading tractor with a given lateral and

longitudinal offset. He has employed RTK GPS

system and wireless Modems for positioning

and tracking of the Tractor.

Chen Jun et al. [10] described an agricultural

mobile robot which was refitted by FT4040

tractor. The tracking control was researched

using fuzzy logic. The stress was more on

designing a fuzzy controller for straight-line

tracking.

In Eaton. R. et al. work [11], the autonomous

farm is seen as a complex system, which deals

with issues of agronomy. The agricultural

robotics uses on-farm sensing and control to

actuate autonomous farm machinery with the

aim of satisfying agronomy-based objectives.

The preliminary results highlight the

autonomous control of vehicles for the

operations of crop seeding and non-herbicidal

weeding.

The present work aims at developing the IP

Core of 8051Microcontroller system for Robot

Based Agricultural Implement such as a

Trencher, which would automate the trenching

operation and reduce considerable amount of

cost, labor and time. To dig a 1 KM trench

manually, about 100 man days are required

incurring quite a large expenditure. It is also

difficult to muster so many laborers in time to

meet the schedule. In contrast, the proposed

trencher can dig the same trench in about 2

hours, incurring far less expenditure. The

trenching operation can be used for agricultural,

waste land, dry land, horticultural and forest

developmental activities. It can be used to form

trenches to plant areca nut, papaya, banana,

apple, chickoo (sapota), mango, sugarcane etc.

as per the recommended spacing. In the

agricultural area, it finds vast applications such

as eliminating perennial weeds, forming cross

drains in sloppy terrain to avoid soil erosion

and retain soil moisture. It makes agriculture

more profitable. It can also be used to form

seepage drains in submerged soil. In addition to

these applications, it can also be used for laying

telephone cables along the road side, fencing,

compound walls, and laying irrigational pipe.

With the intent of improving the throughput

and reducing the system cost, the Intellectual

Property (IP) Core is targeted on an FPGA. It

may also be implemented as an ASIC.

The paper is organized as follows. Section 2

presents the basic Architecture of a Robotic

system for automating trenching operations.

Section 3 presents the implementation of the

designed IP Core of the Micro Controller

System. Section 4 presents the development of

Algorithmic State Machine (ASM) charts for

the development of the IP Core. Various groups

of instructions are implemented in this work

and the processing speed achieved is compared

with that of the Intel‟s 8051 Microcontroller

[12-14]. The simulation results are presented in

Section 5. The last section presents the

conclusions derived as well as scope for future

work.

2. BASIC ARCHITECTURE OF THE

PROPOSED ROBOT BASED

AGRICULTURAL TRENCHING

SYSTEM

This work proposes the complete development

of the IP Core for 8051 microcontroller for

automating trenching operations for agricultural

and other applications as described in the

previous section. The trencher is currently

tractor mounted. In the proposed work, a

driverless Robotic vehicle system is being

designed in order to speed up trenching work.


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The length and breadth of the field along with

the spacing between the trench lines are made

user programmable. To commence the

trenching operation of a farm land the Robotic

vehicle along with the trencher equipment is

positioned as shown on the top left of Fig. 1.

The farmer with little training specifies the

length, breadth and spacing using the keyboard

on the vehicle. The ploughing operation

commences once the start button is pressed.

The vehicle moves forward and trenches the

field for the specified length, thereafter raises

the trencher off the ground and moves to the

next line and repeats the same operation in the

opposite direction. This operation goes on line

by line in a particular order until the entire field

is trenched. After the completion of the last

row, the vehicle stops and gives out a signal

indicating that the task has been completed.

Top view of the Robotic Vehicle is presented

in Fig. 2.

2.1 FPGA Based Controller

The FPGA based Controller is the central

control unit of the system used to control and

coordinate all the functions of various

devices such as keyboard, LCD display, lift,

wheels of the Robotic Vehicle and also the

trencher. The vehicle with trencher fixed on

it is positioned in the field. Safe initial

positions of the Robot vehicle system are

ascertained before starting the vehicle. Then the

vehicle is activated by the FPGA based

Controller and the trencher trenches the field

forward until it reaches the end of the field

length. On reaching the end, the Robot lifts the

trencher off the ground and takes a turn to the

next line. This process is repeated until the field

is trenched completely.

2.2 Robotic Vehicle

This is the heart of the system. It facilitates the

forward movement of the vehicle by aligning

the wheels straight for forward movement. The

vehicle is also capable of moving in the reverse

direction.

2.3 Key Board and LCD Display

All user inputs like area of the field whose

length and breadth are to be trenched and

spacing between trench lines and the depth to

which the trencher has to trench are entered

through the keyboard. These keyed in

parameters, which depend upon the crop to be

grown, can be viewed on the LCD display.

2.4 Lift

The trencher is connected to the lift. The

vehicle is initially positioned in the field with

the trencher off the ground with the help of lift.

The lift lowers the trencher on to the ground

when the trenching operation begins. The

trencher is lifted off the ground while turning to

the next line and when an obstacle is

encountered during trenching. The trencher is

always on the rear end of the vehicle while

travelling along the length.

3. ARCHITECTURE OF THE IP CORE

The architectural design of the IP Core of the

Micro Controller system that emulates Intel‟s

8051 is presented in Fig. 3. The architecture

consists of the following blocks:

Internal RAM/ROM, External RAM/ROM,

Special Function Registers (SFRs), Input/output

Ports, Address Decoder, Address Generator,

Timers, Interrupts, and Serial Communication.

These blocks are described in the following

sections.

FP

IP posit

ionn pos

n

post

npo

Spacing between trench lines

Length

B

r

e

a

d

t


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Figure 1. Proposed Trenching Pattern

IP : Initial Position of Trencher

FP: Final Postion of Trencher

Figure 2. Top view of the Robotic Vehicle

W: Wheels

Figure 3. Architecture of Micro Controller IP Core as

Implemented

3.1 Memory Design

A flexible memory size has been designed for

the internal RAM, internal ROM, external

RAM and external ROM. The Program and

Data Memory Map are presented in Fig. 5 and

Fig. 6 respectively along with their memory

select external access (ea_n) signal. Internal

RAM is organized into three distinct types:

Register bank, bit addressable RAM, and

scratch pad area respectively. Register banks

occupy the address space of 0 to 1F H. Sixteen

8-bit locations, 20 H through 2F H are bit

addressable. This gives rise to 128 bit locations.

Each of these bits can be directly accessed

using their direct address. A unique algorithm

has been developed to identify the bit address

specified in the instruction. Scratch pad

locations can store any temporary data bytes

and are addressed in the range: 30 H through

7F H.

3.2 Special Function Registers

Special Function registers are available as On-

Chip RAM Memory. Many of these SFRs are

bit addressable and their names are specified in

instructions. The SFRs in the system are

Accumulator (A), B registers and bits of PSW.

Timer or Counter functions are realized by

using Timer Mode Control (TMOD) and Timer

Control (TCON) flags. Serial Communication

is effected by the usage of SCON (Serial

Control) and Serial Buffer registers

(SBUF_TXD, and SBUF_RXD). Interrupt

functions are taken care of by IE (Interrupt

Enable) and IP (Interrupt Priority) SFRs. The

only registers that are 16 bits wide are PC and

DPTR (Data Pointer). PC holds the address of

the current instruction being executed. DPTR is

used for external memory access to hold the

address of the external RAM or ROM as the

case may be. Stack Pointer (SP) is used to keep

track of the internal stack, which is a part of the

internal RAM.

KB

Depth

in

mts

start

FPGA Based System

Lift

LCDS

W W

W W

EXTERNALLY IMPLEMENTED

D0-D7 PSEN

CS0 CS0

Bus control Control

Control

INTO INT1

CPU

Clock

ROM RAM

Timer 0

Timer1

I/O Ports Serial

Port

Interrupt

Control

PO P1 P2 P3 TXD RXD

T0

T1

EA

Address

Decoder

Rd WR

External RAM

CS1

Address Generator External ROM

A0-A15

A0-A15

D0-D7

A15

A8-A15 AD0-AD7 ALE

ONCHIP

T1

T1

CS0

1

A0-A15

A0-A15


534

3.3 Input and Output Ports

The system has four ports designated as Port 0,

1, 2 and 3. The data and address bus are

multiplexed and is available at Port 0. ALE

signal is used to latch the address from the time

multiplexed bus. Port1 functions as pure input

or output line. Port 2 has independent higher

order address bus, whereas Port 3 has multiple

functions such as event counters, interrupts

serial communication and read/write control

signals. All individual bits of these ports are bit

addressable.

3.4 Address Decoder

The Address Decoder provides the chip

selection signals for the External ROM and

RAM. Chip select signal for ROM is “cs_0”

and that for RAM, it is “cs_1”.

3.5 Address Generation

The microcontroller designed has time

multiplexed lower order address and data bus

designated as AD0-AD7 and is available on

Port 0. The Address lines A8–A15 are

independently available on Port 2. For external

memory access, 16 bit address is required. The

lower order address data bus is de-multiplexed

using Address Latch Enable (ALE) signal.

8051 ea_n = Vcc 8051 ea_n = 0

Figure 4. Mapping of Program Memory

Figure 5. Mapping of Data Memory

The higher order address bus and lower order

de-multiplexed address bus are concatenated to

get a 16 bit address.

3.6 Timers/Counters

Timing of events is essential for successful

operation of the Robot based Agricultural

Implement System. In order to maintain timing,

two hardware timers, Timer 0 and Timer1 of

sixteen bits each are designed. Timer registers

increment once every rising edge of the clock

and continues to increment till the terminal

count is reached. The Counters also function in

the same way but counts the external pulses that

appear on T0 and T1 port pins. For both Timers

and Counters, the last count is 1FFF H for

mode 0. For mode 1, it is FFFF H and for mode

2, it is FF H. Timer 0 is designed to work in

Mode 3, which is called as split timer mode,

where TH0 and TL0 function as two 8 bit

timers. The Algorithmic State Machine chart

for the realization of Timer 0 and Timer 1 in

Mode 0 is presented in the next section.

Simulation waveforms for Timer 0 in Mode 1,

Timer 0 in Mode 3 and Timer 1 in Mode 2 are

also presented as examples. Timer 1 operating

in Mode 2 is important in serial communication

as it is required for deciding the baud rate of

transmission and reception.

1000 H

External

External

and

Internal

or

FFFF H

0000 H

FFFF H

0FFF H

0000 H

Internal

7F H

and

FFFF H

00 H

External

0000 H


535

3.7 Interrupts

The microcontroller IP Core features six

interrupts including a reset. Two of them are

external hardware interrupts from external

source named “INTO_n” and “INT1_n”. In

addition to these, there are three internal

software interrupts: two from timer flags TF0,

TF1 and the third from serial communication

flag TI or RI. Reset is a non maskable highest

priority interrupt. Other interrupts can be

masked and prioritized using IE and IP SFRs

respectively. The Interrupt vector table

addressed from 1000 H is realized as 256 bytes

reserved for each Interrupt Service Routine

(ISR) in contrast to only 8 bytes per interrupt

vector address in the original 8051. The starting

addresses of the interrupt vector table for INT

0, INT 1, Timer 0, Timer 1 and, interrupts

generated during serial communication are

1000 H, 1100 H, 1200 H, 1300 H and 1400 H

respectively.

3.8 Serial Communication

The serial port of 8051 is full duplex. Serial

data is transmitted on TXD port pin and

received on RXD pin. Eight bits of data

representing a character can be sent or received

in 8 clock pulses. Transmit SBUF

(SBUF_TXD) holds the 8 bit value to be

transmitted. As soon as all the eight bits are

transmitted, TI flag is raised to indicate the

completion of transmission of data in

SBUF_TXD. Similarly, receive SBUF

(SBUF_RXD) receives serial data sent on RXD

pin. RI flag is raised when all 8 bits of data has

been received by SBUF_RXD. The ASM chart

for serial communication is presented in the

next section. The simulation waveform for

serial transmission and reception is presented in

Section 5.

4. DEVELOPMENT OF ALGORITHMIC

STATE MACHINE

The proposed system emulates the existing

8051 based system completely. The system is

primarily realized as an FSM. The process

Algorithm may be easily designed using

Algorithmic State Machine charts [5] rather

than by the traditional state diagram.

When the system is switched on, a power on

reset signal is issued taking the processor

system to initialize the internal registers and

then the microcontroller system enters state

“0”. The ASM chart for the internal and

external Op code fetch operation starting from

state 0 is depicted in Fig. 6. In state 0, the

processor initializes the ROM address and

program counter (pc) address to 0. The program

counter and the address bus “rom_addr” are 16

bits wide. In state 1, the address is checked to

see whether it is internal ROM access or

External ROM access. If the pc address is less

than 4 K bytes, then with the arrival of the

clock, the address bus derives the 16 bit ROM

address of the program counter. The “Op Code

Fetch” starts from internal ROM as shown in

state 2; otherwise the next state branches to

state 5 meant for external ROM access. The Op

code fetched from the internal ROM in state 2

is examined in state 3 and depending upon

which instruction is being fetched, the control

goes to other states to execute the Instruction

fetched. If the pc address is greater than 4K

bytes, then the control goes to state 5 indicating

that the Op code is to be fetched from external

ROM. In state 5, various control signals such as

the read (“rd_n”), write (“wr_n”), address latch

enable (“ale”) and external access (“ea_n”)

signals are initialized.

As an example, the execution of MOV

instruction is shown in Fig. 7. The external

ROM fetch for the processing of the instruction

stored in external ROM begins from state 500.

In this state, the address of the data from

external ROM is fetched first for which “ale” is


536

asserted to latch lower order address bus. Then

the control branches to state 501, where the

“ale” signal is deactivated. Next, in state 502,

“psen_n” signal is activated and then the data is

read into the Accumulator.

The Op code fetch starts from state 2 for

Internal ROM Access. The ASM chart for the

execution of instruction ADD A, #R0 is shown

in Fig. 8. The Op code fetched in state 2 is

processed from state 3. The content of R0

register is stored in a temporary register (temp).

In state 154, contents of R0 stored in temp is

added with the contents of the Accumulator and

stored in a register with carry and the sum.

Auxiliary carry is also determined and stored in

a register temp3. Parity is also determined and

is stored in a Parity “P” bit. In state 166,

auxiliary carry determined is stored in AC flag

register and the control goes to state 1 to

process the next instruction.

As examples, the ASM charts for processing a

couple of instructions such as “DJNZ R0, code

address” and bit manipulation instruction “ANL

C, bit address” are shown in Fig. 9 and Fig. 12

respectively. In bit manipulation instruction, an

unique algorithm has been developed in this

work to identify the bit specified in the

instruction. The ASMs developed for these

features can be analyzed in a similar manner to

that presented earlier.

ASM for Serial Communication is presented in

Fig 10. In State 1, the Timer1 receives the

count for the desired baud rate. Timer flag

“tr1” is checked in state 2. If it is ready, then

the timer starts counting. After running for the

desired time as shown in states 2, 3 and 4, the

SCON register is checked in state 5 to see

whether it is serial transmission or reception. If

SCON is 40 H, then from state 6 all the eight

bits of data in SBUF_TXD are transmitted bit

by bit and then the TI flag is set as seen in state

8. Thereafter the control returns to state 0. If

SCON is not 40 H, then SCON is checked for

50 H which is for reception of serial data. If it

is 50 H, then the reception of data begins from

state 9 and the data on RXD line is received bit

by bit into SBUF_RXD. Once all 8 bits are

received, then RI flag is raised high as shown in

the state 11 and the control returns to state 0. If

SCON is neither 40 H nor 50 H, then the

control returns to state 0. The simulation

waveform for the same is presented in the next

section.

The ASM chart for the functioning of Timers in

Mode 0 is depicted in Fig.11. In state 0 the

Timer 0 and Timer 1 registers are initialized to

zero. In state 1, the desired count values are

loaded into Timer 0 and Timer 1 registers. In

state 3, 8 bits of TH0 and 4 bits of TL0 registers

of Timer 0 is concatenated to get a 13 bit timer.

Likewise, TH1 and TL1 registers of Timer1 are

concatenated. In state 3, the timer run bits “tr0”

and “tr1” for Timer 0 and Timer 1 respectively

are checked to see if they are activated. If “tr0”

is activated, then in state 4, Timer 0 begins to

advance every clock cycle and in state 5, it

checks for the rollover after the terminal count

of 1FFF H is touched for Mode 0. If the

terminal count is not reached then Timer 0 goes

back to state 4 to increment every cycle.

Otherwise, the timer flag 0 “tf0” is raised high

to indicate that the counting is completed and

the control returns to state 0. Timer 1 in Mode 0

functions in a similar way. Timer 1 is

incremented in state 6 and checked for the

terminal count in state 7 and after reaching the

terminal count, during the roll over “tf1” flag is

set and the control returns to state 0. The

simulation waveforms for timers are presented

in the next section.

Byte and bit manipulation instructions are

realized in Immediate, Register, Direct and

Indirect Addressing Modes in the present work.

All the 8051 instructions have been coded.

Table 1 presents some of the instructions

realized along with their processing times. Each

instruction is presented in different addressing

modes. The execution speed of the proposed

Verilog realization of our system is also


537

Figure 6. ASM Chart for Processing Sample Instructions

Figure 7. ASM Chart for Data Transfer Instruction

Figure 8. ASM Chart for Arithmetic Instruction

Figure 9. ASM Chart for Jump Instruction

Execution from External ROM

Op Code: 74 MOV A, #data

Go to State 5

502

501

500

Addr15_8 = pc [15:8]

D2 = pc [7:0]

ale = 1

psen_n = 1

wr_n = 1

rd_n = 1

ale = 0

psen_n = 0

read_cnt = 0

pc = pc + 1

psen_n = 1

A = ad_ext

OP CODE : D8 DJNZ R0, ADDR

Go to State 1

temp = ram(addr_R0)

rom_addr = pc

temp = temp + 1

pc = {pc[15:8],ad}

pc = pc + 1 temp = 0?

rom_addr = pc

3

290

NO

YES

292

OP Code: D8 DJNZ R0, ADDR

Go to state 1

OP Code: 28 ADD A, R0

temp = ram[addr_R0]

{CY,A} = A + temp

temp3 =A[3:0]+temp[3:0]

(^(A+ad)=0)? =1?

P=1

AC = temp3[4]

3

154

653

No

3

166

3

yes

3

P =0


538

Figure 10. ASM Chart for Serial Communication

Figure 11. ASM Chart for Timers in Mode 0 Operation

Go to state 0

to state 0

Go to state 0

to state 0

No

O

Go to state 1

TL1=0?

yes

1

2

SBUF_RXD[y] = RXD

TXD = SBUF_TXD[x]

tr1=1?

3

TL1 = TH1

62

TL1 = TL1 + 1

SCON =40h? SCON=50h?

7

No

yes

N

O

No

O

tf1 = 1

yes

yes

No

es

yes

Noyes

No

yes

x = x + 1

x=8?

TI = 1

10

9

6

2

y = y + 1

No

yes

y=8?

RI = 1

Go to state 0

TH0 = 0

TL0 = 0

TH1 = 0

TL1 = 0

tr0=1?

tf1 = 1

0

1

Go to state 1

2

Timer 0 Mode 0/Timer1 Mode0

Timer1 mode02

TH0 = xx0

TL0 = yy0

TH1 = xx1 TL1 = yy1

T0M0 ={ TL0 [4:0],TH0[7:0] } T1M0 = { TL1 [4:0],TH1[7:0]}

tf0 = 0

tf1 = 0

tr1=1?

T1M0 = T1M0 + 1

42

62

T0M0 = T0M0 + 1

T0M0=1? T1M0=1???

No

O yes yes

N

O

No

O

tf0 = 1

46

2

7

No

3

4

2

yes yes

0 Serial Communication

TH1 = baud, TL1 = 0 TI = 0, RI = 0

x = 0 , y = 0

tf1 = 0


539

OP Code: 82 ANL C, BIT_ADDR

Figure 12. ASM Chart for Bit Manipulation Instruction

compared with the existing Intel‟s 8051

microcontroller. The proposed implementation

scores over the 8051 especially for instructions

such as “MUL AB” and “DIV AB”. As can be

seen from Table 1, the proposed IP Core is

faster than the existing 8051 systems by over a

range of 8 to 54 times.

5. SIMULATION RESULTS

The complete IP Core was coded in RTL

compliant Verilog. The simulation was run on

Modelsim and the results for various groups of

instructions such as data transfer, arithmetic,

logic, bit manipulation and external ROM

access are presented in this section. The

processing times of individual instructions are

presented in Table 1. It may be noted that the

waveforms are in conformity with the execution

of the instructions of the Intel‟s 8051

microcontroller. The Timer operations have

also been realized.

The simulation waveform for data transfer

instruction is presented in Fig. 13. As an

example, execution of “MOV A, #54 H” is

shown in the waveform. The Op code for this

instruction is 74 H. This instruction transfers 54

H data into the “A” register as revealed in Fig.

13. The first signal from the top is the system

“clk” operating at 50 MHz frequency. Both the

“pc” and the “rom_address” are 0. The “state”

represents the current operating state of the

controller. The “ad” bus has 74 H on it to

indicate that the first fetch is the Op code. Next

fetch from the ROM is the data 54 H. On the

“ad” line, 54 H appears at the appropriate time.

The total number of cycles taken to complete

this instruction is 80 ns, i.e., 4 clock periods.

This timing is presented in Table 1.

Fig. 14 presents the Arithmetic operation

“MUL AB” and “DIV AB”. The Op code for

multiplication is A4 H and that of division is 84

H. For “MUL AB” operation, the “A” register

contents are FF H and that of B register is FF H

before the execution of the instruction. After

the execution, “A” register has 1, being the

lower byte of the product and, the upper byte

FE H is stored in register B. Similarly “DIV

AB” instruction divides A by B and the LSB

result manifests in A register while the

remainder appears in B. It takes 4 clock cycles

to execute each of these instructions and is

tabulated in Table 1.

The simulation waveform for “DA A

“instruction is shown in Fig. 15. After the

addition of two numbers 59 H and 54 H, “A”

register is adjusted for BCD result which is

equal to decimal number 13.

The simulation waveform for Logical

instruction is presented in Fig. 16. The

instruction “ORL A, #33 H” performs the

bitwise ORing of the accumulator content “DF

H” and the immediate data 33 H producing the

result “FF H. The operation takes 100 ns.

3

3 rom_addr = pc

temp1 = ad/8

temp2 = ad%8

temp1 = temp1 + 20 H

temp = ram [temp1]

225

226

227

bit1 = temp [temp2]

228

cy = cy & bit1

pc = pc + 1

229

Go to state 1


540

Table 1. Comparison of Execution Speeds of Instructions: Proposed IP Core vis-a-vis the Intel‟s 8051 (Continued)

Sample Instructions

Proposed

8051 IP Core

Intel’s 8051

Microcontroller

No. of

clock

cycles

Processing speed

in nanoseconds

working @ 50 MHz

No. of

clock

cycles

Execution speed

in nanoseconds

operating @

11.0592 MHZ

INTERNAL RAM OPERATIONS

Data transfer Instructions

MOV A, # data 4 80 12 1085

MOV A, R0 4 80 12 1085

MOV @R0, # data 6 120 12 1085

MOV data addr, R0 7 140 24 2170

CLR A; CPL A; INC A 4 80 12 1085

RR A; RRC A; RL A

RLC A

4 80 12 1085

INR reg; DCR reg 4 80 12 1085

INR data addr

DCR data addr

4 80 12 1085

Stack Instructions

PUSH direct addr

POP direct addr

6 120 24 2170

Arithmetic Instructions

ADD A, data addr

ADDC A, data addr

7 140 12 1085

ADD A, #data 6 120 12 1085

SUBB A, #data

SUBB A, data addr

7 140 12 1085

SUBB A, reg 6 120 12 1085

MUL AB; DIV AB 4 80 48 4340

DA A 8 160 12 1085

Logical Instructions

ANL A, reg; ORL A, reg

XRL A, reg

5 100 12 1085

ANL A,@R0; ORL A,@R0

XRL A,@R0

5 100 12 1085

ANL A, #data; ORL A, #data

XRL A, #data

5 100 12 1085


541

Table 1. Comparison of Execution Speeds of Instructions: Proposed IP Core vis-a-vis the Intel‟s 8051

Sample Instructions

Proposed FPGA

Implementation of our System

Existing Classical

8051 System

No. of

clock

cycles

Processing speed

in nanoseconds

working @ 50MHz

No. of

clock

cycles

Execution

speed

in

nanoseconds

operating @

11.0592MHZ

Logical Instructions

ANL direct addr, A

ORL direct addr, A

XRL direct addr, A

6 120 12 1085

ANL direct addr, # data

ORL direct addr, # data

XRL direct addr, # data

7 140 24 2170

Data Exchange Instructions

SWAP A 4 80 12 1085

XCH A, data addr 7 140 12 1085

XCH A,reg 6 120 12 1085

XCH A,@R0 6 120 12 1085

XCHD A,@R0 7 140 12 1085

BIT Manipulation Instructions

ORL C, bit addr

ANL C, bit addr

XRL C, bit addr

9 180 24 2170

MOV C, bit addr

MOV bit addr, C

9 180 24 2170

CPL bit addr

SETB bit addr

CLR bit addr

9 180 24 2170

CPL C; CLR C; SETB C 4 80 12 1085

JB bit addr, bit addr

JNB bit addr, bit addr

9 180 24 2170

Jump and Call Instructions

JZ code addr 4 80 24 2170

CJNE A, #data, rel addr 6 120 24 2170

LCALL 16 bit addr 13 260 24 2170

LJMP 16 bit addr 6 120 24 2170

JMP @A + DPTR 7 140 24 2170

SJMP code addr 5 100 24 2170

DJNZ reg, data addr 7 140 24 2170

EXTERNAL ROM OPERATIONS

Data Transfer Instructions

MOVX A, #data 8 160 24 2170

MOVX @DPTR, A 10 200 24 2170

MOVX A,@R0 11 220 24 2170

MOV DPTR, # 16 bit data 13 260 24 2170


542

Figure 13. Simulation Waveform for Data Transfer Instructions

Figure 14. Simulation Waveform for Arithmetic Instructions: “MUL AB” and “DIV AB”


543

Figure 15. Simulation Waveform for “DA A” Instruction

Figure 16. Simulation Waveform for Logical Instruction “ORL A, #33h”

The simulation waveform for Bit manipulation

instruction such as “CPL C”, “CLR C” and

“SETB C” are presented in Fig. 17. These

instructions have Op codes B3 H, C3 H and D3

H respectively. The carry flag “CY” is initially

at logic level „0‟ and after the execution of the

instruction “CPL C” , “CY” flag goes high. For

“CLR C” instruction, CY flag is cleared.

Similarly, for the instruction “SETB C”, the

carry flag goes high. It takes 80 ns each to

execute these instructions and is tabulated in

Table 1.

The simulation waveform for data transfer

instruction from external ROM is presented in

Fig. 18. Op Code for the instruction “ MOV A,

#54 H” is 74 H and is stored in external ROM

locations 4096 and 4097. Thereafter the

external ROM select signal “cs0_n” is asserted

and the “pc” is loaded with address 4096.

“psen_n” goes low to indicate that the data 54

H is read onto “ad_ext” bus.

As an example, the simulation waveform for

the operation of Timer 0 in Mode 1 is presented

in Fig. 19. The Timer 0 is initialized to Mode 1


544

by loading “1” in “TMOD” register. The initial

count in “T0M1” is FFF9 H. The timer enable

signal “tr0” is set in order to start the timer. The

count value advances by “1” at the rising edge

of every clock cycle thereafter until the

terminal count is reached (rolling over to 0 after

FFFF H). Then the flag “tf0” is set to indicate

that the set timing is over. Fig. 20 presents

Timer 0 in Mode 3, where in “TL0” register

functions like an 8 bit timer.

Figure 17. Simulation Waveform for Bit Manipulation Instructions “CPL C”, “CLR C” and “SETB C”

Figure 18. Simulation Waveform for Data Transfer Instruction Stored in External ROM


545

Figure 19. Simulation Waveform of Timer 0 in Mode 1 Operation

Figure 20. Simulation Waveform of Timer 0 in Mode 3 Operation: TL0 as 8 bit Timer Setting

The initial count on “TL0” register is set to FA

H. The start bit is “tr0” and after the terminal

count is attained, the “tf0” flag is set.

Fig. 21 presents Timer 0 in Mode 3, where in

“TH0” register functions like an 8 bit timer.

The initial count on TH0 is set to F0 H. The

start bit is “tr1” and after the terminal count, the

“tf1” flag is set. Fig. 22 presents Timer 1 in

Mode 2, where in “TH1” register functions like

an 8 bit timer and the count on it is

automatically reloaded when the terminal count

is reached. Fig. 23 presents the simulation

waveforms for serial transmission. The 8 bit

data to be transmitted is loaded into

“SBUF_TXD”. The baud rate is decided by

Timer 1 in Mode 2. The data is transmitted bit

by bit on TXD line. After the transmission of 8

bits of data is completed, “TI” flag is set.

Fig. 24 presents the simulation waveforms for

serial reception. The 8 bit data on “RXD” line

is received bit by bit into “SBUF_RXD”. After

the reception of 8 bits of data in “SBUF_RXD”

register, “RI” flag is set.


546

Figure 21. Simulation Waveform of Timer 0 in Mode3 Operation, TH0 as 8 bit timer

Figure 22. Simulation Waveform of Timer 1 in Mode 2 Operation(Auto reload mode)

Figure 23. Simulation Waveform of Serial Transmission


547

Figure 24. Simulation Waveform of Serial Reception

6. CONCLUSIONS AND SCOPE FOR

FUTURE WORK

IP Core has been designed for a

Microcontroller system for developing a Robot

based Agricultural Implement. The Verilog

design of the system conforms to RTL coding

guidelines and is independent of platform and

technology. The IP Core was designed with 4K

internal ROM and 128 bytes of internal RAM.

The external memory designed is of size 60 K

bytes for ROM and 64 K bytes for RAM. The

design includes the realization of two timers.

The sizes of ROM and RAM can be increased

far beyond that of the conventional 8051 since

the proposed IP Core is parameterized. The

number of timers and ports can also be

increased prorate. A Test bench has been

developed using Verilog to validate the

instructions as well as the resources designed.

New Instructions and IP Cores such as a PID

Controller can also be developed. This work is

under progress currently.

The designed IP Core is faster than the Intel‟s

8051 microcontroller by 7 to 54 times

depending upon the complexity of the

instructions realized. The system runs using a

conservative operational frequency of 50 MHz

to suit Spartan 3 FPGA. The same Core can

also work on faster FPGAs at 100 MHz or more

and ASICs at 400 MHz or more since the

design is truly platform and technology

independent. The IP core developed can be

used for all applications, whether they are for a

past product, the current ongoing project or for

future applications. It may be noted that 8051

microcontroller is given a new lease of life by

the present work.

REFERENCES

[1] Yuanyuan, Liu Jia and Liu Runsheng. : Single-Chip

Speech Recognition System Based on 8051

MicrocontroIler Core. In: Proc. IEEE Transactions on

Consumer Electronics, Vol. 47, pp. 149--153 (2001).

[2] A. Moore Scott.: 8080 compatible CPU in Verilog,

http://opencores.org/project, cpu8080.

[3] Aviral Mittal, Philips Semiconductors, Southampton,

UK. : http://www.vlsiip.com/vhdl/8085.vhd.

[4] R. V. Siva Reddy, S. Ramachandran and

K. Nagabhushana Raju.: IP Core Design for Electrostatic

Precipitator Controller System. In: Proc. 2010

International Conference on Advances in Information,

Communication Technology and VLSI Design

(ICAICV), PSG College of Technology, Coimbatore

(2010).

[5] S. Ramachandran. : Digital VLSI Systems Design,

Springer, Netherlands (2007).

[6] Noboru Noguchi, Michio Kise, Kazunobu Ishii and

Hideo Terao.: Field Automation using Robot Tractor. In:

Proc. Conference in Automation Technology for Off-


548

Road Equipment, pp. 239--245. The American Society of

Agricultural and Biological Engineers, St. Joseph,

Michigan (2002).

[7] K. C. Jones.: Tools Carrying Robots Could Weed

Out Tedious Farming Tasks. In: Information Week, July

5 (2007).

[8] D. W. I. Brooke.: Automata for Agriculture-

Driverless Tractor System, Kybernetes, Vol. 4, Iss: 1, pp.

29--32. MCB UP Ltd (1975).

[9] Zhang, X., Geimer, M., Grandl, L., and

Kammerbauer, B.: Vehicular Electronics and Safety. In:

Proc. IEEE International Conference on Vehicular

Electronics and Safety (ICVES), pp. 156--161 (2009).

[10] Chen Jun et al.: On-Tracking Control of Agricultural

Mobile Robot Based on Inner Information. In: Proc.

2011 Computer Distributed Control and Intelligent

Environmental Monitoring (CDCIEM), pp. 103--106,

(2011).

[11] Eaton, R., Katupitiya, J., Siew K. W. and

Howarth, B. : Autonomous Farming: Modeling and

Control of Agricultural Machinery in a Unified

Framework. pp. 499-504, Mechatronics and Machine

Vision in Practice (M2VIP) (2008).

[12] Muhammad Ali Mazidi and Janice Gillispie Mazidi:

The 8051 Microcontroller and Embedded Systems,

Pearson Education (2002).

[13] Kenneth J. Ayala.: The 8051 Microcontroller

Architecture, Programming and Applications, Penram

International India (1997).

[14] Raj Kamal: Microcontollers Architecture,

Programming, Interfacing and System Design, Pearson

Education (2008).


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