real-time turbo decoder nasir ahmed mani vaya elec 434 rice university
TRANSCRIPT
Real-Time Turbo Decoder
Nasir Ahmed
Mani Vaya
Elec 434Rice University
Outline
Description of Turbo Encoding
Description of Turbo Decoding
DSP Implementation issues
Performance Analysis
Conclusions
Turbo Codes
First introduced in 1993
Parallel Concatenation of two Convolutional Coders with interleaving
Original results showed a BER of 10E-5 at 0.7dB using block size 65,536 bits
For rate R=1/2 code, 0.7dB off channel capacity
Turbo Encoder
Parallel concatenation of at least two RSC encoders, with second encoder seeing interleaved version of data
Utilize only one of the systematic streams
RSC1
RSC2 I
xs
xp1
xp2
u
Turbo Encoder
The output stream of data consists of the systematic data, parity bits from encoder1, and parity bits from encoder2
Through the use of the interleaver, the decoder will have two independent looks at the same data, and can use both streams to decode the information sequence
Convolutional Coder
Utilize recursive systematic (RSC) encoders Unlike feed forward coders, a single 1 in the input
will lead to large weight codeword Performance of turbo codes dependent on low
weight codewords
D D u
xp
xs
State transition Diagram
Interleaver
Interleaving is used to reorder the input bits
Random interleaver used for large block sizes
For small block sizes (<1000), random/block interleavers show similar performance
Block interleavers have simple interleaving/de-interleaving mechanism
Importance of Interleaver
At a given SNR, tradeoff between latency due to interleaver and QOS
Small block sizes (~300 bits) can be used for real time voice
Mid range block sizes (~4000 bits) used for video play back
Large block sizes (~16000 bits) large latency, very low BER, useful for file transfer
Turbo Decoding
Two decoders used in serial fashion, with output of one decoder used as prior information to next decoder
Feedback in decoding circuit allows for multiple iterations, and improves bit error performance
D1 D2 I
Inv(I)
Parity2
Parity1 Le12 Le21
Systematic
Decoder
Constituent decoders need bit probability estimates to be used as priors to the next decoder: standard Viterbi cannot be used for this reason
Soft Output Viterbi Algorithm used (SOVA)
The output of decoder1 contains information that can be used as a prior probabilities for decoder2, and vice versa
Steps in Viterbi Algorithm
Calculation of branch metric (distance from received data)
Calculation of path metric (Add compare select)
On reaching the end of trellis, start from the best state
Trace back (knowing the Path metrics)
Decide the data bits while tracing back
Hard Decision Viterbi Basics
Steps in Turbo Decoding
Evaluate the path metrics Trace back to obtain the decisions (x) Trace back using alternate paths to obtain the metric
differences Compute the minimum of all possible metric
differences for that stage Obtain the reliability of decision Pass this reliability of decision to next decoder Iterate the above steps
Path Metric Calculation for SOVA
kpcksc
ikk
ik
ik
uyLuyL
uuLsMsM
***5.0***5.0
*)(*5.0)()(
1
)()('1
)(
s(i) : state of ith path at time k
uk(i): information bit
Ys: received systematic bit, Yp: received parity bit
Mk(s(i)): path metric of ith path at time k
Lc : Channel value = 4*Ec/N0
L(uk): output from previous decoder
Soft Value (L(u)) Computation
Reliability of decisions
Δlk= Mk+l(s(i
l)) – Mk+l
(s(i’l))
Δlk : Metric difference
l: index of all non surviving paths
L(uk) = uk * Min( Δlk)
Min(Δlk ) : Reliability of the decision
Our Implementation
Rate 1/3 coding
Constraint length = 3
Frame length = 400
SOVA algorithm used
Number of iterations are flexible
Algorithmic Issues
Two iterations of Turbo decoding used Traceback depth set at 5 times the constraint length
(optimal for Viterbi decoding)
BPSK modulation used (+/-1)
Extrinsic Information (Le(u)) scaled after every decoder
Fixed point Issues
Used Q-15 format
Received signal (from AWGN channel) clipped to lie in a range of +/-1
Received signal scaled by a constant factor (32) to avoid overflow
Performance in AWGN channel
Data Rates
•Clock cycles / decoder = 654659
•Execution time / decoder = 4.36 ms
•Data rate /decoder = 91.6 Kbps
•Data rate/ iteration = 45.8 Kbps
Conclusions
Fixed point SOVA based Turbo decoder implemented
Performance of DSP matches MATLAB at high SNRs
Real time voice processing possible using our implementation (~22 Kbps for 2 iterations)